Layout pattern for static random access memory

Abstract

This invention proposes a layout pattern for static random access memory (SRAM), comprising four SRAM cell patterns, each containing a six-transistor SRAM cell. Each transistor includes at least one diffusion region located in the substrate beneath the transistor. The first transmission gate transistor PG1 of SRAM1 has a P-type diffusion region D11, and the first transmission gate transistor PG1 of SRAM2 has a P-type diffusion region D21. The P-type diffusion regions D11 and D21 are not in direct contact but are connected and bridging each other via a contact structure BCT1. Word lines are electrically connected to the word lines of adjacent cells via a first metal layer M1. The configuration of the central contact structure satisfies the minimum diffusion enclosure area rule, reducing the rounded corner effect.

Claims

1. A static random access memory (SRAM) layout pattern, comprising: four SRAM cell patterns arranged on a substrate, wherein the four SRAM cell patterns include a first SRAM cell pattern SRAM1, a second SRAM cell pattern SRAM2, a third SRAM cell pattern SRAM3, and a fourth SRAM cell pattern SRAM4 arranged in an array, wherein each SRAM cell pattern includes a first pull-up transistor PU1, a second pull-up transistor PU2, a first pull-down transistor PD1, a second pull-down transistor PD2, a first transmission gate transistor PG1, and a second transmission gate transistor PG2 constituting a six-transistor SRAM cell (6T-SRAM). Multiple diffusion regions, wherein each transistor includes at least one diffusion region located in the substrate below the transistor, wherein the first transmission gate transistor PG1 included in the first static random access memory cell pattern SRAM1 has a P-type diffusion region D11, and the first transmission gate transistor PG1 included in the second static random access memory cell pattern SRAM2 has a P-type diffusion region D21, wherein the P-type diffusion regions D11 and D21 are not in direct contact with each other; a plurality of contact structures, wherein the plurality of contact structures includes a contact structure BCT1 spanning the P-type diffusion region D11 and the P-type diffusion region D21, and electrically connecting the P-type diffusion regions D11 and D21.

2. The static random access memory (SRAM) layout pattern as described in claim 1, wherein the first SRAM cell pattern SRAM1 and the second SRAM cell pattern SRAM2 are aligned in a vertical direction (Y direction), the third SRAM cell pattern SRAM3 and the fourth SRAM cell pattern SRAM4 are aligned in the vertical direction, the first SRAM cell pattern SRAM1 and the third SRAM cell pattern SRAM3 are aligned in a horizontal direction (X direction), and the second SRAM cell pattern SRAM2 and the fourth SRAM cell pattern SRAM4 are aligned in the horizontal direction (X direction).

3. The static random access memory layout pattern as described in claim 1, wherein the first transmission gate transistor PG1 included in the first static random access memory cell pattern SRAM1 has the P-type diffusion region D11, and the first transmission gate transistor PG1 included in the third static random access memory cell pattern SRAM3 has a P-type diffusion region D31, wherein, from a top view, the P-type diffusion region D11 and the P-type diffusion region D31 are directly connected.

4. The static random access memory layout pattern as described in claim 1, wherein the first transmission gate transistor PG1 included in the second static random access memory cell pattern SRAM2 has the P-type diffusion region D21, and the first transmission gate transistor PG1 included in the fourth static random access memory cell pattern SRAM4 has a P-type diffusion region D41, wherein, from a top view, the P-type diffusion region D21 and the P-type diffusion region D41 are directly connected.

5. The layout pattern of the static random access memory as described in claim 1, wherein the plurality of diffusion regions further includes: a P-type diffusion region D12 of the first pull-down transistor PD1 included in the first static random access memory cell pattern SRAM1, wherein at least one substrate contact structure BCT2 is located on the P-type diffusion region D12 among the plurality of contact structures.

6. The static random access memory (SRAM) layout pattern as described in claim 1, wherein: the first SRAM cell pattern SRAM1 includes: a P-type diffusion region D11 of the first transmission gate transistor PG1, a P-type diffusion region D12 of the first pull-down transistor PD1, and an N-type diffusion region D13 of the first transmission gate transistor PG1; the second SRAM cell pattern SRAM2 includes: a P-type diffusion region D21 of the first transmission gate transistor PG1, a P-type diffusion region D22 of the first pull-down transistor PD1, and an N-type diffusion region D23 of the first transmission gate transistor PG1; the third SRAM cell pattern SRAM3 includes: a P-type diffusion region D31 of the first transmission gate transistor PG1, a P-type diffusion region D32 of the first pull-down transistor PD1, and an N-type diffusion region D33 of the first transmission gate transistor PG1; The fourth static random access memory cell pattern SRAM4 includes: a P-type diffusion region D41 of the first transmission gate transistor PG1, a P-type diffusion region D42 of the first pull-down transistor PD1, and an N-type diffusion region D43 of the first transmission gate transistor PG1.

7. The layout pattern of the static random access memory as described in claim 6, wherein, The P-type diffusion region D11, the N-type diffusion region D13, the P-type diffusion region D21, the N-type diffusion region D23, the P-type diffusion region D31, the N-type diffusion region D33, the P-type diffusion region D41, and the N-type diffusion region D43 are connected together and defined as a first closed pattern, wherein the first closed pattern surrounds the substrate.

8. The layout pattern of the static random access memory as described in claim 6, wherein, The P-type diffusion region D11, the P-type diffusion region D12, the N-type diffusion region D13, the P-type diffusion region D31, the P-type diffusion region D32, and the N-type diffusion region D33 are connected to each other to form a second closed pattern, and the second closed pattern surrounds the substrate.

9. The layout pattern of the static random access memory as described in claim 8, wherein, viewed from a top view, the first transmission gate transistor PG1 of the first static random access memory cell pattern SRAM1 has a T-type gate and includes a word line contact WLCT located on the T-type gate, wherein the word line contact WLCT is located within the area of ​​the second closed pattern, and the word line contact WLCT does not overlap with the P-type diffusion region D11.

10. The layout pattern of the static random access memory as described in claim 9, wherein the P-type diffusion region D11 and the P-type diffusion region D12 are not in direct contact with each other.

11. The layout pattern of the static random access memory as described in claim 9 further includes forming a first metal layer M1 and a plurality of first contact pillars V1 on each of the transistors, wherein, viewed from a top view, at least a portion of the first metal layer M1 and at least one of the first contact pillars V1 overlap the contact structure BCT1.

12. The static random access memory layout pattern as claimed in claim 11, wherein the word line contact WLCT in the first static random access memory cell pattern SRAM1 and another word line contact WLCT in the third static random access memory cell pattern SRAM3 are electrically connected to each other via the first metal layer M1.

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