Memory system and memory chip

Abstract

The memory chip includes a memory block, an input / output bus, and a plurality of first sense amplifiers. The plurality of first sense amplifiers are disposed between the memory block and the input / output bus, and are used to output a plurality of first data to the input / output bus in parallel. The memory chip does not contain parallel-to-serial or serial-to-parallel circuitry.

Description

[Technical Field]

[0001] The present invention relates to a memory system, a memory controller, and a memory chip, and more particularly to a memory system, a memory controller, and a memory chip that can effectively utilize the area of ​​a substrate and effectively reduce read / write latency during the refresh of dynamic random access memory. [Previous Technology]

[0002] Currently, memory systems used in high-performance computing or artificial intelligence systems typically include dynamic random access memory (DRAM) chips and logic circuits. Due to the stacked structure of the DRAM chips, the size of the DRAM chips cannot keep up with the size of the logic circuits. Therefore, the memory-wall effect occurs, resulting in a decrease in the data transfer rate between the logic circuits and the DRAM chips. To overcome the memory wall effect, existing technologies typically use faster data rates (e.g., from double data rate three (DDR3) to double data rate fourth (DDR4) or double data rate fifth (DDR5)) to transfer data between the dynamic random access memory (DRAM) chip and the logic circuitry, or use wide data buses of the logic circuitry and the DRAM chip (e.g., high-bandwidth memory, HBM) to transfer data between the DRAM chip and the logic circuitry. However, faster data rates have some disadvantages (e.g., more expensive test equipment, smaller noise margin, etc.), and wide data buses of the logic circuitry and the DRAM chip also have some disadvantages (e.g., higher power consumption, larger die area, expensive through-silicon vias). (Via) manufacturing process, etc. Moreover, both the faster data rate of the aforementioned dynamic random access memory (DRAM) chip and the wide data bus of the aforementioned DRAM chip require serial-parallel circuits and parallel-serial circuits, which both increase clock delay and power consumption.

[0003] Please refer to Figure 1, which is a schematic diagram illustrating a memory system 10 disclosed in the prior art. As shown in Figure 1, the memory system 10 includes a memory 20 and a logic circuit 30, wherein the memory 20 is a dynamic random access memory. As shown in Figure 1, the memory 20 includes a cell array 21, a parallel-to-serial circuit 22, and a serial-to-parallel circuit 23; the logic circuit 30 includes a physical layer 31 and a controller 32, and the physical layer 31 further includes a serial-to-parallel circuit 312 and a parallel-to-serial circuit 314. In addition, the logic circuit 30 also includes other functional circuits (not shown in Figure 1), wherein the other functional circuits may include a central processing unit, a digital signal processor, a peripheral interface, etc. As shown in Figure 1, when the logic circuit 30 writes data to the memory 20, the parallel-serial circuit 314 can receive data (e.g., N-bit data) in parallel from the controller 32, convert the N-bit data into several sets of Q-bit data, where Q is less than N, and transmit the several sets of Q-bit data to the serial-parallel circuit 23; the serial-parallel circuit 23 can receive the several sets of Q-bit data from the parallel-serial circuit 314, convert the several sets of Q-bit data into the N-bit data, and transmit the N-bit data in parallel to the cell array 21. Furthermore, when the logic circuit 30 reads data from the controller 20, the parallel-serial circuit 22 can receive data (e.g., the N-bit data) in parallel from the cell array 21, convert the N-bit data into the several sets of Q-bit data, and transmit the several sets of Q-bit data to the serial-parallel circuit 312; the serial-parallel circuit 312 can receive the several sets of Q-bit data from the parallel-serial circuit 22, convert the several sets of Q-bit data into the N-bit data, and transmit the N-bit data in parallel to the controller 32.

[0004] Please refer to Figures 2A and 2B. Figures 2A and 2B are timing diagrams of the logic circuit 30 writing data into memory 20. As shown in Figure 2A, taking the logic circuit 30 writing 8-bit metadata D0-D7 into memory 20 as an example, when the logic circuit 30 writes the 8-bit metadata D0-D7 into memory 20, the temporary register of the parallel-serial circuit 314 (not shown in Figure 1) can use three signals clk1, clk2, and clk3 to serially transmit the 8-bit parallel data D0-D7 to the serial-parallel circuit 23. For example, when clk1=1, clk2=1, and clk3=1, the parallel-serial circuit 314 transmits data D0 to the serial-parallel circuit 23; when clk1=1, clk2=1, and clk3=0, the parallel-serial circuit 314 transmits data D1 to the serial-parallel circuit 23, and so on. Therefore, the parallel-serial circuit 314 starts transmitting data D0 at time T0 and finally transmits data D7 at time T4.

[0005] As shown in Figure 2B, similarly, the temporary register of the serial-parallel circuit 23 (not shown in Figure 1) can also use clock signals clk1, clk2, and clk3 to serially process the 8-bit serial data D0-D7 from the parallel-serial circuit 314. As shown in Figure 2B, when clk1=1, clk2=1, and clk3=1, the serial-parallel circuit 23 receives data D0 from the parallel-serial circuit 314; when clk1=1, clk2=1, and clk3=0, the serial-parallel circuit 23 receives data D1 from the parallel-serial circuit 314, and so on. Therefore, the serial-parallel circuit 23 starts receiving data D0 at time T0 and finally receives data D7 at time T4, where there is a 4-clock delay in the clock signal clk3 between time T0 and time T4. That is to say, the serial-parallel circuit 23 will only start transmitting the 8-bit data D0-D7 in parallel to the cell array 21 after waiting for a 4-clock delay.

[0006] Although existing technology can reduce the latency by 4 clock cycles (e.g., to 3.5 clock cycles) by optimizing the memory system 10, the serial-to-parallel conversion process performed by the serial-to-parallel circuit 23 and the serial-to-parallel conversion process performed by the parallel-to-serial circuit 314 require additional power, transmission latency, and die area, resulting in low efficiency of the memory system 10. Therefore, how to reduce power consumption, transmission latency, and die area is an important problem that memory system designers need to solve. [Summary of the Invention]

[0007] One embodiment of the present invention provides a memory controller for a dynamic random-access memory (DRAM) system. The DRAM system includes a system bus interface and a memory chip, the memory chip including an input / output bus. The memory controller includes a control circuit and a physical layer circuit. The control circuit is coupled to the system bus interface. The physical layer circuit is coupled to the control circuit and is used to receive a plurality of first data in parallel from the input / output bus of the memory chip. The physical layer circuit of the memory controller does not include parallel-to-serial or serial-to-parallel circuits.

[0008] In one embodiment of the present invention, the physical layer circuit is further used to output a plurality of second data to the input / output bus of the memory chip in parallel.

[0009] In one embodiment of the present invention, the memory controller receives a handshake signal from the memory chip to selectively notify the memory controller whether the memory chip has not performed a refresh operation.

[0010] In one embodiment of the present invention, the handshake signal is activated when the memory chip performs the refresh operation, and the handshake signal is deactivated when the memory chip does not perform the refresh operation.

[0011] In one embodiment of the present invention, when the handshake signal is activated, the memory controller generates an access instruction to read data from the memory chip or write data to the memory chip.

[0012] In one embodiment of the present invention, after the handshake signal is deactivated, the memory controller sends the access instruction to the memory chip.

[0013] Another embodiment of the present invention provides a memory system. The memory system includes a system bus interface, a memory controller, a memory chip, and a substrate. The memory controller has a controller input / output bus coupled to a plurality of second bump groups. The memory controller is coupled to the system bus interface and further includes a physical layer, in which there are no parallel-to-serial or serial-to-parallel circuits. The memory chip has a memory input / output bus coupled to a plurality of first bump groups. The memory chip is coupled to the memory controller and also in which there are no parallel-to-serial or serial-to-parallel circuits. The memory controller and the memory chip are disposed on the substrate and horizontally spaced apart from each other.

[0014] In one embodiment of the present invention, the plurality of first bump groups are arranged in a side-by-side order, the plurality of second bump groups are arranged in a side-by-side order, each of the plurality of first bump groups is connected to a corresponding second bump group in the plurality of second bump groups through a corresponding track in the substrate, and the plurality of tracks connecting the plurality of first bump groups to the plurality of second bump groups do not intersect each other.

[0015] Another embodiment of the present invention provides a memory chip. The memory chip includes a first group of memory blocks and an input / output bus. The input / output bus is electrically coupled to the first group of memory blocks, wherein each first memory block in the first group of memory blocks is used to transmit data having a first predetermined width to the input / output bus in parallel, the width of the input / output bus being equal to the sum of the first predetermined widths of the data transmitted by each first memory block in the first group of memory blocks, and the first predetermined width being programmed according to a set of control signals. There are no parallel-to-serial or serial-to-parallel circuits in the memory chip.

[0016] In one embodiment of the present invention, the memory chip further includes a second group of memory blocks, wherein each second memory block in the second group of memory blocks is used to transmit data having a second predetermined width to the input / output bus in parallel, wherein, according to a selection signal, the width of the input / output bus is selectively equal to the sum of the first predetermined widths of the data transmitted by each first memory block in the first group of memory blocks or the sum of the second predetermined widths of the data transmitted by each second memory block in the second group of memory blocks.

[0017] In one embodiment of the present invention, when the width of the input / output bus is equal to the sum of the second predetermined widths of the data transmitted by each second memory block in the second set of memory blocks, the second predetermined width is programmed according to the set of control signals.

[0018] Another embodiment of the present invention provides a memory chip. The memory chip includes a plurality of memory blocks, a plurality of data lines, a plurality of sense amplifiers, and an input / output bus. The plurality of sense amplifiers are coupled to the plurality of data lines, wherein each sense amplifier corresponds to one of the plurality of memory blocks and is used to output multiple data in parallel. The memory chip does not have parallel-to-serial or serial-to-parallel circuitry, and the memory chip sends a handshake signal to selectively notify the memory chip whether a refresh operation has not been performed.

[0019] In one embodiment of the present invention, the memory chip further includes an additional output pin, wherein the handshake signal is transmitted to a memory controller through the additional output pin, wherein the memory controller is separate from the memory chip entity.

[0020] In one embodiment of the present invention, the handshake signal is activated when the memory chip performs the refresh operation, and the handshake signal is deactivated when the memory chip does not perform the refresh operation.

[0021] In one embodiment of the present invention, the memory chip further includes a refresh counter, wherein the handshake signal is selectively activated according to the number of clock cycles counted by the refresh counter.

[0022] In one embodiment of the present invention, the plurality of memory blocks include a first memory block and a second memory block; the plurality of sense amplifiers include a first set of sense amplifiers coupled to the plurality of data lines and a second set of sense amplifiers coupled to the plurality of data lines; the first set of sense amplifiers corresponds to the first memory block and is used to output a plurality of first data in parallel, and the second set of sense amplifiers corresponds to the second memory block and is used to output a plurality of second data in parallel; the width of the input / output bus is equal to the sum of the widths of the plurality of first data and the widths of the plurality of second data.

[0023] In one embodiment of the present invention, the memory chip further includes a plurality of bit lines, a third set of sense amplifiers, and a fourth set of sense amplifiers. The third set of sense amplifiers is coupled to the plurality of bit lines and disposed in the first memory block and the first set of sense amplifiers. The fourth set of sense amplifiers is coupled to the plurality of bit lines and disposed in the second memory block and the second set of sense amplifiers. A portion of the third set of sense amplifiers selectively couples to the first set of sense amplifiers, and the number of the third set of sense amplifiers is equal to the number of the first set of sense amplifiers. A portion of the fourth set of sense amplifiers selectively couples to the second set of sense amplifiers, and the number of the fourth set of sense amplifiers is equal to the number of the second set of sense amplifiers.

[0024] In one embodiment of the present invention, the third sensing amplifier of this portion is selectively coupled to the first group of sensing amplifiers according to a control signal input to the memory chip, and the fourth sensing amplifier of this portion is selectively coupled to the second group of sensing amplifiers according to the control signal.

Implementation Method

[0026] Please refer to Figure 3, which is a schematic diagram of the memory system 100 disclosed in the first embodiment of the present invention. As shown in Figure 3, the memory system 100 includes a memory 101 and a logic circuit 102. The memory 101 may be dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, or other memory. The logic circuit 102 may be an artificial intelligence chip or a system on a chip (SOC). Furthermore, in one embodiment of the present invention, the memory 101 may include a base DRAM chip and multiple DRAM chips stacked on the base DRAM chip. Furthermore, the logic circuit 102 can be coupled to other devices or processors via an Advanced eXtensible Interface (AMBA) bus, which is a bus protocol part of the Advanced Microcontroller Bus Architecture (AMBA) 3.0 protocol. The AMBA bus includes a write data bus and a read data bus. Moreover, the operation of the AMBA bus is well-known to those skilled in the art and will not be described further here.

[0027] The memory 101 includes a first alignment circuit 1011 and a plurality of first pads FP, wherein the first alignment circuit 1011 is used to align data with respect to the memory 101, and the first alignment circuit 1011 includes a plurality of transceivers. That is, the first alignment circuit 1011 is used to transmit the data simultaneously or receive the data simultaneously (e.g., transmit the data in the same clock cycle, or receive the data in the same clock cycle; that is, the plurality of transceivers of the first alignment circuit 1011 can transmit the data in parallel or receive the data in parallel). On the other hand, the logic circuit 102 includes a physical layer 103 and a controller 105, wherein the physical layer 103 is electrically connected to the controller 105 via a dual data rate physical layer interface (DDR PHY Interface, DFI) bus. The dual data rate physical layer interface bus includes a plurality of transmission line pairs, wherein the plurality of transmission line pairs include a plurality of write lines and a plurality of read lines. Furthermore, physical layer 103 includes a second alignment circuit 1031 and a plurality of second pads SP, wherein the second alignment circuit 1031 is used to align the data, and the second alignment circuit 1031 also includes a plurality of transceivers. That is, the second alignment circuit 1031 is used to transmit the data simultaneously or receive the data simultaneously (e.g., transmit the data in the same clock cycle, or receive the data in the same clock cycle; that is, the plurality of transceivers of the second alignment circuit 1031 can transmit the data in parallel or receive the data in parallel).

[0028] In one embodiment of the present invention, the first alignment circuit 1011 and the second alignment circuit 1031 can align the data and transmit the data in parallel, or can align and receive the data in parallel. In the memory 101 and physical layer 103, conventional parallel-to-serial circuits and serial-to-parallel circuits are not required to transmit the data between the memory 101 and the logic circuit 102. Therefore, the controller (or memory controller) 105 can utilize the plurality of transmission line pairs, the second alignment circuit 1031, the plurality of second pads SP, the plurality of first pads FP, and the first alignment circuit 1011 to access data about the memory 101 in parallel. The number of the plurality of first pads FP can be equal to the number of the plurality of write lines (or the plurality of read lines) in the plurality of transmission line pairs. Additionally, the number of the plurality of second pads SP can be equal to the number of the plurality of write lines (or the plurality of read lines) in the plurality of transmission line pairs.

[0029] For example, as shown in FIG3, the number of multiple first pads FP or the number of multiple second pads SP is equal to N, and the data can be N-bit metadata RD read from the cell array of memory 101 or N-bit metadata WD written to the cell array of memory 101. When logic circuit 102 reads N-bit metadata RD in parallel from the cell array of memory 101, first alignment circuit 1011 receives N-bit metadata RD in parallel from the cell array of memory 101, and simultaneously transmits N-bit metadata RD in parallel to second alignment circuit 1031 through multiple first pads FP and multiple second pads SP. After second alignment circuit 1031 receives N-bit metadata RD in parallel, second alignment circuit 1031 transmits N-bit metadata RD in parallel to controller 105 through multiple read lines of multiple transmission line pairs of the dual data rate physical layer interface bus. On the other hand, when logic circuit 102 writes N-bit metadata WD in parallel to the cell array of memory 101, second alignment circuit 1031 receives N-bit metadata WD in parallel from controller 105 through the multiple write lines of the multiple transmission line pairs of the dual data rate physical layer interface bus. Then, second alignment circuit 1031 can simultaneously transmit N-bit metadata WD to first alignment circuit 1011 without using conventional parallel-to-serial and serial-to-parallel circuits. After receiving N-bit metadata WD, first alignment circuit 1011 writes N-bit metadata WD in parallel to the cell array of memory 101.

[0030] Furthermore, each alignment circuit in the first alignment circuit 1011 and the second alignment circuit 1031 includes a plurality of transceivers, wherein each transceiver in the first alignment circuit 1011 is coupled to a corresponding pad of a plurality of first pads FP, and each transceiver in the second alignment circuit 1031 is coupled to a corresponding pad of a plurality of second pads SP. Referring to FIG4, FIG4 is a schematic diagram of the structure of two transceivers TR1 and TR2 disclosed in another embodiment of the present invention, wherein each transceiver in the first alignment circuit 1011 (not shown in FIG4) can be transceiver TR1, and each transceiver in the second alignment circuit 1031 (not shown in FIG4) can be transceiver TR2. Furthermore, the components of transceivers TR1 and TR2 are known to those skilled in the art and will not be described further here. Furthermore, the coupling relationship between the components of transceivers TR1 and TR2 can be seen in FIG4 and will not be described further here. When the write enable signal W_EN is enabled and the read enable signal R_EN is disabled, transceiver TR2 transmits one bit of metadata WD_N of N-bit metadata WD to transceiver TR1 via a first pad FPN and a second pad SPN. Conversely, when the write enable signal W_EN is disabled and the read enable signal R_EN is enabled, transceiver TR1 transmits one bit of metadata RD_N of N-bit metadata RD to transceiver TR2 via the first pad FPN and the second pad SPN. Because the write enable signal W_EN and the read enable signal R_EN are common signals for the first alignment circuit 1011 and the second alignment circuit 1031, the first alignment circuit 1011 can simultaneously transmit N-bit metadata RD or receive N-bit metadata WD in parallel, and the second alignment circuit 1031 can simultaneously transmit N-bit metadata WD or receive N-bit metadata RD in parallel.

[0031] In another embodiment of the present invention, a first write enable signal and a first read enable signal are signals for the first alignment circuit 1011, and a second write enable signal and a second read enable signal are signals for the second alignment circuit 1031, wherein the first write enable signal and the first read enable signal correspond to the second write enable signal and the second read enable signal, respectively.

[0032] The first alignment circuit 1011 and the second alignment circuit 1031 do not need to be connected to conventional parallel-to-serial circuits and serial-to-parallel circuits. The first alignment circuit 1011 can simultaneously transmit N bits of metadata RD to the second alignment circuit 1031 in parallel, or receive N bits of metadata WD from the second alignment circuit 1031 in parallel. Similarly, the second alignment circuit 1031 can simultaneously receive N bits of metadata RD from the first alignment circuit 1011 in parallel, or transmit N bits of metadata WD to the first alignment circuit 1011 in parallel. Furthermore, as shown in FIG4, the present invention is not limited to each transceiver of the first alignment circuit 1011 being transceiver TR1 and each transceiver of the second alignment circuit 1031 being transceiver TR2. That is, each transceiver of the first alignment circuit 1011 and each transceiver of the second alignment circuit 1031 can be other transceiver circuits, buffers, or registers.

[0033] Please refer to Figure 5, which is a timing diagram used to compare a conventional memory system and memory system 100. For example, as shown in Figure 5(a), when a conventional logic circuit reads 8-bit serial data D0-D7 from a conventional memory, the conventional memory must use three clock cycles clk1, clk2, and clk3 to form 8 states (e.g., data D0 corresponds to states clk1=1, clk2=1, clk3=1, data D1 corresponds to states clk1=1, clk2=1, clk3=0, etc.), so that the 8-bit serial data D0-D7 can be converted into parallel states. Therefore, a controller of the conventional logic circuit can only start receiving data D0-D7 in parallel at a time T4.

[0034] However, as shown in FIG5(b), since there is no need to connect conventional parallel-serial circuits and serial-parallel circuits, the data D0-D7 are simultaneously transmitted in parallel by the first alignment circuit of memory 101, and the second alignment circuit of controller 105 can start receiving parallel data D0-D7 at a time T0. Therefore, compared with the conventional memory system, the present invention can save 4 clock delays. In addition, the operation method of writing 8-bit metadata D0-D7 is similar to the operation method described above, and will not be repeated here.

[0035] Please refer to Figure 3 again. As shown in Figure 3, the controller 105 is further coupled to the physical layer 103 via multiple control lines. The physical layer 103 further includes multiple second control pads (SCPs), and the memory 101 further includes multiple first control pads (FCPs). The multiple first control pads (FCPs) are electrically connected to the multiple second control pads (SCPs). Therefore, the controller 105 can use the multiple control lines, the multiple second control pads (SCPs), and the multiple first control pads (FCPs) to transmit control signals such as CS to the memory 101. In addition, Figure 3 only shows three first control pads, three second control pads, and three control lines, but the present invention is not limited thereto. Furthermore, the multiple control lines and the multiple transmission line pairs between the physical layer 103 and the controller 105 are all included in a dual data rate physical layer interface bus, wherein the dual data rate physical layer interface bus defines the signals, timing parameters, and programmable parameters required for communication between the physical layer 103 and the controller 105. Therefore, control signals such as CS are defined by the Dual Data Rate Physical Layer Interface bus and may include, for example, write enable signals, read enable signals, and chip select signals. Furthermore, the operation methods of the Dual Data Rate Physical Layer Interface bus are well-known to those skilled in the art and will not be described further here. In another embodiment of the invention, the logic circuit 102 may further include system circuitry (not shown in FIG. 3), wherein the system circuitry may include other peripheral interfaces. The controller (or memory controller) 105 communicates with the system circuitry via the Advanced Scalable Interface Bus (AXI bus). For example, the controller 105 may transmit N-bit metadata RD to the system circuitry via the AXI bus, or receive N-bit metadata WD from the system circuitry to other devices or processors via the AXI bus.

[0036] Furthermore, the plurality of first pads FP can be electrically connected to the plurality of second pads SP via metal wires, metal bridges, flip chips, microbumps, or other bonding technologies. In other embodiments of the invention, because the plurality of first pads FP are electrically connected to the plurality of second pads SP, the plurality of first pads FP and the plurality of second pads SP are not coupled to an environment outside the memory system 100. Therefore, the plurality of first pads FP and the plurality of second pads SP do not need to include conventional electrostatic discharge protection circuitry, and the size of the plurality of first pads FP and the plurality of second pads SP can be reduced.

[0037] In other embodiments of the present invention, the second alignment circuit 1031 of the physical layer 103 can be applied to different data widths, depending on the data width of the advanced scalable interface bus. However, in other embodiments of the present invention, both the second alignment circuit 1031 of the physical layer 103 and the first alignment circuit 1011 of the memory 101 can be applied to different data widths simultaneously, depending on the data width of the advanced scalable interface bus. For example, when the logic circuit 102 is applied to a memory with a Q-bit data width, the controller 105 can instruct the physical layer 103 to adjust the second alignment circuit 1031 so that the second alignment circuit 1031 uses only the Q read lines of the plurality of transmission line pairs to transmit Q-bit data to the controller 105 (or uses only the Q write lines of the plurality of transmission line pairs to receive Q-bit data from the controller 105), where Q is a positive integer greater than 1 and less than N. Therefore, the physical layer 103 and the controller 105 can be applied to different system circuits and different memories with different data widths.

[0038] Since the first alignment circuit 1011 and the second alignment circuit 1031 become smaller and simpler, and the traditional parallel-serial circuit and serial-parallel circuit are omitted from the memory 101 and the physical layer 103, the write / read speed of the memory 101 is significantly increased. The area of ​​the memory 101 is smaller than that of the traditional memory, and the area of ​​the physical layer 103 is also smaller than that of the physical layer in the traditional logic circuit (as shown in Figure 6). The memory wall problem between the memory 101 and the logic circuit 102 is also reduced. Furthermore, the physical layer 103 can receive signals such as Dfi cke, Dfi CK / CKB, Dfi BA, Dfi address, Dfi cs, Dfi ras, Dfi cas, Dfi we, Dfi wrdata, Dfi wrdata mask, and Dfi wrdata valid from the controller 105 through the dual data rate physical layer interface bus (DFI bus), and transmit signals such as Dfi rddata and Dfi rddata valid to the controller 105. The dual data rate physical layer interface specification defines signals such as Dfi cke, Dfi CK / CKB, Dfi BA, Dfi address, Dfi cs, Dfi ras, Dfi cas, Dfi we, Dfi wrdata, Dfi wrdata mask, and Dfi wrdata valid, as well as signals such as Dfi rddata and Dfi rddata valid, so they will not be described in detail here. Furthermore, physical layer 103 can transmit signals such as CKE, CK / CKB, BA, Addr, CSB, RASB, CASB, WEB, DQ, DM, and DQS / DQSB to memory 101. The Dual Data Rate Physical Layer Interface specification also defines signals such as CKE, CK / CKB, BA, Addr, CSB, RASB, CASB, WEB, DQ, DM, and DQS / DQSB, so they will not be elaborated upon here. Therefore, even if memory 101 and logic circuit 102 are manufactured using a heterogeneous process, multiple first pads FP can still be electrically connected to multiple second pads SP. For example, the transistor of memory 101 can be a planar transistor or a trench transistor used in current memory technologies (such as dynamic random access memory or high bandwidth memory technology), while the transistor of logic circuit 102 can be a three-dimensional transistor (such as a three-gate transistor, a fin field-effect transistor (FinFET) or a gate-all-around transistor).However, in other embodiments of the invention, the memory 101 and logic circuit 102 are manufactured using a homogeneous process. That is, the transistors of the memory 101 and logic circuit 102 can be planar transistors, trench transistors, tri-gate transistors, fin field-effect transistors, all-around gate transistors, or other transistors. Furthermore, because the memory 101 and logic circuit 102 employ a first alignment circuit 1011 and a second alignment circuit 1031, instead of conventional parallel-serial and serial-parallel circuits, power consumption of the memory 101 and logic circuit 102 can be saved, latency of the memory processor 101 can be reduced, and area cost of the memory 101 and logic circuit 102 can be lowered. Therefore, the read / write window margins of the memory system 100 can be improved.

[0039] Furthermore, please refer to Figure 7. Figure 7 is a schematic diagram of the data width of a memory changing according to a control signal according to another embodiment of the present invention. For example (but not limited thereto), the memory 101 includes a memory cell array (hereinafter referred to as the cell array), M second sense amplifiers BLSA (e.g., bit line sense amplifiers), and N first sense amplifiers DLSA (e.g., data line sense amplifiers), wherein the number of connections of the M second sense amplifiers BLSA electrically connected to the N first sense amplifiers DLSA can be changed according to a control signal (e.g., according to SB0-SB4 in Table 1), the second sense amplifiers BLSA are located between the cell array and the first sense amplifiers DLSA, the first sense amplifiers DLSA are located between the second sense amplifiers BLSA and the first alignment circuit 1011, wherein the first alignment circuit 1011 includes a plurality of transceivers, the first alignment circuit 1011 is located between the first sense amplifiers DLSA and the input / output data bus of the memory 101 (not shown in Figure 7), N is a positive integer not greater than M, and the input / output data bus is coupled to a plurality of first pads FP.

[0040] In one embodiment, the control signal is stored in a register (not shown in FIG. 7) of memory 101, such as a mode register. Furthermore, a second sense amplifier BLSA is coupled to a bit line (not shown in FIG. 7) of memory 101, and a first sense amplifier DLSA is coupled to a data line (not shown in FIG. 7) of memory 101. N first sense amplifiers DLSA are electrically connected to all or part of M second sense amplifiers BLSA via multiple bit switches, and the multiple bit switches can be selected or enabled according to the aforementioned control signal.

[0041] As shown in Table 1 and Figure 7, for example, when the control signals SB0-SB4 are 0 / 0 / 0 / 0 / 1, the second sense amplifier will transmit 128 bits to the first sense amplifier through bit switches (not shown in Figure 7, a set of selected bit switches, for example, 128 or fewer bit switches selected by the control signals SB0-SB4 (0 / 0 / 0 / 0 / 1) based on a given column address). That is, the 128 bits of data can be read from the cell array of memory 101 through all or part of the second sense amplifier and the first sense amplifier (e.g., through 128 connected second sense amplifiers and 128 first sense amplifiers), or the 128 bits of data can be written to the cell array of memory 101 by the first alignment circuit 1011 through all or part of the second sense amplifier and the first sense amplifier (e.g., through 128 connected second sense amplifiers and 128 first sense amplifiers). In other words, when the 128-bit metadata is read from the cell array of memory 101, the plurality of transceivers of the first alignment circuit 1011 receive the 128-bit metadata in parallel from the 128 first sense amplifiers and then transmit it to the input / output data bus of memory 101; or when the 128-bit metadata is written to the cell array of memory 101, the plurality of transceivers of the first alignment circuit 1011 receive the 128-bit metadata in parallel from the input / output data bus and then transmit it to the 128 first sense amplifiers. In other words, when the 128-bit metadata is read from the cell array of memory 101, a portion of the second sense amplifiers (BLSAs) (e.g., the 128 connected second sense amplifiers) output the 128-bit metadata to the first sense amplifiers (DLSAs) (e.g., the 128 first sense amplifiers), and then the first sense amplifiers (DLSAs) output the 128-bit metadata in parallel to the first alignment circuit 1011, after which the first alignment circuit 1011 transmits the 128-bit metadata in parallel via the input / output data bus; or when the 128-bit metadata is written to the cell array of memory 101, the input / output data bus transmits the 128-bit metadata in parallel to the first alignment circuit 1011, and then the first alignment circuit 1011 outputs the 128-bit metadata in parallel to the 128 first sense amplifiers, after which the 128 first sense amplifiers output the 128-bit metadata in parallel to the connected second sense amplifiers (e.g., the 128 connected second sense amplifiers (BLSAs)). Furthermore, based on the 128-bit metadata width output in parallel by the first sensing amplifier, the data width of memory 101 (that is, the width of the input / output data bus of memory 101) is equal to the 128-bit width.At this time, because the data width of memory 101 is equal to 128 bits, according to control signals SB0-SB4, the data width of the write line (or read line) of the dual data rate physical layer interface bus (DFI bus) coupled to physical layer 103 is also equal to or set to 128 bits. The data width of controller 105 and the data width of the write data bus (or read data bus) of the advanced scalable interface bus are also equal to 128 bits. As shown in FIG7, when logic circuit 102 is included in a computing system, this computing system has a system interface bus (i.e., the advanced scalable interface bus) including a read data bus and a write data bus. According to control signals SB0-SB4 (0 / 0 / 0 / 0 / 1) input to controller 105, the width of the read data bus and the width of the write data bus are both equal to 128 bits. Furthermore, the width of the dual data rate physical layer interface bus is selectively adjusted according to the control signals SB0-SB4 (0 / 0 / 0 / 0 / 1) input to the physical layer 103.

[0042] Similarly, as shown in Table 1 and Figure 7, when the control signals SB0-SB4 are 0 / 0 / 0 / 1 / 0, 256 of the M second sensing amplifiers are electrically connected to the 256 first sensing amplifiers through another set of selected bit switches (e.g., 256 or fewer bit switches selected based on a given column address). Therefore, according to the 256 first sensing amplifiers, the data width of memory 101 will be equal to the 256-bit width. When the control signals SB0-SB4 are 0 / 0 / 0 / 1 / 1, 512 of the M second sensing amplifiers are electrically connected to the 512 first sensing amplifiers through another set of selected bit switches (e.g., 512 or fewer bit switches selected based on a given column address). Therefore, according to the 512 first sensing amplifiers, the data width of memory 101 will be equal to the 256-bit width. The memory 101 has a data width of 512 bits. When the control signals SB0-SB4 are 0 / 0 / 1 / 0 / 0, 1024 of the M second sense amplifiers are electrically connected to the 1024 first sense amplifiers through another set of selected bit switches (e.g., 1024 or fewer bit switches selected based on a given column address). Therefore, according to the 1024 first sense amplifiers, the data width of the memory 101 is equal to the 1024-bit width. When the control signals SB0-SB4 are 0 / 0 / 0 / 0 / 0, 64 of the M second sense amplifiers are electrically connected to the 64 first sense amplifiers through another set of selected bit switches (e.g., 64 or fewer bit switches selected based on a given column address). Therefore, according to the 64 first sense amplifiers, the data width of the memory 101 is equal to the 64-bit width.

[0043] That is to say, since there is no need to connect traditional parallel-serial circuits and serial-parallel circuits, the first sensing amplifier can be directly connected to the first alignment circuit. The parallel output data width of the first sensing amplifier is equal to the data width of memory 101. The data width of memory 101 is equal to the write line (or read line) data width of the dual data rate physical layer interface bus (DFI bus) of physical layer 103, and also equal to the data width of controller 105 and the write data bus (or read data bus) data width of the advanced expandable interface bus. From another perspective, once the data width of the write data bus (or read data bus) of the Advanced Scalable Interface Bus in the application environment of memory 101 and logic circuit 102 is confirmed, the data width of memory 101 can be made equal to the data width of the write line (or read line) of the Dual Data Rate Physical Layer Interface Bus (DFI bus) of physical layer 103, and also equal to the data width of controller 105 and the data width of the write data bus (or read data bus) of the Advanced Scalable Interface Bus by setting control signals SB0-SB4. Furthermore, this invention is not limited to memory 101 including M second sense amplifiers, nor is it limited to the configuration of control signals SB0-SB4 shown in FIG. 7. Moreover, this invention is not limited to the number of control signals SB0-SB4; that is, this invention can have more or fewer control signals than the number of control signals SB0-SB4. SB4 / SB3 / SB2 / SB1 / SB0 Data width of memory 101 Data width of controller 105 The data width of the write data bus (or read data bus) of the advanced scalable interface bus. 0 / 0 / 1 / 0 / 0 1024 1024 1024 0 / 0 / 0 / 1 / 1 512 512 512 0 / 0 / 0 / 1 / 0 256 256 256 0 / 0 / 0 / 0 / 1 128 128 128 0 / 0 / 0 / 0 / 0 64 64 64 Table 1

[0044] Furthermore, please refer to Figure 8. Figure 8 is a schematic diagram of a memory 801 disclosed in another embodiment of the present invention, wherein the difference between memory 801 and memory 101 is that memory 801 includes four memory blocks B0-B3, each of which is the cell array of memory 101. However, the present invention is not limited to memory 801 including four memory blocks B0-B3 (that is, memory 801 may include multiple memory blocks). In addition, for simplicity, the M second sensing amplifiers BLSA and N first sensing amplifiers DLSA are not shown in Figure 8.

[0045] As shown in Table 2 and Figure 8, when the control signals SB0-SB4 are 0 / 0 / 0 / 1 / 0, 256 second sense amplifiers (not shown) of a specific memory block of memory 801 can be electrically connected to 256 first sense amplifiers (not shown) according to the control signals SB0-SB4. Therefore, through the 256 connected second sense amplifiers and the 256 first sense amplifiers, 256 bits of metadata can be read from the specific memory block of memory 801 by the first alignment circuit 1011, or through the 256 connected second sense amplifiers and the 256 first sense amplifiers, 256 bits of metadata can be written to the specific memory block of memory 801 by the first alignment circuit 1011. Additionally, the specific memory block of memory 801 can be selected by other signals, such as a block selection signal. That is, as shown in Table 2, according to the 256 first sense amplifiers, the data width of the selected memory block of memory 801 can be adjusted to be equal to 256. Furthermore, since the four memory blocks B0-B3 are independent of each other, the data width of memory 801 (that is, the width of the input / output data bus of memory 801) is also equal to 256. Additionally, in other embodiments of the invention, according to control signals SB0-SB4 (0 / 0 / 0 / 1 / 0), the data width of controller 105 and the write line (or read line) data width of the dual data rate physical layer interface bus are both equal to 256.

[0046] Furthermore, the other data widths of each memory block of memory 801 corresponding to control signals SB0-SB4 (0 / 0 / 1 / 0 / 0), (0 / 0 / 0 / 1 / 1), (0 / 0 / 0 / 0 / 1), and (0 / 0 / 0 / 0 / 0) are described in Table 2, and therefore will not be repeated here. Furthermore, the present invention is not limited to the configuration of control signals SB0-SB4 shown in FIG8. SB4 / SB3 / SB2 / SB1 / SB0 The data width of the write data bus (or read data bus) of the advanced scalable interface bus. Data width of each memory block Data width of memory 801 0 / 0 / 1 / 0 / 0 1024 1024 1024 0 / 0 / 0 / 1 / 1 512 512 512 0 / 0 / 0 / 1 / 0 256 256 256 0 / 0 / 0 / 0 / 1 128 128 128 0 / 0 / 0 / 0 / 0 64 64 64 Table 2

[0047] Furthermore, please refer to Figure 9. Figure 9 is a schematic diagram of memory 901 disclosed in another embodiment of the present invention, wherein memory 901 differs from memory 801 in that memory blocks B0 and B1 are included in block group BG0, and memory blocks B2 and B3 are included in block group BG1. However, the present invention is not limited to block group BG0 including memory blocks B0 and B1, and block group BG1 including memory blocks B2 and B3. For example, all blocks B0, B1, B2, and B3 can be grouped into one block group BGX.

[0048] Taking block group BG0 as an example, a first set of sense amplifiers is coupled to the data line and a second set of sense amplifiers is coupled to the data line. The first set of sense amplifiers corresponds to memory block B0 and is used to output multiple first data in parallel. The second set of sense amplifiers corresponds to memory block B1 and is used to output multiple second data in parallel. The first set of sense amplifiers and the second set of sense amplifiers are the previously mentioned first sense amplifiers (i.e., DLSA). In addition, a third set of sense amplifiers is coupled to the bit line and is disposed between memory block B0 and the first set of sense amplifiers. A fourth set of sense amplifiers is coupled to the bit line and is disposed between memory block B1 and the second set of sense amplifiers. The third set of sense amplifiers and the fourth set of sense amplifiers are the previously mentioned second sense amplifiers (i.e., BLSA).

[0049] Therefore, as shown in Table 3 and Figure 9, when the control signals SB0-SB4 are 0 / 1 / 0 / 1 / 0, according to the control signals SB0-SB4, the 128 second sense amplifiers corresponding to each memory block of a specific block group (e.g., block group BG0) are electrically connected to the 128 first sense amplifiers corresponding to each memory block of the specific block group. Therefore, through the 256 connected second sense amplifiers and the 256 first sense amplifiers, the 256-bit metadata can be read from the specific block group by the first alignment circuit 1011 (because the first alignment circuit 1011 can read the 128-bit metadata of the 256-bit metadata from the memory block of the specific block group through the 128 connected second sense amplifiers and the 128 first sense amplifiers corresponding to one memory block, and the first alignment circuit 1011 can also read the 128-bit metadata of the 256-bit metadata from the memory block of the specific block group through the 128 connected second sense amplifiers and the 128 first sense amplifiers corresponding to another memory block). The second sensing amplifier and another 128 first sensing amplifiers are connected to read another 128 bits of the 256-bit metadata from the other memory block of the specific block group, or the 256-bit metadata can be written to the specific block group by the first alignment circuit 1011 through the 256 connected second sensing amplifiers and the 256 first sensing amplifiers (because the first alignment circuit 1011 can write 128 bits of the 256-bit metadata to the memory block of the specific block group through the 128 connected second sensing amplifiers and the 128 first sensing amplifiers corresponding to a memory block, and the first alignment circuit 1011 can write another 128 bits of the 256-bit metadata to the other memory block of the specific block group through the other 128 connected second sensing amplifiers and the other 128 first sensing amplifiers corresponding to another memory block). In other words, as shown in Table 3, based on the 128 first sensing amplifiers, the data width of each memory block in the specific block group is limited to 128. Furthermore, since memory blocks B0 and B1 are included in block group BG0, the data width of memory 901 (i.e., the width of the input / output data bus of memory 901) is equal to the sum of the data widths of all memory blocks in the specific block group (i.e., 128 + 128 = 256). And compared to Figure 8, the available memory blocks will be reduced by half.

[0050] Because there is no need to connect traditional parallel-to-serial and serial-to-parallel circuits, and the first sensing amplifier can be directly connected to the first alignment circuit, the data width of memory 101 is equal to the write line (or read line) data width of the dual data rate physical layer interface bus (DFI bus) of physical layer 103, and also equal to the data width of controller 105 and the write data bus (or read data bus) data width of the advanced expandable interface bus. From another perspective, after confirming the write data bus (or read data bus) data width of the advanced expandable interface bus in the application environment of memory 101 and logic circuit 102, by setting control signals SB0-SB4, the data width of memory 101 can be made equal to the write line (or read line) data width of the dual data rate physical layer interface bus (DFI bus) of physical layer 103, and also equal to the data width of controller 105 and the write data bus (or read data bus) data width of the advanced expandable interface bus. Furthermore, the other data widths of each memory block of memory 901 corresponding to control signals SB0-SB4 (0 / 1 / 0 / 0 / 0), (0 / 1 / 0 / 0 / 1), (0 / 1 / 0 / 1 / 1), and (0 / 0 / 0 / 0 / 0) can be found in Table 3, and therefore will not be repeated here. Moreover, the present invention is not limited to the configuration of control signals SB0-SB4 shown in FIG9. SB4 / SB3 / SB2 / SB1 / SB0 The data width of the write data bus (or read data bus) of the advanced scalable interface bus. Data width of memory 901 Data width of each memory block 0 / 1 / 0 / 0 / 0 1024 1024 512 0 / 1 / 0 / 0 / 1 512 512 256 0 / 1 / 0 / 1 / 0 256 256 128 0 / 1 / 0 / 1 / 1 128 128 64 0 / 0 / 0 / 0 / 0 64 64 32 Table 3

[0051] Next, please refer to FIG10. FIG10 is a schematic diagram of connecting a chip 1002 to another chip 1004 using a multilayer structure in a substrate 1006, as disclosed in another embodiment of the present invention. The chip 1002 can refer to the logic circuit 102 shown in FIG7, the chip 1004 can refer to the memory 101 shown in FIG7, and both the chip 1002 and the chip 1004 have micro-bumps or pillars of any form (e.g., copper pillars) on their bottom. As shown in Figure 10(a), because the data input / output bus width of the memory (chip 1004) is relatively large, or the number of microbumps or pillars is relatively large, when the first layer track 1008 in the substrate 1006 is insufficient to complete all the connections between the chip 1002 and the chip 1004 due to the small size of the substrate 1006, for example, a second layer track 1010, a third layer track 1012, and a fourth layer track 1014 in the substrate 1006 can be additionally provided to complete all the connections between the chip 1002 and the chip 1004. As shown in Figure 10(a), the first layer track 1008, the second layer track 1010, the third layer track 1012, and the fourth layer track 1014 are located at different depths in the substrate 1006. Furthermore, the present invention is not limited to using the first layer track 1008, the second layer track 1010, the third layer track 1012, and the fourth layer track 1014 to complete all the connections between the chip 1002 and the chip 1004. In other words, the present invention can utilize more than two layers of tracks to complete all connections between wafer 1002 and wafer 1004. In addition, as shown in FIG10(a), the microbumps or pillars under wafer 1002 can be arranged into multiple regions (e.g., region 1, region 2, region 3, region 4) according to the size of substrate 106 and the number of microbumps (or pillars). The microbumps in region 1 are the first ones close to wafer 1004, and the microbumps in region 1 can use the first layer of tracks 1008 to complete the connection between wafer 1002 and wafer 1004. As shown in FIG10(b), the microbumps in region 1 can be arranged into columns 1 and 2 (or more than two columns). Similarly, the microbumps in region 2 are the second ones closest to wafer 1004, and the microbumps in region 2 will use the second layer track 1010 to complete the connection between wafer 1002 and wafer 1004. As shown in FIG10(b), the microbumps in region 2 can be arranged in columns 3 and 4 (or more than two columns). In addition, the arrangement of the microbumps in region 3 and the microbumps in region 4 can refer to the arrangement of the microbumps in region 1 and region 2, so it will not be described again here.Similarly, as shown in Figures 10(a) and 10(b), the microbumps under the wafer 1004 can also be arranged into multiple regions (e.g., region 1, region 2, region 3, region 4) according to the size of the substrate 106 and the number of microbumps (or pillars). The arrangement of the microbumps under the wafer 1004 can refer to the arrangement of the microbumps under the wafer 1002, so it will not be described again here.

[0052] Additionally, as shown in FIG11, via 1016 connects the second depth track (e.g., the portion of the second layer track 1010 in the second depth, the upward extension portion of the third layer track 1012 in the second depth, and / or the upward extension portion of the fourth layer track 1014 in the second depth) to the first depth track (e.g., the first layer track 1008), and via 1018 connects the third depth track (e.g., the portion of the third layer track 1012 in the third depth, and / or the upward extension portion of the fourth layer track 1014 in the third depth) to the second depth track, and via 1020 connects the fourth depth track (e.g., the fourth layer track 1014) to the third depth track. Furthermore, the position of the upward extension portion of the third layer track 1012 is outside the position of the upward extension portion of the second layer track 1010. If this were not done, as shown in Figure 12, if the third-layer track 1012 instead of the second-layer track 1010 were used to connect the microbumps of region 2 of wafer 1002 and region 2 of wafer 1004, the second-layer track 1010, which is traversed by the third-layer track 1012, might become unusable (as indicated by the cross symbol in Figure 12), thus reducing the number of usable tracks in the second-layer track 1010. Similarly, the upward extension of the fourth-layer track 1014 is located outside the upward extension of the third-layer track 1012. If this were not done, as shown in Figure 13, the third-layer track 1012, which is traversed by the fourth-layer track 1014, might become unusable (as indicated by the cross symbol in Figure 13), thus reducing the number of usable tracks in the third-layer track 1012.

[0053] Next, the present invention will introduce (but is not limited to) the parameters of two design embodiments, wherein design embodiment 1 uses four layers of tracks (first layer track, second layer track, third layer track, fourth layer track) and design embodiment 2 uses nine layers of tracks (first layer track, second layer track, third layer track, fourth layer track, fifth layer track, sixth layer track, seventh layer track, eighth layer track, ninth layer track).

[0054] Design Implementation Example 1

[0055] Table 4 illustrates the parameters of design embodiment 1, where "ubump pitch1" represents the pitch of the microbumps in zone 1, "line pitch1" represents the pitch between the first layer tracks, "ubump pitch2" represents the pitch of the microbumps in zones 2, 3, and 4, and "line pitch2" represents the pitch between the second layer tracks, the third layer tracks, and the fourth layer tracks. Additionally, "via12 pitch" represents the pitch of the through-holes connecting the first depth track and the second depth track, "via23 pitch" represents the pitch of the through-holes connecting the second depth track and the third depth track, and "via34 pitch" represents the pitch of the through-holes connecting the third depth track and the fourth depth track. Width (um) ubump pitch1 85+8 line pitch1 6+8 via12 pitch 85+8 ubump pitch2 85+12 line pitch2 12+12 via23 pitch (via34 pitch) 85+12 Table 4

[0056] The following is Table 5, in which design embodiment 1 has 407 micro-bumps, the via pitch corresponding to the first layer track and the second layer track is via12, the via pitch corresponding to the third layer track is via23, and the via pitch corresponding to the fourth layer track is via34: First level track Second-level track Third-level track Fourth-level track ubump pitch(um) 85+8 (Area 1) 85+12 (District 2) 85+12 (District 3) 85+12 (District 4) via pitch(um) 85+8 (via12) 85+12 (via23) 85+12 (via34) line pitch(um) 6+8 12+12 12+12 12+12 number of lines 119 96 96 96 Table 5

[0057] Design Implementation Example 2

[0058] Table 6 illustrates the parameters of Design Embodiment 2, which has 400 microbumps and nine layers of tracks in the substrate. Furthermore, the number of tracks in each of the first to eighth layers is 46, and the number of tracks in the ninth layer is 32. The following is Table 6, where "ubump pitch" represents the spacing between the microbumps in zones 1 to 9, "line pitch" represents the spacing between each track in the first to ninth layers, and "via pitch" represents the spacing between via12, via23, via34, via45, via56, via67, via78, and via89 (where via12 connects the first and second depth tracks, via23 connects the second and third depth tracks, via34 connects the third and fourth depth tracks, via45 connects the fourth and fifth depth tracks, via56 connects the fifth and sixth depth tracks, via67 connects the sixth and seventh depth tracks, via78 connects the seventh and eighth depth tracks, and via89 connects the eighth and ninth depth tracks): Width (um) ubump pitch 85+25 line pitch 25+25 via pitch 85+25 Table 6

[0059] In addition, the present invention can also improve the refresh mechanism of conventional memory. Please refer to FIG14 for a conventional dynamic random-access memory (DRAM) and its controller, wherein FIG14(a) illustrates a logic circuit 1402 and a dynamic random-access memory (e.g., DDR3~DDR5 or low-power DDR3~DDR5) 1404, and FIG14(b) illustrates the timing diagram of the access instruction or read / write instruction corresponding to the dynamic random-access memory 1404 in the prior art (for simplification, the read / write instruction includes an activation instruction-read / write instruction-precharge instruction), read / write time 1, refresh instruction RFC, another read / write instruction and read / write time 2. As shown in Figure 14(a), the refresh counter 14026 in the dynamic random access memory controller 14022 of the logic circuit 1402 counts the dynamic random access memory refresh interval tREFI according to the number of clock cycles, and issues a refresh instruction RFC when the number of clock cycles reaches the target according to the dynamic random access memory specification. The refresh instruction RFC is transmitted to the dynamic random access memory 1404 through the physical layer 14024. For example, when 1 clock cycle = 1 ns, tREFI = 4 μs means every 4000 clock cycles (4 μs) or tREFI = 8 μs means every 8000 clock cycles (8 μs).

[0060] Additionally, as shown in Figure 14(a), when a refresh instruction RFC is received, the refresh counter 14042 in the dynamic random access memory 1404 sends out the address of the next word line for which a refresh operation needs to be performed. When the refresh instruction RFC is issued, the refresh counter 14042 also needs to count the dynamic random access memory refresh interval tREFI according to the clock count, and according to the dynamic random access memory specification, when the clock count reaches the target, an internal refresh instruction is issued. For example, when 1 clock = 1 ns, tREFI = 4 μs means every 4000 clocks (4 μs) or tREFI = 8 μs means every 8000 clocks (8 μs).

[0061] The refresh counter 14042 counts the digital line address in automatic refresh mode or self-refresh mode, and also counts the dynamic random access memory refresh interval in self-refresh mode. On the other hand, in automatic refresh mode or self-refresh mode, the refresh counter 14026 in the dynamic random access memory controller 14022 does not count the digital line address. However, the refresh counter 14026 in the dynamic random access memory controller 14022 can count the dynamic random access memory refresh interval in automatic refresh mode.

[0062] Furthermore, as shown in the timing diagram of a conventional dynamic random access memory (DRAM) in Figure 14(b), after a read / write instruction is issued, read / write time 1 (corresponding to the read / write instruction) is the time used to read data from DRAM 1404 or write data to DRAM 1404. Afterwards, there is a period of idle time id1 between read / write time 1 and refresh instruction RFC. Then, after receiving refresh instruction RFC, time tRFC is used to refresh DRAM 1404, and there is an idle time id2 after time tRFC and before the next read / write instruction. Afterwards, read / write time 2 (corresponding to the next read / write instruction) is the time used to read data from DRAM 1404 again or write data to DRAM 1404. Thus, there will be a time interval (id1 + tRFC + id2) between read / write time 1 and read / write time 2.

[0063] Next, please refer to Figure 15 for a conventional pseudo static random-access memory (pseudo SRAM) and its controller, wherein Figure 15(a) illustrates a pseudo static random-access memory controller 1502 and a pseudo static random-access memory 1504, and Figure 15(b) illustrates a timing diagram of the read / write instructions (for simplicity, the read / write instructions include activation instruction-read / write instruction-precharge instruction), time trow1, read / write time 1, another read / write instruction, time trow1, and read / write time 2 corresponding to the pseudo static random-access memory 1504 in the prior art. As shown in Figure 15(a), it is worth noting that the difference between the dynamic random access memory controller 14022 and the virtual static random access memory controller 1502 is that the virtual static random access memory controller 1502 does not have a refresh counter. Therefore, the virtual static random access memory controller 1502 does not need to issue any refresh instructions to the virtual static random access memory 1504. When the virtual static random access memory 1504 is powered on, the refresh counter 15042 in the virtual static random access memory 1504 starts counting and sends internal refresh instructions and the address of the next word line that needs to be refreshed internally to prevent any memory cell in the virtual static random access memory 1504 from failing. However, as shown in Figure 15(b), when a read / write instruction is received from the virtual static random access memory controller 1502, assuming that a refresh has just occurred before the virtual static random access memory 1504 executes the read / write instruction, the virtual static random access memory 1504 needs to wait for time trow1, which will result in additional read / write latency and a longer read / write cycle time. There is an idle time id2 before receiving the next read / write instruction from the virtual static random access memory controller 1502, and another time trow1 is needed before executing the next read / write instruction.

[0064] Next, please refer to Figure 16. Figure 16(a) is a schematic diagram illustrating a logic circuit 1602 and a dynamic random access memory (e.g., DDR2, DDR3, DDR4, DDR5 or low-power DDR2, DDR3, DDR4) 1604 according to another embodiment of the present invention, and Figure 16(b) is a timing diagram illustrating the read / write instructions 1~3, read / write times 1~3, and signals on the additional output pin BUSY of the dynamic random access memory 1604 corresponding to the dynamic random access memory 1604. As shown in Figure 16(a), there is no refresh counter in the dynamic random access memory controller 16022 of the logic circuit 1602, so the dynamic random access memory controller 16022 will not issue refresh instructions to the dynamic random access memory 1604. However, a refresh counter 16042 exists within dynamic random access memory 1604, so dynamic random access memory 1604 can calculate the time to automatically perform a refresh based on the number of clock cycles (clks) counted by refresh counter 16042. It is worth noting that the difference between dynamic random access memory 1404 and dynamic random access memory 1604 is that dynamic random access memory 1604 has an additional output pin BUSY. Therefore, for example, during the refresh of dynamic random access memory 1604 (or during a refresh operation performed by dynamic random access memory 1604), the signal on the additional output pin BUSY is active (e.g., the signal on the additional output pin BUSY is high or "1"), and when dynamic random access memory 1604 is not performing a refresh operation, the signal on the additional output pin BUSY is inactive (e.g., the signal on the additional output pin BUSY is low or "0"). In addition, apart from the additional output pin BUSY, any configuration that provides a handshake method between the dynamic random access memory (DRAM) and the logic circuit 1602 still falls within the scope of this invention. Furthermore, because the DRAM 1604 can perform automatic refresh, the DRAM controller 16022 of the logic circuit 1602 no longer needs to control the refresh of the DRAM 1604.

[0065] Therefore, as shown in FIG16(b), after the dynamic random access memory controller 16022 issues read / write command 1, read / write time 1 (corresponding to read / write command 1) is the time used to read data from dynamic random access memory 1604 or write data to dynamic random access memory 1604. At this time, since dynamic random access memory 1604 does not need to perform refresh operation, the signal on the additional output pin BUSY is at a low level, and dynamic random access memory controller 16022 can issue the next read / write command 2 to dynamic random access memory 1604 according to the state (low level) of the signal on the additional output pin BUSY. Then, read / write time 2 (corresponding to read / write command 2) is also the time used to read data from dynamic random access memory 1604 or write data to dynamic random access memory 1604. As shown in Figure 16(b), during read / write time 2, when dynamic random access memory 1604 needs to be refreshed, the signal on the additional output pin BUSY goes high, causing the dynamic random access memory controller 16022 to store the next read / write instruction 3 into an additional register (e.g., a first-in-first-out (FIFO) data register, not shown in Figure 16(a)) within the logic circuit 1602 and to issue a no-operation (NOP) signal while the signal on the additional output pin BUSY is high. Then, as shown in Figure 16(b), when the signal on the additional output pin BUSY goes low again, the dynamic random access memory controller 16022 can issue the previously stored read / write instruction 3 to the dynamic random access memory 1604. Read / write time 3 (corresponding to read / write instruction 3) is also the time used to read data from or write data to the dynamic random access memory 1604. Thus, the dynamic random access memory 1604 will no longer require the refresh time tRFC required after the dynamic random access memory 1404 receives the refresh instruction RFC from the dynamic random access memory controller 14022, as shown in FIG14(b).

[0066] Next, please refer to Figure 17. Figure 17(a) is a schematic diagram illustrating a virtual static random access memory (VRAM) controller 1702 and a VRAM (or other memory with dynamic random access memory units) 1704 according to another embodiment of the present invention. Figure 17(b) is a timing diagram illustrating the read / write instructions 1-4, read / write times 1-4, and signals on the additional output pin BUSY of the VRAM 1704 corresponding to the VRAM 1704. Similar to Figure 16(a), as shown in Figure 17(a), because the refresh counter 17042 is in the VRAM 1704 and there is no refresh counter in the VRAM controller 1702, the VRAM 1704 can automatically perform refresh according to the clock count (clks) counted by the refresh counter 17042. In addition, similar to the Dynamic Random Access Memory 1604, the Virtual Static Random Access Memory 1704 also has an additional output pin BUSY to notify the Virtual Static Random Access Memory Controller 1702 whether it is in a refresh operation. Furthermore, because the Virtual Static Random Access Memory 1704 can automatically perform refresh operations and notify the Virtual Static Random Access Memory Controller 1702 of its refresh status via the additional output pin BUSY, the Virtual Static Random Access Memory 1704 does not need to wait for the time trow1 shown in Figure 15(b), thus avoiding additional read / write latency and longer read / write cycle times.

[0067] As shown in Figure 17(b), after the Virtual Static Random Access Memory (VRAM) controller 1702 issues a read / write instruction 1, the read / write time 1 (corresponding to read / write instruction 1) is the time used to read data from the VRAM 1704 or write data to the VRAM 1704. No time trow1 is required before read / write time 1. At this time, because the VRAM 1704 does not need to perform a refresh operation, the signal on the additional output pin BUSY is at a low level, and the VRAM controller 1702 can issue the next read / write instruction 2 to the VRAM 1704 based on the state (low level) of the signal on the additional output pin BUSY. Then, read / write time 2 (corresponding to read / write instruction 2) is also the time used to read data from the VRAM 1704 or write data to the VRAM 1704. No time trow1 is required before read / write time 2 either. Then, while the signal on the additional output pin BUSY is still low, the virtual static random access memory controller 1702 can issue the next read / write instruction 3 to the virtual static random access memory 1704. The read / write time 3 (corresponding to the read / write instruction 3) is the time for reading data from or writing data to the virtual static random access memory 1704. As shown in Figure 17(b), during the read / write time 3, because the virtual static random access memory 1704 needs to be refreshed, the signal on the additional output pin BUSY becomes high, causing the virtual static random access memory controller 1702 to store the next read / write instruction 4 to an additional register (e.g., a first-in-first-out data register) and issue a no-operation (NOP) signal while the signal on the additional output pin BUSY is high. Subsequently, as shown in Figure 17(b), when the signal on the additional output pin BUSY goes low again, the virtual static random access memory controller 1702 can issue the previously stored read / write instruction 4 to the virtual static random access memory 1704, and the read / write time 4 (corresponding to the read / write instruction 4) is also the time used to read data from the virtual static random access memory 1704 or write data to the virtual static random access memory 1704.

[0068] In summary, compared to the prior art, the multi-layer structure connecting memory and logic circuits can be applied to a small substrate to effectively utilize its area, and the signals on the additional output pins used to notify the refresh status can effectively reduce read / write latency during the refresh of dynamic random access memory. The above description is merely a preferred embodiment of the present invention, and all equivalent variations and modifications made within the scope of the claims of this invention should be considered within the scope of this invention. [Simplified Explanation of the Diagram]

[0025] Figure 1 is a schematic diagram of a memory system disclosed in the prior art. Figures 2A and 2B are timing diagrams of logic circuits writing data into memory. Figure 3 is a schematic diagram of a memory system disclosed in the first embodiment of the present invention. Figure 4 is a schematic diagram of two transceiver structures disclosed in another embodiment of the present invention. Figure 5 is a timing diagram used to compare a conventional memory system and a memory system of the present invention. Figure 6 is a schematic diagram illustrating that the area of ​​the memory in the present invention is smaller than that of a conventional memory, and that the area of ​​the physical layer in the present invention is also smaller than that of the physical layer in a conventional logic circuit. Figure 7 is a schematic diagram of the data width of the memory disclosed in another embodiment of the present invention changing according to a control signal. Figures 8 and 9 are schematic diagrams of memory disclosed in different embodiments of the present invention. Figure 10 is a schematic diagram of connecting a chip to another chip using a multilayer structure in a substrate, disclosed in another embodiment of the present invention. Figure 11 is a schematic diagram illustrating the presence of vias between two adjacent layer tracks and that different layer tracks do not intersect each other. Figures 12 and 13 are schematic diagrams illustrating that different layer tracks intersect each other. Figure 14 is a timing diagram illustrating the logic circuit and dynamic random access memory (DRAM) in the prior art, as well as the corresponding read / write instructions, read / write times, idle times, and auto-refresh instructions for DRAM in the prior art. Figure 15 is a timing diagram illustrating the virtual static random access memory (VRAM) controller and VRAM in the prior art, as well as the corresponding read / write instructions, read / write times, idle times, and time trow for VRAM in the prior art. Figure 16 is a timing diagram illustrating the logic circuit and DRAM in another embodiment of the present invention, as well as the corresponding read / write instructions, read / write times, and signals on the additional output pins of the DRAM. Figure 17 is a timing diagram illustrating the VRAM controller and VRAM in another embodiment of the present invention, as well as the corresponding read / write instructions, read / write times, and signals on the additional output pins of the VRAM.

Claims

1. A memory controller for use in a dynamic random-access memory (DRAM) system, the DRAM system including a system bus interface and a memory chip, the memory chip including an input / output bus, the memory controller including: a control circuit coupled to the system bus interface; and a physical layer circuit coupled to the control circuit and configured to receive a plurality of first data in parallel from the input / output bus of the memory chip; wherein the physical layer circuit of the memory controller does not have parallel-to-serial circuitry or serial-to-parallel circuitry, the memory chip sends a handshake signal to the memory controller to selectively notify the memory controller whether the memory chip has not performed a refresh operation, the memory controller does not have a refresh counter, and the memory controller is located outside the memory chip.

2. The memory controller as claimed in claim 1, wherein the physical layer circuitry is further configured to output a plurality of second data to the input / output bus of the memory chip in parallel.

3. The memory controller as claimed in claim 1, wherein the handshake signal is activated when the memory chip performs the refresh operation, and the handshake signal is deactivated when the memory chip does not perform the refresh operation.

4. The memory controller as claimed in claim 3, wherein when the handshake signal is activated, the memory controller generates an access instruction to read data from the memory chip or write data to the memory chip.

5. The memory controller as claimed in claim 4, wherein the memory controller sends the access instruction to the memory chip after the handshake signal is deactivated.

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