Semiconductor structure

Abstract

A semiconductor structure includes a substrate, an epitaxial layer, a first well region, a second well region, a first doped region, a second doped region, and a first gate structure. The substrate has a first conductivity type. The epitaxial layer has a first conductivity type and is disposed on the substrate. The first well region has a second conductivity type and is disposed on the epitaxial layer. The second well region has a first conductivity type and is disposed on the first well region. The first doped region has a second conductivity type and is disposed within the second well region. The second doped region has a second conductivity type and is disposed within the second well region. The first gate structure is disposed on the second well region. The doping concentration of the substrate is higher than the doping concentration of the second well region. The first doped region, the first gate structure, and the second doped region constitute a metal-oxide-semiconductor transistor.

Claims

1. A semiconductor structure, comprising: A substrate having a first conductivity type; An epitaxial layer having the first conductivity type is disposed on the substrate; A first well region having a second conductivity type is disposed on the epitaxial layer; a second well region having the first conductivity type is disposed on the first well region; a first doped region having the second conductivity type is disposed in the second well region; a second doped region having the second conductivity type is disposed in the second well region. A first gate structure is disposed on the second well region, wherein: the doping concentration of the substrate is higher than the doping concentration of the second well region, the first doped region, the first gate structure and the second doped region constitute a first metal-oxide-semiconductor transistor, and the second doped region is electrically connected to the first gate structure.

2. The semiconductor structure as described in claim 1, wherein the first well region is electrically floating.

3. The semiconductor structure as described in claim 2, wherein the first conductivity type is P-type and the second conductivity type is N-type.

4. The semiconductor structure as described in claim 3 further includes: A first protective structure is provided to prevent the surface metal layer of the first doped region from contacting the first gate structure.

5. The semiconductor structure as described in claim 3, further comprising: A third doped region having the first conductivity type is disposed in the second well region; wherein: the doping concentration of the third doped region is higher than the doping concentration of the second well region, the third doped region serves as the substrate electrode of the first metal-oxide-semiconductor transistor, the first doped region serves as the drain electrode of the first metal-oxide-semiconductor transistor, the second doped region serves as the source electrode of the first metal-oxide-semiconductor transistor, and the first gate structure serves as the gate electrode of the first metal-oxide-semiconductor transistor.

6. The semiconductor structure as described in claim 5, further comprising: An internal interconnect structure electrically connects the first gate structure, the second doped region, and the third doped region.

7. The semiconductor structure as described in claim 5 further includes: A fourth doped region having the second conductivity type is disposed between the second well region and the first doped region; And a fifth doped region having the second conductivity type and disposed between the second well region and the second doped region; wherein the doping concentration of the fourth doped region is less than the doping concentration of the first doped region, and the doping concentration of the fifth doped region is less than the doping concentration of the second doped region.

8. The semiconductor structure as claimed in claim 7, wherein the first well region is located between the second well region and the epitaxial layer.

9. The semiconductor structure as claimed in claim 7, wherein the first gate structure has a first distance between itself and the first well region, the second well region has a second distance between itself and the epitaxial layer, and the first well region has a third distance between itself and the substrate, wherein the sum of the first distance, the second distance and the third distance is less than 4 micrometers.

10. The semiconductor structure as described in claim 4, further comprising: A sixth doped region, having the second conductivity type, is located in the second well region; A second gate structure is installed in the second well area; And a second protective structure to prevent the surface metal layer of the sixth doped region from contacting the second gate structure, wherein the second doped region, the second gate structure and the sixth doped region constitute a second metal-oxide-semiconductor transistor.

11. A semiconductor structure, comprising: A substrate having a first conductivity type; A core circuit is coupled between a first input / output pad and a second input / output pad and is disposed on the substrate; The device also includes a metal-oxide-semiconductor transistor disposed on the substrate, comprising: a first well region having a second conductivity type and disposed on the substrate; a second well region having the first conductivity type and disposed on the first well region; a drain region disposed in the second well region and electrically connected to the first input / output pad; a source region disposed in the second well region and electrically connected to the second input / output pad; and a gate structure disposed on the second well region and electrically connected to the second input / output pad, wherein the doping concentration of the substrate is higher than the doping concentration of the second well region.

12. The semiconductor structure as described in claim 11, wherein: When an electrostatic discharge (ESD) event occurs at the first input / output pad and the second input / output pad receives a ground voltage, the metal-oxide-semiconductor (MOSFET) transistor is turned on, and an ESD current flows from the first input / output pad, through the MOSFET, and into the second input / output pad. When the ESD event does not occur, the MOSFET is not turned on, and the core circuit operates according to the voltages of the first and second input / output pads.

13. The semiconductor structure as claimed in claim 12, wherein the electrostatic discharge current flows from the first input / output pad, through the drain region, the second well region, and the source region, into the second input / output pad.

14. The semiconductor structure as described in claim 12, further comprising: An epitaxial layer having the first conductivity type is disposed between the substrate and the first well region.

15. The semiconductor structure as claimed in claim 14, wherein the gate structure has a first distance from the first well region, the second well region has a second distance from the epitaxial layer, and the first well region has a third distance from the substrate, the sum of the first distance, the second distance and the third distance being less than 4 micrometers.

16. The semiconductor structure as described in claim 15, wherein the first well region is electrically floating.

17. The semiconductor structure as described in claim 16, wherein the first conductivity type is P-type and the second conductivity type is N-type.

18. The semiconductor structure as described in claim 17, further comprising: A protective structure is provided to prevent the surface metal layer of the drain region from contacting the gate structure.

19. The semiconductor structure as described in claim 18, further comprising: A substrate region having the first conductivity type is disposed in the second well region; wherein: the doping concentration of the substrate region is higher than the doping concentration of the second well region and similar to the doping concentration of the substrate.

20. The semiconductor structure as described in claim 19, further comprising: A first lightly doped region having the second conductivity type is disposed between the second well region and the drain region; And a second lightly doped region having the second conductivity type and disposed between the second well region and the source region; wherein the doping concentration of the first lightly doped region is less than the doping concentration of the drain region, and the doping concentration of the second lightly doped region is less than the doping concentration of the source region.

Images