Semiconductor devices

Abstract

A semiconductor device has a substrate. A first semiconductor die and a second semiconductor die are disposed on the substrate. A metal rod has an EMI absorbing material disposed on the metal rod. The metal rod is disposed on the substrate between the first semiconductor die and the second semiconductor die. An encapsulation is deposited on the first semiconductor die, the second semiconductor die, and the metal rod. A shielding layer is formed on the encapsulation.

Description

[Technical Field]

[0001] The present invention generally relates to a semiconductor device, and more particularly to a semiconductor device and a method for absorbing electromagnetic interference (EMI) metal rods. [Previous Technology]

[0002] Semiconductor devices are commonly found in modern electronic products. They perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electricity, and generating visual images for television displays. Semiconductor devices are found in communications, power conversion, networking, computers, entertainment, and consumer products. They are also found in military applications, aerospace, automotive, industrial controllers, and office equipment.

[0003] Semiconductor devices are often susceptible to electromagnetic interference (EMI), radio frequency interference (RFI), harmonic distortion, or other inter-device interference (such as capacitive, inductive, or conductive coupling, also known as crosstalk) that can interfere with their operation. High-speed analog circuits, such as radio frequency (RF) filters, or digital circuits also generate interference.

[0004] EMI shielding is provided to prevent in-package interference by placing conductive barriers between adjacent components. Conductive barriers are typically coupled to ground, causing EMI radiation between adjacent components to be shunted to ground. However, conductive barriers reflect a significant portion of EMI radiation rather than absorbing it. Reflected signals can cause interference within RF-emitting components. Therefore, an improved device and method for in-package EMI shielding is needed. [Summary of the Invention]

[0005] One aspect of the present invention is a method for manufacturing a semiconductor device, comprising: providing a substrate; disposing a first semiconductor die and a second semiconductor die on the substrate; providing a metal rod; disposing an EMI absorbing material on the metal rod; disposing the metal rod on the substrate between the first semiconductor die and the second semiconductor die; depositing an encapsulant on the first semiconductor die, the second semiconductor die and the metal rod; and forming a shielding layer on the encapsulant.

[0006] The method of the present invention further includes forming a groove in the encapsulation before forming the shielding layer.

[0007] The method of the present invention further includes forming a protective layer over the EMI absorbing material.

[0008] The method of the present invention further includes forming a wetting layer between the metal rod and the EMI absorbing material.

[0009] In the method described in this invention, the EMI absorbing material comprises nickel.

[0010] In the method as described in the present invention, the EMI absorbing material includes a polymer substrate and a magnetic metal sheet disposed in the polymer substrate.

[0011] Another aspect of the present invention is a method of manufacturing a semiconductor device, comprising: providing a substrate; disposing a first electronic component and a second electronic component on the substrate; providing a metal rod; disposing an EMI absorbing material on the metal rod to form an EMI absorbing metal rod; and disposing the metal rod on the substrate between the first electronic component and the second electronic component.

[0012] The method as described in another embodiment of the present invention further includes forming a shielding layer over the first electronic component, the second electronic component and the EMI absorbing metal rod.

[0013] In another embodiment of the invention, the shielding layer is in solid contact with the EMI absorbing metal rod.

[0014] The method as described in another embodiment of the present invention further includes forming a protective layer over the EMI absorbing material.

[0015] Another aspect of the present invention is a semiconductor device comprising: a substrate; a first electronic component and a second electronic component disposed above the substrate; a metal rod disposed above the substrate between the first electronic component and the second electronic component; an EMI absorbing material disposed above the metal rod to form an EMI absorbing metal rod; and a shielding layer formed above the first electronic component, the second electronic component and the EMI absorbing metal rod.

[0016] In another embodiment of the semiconductor device, the shielding layer is in solid contact with the EMI absorbing metal rod.

[0017] The semiconductor device as described in another embodiment of the present invention further includes a protective layer formed over the EMI absorbing material.

[0018] The semiconductor device as described in another embodiment of the present invention further includes a wetting layer formed between the metal rod and the EMI absorbing material.

[0019] In another embodiment of the semiconductor device, both the protective layer and the wetting layer comprise stainless steel.

Implementation Method

[0021] The invention is described in the following description with reference to the accompanying drawings in one or more specific examples, in which similar designations denote the same or similar elements. Although the invention is described according to the best mode for achieving the objectives of the invention, it will be understood by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents that may include, as defined by the appended claims and their equivalents supported by the following disclosure and drawings, within the spirit and scope of the invention. As used herein, the term "semiconductor die" refers to both the singular and plural forms of the word, and therefore may refer to both a single semiconductor device and multiple semiconductor devices.

[0022] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming a plurality of dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, establish a relationship between the voltage and current required to perform the circuit function.

[0023] Back-end manufacturing refers to the process of dicing or singulating finished wafers into individual semiconductor dies and encapsulating these dies for structural support, electrical interconnection, and environmental isolation. To singulate semiconductor dies, the wafer is scribed and broken along non-functional areas known as scribe lines or kerfs. The wafer is singulated using a laser cutting tool or saw blade. After singulation, the individual semiconductor dies are mounted onto a package substrate, which includes pins or contact pads for interconnection with other system components. Contact pads formed on top of the semiconductor dies are then connected to contact pads within the package. Electrical connections can be made with conductive layers, bumps, column bumps, conductive paste, bonding wires, or other suitable interconnect structures. Encapsulation or other molding compounds are deposited on top of the package to provide physical support and electrical isolation. The finished package is then inserted into an electrical system, enabling the functionality of the semiconductor device to be used with other system components.

[0024] FIG1a illustrates a semiconductor wafer 100 having a substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk semiconductor materials. A plurality of semiconductor dies or components 104 are formed on the wafer 100 separated by non-active inter-die wafer regions or saw tracks 106 as described above. The saw tracks 106 provide dicing areas to monolithize the semiconductor wafer 100 into individual semiconductor dies 104. In one specific example, the semiconductor wafer 100 has a width or diameter of 100 to 450 millimeters (mm).

[0025] FIG1b shows a cross-sectional view of a portion of a semiconductor wafer 100. Each semiconductor die 104 has a back or non-active surface 108 and an active surface 110, which contain analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers. These active devices, passive devices, conductive layers, and dielectric layers are formed within or above the die and electrically interconnected according to the electrical design and function of the die. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuitry, such as a digital signal processor (DSP), ASIC, MEMS memory, or other signal processing circuitry. The semiconductor die 104 may also contain integrated passive devices (IPDs) such as inductors, capacitors, and resistors for RF signal processing. The back surface 108 of the semiconductor wafer 100 can be subjected to a back grinding operation, whichever is appropriate, by mechanical grinding or etching processes to remove a portion of the substrate material 102 and reduce the thickness of the semiconductor wafer 100 and the semiconductor die 104.

[0026] The conductive layer 112 is formed on the active surface 110 using physical vapor deposition (PVD), chemical vapor deposition (CVD), electroplating, electroless plating, or other suitable metal deposition processes. The conductive layer 112 includes one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 112 functions as a contact pad for electrical connections to circuits on the active surface 110.

[0027] The conductive layer 112 may be formed as contact pads arranged side-by-side with respect to the edge of the semiconductor die 104 at a first distance, as shown in FIG1b. Alternatively, the conductive layer 112 may be formed as contact pads offset in a plurality of columns such that a first column of contact pads is arranged at a first distance from the edge of the die, and a second column of contact pads alternates with the first column arranged at a second distance from the edge of the die. The conductive layer 112 represents the final conductive layer formed above the semiconductor die 104 having contact pads for subsequent electrical interconnection to a larger system. However, one or more intermediate conductive and insulating layers may be present between the actual semiconductor device formed on the active surface 110 and the contact pads 112 for signal routing.

[0028] Conductive bump material is deposited on the conductive layer 112 using evaporation, electrolytic plating, electroless plating, drop ball, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, or combinations thereof, with a flux solution selected as appropriate. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer 112 using a suitable attachment or bonding process. The bump material can be reflowed to form conductive balls or bumps 114 by heating the material above its melting point. In one specific example, the conductive bumps 114 are formed on top of an under-bump metallization (UBM) having a wetting layer, a barrier layer, and an adhesive layer. The conductive bumps 114 can also be compression bonded or thermocompressed to the conductive layer 112. Conductive bump 114 represents a type of interconnect structure that can be formed above conductive layer 112 for electrical connection to a substrate. The interconnect structure may also use bonding wires, conductive paste, column bumps, micro bumps, conductive pillars or other electrical interconnects.

[0029] In Figure 1c, the semiconductor wafer 100 is monolithically divided into individual semiconductor dies 104 by a saw blade or laser cutting tool 118 via sawing kerf 106. The individual semiconductor dies 104 can be detected and electrically tested for identification after monolithization of known-good dies (KGD).

[0030] Figures 2a to 2g illustrate the use of multiple semiconductor dies 104 and EMI-absorbing metal wafers or rods between the semiconductor dies for shielding against electromagnetic interference (EMI) within the package to form a system-in-package (SiP) device 150.

[0031] FIG2a shows a partial cross-sectional view of substrate 152. Although only a single substrate 152 is shown, hundreds or thousands of substrates are typically processed on a common carrier using the same steps described herein for a single unit but performed overall. Substrate 152 may also begin as a single larger substrate of multiple units that are monolithized from each other during or after the manufacturing process.

[0032] The substrate 152 includes one or more insulating layers 154 interleaved with one or more conductive layers 156. In one specific embodiment, the insulating layer 154 is a core insulating board, wherein the conductive layers 156 are patterned above, for example, the top and bottom surfaces of a copper-clad laminate substrate. The conductive layers 156 also include conductive vias electrically coupled through the insulating layers 154. The substrate 152 may include any number of conductive and insulating layers interleaved above each other. A solder mask or passivation layer may be formed above either side of the substrate 152. In other specific embodiments, any suitable type of substrate or lead frame is used for the substrate 152.

[0033] The SiP device 150 in FIG2a has semiconductor dies 104A and 104B mounted thereon, and any discrete active or passive components, semiconductor dies, or other components required for intended functionality. A ground contact pad 158 is present to separate two sections of the substrate 152. EMI shielding will later be mounted to the ground contact pad 158 to protect the device on either side of the ground contact pad from EMI generated by each other. Any type and number of components can be mounted on the substrate 152 on either side of the ground contact pad 158, and EMI absorbing metal rods will be mounted to the ground contact pad. Solder bumps 114 are reflowed between the conductive layer 156 and the semiconductor die 104 to mechanically and electrically connect the die to the substrate 152. Components can be mounted to the top surface, bottom surface, or both of the substrate 152 as illustrated in FIG2a, and can also be embedded within the substrate in any suitable order and configuration.

[0034] Figure 2b shows the beginning of the formation of the EMI absorbing metal rod 180. The process begins with metal rod 182, which is typically cut from a larger metal sheet or molded into a cubic, trapezoidal, or other desired shape. In other specific examples, metal rod 182 is formed by depositing metal into the openings of a photomask. Metal rod 182 is most commonly formed of copper, but in other specific examples other materials are used, such as iron, chromium, aluminum, gold, titanium, tungsten, tin, other conductive materials, and combinations or alloys thereof.

[0035] In Figure 2c, the EMI absorbing layer 184 is coated over the metal rod 182. In some specific examples, the EMI absorbing layer 184 is formed from a material from the AB5000SHF series manufactured by 3M. The EMI absorbing layer 184 is typically a polymeric resin substrate with a magnetic metal flake filler. In another specific example, the EMI absorbing layer 184 is a nickel layer. Nickel is particularly suitable for specific examples at lower RF frequencies in the range of approximately 400 MHz to 1 GHz. Any suitable EMI absorbing material may be used in other specific examples.

[0036] The EMI absorbing layer 184 may be deposited as a liquid or powder and then cured or hardened. Alternatively, the EMI absorbing layer 184 may be provided as a pre-formed sheet of material, which is disposed on the surface of the metal rod 182. The EMI absorbing layer 184 may be applied by sputtering, electroplating, spraying or other metal or material deposition techniques, depending on the material used.

[0037] Since the metal rod is located on the carrier during the application of the EMI absorbing layer, the bottom surface of the metal rod 182 remains free of the EMI absorbing layer 184. Exposing the bottom surface of the metal rod 182 provides a convenient surface for attaching the EMI absorbing metal rod 180 to the substrate 152 using solder. In other specific embodiments, all surfaces of the metal rod 182 are coated with the EMI absorbing material 184.

[0038] In Figure 2d, a protective layer 186 is formed above the EMI absorbing material 184. In one specific example, the protective layer 186 is formed of stainless steel, such as SUS304. In other specific examples, the protective layer 186 is an insulating layer, such as polyimide or polybenzoxazole (PBO). The protective layer 186 helps to protect portions of the EMI absorbing layer 184 from accidental damage or removal during handling. In some specific examples, the protective layer 186 internally reflects RF signals, such that some EMI reflected by the metal rod 182 is retained within the EMI absorbing material 184 by the protective layer. Internal EMI reflection increases the absorption loss within the EMI absorbing material 184.

[0039] Figure 2e shows an EMI-absorbing metal rod 180 disposed on a substrate 152 between semiconductor dies 104A and 104B. In other specific embodiments, the EMI-absorbing metal rod 180 and other components on the substrate 152 can be mounted in any desired order. The contact pads 158 of the conductive layer 156 are appropriately sized to mount the EMI-absorbing metal rod 180 using solder that is reflowed between the EMI-absorbing metal rod and the contact pads. The solder can be applied as solder paste to the contact pads 158 or the EMI-absorbing metal rod 180 prior to mounting. The EMI-absorbing metal rod 180 can be positioned directly between semiconductor dies 104A and 104B or other components that need to be protected from EMI generated by each other.

[0040] In Figure 2f, an encapsulation or molding compound 190 is deposited over the substrate 152, covering the EMI absorbing metal rod 180 and the top and side surfaces of the semiconductor die 104. The encapsulation 190 also extends below the semiconductor die 104 between the semiconductor die and the substrate 152. In other specific embodiments, a separate mold underfill (MUF) is alternatively used.

[0041] Encapsulation 190 is an electrically insulating material deposited using paste printing, compression molding, transfer molding, liquid encapsulation molding, vacuum lamination, spin coating, or other suitable application processes. Encapsulation 190 may be a polymer composite material, such as epoxy resin, epoxy acrylate, or a polymer with or without fillers. Encapsulation 190 is non-conductive and environmentally friendly, protecting the semiconductor device from external components and contaminants.

[0042] The encapsulation 190 is typically deposited while the substrate 152 remains as a larger panel, forming multiple SiP modules 150. In FIG2g, the larger panel of the substrate 152 and the encapsulation 190 is then formed by single-particle forming units to allow the shielding layer 196 to be formed on the top and side surfaces of each SiP module 150.

[0043] In Figure 2g, conductive material is sputtered over SiP module 150 to form conductive shielding layer 196. Shielding layer 196 is formed using any suitable metal deposition technique (e.g., PVD, CVD, other sputtering methods, spraying, or electroplating). The sputtering material can be copper, steel, aluminum, gold, a combination thereof, or any other suitable conductive material. In some specific instances, shielding layer 196 can be manufactured by sputtering multiple layers of different materials (e.g., stainless steel-copper-stainless steel or titanium-copper). Shielding layer 196 reduces EMI between the components of package 150 and other nearby electronic devices. Shielding layer 196 may be grounded via conductive layer 156 to further improve EMI reduction.

[0044] Figure 2g shows the completed SiP module 150, which has EMI-absorbing metal bars 180 for in-package EMI reduction. The SiP module 150 has a platform grid array on the bottom of a substrate 152 for interconnection to a larger system. In other specific examples, other interconnect structures, such as solder bumps or conductive pillars, are applied.

[0045] The metal rod 182 reduces EMI between semiconductor chips 104A and 104B by being coupled to ground via the contact pad 158. The EMI absorbing material 184 further reduces EMI by capturing and absorbing RF signals. The EMI absorbing material 184 reduces the amount of RF signals from each semiconductor chip 104 that would otherwise be reflected back from the metal rod 182 to the semiconductor chip that generates the RF signal.

[0046] Figures 3a to 3d illustrate another specific example of an EMI absorbing metal rod 200. The EMI absorbing metal rod 200 begins with the metal rod 182 in Figure 3a, similar to the description above. In Figure 3b, a seed layer, adhesive layer, or wetting layer 202 is formed over the metal rod 182. In one specific example, the wetting layer 202 is stainless steel, for example, SUS304. In Figure 3c, EMI absorbing material 184 is applied to the metal rod 182 as described above, but the wetting layer 202 is positioned between the metal rod and the EMI absorbing material. The wetting layer 202 helps to adhere the EMI absorbing material 184 to the metal rod 182. In Figure 3d, a protective layer 186 is applied over the EMI absorbing material 184 as described above. The wetting layer 202 and the protective layer 186 are optional, and other specific examples may omit either or both layers.

[0047] Figure 4 illustrates another specific example as a SiP module 220. The opening or trench 222 is formed through the encapsulation 190 using laser ablation, mechanical drilling, chemical etching, or another suitable method to expose the top surface of the EMI-absorbing metal rod 200 or 180. In other specific examples, one or more layers are also removed from the top of the metal rod 182. In some specific examples, the formation of the trench 222 exposes the metal rod 182.

[0048] The trench 222 is formed before the shielding layer 196 is formed. When the shielding layer 196 is formed, a portion 224 of the shielding layer 196 is formed in the trench 222 on the EMI absorbing metal rod 200. The portion 224 directly connects the shielding layer 196 to the EMI absorbing metal rod 200, which helps to ground the EMI absorbing metal rod and also creates additional vertical shielding along the sidewall of the trench 222.

[0049] The physical dimensions of the metal rod 182 can be adjusted as needed. For example, the SiP module 230 in Figure 5 utilizes a taller metal rod to form the EMI absorbing metal rod 232. The taller metal rod improves performance without requiring additional processing steps to form the trench 222. The EMI absorbing metal rod 232 is formed separately similarly to the EMI absorbing metal rods 180 and 200 described above. The additional height above the substrate 152 improves EMI blocking and absorption performance by reducing the gap between the EMI absorbing metal rod and the shielding layer 196.

[0050] Figures 6a and 6b illustrate a specific example of a SiP module 250 in which the metal rod 182 is exposed by back-grinding the entire top surface of the encapsulation 190 instead of forming grooves or openings as shown in Figure 4. In Figure 6a, the encapsulation 190 is back-grinded using a grinder 240. Chemical mechanical planarization or any other suitable method may be used to reduce the thickness of the encapsulation 190 and thereby expose the metal rod 182 or one of the layers disposed thereon. Using a higher EMI-absorbing metal rod 232 reduces the number of back-grinding operations required, thereby reducing manufacturing time and cost, but any of the aforementioned EMI-absorbing metal rods may be used. In Figure 6b, a shielding layer 196 is formed over the encapsulation 190 as described above and is also formed directly on the metal rod 182.

[0051] Figures 7a and 7b illustrate the integration of the semiconductor package (e.g., SiP module 150) described above into a larger electronic device 340. Figure 7a illustrates a partial cross-section of the SiP module 150 mounted on a printed circuit board (PCB) or other substrate 342 that is part of the electronic device 340. Bumps 260 are formed similarly to those described above for bump 114 at any desired manufacturing stage and are reflowed onto the conductive layer 344 of the PCB 342 to physically attach and electrically connect the SiP module 150 to the PCB. In other specific examples, thermoforming or other suitable attachment and connection methods are used. In some specific examples, an adhesive or underfill layer is used between the SiP module 150 and the PCB 342. The semiconductor die 104 is electrically coupled to the conductive layer 344 via the substrate 152.

[0052] Figure 7b illustrates an electronic device 340 including a PCB 342, wherein a plurality of semiconductor packages are mounted on the surface of the PCB (including the SiP module 150). Depending on the application, the electronic device 340 may have one type or multiple types of semiconductor packages. The electronic device 340 may be a standalone system using semiconductor packages to perform one or more electrical functions. Alternatively, the electronic device 340 may be a sub-component of a larger system. For example, the electronic device 340 may be part of a tablet computer, a cell phone, a digital camera, a communication system, or other electronic device. The electronic device 340 may also be a graphics card, a network interface card, or another signal processing card inserted into a computer. Semiconductor packages may include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete active or passive devices, or other semiconductor chips or electrical components.

[0053] In Figure 7b, PCB 342 provides a general-purpose substrate for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 344 are formed on or within the surface of PCB 342 using evaporation, electroplating, electroless plating, screen printing, or other suitable metal deposition processes. Signal traces 344 provide electrical communication between the semiconductor package, mounted components, and other external systems or components. If necessary, traces 344 also provide power connections and ground connections to the semiconductor package.

[0054] In some specific examples, the semiconductor device has two packaging levels. The first-level packaging is a technique for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second-level packaging involves mechanically and electrically attaching the intermediate substrate to the PCB 342. In other specific examples, the semiconductor device may have only a first-level package, wherein the die is directly mechanically and electrically mounted to the PCB 342.

[0055] For illustrative purposes, several types of first-level packages, including wire bond package 346 and flip chip 348, are shown on PCB 342. Additionally, several types of second-level packages, including ball grid array (BGA) 350, bump chip carrier (BCC) 352, land grid array (LGA) 356, multi-chip module (MCM) 358, quad flat non-leaded (QFN) package 360, quad flat package 362, and embedded wafer level ball grid array (eWLB) 364, are shown mounted on PCB 342 together with SiP module 150. Conductive traces 344 electrically couple the various packages and components mounted on PCB 342 to SiP module 150, thereby enabling components within SiP module 150 to be used by other components on the PCB.

[0056] Depending on system requirements, any combination of semiconductor packages configured with first and second level package designs and other electronic components can be connected to PCB 342. In some specific instances, electronic device 340 includes a single attached semiconductor package, while other specific instances require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate pre-fabricated components into electronic devices and systems. Because semiconductor packages include complex functionality, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less prone to failure and less expensive to manufacture, thereby reducing consumer costs.

[0057] Although one or more specific embodiments of the present invention have been described in detail, those skilled in the art will understand that modifications and adaptations can be made to those specific embodiments without departing from the scope of the invention as set forth in the following claims. [Simplified Explanation of the Diagram]

[0020] [Figures 1a] to [Figures 1c] illustrate a semiconductor wafer having a plurality of semiconductor grains separated by saw marks; [Figures 2a] to [Figures 2g] illustrate the formation of a system-in-package (SiP) module using a metal wafer or rod having an EMI-absorbing coating for blocking and absorbing EMI within the package; [Figures 3a] to [Figures 3d] illustrate specific examples of alternative EMI-absorbing coatings; [Figure 4] illustrates a trench formed on top of a metal rod for additional grounding; [Figure 5] illustrates varying the height of the metal rod; [Figures 6a] and [Figure 6b] illustrate a full-height metal rod; and [Figures 7a] and [Figure 7b] illustrate the integration of the SiP module into an electronic device.

Claims

1. A semiconductor device comprising: a substrate including contact pads; a first semiconductor die and a second semiconductor die disposed above the substrate; a metal rod disposed on the contact pads of the substrate and between the first semiconductor die and the second semiconductor die; an EMI absorbing material coated on a top surface and a side surface of the metal rod, wherein a bottom surface of the metal rod facing the contact pads remains exposed to the EMI absorbing material; an encapsulation deposited above the first semiconductor die, the second semiconductor die and the metal rod; and a shielding layer formed above the encapsulation.

2. The semiconductor device of claim 1, further comprising a trench formed in the encapsulation above the metal rod, wherein the shielding layer extends into the trench to contact the shielding layer.

3. The semiconductor device of claim 1, further comprising a protective layer formed over the EMI absorbing material.

4. The semiconductor device of claim 1, further comprising a wetting layer formed between the metal rod and the EMI absorbing material.

5. The semiconductor device of claim 1, wherein the EMI absorbing material comprises nickel.

6. The semiconductor device of claim 1, wherein the EMI absorbing material comprises a polymer substrate and a magnetic metal sheet disposed therein.

7. A semiconductor device comprising: a substrate; a first semiconductor die and a second semiconductor die disposed above the substrate; a metal rod disposed between the first semiconductor die and the second semiconductor die above the substrate; an EMI absorbing material coated above the top surface and side surface of the metal rod; and a shielding layer formed above the substrate, the first semiconductor die, the second semiconductor die, and the metal rod.

8. The semiconductor device of claim 7, wherein the EMI absorbing material comprises a polymer substrate and a magnetic metal sheet disposed therein.

9. The semiconductor device of claim 7, further comprising an encapsulation deposited on the substrate, the first semiconductor die, the second semiconductor die, and the metal rod, wherein the shielding layer is formed on the encapsulation.

10. The semiconductor device of claim 9, further comprising a trench formed in the encapsulation above the metal rod, wherein the shielding layer extends into the trench to contact the shielding layer.

11. A semiconductor device comprising: a substrate; a metal rod disposed above the substrate; and an EMI absorbing material coated on the metal rod to form an EMI absorbing metal rod.

12. The semiconductor device of claim 11, further comprising: Encapsulation, which is deposited on the EMI absorbing metal rod and the substrate; And a shielding layer, which is formed on top of the capsule.

13. The semiconductor device of claim 12, wherein the shielding layer is in physical contact with the EMI absorbing metal rod.

14. The semiconductor device of claim 11, further comprising a protective layer formed over the EMI absorbing material.

15. The semiconductor device of claim 14, further comprising a wetting layer formed between the metal rod and the EMI absorbing material.

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