Semiconductor pacakge and method for forming the same

Abstract

This application discloses a semiconductor package. The semiconductor package includes: a package substrate; a first plurality of semiconductor dies disposed on the front side of the package substrate; and an embedded sub-package disposed on the back side of the package substrate, including: a sub-package substrate with its front side attached to the back side of the package substrate; an interconnect layer attached to the back side of the sub-package substrate; a second plurality of vertical interconnects and at least one horizontal interconnect; the second plurality of semiconductor dies disposed on the back side of the sub-package substrate via the interconnect layer, each of the second plurality of semiconductor dies being electrically coupled to the sub-package substrate via at least one of the second plurality of vertical interconnects, and at least two of the second plurality of semiconductor dies being electrically coupled to each other via at least one horizontal interconnect, such that the first plurality of semiconductor dies are electrically coupled to each other via the embedded sub-package; the first plurality of vertical interconnects disposed on the back side of the package substrate; and solder bumps attached to the first plurality of vertical interconnects.

Description

[Technical Field]

[0001] This application generally relates to semiconductor devices, and more specifically, to semiconductor packages having embedded semiconductor packages. [Previous Technology]

[0002] The semiconductor industry has always faced complex integration challenges as consumers demand smaller, faster, and higher-performing electronic devices, and increasingly package more and more functions into a single device. To meet these consumer demands, more and more electronic components are being integrated at higher densities. However, semiconductor packaging is structurally complex, and its manufacturing process may have limited efficiency.

[0003] Therefore, there is a need for a method for forming semiconductor packages with improved production efficiency. [Summary of the Invention]

[0004] The objective of this application is to provide a semiconductor package with improved production efficiency.

[0005] According to one aspect of this application, a semiconductor package is provided. The semiconductor package includes: a package substrate having a front side and a back side; a first plurality of semiconductor dies disposed on the front side of the package substrate and electrically coupled to the package substrate; an embedded sub-package disposed on the back side of the package substrate, the embedded sub-package including: a sub-package substrate having a front side and a back side, wherein the front side of the sub-package substrate is attached to the back side of the package substrate and electrically coupled to the package substrate; an interconnect layer attached to the back side of the sub-package substrate and electrically coupled to the sub-package substrate; wherein the interconnect layer includes a second plurality of vertical interconnect portions and at least one horizontal interconnect portion; and a second plurality of semiconductor dies, the second plurality of semiconductor dies being disposed on the front side of the package substrate and electrically coupled to the package substrate; wherein the interconnect layer includes a second plurality of vertical interconnect portions and at least one horizontal interconnect portion; and a second plurality of semiconductor dies, the second plurality of semiconductor dies being disposed on the back side of the package substrate and electrically coupled to the package substrate; The interconnect layer is disposed on the back side of the subpackage substrate, wherein each of the second plurality of semiconductor dies is electrically coupled to the subpackage substrate through at least one of the second plurality of vertical interconnects, and at least two of the second plurality of semiconductor dies are further electrically coupled to each other through the at least one horizontal interconnect, such that the first plurality of semiconductor dies are electrically coupled to each other through the embedded subpackage; and a first plurality of vertical interconnects are disposed on the back side of the package substrate and are parallel to the embedded subpackage, wherein each of the first plurality of semiconductor dies is electrically coupled to one of the first plurality of vertical interconnects; and solder bumps are attached to the first plurality of vertical interconnects.

[0006] According to another aspect of this application, a method for forming a semiconductor package is provided. The method includes: providing a first plurality of semiconductor dies and a second plurality of semiconductor dies; forming an embedded subpackage, including: forming a second plurality of vertical interconnects on the second plurality of semiconductor dies, the second plurality of vertical interconnects being electrically coupled to the second plurality of semiconductor dies; attaching at least one horizontal interconnect to the second plurality of semiconductor dies, wherein at least two of the second plurality of semiconductor dies are electrically connected to each other via the at least one horizontal interconnect; molding the second plurality of semiconductor dies, the second plurality of vertical interconnects, and the at least one horizontal interconnect; forming a subpackage substrate on the second plurality of semiconductor dies, the second plurality of vertical interconnects, and the at least one horizontal interconnect, wherein the second plurality of vertical interconnects are electrically coupled to the subpackage substrate, wherein each of the second plurality of semiconductor dies is electrically coupled to the subpackage substrate via at least one of the second plurality of vertical interconnects. The process involves: mounting a substrate; forming a first plurality of vertical interconnects; molding the embedded subpackage and the first plurality of vertical interconnects, wherein the first plurality of vertical interconnects are parallel to the embedded subpackage; attaching solder bumps such that the solder bumps are electrically coupled to the first plurality of vertical interconnects; forming a package substrate on the embedded subpackage and the first plurality of vertical interconnects, wherein the package substrate includes a front side and a back side, wherein the first plurality of vertical interconnects and the subpackage substrate of the embedded subpackage are attached to and electrically coupled to the back side of the package substrate; and arranging a first plurality of semiconductor dies on the front side of the package substrate, wherein the first plurality of semiconductor dies are electrically coupled to the package substrate, the first plurality of semiconductor dies are electrically coupled to each other through the embedded subpackage, and each of the first plurality of semiconductor dies is electrically coupled to one of the first plurality of vertical interconnects.

[0007] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative only, and not intended to limit the invention. Furthermore, the accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

Implementation Method

[0016] The following detailed description of exemplary embodiments of this application refers to the accompanying drawings, which form a part of the description. The drawings illustrate specific exemplary embodiments in which this application may be practiced. The detailed description, including the drawings, describes these embodiments in sufficient detail to enable those skilled in the art to practice this application. Those skilled in the art can further utilize other embodiments of this application and make logical, mechanical, etc., changes without departing from the spirit or scope of this application. Therefore, the reader of the following detailed description should not interpret it in a limiting manner, and the scope of the embodiments of this application is limited only to the appended claims.

[0017] In this application, unless otherwise expressly stated, the use of the singular includes the plural. In this application, unless otherwise stated, the use of "or" means "and / or". Furthermore, the use of the term "including" and other forms such as "includes" and "included" is not restrictive. Additionally, unless otherwise specifically stated, terms such as "element" or "component" cover elements and components comprising one unit and elements and components comprising more than one subunit. Furthermore, the section headings used herein are for organizational purposes only and should not be construed as limiting the subject matter described.

[0018] As used herein, for ease of description, spatially relative terms such as "below," "below," "above," "upper," "upper," "lower," "left," "right," "vertical," "horizontal," "side," etc., may be used to describe the relationship between an element or feature and another element (or feature) or feature (or feature), as illustrated in the figures. In addition to the orientations depicted in the figures, the spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly. It should be understood that when an element is referred to as "connected to" or "coupled to" another element, the element may be directly connected to or coupled to the other element, or there may be intermediate elements present.

[0019] Referring to FIG1, a semiconductor package 100 according to an embodiment of the present application is illustrated. The semiconductor package 100 includes a package substrate 110 having a front side 111 and a back side 112. A first plurality of semiconductor dies 120 are disposed on the front side 111 of the package substrate 110 and electrically coupled to the package substrate 110. Some other components of the semiconductor package 100 may be disposed on the back side 112 of the package substrate 110, which will be described in detail below.

[0020] The package substrate 110 provides electrical connections between a plurality of semiconductor dies 120 on its front side 111 and components on its back side 112. In some embodiments, the package substrate 110 includes one or more insulating layers interleaved with one or more conductive layers. In one embodiment, the insulating layer may be a core insulating plate, wherein the conductive layers are patterned over a top and bottom surface, such as a copper-clad laminate substrate. The conductive layers also include conductive vias electrically coupled through the insulating layers. The package substrate 110 may include any number of interleaved conductive and insulating layers.

[0021] Referring again to FIG. 1, an embedded subpackage 130 and a first plurality of vertical interconnects 140 are provided on the back side 112 of the package substrate 110. Specifically, the embedded subpackage 130 includes a subpackage substrate 131, an interconnect layer 134, and a plurality of semiconductor dies 137. Preferably, the subpackage substrate 131, the interconnect layer 134, and the plurality of semiconductor dies 137 are arranged from top to bottom and electrically coupled together.

[0022] Specifically, the sub-package substrate 131 has a front side 132 and a back side 133, with the front side 132 of the sub-package substrate 131 attached to and electrically coupled to the back side 112 of the package substrate 110. In some embodiments, the sub-package substrate 131 may include insulating and conductive layers similar to those in the package substrate 110. In some embodiments, the sub-package substrate 131 includes dielectric and conductive layers. The sub-package substrate 131 achieves a redistribution from the upper package substrate 110 to the interconnect layer 134, and particularly to the lower second plurality of vertical interconnect portions 135.

[0023] Interconnect layer 134 is attached to and electrically coupled to the back surface 133 of subpackage substrate 131. Interconnect layer 134 includes a second plurality of vertical interconnect portions 135 and at least one horizontal interconnect portion 136. In some embodiments, the second plurality of vertical interconnect portions 135 include a conductive layer 135 electrically coupled to an underlying second plurality of semiconductor dies 137. In some embodiments, the at least one horizontal interconnect portion 136 is a silicon bridge having terminals or pads. Terminals or pads may include solder, copper, or gold interconnects. In some embodiments, terminals may have a fine interconnect pitch between 0.1µm and 1µm. At least one horizontal interconnect portion 136 may electrically couple at least two of the underlying second plurality of semiconductor dies 137 together. Preferably, the second plurality of vertical interconnect portions 135 may surround at least one horizontal interconnect portion 136 in interconnect layer 134.

[0024] Referring again to FIG1, a second plurality of semiconductor dies 137 are disposed on the back side 133 of the subpackage substrate 131 via an interconnect layer 134. Specifically, each of the second plurality of semiconductor dies 137 is electrically coupled to the subpackage substrate 131 via at least one of the second plurality of vertical interconnects 135.

[0025] As can be seen, the embedded subpackage 130 implements integrated electrical connections therein. Components outside the embedded subpackage 130 can be electrically connected through the embedded subpackage 130 itself without the need for additional electrical wiring. Electrical connections are implemented between the first plurality of semiconductor dies 120 and the second plurality of semiconductor dies 137 of the embedded subpackage 130. Specifically, the first plurality of semiconductor dies 120 are electrically coupled to each other through the embedded subpackage 130.

[0026] Referring again to FIG1, as described above, the semiconductor package 100 further includes a first plurality of vertical interconnects 140 on the back surface 112 of the package substrate 110. Generally, the first plurality of vertical interconnects 140 are parallel to the embedded sub-package 130. Each of the first plurality of semiconductor dies 120 is electrically coupled to one of the first plurality of vertical interconnects 140 via the package substrate 110. Thus, each of the first plurality of vertical interconnects 140 achieves a redistribution of at least a portion of the corresponding semiconductor die. It is understood that the first plurality of vertical interconnects 140 may further include redistribution structures 141 for electrically connecting them to other underlying components. In some embodiments, the first plurality of vertical interconnects 140 may also serve to provide mechanical support for the semiconductor package 100.

[0027] In some embodiments, each of the first plurality of vertical interconnects 140 may include at least one conductive via or at least one conductive post. The first plurality of vertical interconnects 140 may be molded from a polymer composite material, such as epoxy resin, epoxy acrylate, or any suitable polymer, with or without filler, wherein the conductive via or conductive post passes through the polymer composite material.

[0028] In addition, solder bumps 150 are attached to the first plurality of vertical interconnects 140, so that the semiconductor package 100 can be further attached to another circuit board or substrate for integration with other components.

[0029] As described above, electrical interconnection is achieved through the embedded subpackage 130. Specifically, at least one horizontal interconnect portion 136 can serve as the center of the electrical interconnection. Therefore, heat may be generated and accumulate significantly in the semiconductor package 100, and this heat needs to be dissipated to achieve optimal performance. In some embodiments, an interconnect heat sink (not shown) may be provided for at least one horizontal interconnect portion 136. Specifically, the interconnect heat sink may be in thermal contact with at least one horizontal interconnect portion 136. It is understood that in some embodiments, the interconnect heat sink may include thermally conductive vias embedded in the subpackage substrate 131 and the package substrate 110. The interconnect heat sink may also extend above the package substrate 110 for further heat dissipation.

[0030] As described above, the embedded sub-package 130 includes pre-integratable components, i.e., it can be modularly pre-formed before assembly with other components. Similarly, the first plurality of vertical interconnects 140 can also be modularly pre-formed. The semiconductor package 100 achieves a high degree of integration of multiple semiconductor dies, enables rapid electrical connections between multiple semiconductor dies by using at least one horizontal interconnect as a bridging element, and also achieves modularity of packaged components, which is beneficial for custom specifications and dimensions. Therefore, the manufacturing efficiency of the semiconductor package 100 can be improved, and the semiconductor package structure is easy to adjust and adapt.

[0031] Figures 2A to 2F show cross-sectional views of a method for forming an embedded subpackage according to an embodiment of the present application.

[0032] Referring to FIG. 2A, a plurality of semiconductor dies 237 are provided. Furthermore, a plurality of vertical interconnects 235 are formed on the plurality of semiconductor dies 237. In some embodiments, the plurality of vertical interconnects 235 may include a conductive layer.

[0033] Referring to FIG. 2B, a plurality of semiconductor dies 237 are attached to a carrier 260. In some embodiments, the carrier 260 comprises a substrate, such as silicon, polymer, polymer composite, metal foil, ceramic, glass, epoxy glass, beryllium oxide, tape, or other suitable low-cost rigid material for structural support. The carrier 260 may be a wafer or a circle, for example having a diameter of 15-30 cm. An adhesive film or adhesive layer may be formed on the carrier 260. The adhesive layer may be a flexible plastic base film, such as polyvinyl chloride (PVC) or polyolefin, with a synthetic acrylic adhesive or a UV-sensitive adhesive for device mounting and dismounting. The adhesive layer may be removed by light, heat, laser, or mechanical pressure. Alternatively, an adhesive material such as a thermally applied epoxy resin, polymer composite, or inorganic adhesive compound may be applied to the carrier 260.

[0034] Referring to FIG. 2C, at least one horizontal interconnect 236 is attached to a plurality of semiconductor dies 237. As shown in the figure above, at least two of the plurality of semiconductor dies 237 are electrically connected to each other via at least one horizontal interconnect 236. For example, the horizontal interconnect 236 can be attached to the semiconductor dies 237 using a bonding process or a surface mount process.

[0035] Referring to FIG. 2D, a plurality of semiconductor dies 237, a plurality of vertical interconnects 235, and at least one horizontal interconnect 236 are molded. In some embodiments, a molding compound may be deposited using paste printing, compressive molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable processes to cover the plurality of semiconductor dies 237, the plurality of vertical interconnects 235, and at least one horizontal interconnect 236. The molding compound may be a polymer composite material, such as epoxy resin, epoxy acrylate, or any suitable polymer, with or without filler. The molding compound is non-conductive and may provide structural support for other components. It is understood that, preferably, the molding compound is formed around the edges of the semiconductor dies 237 to provide isolation from their respective sides.

[0036] Referring to FIG. 2E, a subpackage substrate 231 is formed on a plurality of semiconductor dies 237, a plurality of vertical interconnects 235, and at least one horizontal interconnect 236. In some embodiments, the subpackage substrate 231 includes a dielectric layer 238 and a conductive layer 239. As shown in FIG. 2E, the plurality of vertical interconnects 235 are electrically coupled to the subpackage substrate 231, wherein each of the plurality of semiconductor dies 237 is electrically coupled to the subpackage substrate 231 through at least one of the plurality of vertical interconnects 235.

[0037] Next, referring to FIG2F, the carrier is removed, and thus an embedded subpackage 230 is formed, which can be used in subsequent processes to integrate it with other components of the semiconductor package.

[0038] Figures 3A to 3E show cross-sectional views of a method for forming a vertical interconnect according to an embodiment of the present application.

[0039] Referring to FIG. 3A, a plurality of conductive posts 343 are disposed on the carrier 342. Preferably, the plurality of conductive posts 343 may include Cu, Al, Sn, Ni, Au, Ag, Pb, Bi, etc., or combinations thereof. In some embodiments, the plurality of conductive posts 343 may be implemented as stacked bumps or stud bumps. It is understood that the number of the plurality of conductive posts 343 should be sufficient to form a plurality of vertical interconnects.

[0040] Referring to FIG. 3B, a plurality of conductive posts 343 are molded using molding material 344. To achieve further electrical connections, the conductive posts 343 may be exposed to the molding material 344. For example, the conductive posts 343 may be exposed by grinding after molding. The molding material may be a polymer composite or any other suitable material.

[0041] Next, referring to FIG. 3C, a redistribution layer 341 is formed on the molded conductive pillars 343. Specifically, the redistribution layer 341 may include a conductive layer 345 and a dielectric layer 346. In this way, the plurality of conductive pillars 343 are electrically connected to the redistribution layer 341.

[0042] Referring to FIG. 3D, the plurality of conductive posts 343 are cut to obtain each of the plurality of vertical interconnects 340 shown in FIG. 3E. For example, the cutting can be performed by cutting at a predetermined cutting channel using a saw or laser cutting tool. These vertical interconnects may have the same shape, size or layout, or may have different shapes, sizes or layouts, depending on the components they are connected to.

[0043] In some other embodiments, the plurality of vertical interconnects may be formed in another manner as shown in Figures 4A to 4C.

[0044] Referring to FIG. 4A, a dielectric layer 443 is formed on a carrier 442. Referring to FIG. 4B, a plurality of vias 444 are formed in the dielectric layer 443. In some embodiments, the plurality of vias 444 may be formed by laser or etching. Referring to FIG. 4C, conductive material is filled into the plurality of vias to form a plurality of conductive vias at the locations of the vias.

[0045] After the steps shown in Figures 4A to 4C, the steps shown in Figures 3C to 3E may be performed subsequently to obtain a plurality of vertical interconnects. The following steps will not be described in detail here.

[0046] Figures 5A to 5G show cross-sectional views of a method for forming a semiconductor package according to an embodiment of this application.

[0047] Referring to FIG5A, the pre-formed embedded subpackage 530 is attached to the carrier 542, wherein the front side 532 of the subpackage substrate 531 is attached to the carrier 542.

[0048] Referring to FIG5B, a plurality of vertical interconnects 540 are also attached to the carrier 542. In some embodiments, the plurality of vertical interconnects 540 include a redistribution layer 541 oriented away from the carrier 542.

[0049] Referring to FIG. 5C, the embedded subpackage 530 and a plurality of vertical interconnects 540 are molded together using a molding process, wherein the first plurality of vertical interconnects 540 are parallel to the embedded subpackage 530. In other words, the vertical interconnects 540 and the embedded subpackage 530 do not overlap each other. In some embodiments, after the molding process, the conductive structure of the redistribution layer 541 may be exposed to the molding material to further form electrical connections, such as solder bumps.

[0050] Referring to FIG. 5D, solder bumps 550 are attached using a process such as surface mount technology, such that solder bumps 550 are electrically coupled to a plurality of vertical interconnects 540. In some embodiments, solder bumps 550 are electrically coupled to a redistribution layer 541 to electrically couple to the plurality of vertical interconnects 540. It will be understood that solder bumps 550 may also be attached at other times, for example after the chip attachment shown in FIG. 5G, as described in the following paragraphs.

[0051] Next, referring to FIG5E, the carrier 542 is removed. In some embodiments, the entire package structure may be flipped so that the package substrate can be further attached to the plurality of vertical interconnects 540 and the embedded sub-package 530 after the molding process.

[0052] Referring to FIG5F, a package substrate 510 is formed on an embedded sub-package 530 and a plurality of vertical interconnects 540. The package substrate 510 includes a front side 511 and a back side 512. The plurality of vertical interconnects 540 and the sub-package substrate 531 of the embedded sub-package 530 are attached to and electrically coupled to the back side 512 of the package substrate 510.

[0053] Referring to FIG. 5G, a plurality of semiconductor dies 520 are disposed on the front side 511 of the package substrate 510, wherein the plurality of semiconductor dies 520 are electrically coupled to the package substrate 510. Thus, the plurality of semiconductor dies 520 are electrically coupled to each other through an embedded sub-package 530. Furthermore, each of the plurality of semiconductor dies 520 is electrically coupled to one of a plurality of vertical interconnects 540. It is understood that in some embodiments, solder bumps 550 may be attached after the plurality of semiconductor dies 520 are attached.

[0054] As described above, at least one horizontal interconnect portion 536 may serve as the center of the electrical interconnect and may generate heat, which needs to be dissipated to achieve optimal performance. In some embodiments, an interconnect portion heat sink (not shown) may be formed, which is in thermal contact with at least one horizontal interconnect portion 536. In some embodiments, thermally conductive vias may be formed, which are embedded in the sub-package substrate 531 and the package substrate 510. The interconnect portion heat sink may also extend above the package substrate 510 for further heat dissipation.

[0055] Figures 6 and 7 show cross-sectional views of semiconductor packages according to two embodiments of this application.

[0056] Referring to FIG. 6, the semiconductor package 600 may include means for further heat dissipation. In particular, the semiconductor package 600 further includes a substrate 601 on which solder bumps 650 are attached. Furthermore, a base thermal interface material layer 602 is formed beneath the embedded sub-package 630. In some embodiments, after the solder bumps 650 are mounted on the substrate 601, the base thermal interface material layer 602 is in thermal contact with the plurality of semiconductor dies 637 of the embedded sub-package 630 and the substrate 601. Therefore, the heat generated by the plurality of semiconductor dies 637 can be effectively transferred to the outside of the substrate 601.

[0057] Referring to FIG7, compared with FIG6, the semiconductor package 700 further includes a top thermal interface material layer 703 located on a plurality of semiconductor dies 720. In addition, the semiconductor package 700 also includes a top heat sink 704, which may be disposed on the top thermal interface material layer 703 for direct heat dissipation of the plurality of semiconductor dies 720.

[0058] This discussion includes numerous illustrative figures illustrating various parts of a semiconductor package and methods of manufacturing the semiconductor package. For clarity, these figures do not show all aspects of each example component. Any example component and / or method provided herein may share any or all features with any or all other components and / or methods provided herein.

[0059] Various embodiments have been described herein with reference to the accompanying drawings. However, it will be apparent that various modifications and changes can be made thereto, and other embodiments can be implemented without departing from the broader scope of the invention as set forth in the appended claims. Furthermore, other embodiments will be apparent to those skilled in the art upon consideration of the practice of one or more embodiments of the invention disclosed herein. Therefore, the embodiments in this application and herein are intended to be considered exemplary only, and the true scope and spirit of the invention are indicated by the appended list of exemplary claims. [Simplified Explanation of the Diagram]

[0008] The accompanying drawings referenced herein form part of the specification. The features shown in the drawings illustrate only some embodiments of this application, and not all embodiments of this application, unless otherwise expressly stated in the detailed description, and the reader of the specification should not draw the contrary inference.

[0009] FIG1 shows a cross-sectional view of a semiconductor package according to an embodiment of the present application.

[0010] Figures 2A to 2F show cross-sectional views of a method for forming an embedded subpackage according to an embodiment of the present application.

[0011] Figures 3A to 3E show cross-sectional views of a method for forming a vertical interconnect according to an embodiment of the present application.

[0012] Figures 4A to 4C show cross-sectional views of a portion of a method for forming a vertical interconnect according to another embodiment of this application.

[0013] Figures 5A to 5G show cross-sectional views of a method for forming a semiconductor package according to an embodiment of the present application.

[0014] Figures 6 and 7 show cross-sectional views of semiconductor packages according to two embodiments of this application.

[0015] The same reference numerals will be used throughout the accompanying drawings to denote the same or similar parts.

Claims

1. A semiconductor package, wherein, The semiconductor package includes: a package substrate having a front side and a back side; a first plurality of semiconductor dies disposed on the front side of the package substrate and electrically coupled to the package substrate; and an embedded subpackage disposed on the back side of the package substrate, the embedded subpackage including: a subpackage substrate having a front side and a back side, wherein the front side of the subpackage substrate is attached to the back side of the package substrate and electrically coupled to the package substrate; An interconnect layer is attached to and electrically coupled to the back side of the subpackage substrate; wherein the interconnect layer includes a second plurality of vertical interconnects and at least one horizontal interconnect; and a second plurality of semiconductor dies disposed on the back side of the subpackage substrate via the interconnect layer, wherein each of the second plurality of semiconductor dies is electrically coupled to the subpackage substrate via at least one of the second plurality of vertical interconnects, and at least two of the second plurality of semiconductor dies are further electrically coupled to each other via the at least one horizontal interconnect; and a first plurality of vertical interconnects disposed on the back side of the package substrate and parallel to the embedded subpackage; and a solder bump attached to the first plurality of vertical interconnects.

2. The semiconductor package according to claim 1, wherein, Each of the first plurality of vertical interconnects includes at least one conductive via or at least one conductive post.

3. The semiconductor package according to claim 1, wherein, The semiconductor package further includes: an interconnect heat sink, the interconnect heat sink being in thermal contact with the at least one horizontal interconnect.

4. The semiconductor package according to claim 3, wherein, The interconnect heat sink includes thermally conductive vias embedded in the sub-package substrate and the package substrate.

5. The semiconductor package according to claim 1, wherein, Both the embedded sub-package and the first plurality of vertical interconnects are modularly pre-formed.

6. The semiconductor package according to claim 1, wherein, The semiconductor package further includes: a substrate, wherein the solder bumps are mounted on the substrate; and a base thermal interface material layer located between the substrate and the embedded subpackage, wherein the base thermal interface material layer is in thermal contact with the second plurality of semiconductor dies.

7. The semiconductor package according to claim 6, wherein, The semiconductor package further includes: a top thermal interface material layer located on the first plurality of semiconductor dies; and a top heat sink disposed on the top thermal interface material layer.

8. A method for forming a semiconductor package, wherein, The method includes: providing a first plurality of semiconductor dies and a second plurality of semiconductor dies; forming an embedded subpackage, including: forming a second plurality of vertical interconnects on the second plurality of semiconductor dies, the second plurality of vertical interconnects being electrically coupled to the second plurality of semiconductor dies; attaching at least one horizontal interconnect to the second plurality of semiconductor dies, wherein at least two of the second plurality of semiconductor dies are electrically connected to each other via the at least one horizontal interconnect; molding the second plurality of semiconductor dies, the second plurality of vertical interconnects, and the at least one horizontal interconnect; forming a subpackage substrate on the second plurality of semiconductor dies, the second plurality of vertical interconnects, and the at least one horizontal interconnect, wherein the second plurality of vertical interconnects are electrically coupled to the subpackage substrate, wherein each of the second plurality of semiconductor dies is electrically coupled to the subpackage substrate via at least one of the second plurality of vertical interconnects; forming a first plurality of vertical interconnects; molding the embedded subpackage and the first plurality of vertical interconnects, wherein the first plurality of vertical interconnects are parallel to the embedded subpackage; attaching solder bumps such that the solder bumps are electrically coupled to the first plurality of vertical interconnects; A package substrate is formed on the embedded subpackage and the first plurality of vertical interconnects, wherein the package substrate includes a front side and a back side, wherein the first plurality of vertical interconnects and the subpackage substrate of the embedded subpackage are attached to and electrically coupled to the back side of the package substrate; and the first plurality of semiconductor dies are disposed on the front side of the package substrate, wherein the first plurality of semiconductor dies are electrically coupled to the package substrate, and the first plurality of semiconductor dies are electrically coupled to each other through the embedded subpackage.

9. The method according to claim 8, wherein, Forming the first plurality of vertical interconnects includes: molding a plurality of conductive pillars; forming a redistribution layer on the plurality of conductive pillars, wherein the plurality of conductive pillars are electrically connected to the redistribution layer; and cutting the plurality of conductive pillars to obtain the first plurality of vertical interconnects.

10. The method according to claim 8, wherein, Forming a first plurality of vertical interconnects includes: forming a plurality of vias in a dielectric layer; filling the plurality of vias with a conductive material to form a plurality of conductive vias; forming a redistribution layer on the plurality of conductive vias, wherein the plurality of conductive vias are electrically connected to the redistribution layer; and cutting the plurality of conductive vias to obtain the first plurality of vertical interconnects.

11. The method according to claim 8, wherein, The method further includes: forming an interconnect heat sink, the interconnect heat sink being in thermal contact with the at least one horizontal interconnect.

12. The method according to request item 11, wherein, Forming an interconnect heat sink includes forming thermally conductive vias embedded in the sub-package substrate and the package substrate.

13. The method according to claim 8, wherein, The method further includes: providing a substrate; forming a base thermal interface material layer beneath the embedded subpackage; and mounting the solder bumps on the substrate, wherein the base thermal interface material layer is in thermal contact with the second plurality of semiconductor dies.

14. The method according to claim 13, wherein, The method further includes: forming a top thermal interface material layer on the first plurality of semiconductor dies; and disposing a top heat sink on the top thermal interface material layer.

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