Semiconductor device and method for making the same

Abstract

A method for separating a semiconductor substrate into individual semiconductor devices includes: providing a semiconductor substrate having a front side and a back side, wherein the semiconductor substrate includes a plurality of device regions separated from each other by respective predetermined dicings; forming an interconnect layer on the front side of the semiconductor substrate; etching the front side of the semiconductor substrate at the predetermined dicings to form respective front openings having a first depth, wherein the first depth is less than the thickness of the semiconductor substrate; attaching semiconductor elements to the front side of the semiconductor substrate in each device region; and etching the back side of the semiconductor substrate at the respective predetermined dicings to form respective back openings having a second depth, wherein the front openings are at least partially aligned with the back openings at the same dicing to separate the plurality of device regions of the semiconductor substrate into individual semiconductor devices.

Description

Technical Field

[0001] This application generally relates to semiconductor packaging technology, and more specifically, to a semiconductor device and a method for manufacturing the same. Prior Technology

[0002] The semiconductor industry has long faced the challenge of complex integration as consumers demand smaller, faster, and higher-performing electronics, and more and more functions are integrated into a single device. One solution is System-in-Package (SiP). A SiP is a functional electronic system or subsystem that comprises two or more heterogeneous semiconductor dies, such as logic chips, memory, integrated passive devices (IPDs), RF filters, sensors, heat sinks, or antennas.

[0003] Wafer-to-chip (C2W) packaging is widely used in optical devices, where a small wafer is attached to a larger wafer, which is then attached to a substrate. Optical devices may have waveguide regions where the small wafer and other components (e.g., copper pillars) are excluded. However, the need for such exclusion regions increases the difficulty of manufacturing optical devices.

[0004] Therefore, there is a need to provide a semiconductor device with an improved layout design. Summary of the Invention

[0005] One object of this application is to provide a semiconductor device with an improved layout design to facilitate the manufacture of semiconductor devices.

[0006] According to one aspect of this application, a method for separating a semiconductor substrate into individual semiconductor devices is provided. The method includes: providing a semiconductor substrate having a front side and a back side, wherein the semiconductor substrate includes a plurality of device regions separated from each other by respective predetermined dicings; forming an interconnect layer on the front side of the semiconductor substrate; etching the front side of the semiconductor substrate at the predetermined dicings to form respective front openings having a first depth, wherein the first depth is less than the thickness of the semiconductor substrate; attaching semiconductor elements to the front side of the semiconductor substrate in each device region; and etching the back side of the semiconductor substrate at the respective predetermined dicings to form respective back openings having a second depth, wherein the front openings are at least partially aligned with the back openings at the same dicing to separate the plurality of device regions of the semiconductor substrate into individual semiconductor devices.

[0007] According to another aspect of this application, a method for manufacturing a semiconductor device is provided. The method includes: providing a semiconductor substrate having a front side and a back side, wherein the semiconductor substrate includes a plurality of device regions separated from each other by respective predetermined dicings; forming an interconnect layer on the front side of the semiconductor substrate; etching the front side of the semiconductor substrate at the predetermined dicings to form respective front openings, the front openings having a first depth and a first width, wherein the first depth is less than the thickness of the semiconductor substrate, and the first width is less than the width of the corresponding predetermined dicing; attaching semiconductor elements to the front side of the semiconductor substrate in each device region; etching the back side of the semiconductor substrate at the respective predetermined dicings to form respective back openings, the back openings having a second depth and a second width, wherein the front openings are at least partially aligned with the back openings at the same dicing to separate the plurality of device regions of the semiconductor substrate into individual semiconductor devices, and forming steps at the edges of the respective semiconductor devices at the dicings; attaching the individual semiconductor devices to an external substrate via a first set of conductive pillars; and attaching auxiliary structures to the steps of each semiconductor device.

[0008] According to another aspect of this application, a semiconductor device is provided. The semiconductor device includes: a first semiconductor element having a front side and a back side opposite to the front side, wherein the first semiconductor element further includes: an active layer on the front side; a waveguide formed in the active layer and adjacent to a side of the interface layer; an interconnect layer on the active layer; a second semiconductor element attached to the interconnect layer; and a first set of conductive pillars on the interconnect layer, wherein the height of the first set of conductive pillars is greater than the height of the second semiconductor element; a substrate connected to the front side of the first semiconductor element via the first set of conductive pillars; and an auxiliary structure attached to an edge of the first semiconductor element, wherein the auxiliary structure includes an external waveguide aligned with the waveguide within the active layer.

[0009] It should be understood that the foregoing general description and the following detailed description are exemplary and illustrative only, and not intended to limit the invention. Furthermore, the drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. Simple Explanation of the Diagram

[0010] The drawings referenced herein form part of the specification. The features shown in the drawings illustrate only some embodiments of this application, and not all embodiments of this application, unless otherwise expressly stated in the detailed description, and the reader of the specification should not imply the contrary.

[0011] Figures 1A and 1B are schematic diagrams of semiconductor devices;

[0012] Figure 2 is a cross-sectional view illustrating a semiconductor device according to an embodiment of this application;

[0013] Figure 3 is a cross-sectional view illustrating a semiconductor device according to another embodiment of this application;

[0014] Figure 4 is a cross-sectional view showing a semiconductor device with an auxiliary structure according to another embodiment of this application;

[0015] Figure 5 is a flowchart illustrating a method for manufacturing a semiconductor device according to an embodiment of this application;

[0016] Figures 6A to 6I are cross-sectional views illustrating various steps of a method for manufacturing a semiconductor device according to embodiments of this application;

[0017] Figures 7A to 7G are cross-sectional views illustrating various steps of a method for manufacturing a semiconductor device according to yet another embodiment of this application;

[0018] Figures 8A and 8B are cross-sectional views of another exemplary semiconductor device manufactured using the methods in Figures 7A to 7G;

[0019] Figures 9A and 9B are cross-sectional views of another exemplary semiconductor device manufactured using the methods in Figures 7A to 7G;

[0020] Figures 10A to 10F are cross-sectional views illustrating various steps of a method for manufacturing a semiconductor device according to yet another embodiment of this application.

[0021] The same diagrammatic symbols will be used throughout the diagram to represent the same or similar parts. Implementation

[0022] The following detailed description of exemplary embodiments of this application refers to the drawings that form a part of the description. The drawings illustrate specific exemplary embodiments in which this application may be practiced. The detailed description, including the drawings, describes these embodiments in sufficient detail to enable those skilled in the art to practice this application. Those skilled in the art can further utilize other embodiments of this application and make logical, mechanical, and other changes without departing from the spirit or scope of this application. Therefore, the reader of the following detailed description should not interpret it in a limiting manner, and the scope of the embodiments of this application is limited only by the appended claims.

[0023] In this application, unless otherwise expressly stated, the singular is used to include the plural. In this application, unless otherwise stated, the use of "or" means "and / or". Furthermore, the use of the term "comprising" and other forms such as "including" and "containing" is not restrictive. Furthermore, unless otherwise expressly stated, terms such as "element" or "component" cover elements and components comprising one unit, as well as elements and components comprising more than one subunit. Moreover, the section headings used herein are for organizational purposes only and should not be construed as limiting the subject matter described.

[0024] As used herein, spatially relative terms such as “below,” “under,” “above,” “over,” “up,” “down,” “front,” “back,” “left,” “right,” “vertical,” “horizontal,” “side,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the diagrams. In addition to the directions depicted in the diagrams, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein may be interpreted accordingly. It should be understood that when an element is referred to as “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or there may be intermediate elements present.

[0025] Figures 1A and 1B are schematic diagrams illustrating the semiconductor device 100. Figure 1A shows the top surface of the semiconductor device 100, and Figure 1B shows a cross-sectional view of the semiconductor device 100 in Figure 1A along section line AA.

[0026] As shown in Figures 1A and 1B, the semiconductor device 100 includes a first semiconductor element 101 and a second semiconductor element 102 interconnected. Both the first semiconductor element 101 and the second semiconductor element 102 can be semiconductor dies. The first semiconductor element 101 is larger in size than the second semiconductor element 102 so that the semiconductor element 102 can be attached to the front side 101a of the first semiconductor element 101 via a set of conductive posts 104. Furthermore, the first semiconductor element 101 is attached to the substrate 105 via another set of conductive posts 103 of the second semiconductor element 102. A waveguide is formed on the front side 101a of the first semiconductor element 101, excluding the semiconductor element 102 from the waveguide region 101c used to form the waveguide. Thus, the waveguide region 101c is an exclusion region for the second semiconductor element 102 and the conductive posts 103, 104, thereby the front side 101a of the first semiconductor element 101 cannot be fully utilized for the circuitry of the first semiconductor element 101.

[0027] Figure 2 is a cross-sectional view showing a semiconductor device 200 according to an embodiment of the present application.

[0028] Referring to Figure 2, the semiconductor device 200 includes a first semiconductor element 201, such as a semiconductor die, and a substrate 205 on which the first semiconductor element 201 is mounted. The semiconductor substrate 205 may be a laminated interposer, a PCB, a wafer form, a strip interposer, a lead frame, or other suitable substrate. The substrate 205 may include one or more insulating or passivation layers, one or more conductive pathways formed through the insulating layers, and one or more conductive layers formed on or between the insulating layers. The substrate 205 may include one or more laminates of pre-impregnated polytetrafluoroethylene, FR-4, FR-1, CEM-1, or CEM-3, as well as compositions of phenolic cotton paper, epoxy resin, resin, glass fabric, frosted glass, polyester, or other reinforcing fibers or fabrics. The substrate 205 may also be a multilayer flexible laminate, ceramic, copper-clad laminate, glass, or a semiconductor wafer, the semiconductor wafer including an active surface containing one or more transistors, diodes, and other circuit elements to realize analog or digital circuitry. The substrate 205 may include one or more conductive layers or redistribution layers (RDLs) formed using sputtering, electroplating, electroless plating, or other suitable deposition processes. The conductive layers may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, Ti, W, or other suitable conductive materials.

[0029] As shown in FIG. 2, the first semiconductor element 201 includes a front side 201a and a back side 201b opposite to the front side 201a. In the embodiment of FIG. 2, the front side 201a faces the substrate 205, while the back side 201b faces away from the substrate 205. An active layer 206 is formed on the front side 201a, and a waveguide 208, for example, is formed within the active layer 206 and adjacent to the side surface of the active layer 206. The waveguide 208 can be exposed from the side surface of the active layer 206 for optical communication with an optical device (not shown) outside the semiconductor device 200. In some embodiments, the active layer 206 may include a dielectric layer on which the waveguide and other optical elements are formed, which may be a silicon oxide layer, a silicon nitride layer, a polymer layer, or a silicon-on-insulator layer. For example, the waveguide 208 can be formed by patterning a portion of the active layer 206. It is understood that the active layer 206 may include a semiconductor layer on which one or more active circuits are formed. For example, the active circuitry may include one or more optical detector arrays, one or more signal modulators, one or more amplifiers, one or more input / output circuits, and one or more power supplies. Furthermore, interconnect layer 207 may be formed on active layer 206. For example, interconnect layer 207 may be a redistribution layer (RDL). Details of interconnect layer 207 will be described in detail below. It is understood that conductive vias may be formed through active layer 206 to ensure the desired electrical connection between the first semiconductor element 201 and interconnect layer 207. It is understood that conductive vias may be formed on active layer 206 by drilling after interconnect layer 207 is formed.

[0030] A first semiconductor element 201 is attached to a substrate 205 via a first set of conductive posts 203. Specifically, a first end of the first set of conductive posts 203 is connected to an interconnect layer 207 of the first semiconductor element 201, and a second end of the first set of conductive posts 203 is connected to the top surface of the substrate 205. A second semiconductor element 202 is attached to the interconnect layer 207 via a second set of conductive posts 204, which is opposite to the first semiconductor element 201 and located between the first semiconductor element 201 and the substrate 205. It is understood that the interconnect layer 207 may have a conductive pattern facing the substrate 205, and multiple conductive vias and / or conductive interlayers within the interconnect layer 207. Therefore, the interconnect layer 207 enables the internal circuitry of the first semiconductor element 201 to be electrically connected to the second semiconductor element 202 via the second set of conductive posts 204, and to the substrate 205 via the first set of conductive posts 203. In addition, insulating material (e.g., underfill material) can be filled between the first semiconductor element 201 and the substrate 205 to provide protection and support for the conductive pillars 203, 204 and the second semiconductor element 202.

[0031] In this embodiment, the height of the first set of conductive pillars 203 is greater than the sum of the heights of the second semiconductor element 202 and the second set of conductive pillars 204, so that the second semiconductor element 202 does not need to contact the top surface of the substrate 205, thus not interfering with the attachment of the first semiconductor element 201 to the substrate 205. Although the semiconductor device 200 shown in FIG. 2 has only one second semiconductor element 202 located between the first semiconductor element 201 and the substrate 205, those skilled in the art will understand that the semiconductor device may include one or more second semiconductor elements. In some embodiments, the first semiconductor element 201 and the second semiconductor element 202 may include a digital signal processor (DSP), a microcontroller, a microprocessor, a network processor, a power management processor, an audio processor, a video processor, a radio frequency (RF) circuit, a wireless bandwidth system-on-a-chip (SoC) processor, a sensor, a memory controller, a storage device, a dedicated integrated circuit, etc. In some embodiments, the body layer between the front side 201a and the back side 201b of the first semiconductor element 201 may be silicon or other suitable semiconductor materials. In some embodiments, the first set of conductive pillars 203 and the second set of conductive pillars 204 may be copper pillars or other conductive pillars. An auxiliary structure (not shown) (e.g., an optical device) may be attached to the first semiconductor element 201 so that the external waveguide in the auxiliary structure can be aligned with the waveguide 208 in the active layer.

[0032] Figure 3 is a cross-sectional view showing a semiconductor device 300 according to another embodiment of this application.

[0033] As shown in Figure 3, unlike the semiconductor device 200 shown in Figure 2, the semiconductor device 300 has a step 310 at the edge of the first semiconductor element 301. The step 310 does not interfere with the circuitry formed within the first semiconductor element 301. For example, the step 310 may be formed adjacent to the front side of the first semiconductor element 301, away from the back side where the circuitry is formed. In the embodiment of Figure 3, the step may be close to the waveguide 308 formed within the active layer 306 of the first semiconductor element 301. Accordingly, the step 310 provides an anchoring area for auxiliary structures (not shown) (e.g., optical devices attached to the semiconductor device 300) so that the auxiliary structures can be more securely fixed to the semiconductor device 300. It is understood that one or more additional steps may be formed near the sides of the first semiconductor element 301. Furthermore, one or more steps may be used for attaching a single external device to the semiconductor device 300.

[0034] Figure 4 is a cross-sectional view showing a semiconductor device 400 with an auxiliary structure according to another embodiment of this application.

[0035] As shown in Figure 4, a first semiconductor element 401 is attached to a substrate 405 via a set of conductive posts. Furthermore, a second semiconductor element 402a and a third semiconductor element 402b are attached to the interconnect layer 407 of the first semiconductor element 401 via a second set of conductive posts 404. An auxiliary structure 411 is attached to a step formed on the first semiconductor element 401 via an adhesive 412 (e.g., UV-curable epoxy resin), and an external waveguide 413 within the auxiliary structure 411 can be aligned with an internal waveguide 408 within the first semiconductor element 401 (or specifically within the active layer of the first semiconductor element 401).

[0036] To manufacture one or more of the aforementioned semiconductor devices or similar devices, various methods are proposed according to some embodiments of this application. These methods can be implemented as wafer-to-wafer level processes, that is, various smaller semiconductor elements in the form of wafers or dies can be attached to a semiconductor wafer, which is then separated into multiple wafers, each wafer mounting one or more desired semiconductor elements. Figure 5 is a flowchart illustrating a method 500 for manufacturing a semiconductor device according to an embodiment of this application. For example, the semiconductor device 200 shown in Figure 2 can be manufactured using this method.

[0037] As shown in Figure 5, method 500 may begin at block 510, providing a semiconductor substrate. In block 520, an interconnect layer is formed on the semiconductor substrate. Subsequently, in block 530, a plurality of conductive pillars are formed on the interconnect layer. In block 540, the front side of the semiconductor substrate is etched at one or more predetermined cleavages without cutting through the semiconductor substrate. Next, in block 550, semiconductor elements can be attached to the semiconductor substrate. Finally, in block 560, the back side of the semiconductor substrate can be etched at the predetermined cleavages, thereby separating the semiconductor substrate into a plurality of individual semiconductor devices at the predetermined cleavages.

[0038] Figures 6A to 6I are cross-sectional views illustrating various steps of a method for manufacturing a semiconductor device according to embodiments of this application. Hereinafter, the method 500 of Figure 5 will be described in more detail with reference to Figures 6A to 6I.

[0039] As shown in Figure 6A, a semiconductor substrate 601 is provided. The semiconductor substrate 601 has a front side 601a, a back side 601b, and a body layer between the front side 601a and the back side 601b. Viewed from the top surface of the semiconductor substrate 601, the semiconductor substrate 601 may have one or more device regions 602 and one or more cleavages 603. It should be noted that, for illustrative purposes, only one cleavage is shown in Figure 6A, which divides the semiconductor substrate 601 into two device regions. However, when it is desired that there are more device regions 602 (which will later be separated into individual semiconductor devices), there may be multiple cleavages, such as two, three, or more cleavages. The cleavages 603 may be generally strip-shaped or other suitable shapes so that the semiconductor substrate 601 can be etched at the cleavages 603 using a knife or other separation method (e.g., plasma etching or reactive ion etching). In some embodiments, each strip-shaped cut can have a width ranging from 80 μm to 100 μm in the horizontal direction X shown in FIG6A, for example, 80 μm, 90 μm, or 100 μm.

[0040] The semiconductor substrate 601 also has an active layer 604 formed on the body layer and a waveguide 605 formed within the active layer 604. It is understood that the number of waveguides may correspond to the number of semiconductor devices formed from the substrate 601 such that each semiconductor device may have one waveguide 605. Each waveguide 605 may be located at the edge of a cleavage or the edge of the semiconductor substrate 601 so that the waveguide 605 can be exposed when the semiconductor substrate located at the cleavage is removed. The body layer of the semiconductor substrate 601 may have a thickness ranging from 600 μm to 1000 μm in the vertical direction Y shown in FIG. 6A, for example, 600 μm, 700 μm, 750 μm, 800 μm, 850 μm, 900 μm, or 1000 μm. The active layer 604 on the top surface of the body layer may have a thickness ranging from 6 μm to 12 μm, for example, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm, 11 μm, or 12 μm.

[0041] Next, referring to FIG. 6B, an active layer 604 is etched at the cleavage 603 to form an active window 604a for exposing the front side 601a of the semiconductor substrate 601, particularly the body layer. Each waveguide 605 in the active layer 604 is adjacent to or located at the edge of the cleavage 603, so that the waveguide 605 can be exposed from the side of the active layer 604 via the active window 604a. The active window 604a may have a width equal to or smaller than the width of the cleavage 603. In one example, the width of the cleavage 603 is 100 μm, and the width of the active window is 80 μm, which is smaller than the width of the cleavage 603. In some embodiments, the patterned active layer 604 (and certain other layers, such as the interconnect layer 606 shown in FIG. 6C, or other additional patterned photoresist layers) can be used as a mask for subsequent etching of the body layer using a deep reactive ion etching process.

[0042] Next, as shown in FIG6C, an interconnect layer 606 (e.g., a redistribution layer) may be formed on the front side 601a of the semiconductor substrate 601. It should be noted that the interconnect layer 606 may specifically be formed on the active layer 604. For example, the interconnect layer 606 may be deposited on the semiconductor substrate 601, and a portion (not shown) of the interconnect layer 606 in the active layer 604 may be removed. In some embodiments, the interconnect layer 606 may be deposited on the semiconductor substrate 601 before forming the active window 604a, and the subsequently deposited interconnect layer 606 and active layer 604 may be etched together to form the main layer active window 604a exposing the underlying semiconductor substrate 601. Furthermore, as shown in FIG6D, a first set of conductive pillars 607 electrically connected to the interconnect layer 606 may be formed in each device region 602.

[0043] Referring to Figure 6E, the front side 601a of the semiconductor substrate 601 is etched at the dicing 603 to form a front opening 608. The depth of the front opening 608 in the vertical direction Y is less than the height of the body layer of the semiconductor substrate 601. For example, the front side 601a can be formed using a deep reactive ion etching process at the active window. Later, in Figure 6F, one or more second semiconductor elements 609 and a second set of conductive pillars 610 are attached to each device region 602 of the semiconductor substrate 601. The height of the first set of conductive pillars 607 is greater than the height of the semiconductor element and / or the height of the second set of conductive pillars 610. That is, the topmost surface of the second semiconductor element shown in Figure 6F may not be higher than the top of the first set of conductive pillars 607.

[0044] Next, as shown in FIG6G, the semiconductor substrate 601 is flipped so that its back side 601b faces upward. Then, the back side 601b of the semiconductor substrate 601 is etched at the dicing 603 to form a back side opening 611 aligned with the front side opening 608. The sum of the depths of the front side opening 608 and the back side opening 611 in the vertical direction is equal to or greater than the height of the semiconductor substrate 601 (when there is an offset between the openings), so that the device region 602 of the semiconductor substrate 601 can be separated into individual semiconductor elements 612. In some embodiments, the back side 601b can be etched using a deep reactive ion etching process.

[0045] Subsequently, each individual semiconductor element 612 is attached to the substrate 613 via the first set of conductive posts 607, as shown in FIG6H. As shown in FIG6H, an underfill material 614 can be filled into the space between the semiconductor element 612 and the substrate 613 to seal the semiconductor element and the conductive posts. The underfill material 614 can be made of a polymer material, such as an epoxy resin with filler, an epoxy acrylate with filler, or a polymer with a suitable filler. This forms a semiconductor device 600, which includes a substrate 613 and at least two semiconductor elements directly or indirectly mounted on the substrate 613.

[0046] Furthermore, other methods are proposed according to embodiments of this application for manufacturing the stepped semiconductor device 400. Similarly, these methods can be implemented as a wafer-to-wafer level process, that is, various smaller semiconductor elements in the form of wafers or dies can be attached to a semiconductor wafer, which can then be separated into multiple wafers, each wafer mounting one or more desired semiconductor elements.

[0047] Figures 7A to 7G are cross-sectional views illustrating various steps of a method for manufacturing a semiconductor device 700 according to another embodiment of this application. Figures 7A to 7D and 7F show a semiconductor substrate 701, which is a variation of the semiconductor substrate 601 shown in Figures 6C to 6F in some steps of the method. Figure 7E is a partially enlarged view of a step at the edge of the semiconductor substrate 701 shown in Figure 7D, and Figure 7G is a cross-sectional view of a semiconductor device with an auxiliary structure mounted thereon.

[0048] As shown in Figures 7A and 7B, compared to the semiconductor substrate 601 in Figure 6E, the waveguide region of the active layer 706 is located within a cleavage 703. The semiconductor substrate 701 has one or more front openings 708 formed within each active window 704a on its front side, and the active window 704a is adjacent to the waveguide within the active layer 706 to expose the waveguide from the side. The active window 704a extends through the active layer 704 and the interconnect layer 706 on the substrate 701. The width of each front opening 708 can be 20% to 90% of the width of the cleavage 703 forming it. For example, the width of the front opening 708 can be 20%, 30%, 40%, 50%, 60%, 70%, 80%, or 90% of the width of the cleavage 703, which divides the substrate 701 into multiple device regions 702. In the embodiment shown in FIG7B, the width of the front opening 708 is 40% of the cut channel 703, i.e., 40 μm, and the front opening 708 can reach the edge of the cut channel 703 that is away from the waveguide region. In some embodiments, the front opening 708 may not reach the edge of the cut channel 703.

[0049] Next, in FIG. 7C, a second semiconductor element 709 is mounted on a separate device region 702 of the semiconductor substrate 701, and a front opening is formed at the dicing kerf by etching. Subsequently, in FIG. 7D, the semiconductor device 701 is flipped so that its back side faces upward. Subsequently, the back side of the semiconductor substrate 701 is further etched at the dicing kerf 703 to form a back opening 711. Referring to FIG. 7E, the width of the back opening 711 is smaller than the width of the dicing kerf 703, and the back opening 711 is offset relative to the front opening 708 at the dicing kerf 703. In this way, the semiconductor substrate 701 can be separated into individual semiconductor elements 712, and a step 714 can be formed at the edge of the corresponding semiconductor device 700 in FIG. 7F. In some embodiments, the width of the back opening 711 can be substantially equal to the dicing kerf. In some embodiments, for example, the width of the step 714 can be 10 μm, 20 μm, 30 μm, or 40 μm, which is less than the depth of the front opening 708.

[0050] It should be noted that active windows, front openings, and back openings can be cut using methods such as mechanical sawing, laser ablation, plasma etching, and reactive ion etching. In particular, plasma etching or reactive ion etching processes are preferred because these processes are clean and do not damage the semiconductor substrate.

[0051] Next, in Figure 7F, semiconductor element 712 can be attached to substrate 713 to form semiconductor device 700, and the space between semiconductor element 712 and substrate 713 can be filled with underfill material for encapsulation and protection purposes. Subsequently, auxiliary structure 715 can be attached to semiconductor device 700, particularly to step 714 of semiconductor device 700 in Figure 7G. For example, adhesive can be used at the step to attach auxiliary structure 715 to semiconductor device 700. Accordingly, step 714 provides an anchoring area for auxiliary structure (e.g., external optical device). Furthermore, optical region (e.g., waveguide region) within auxiliary structure 715 can be aligned with internal waveguide region of semiconductor device 700. It is understood that after alignment, there is no gap between auxiliary structure 715 and internal waveguide region of semiconductor device 700 for optical communication therein.

[0052] Figures 8A and 8B are cross-sectional views of another exemplary semiconductor device manufactured using the methods in Figures 7A to 7G. Figure 8B is a partially enlarged view of the step at the edge of the semiconductor element shown in Figure 8A.

[0053] As shown in Figure 8A, two device regions 802 can be separated by etching a front opening 808 and a back opening 811 at the dicing 803. Specifically, as shown in Figure 8B, the back opening 811 is adjacent to the edge of the dicing 803, while the front opening 808 is relatively far from the edge. The back opening 811 and the front opening 808 can have only a very small overlap. Because the depth of the back opening 811 and the front opening 808 is subsequently greater than the thickness of the device region 802, the semiconductor substrate can be separated into individual semiconductor elements. Furthermore, since the depth of the back opening 811 is less than the thickness of the device region, a step is formed at the edge of each semiconductor element.

[0054] Figures 9A and 9B are cross-sectional views of another exemplary semiconductor device manufactured using the methods in Figures 7A to 7G. Figure 9B is a partially enlarged view of the step at the edge of the semiconductor element shown in Figure 9A.

[0055] The semiconductor element shown in Figure 9A is similar to one of the semiconductor elements shown in Figure 7D. As shown in Figure 9A, the semiconductor substrate can be separated at a cleavage 903 between the two device regions 902. Furthermore, as shown in Figure 9B, the width of the back opening 911 formed by the separation is greater than the width of the front opening 908 formed at the active window 904a by other separation methods, and the front opening 908 is located horizontally within the back opening 911. The edges of the front opening 908 and the back opening 911 are misaligned to form two steps at the edges of the two separated semiconductor elements.

[0056] Figures 10A to 10F are cross-sectional views illustrating various steps of a method for manufacturing a semiconductor device 1000 according to yet another embodiment of this application. The embodiment shown in Figures 10A to 10F illustrates that an interconnect window 1006a may be formed through an interconnect layer 1006 for exposing an active layer 1004 of a semiconductor substrate 1001 at a cleavage 1003 between two device regions 1002.

[0057] Referring to Figure 10A, an interconnect window 1006a is formed at the interconnect layer 1006, and a waveguide 1005 in the active layer 1004 is partially located below the interconnect window 1006a.

[0058] Turning to Figure 10B, the semiconductor substrate 1001, including the active layer 1004, is etched to form a front opening 1008. The edge of the waveguide 1005 is adjacent to the front opening 1008 so that the waveguide 1005 can be exposed from the side of the active layer 1004 via the front opening 1008. The front opening 1008 can be etched using a dicing tool or plasma or reactive ion etching (as is widely used in photolithography processes, where patterned photoresist layers can be pre-formed on the active layer and interconnect layers). Because the front opening 1008 is within the interconnect window 1006a, the waveguide 1005 can be formed in the remaining portion of the active layer 1004 within the interconnect window 1006a.

[0059] Next, multiple second semiconductor elements can be mounted to the substrate 1001 at various device regions 1002 in FIG. 10C, and the semiconductor substrate 1001 is flipped so that its back side faces upward, as shown in FIG. 10D. The back side of the semiconductor substrate 1001 is etched at the dicing 1003 using the method shown in FIG. 7D to 7E to form a back side opening 1011. Thus, the waveguide portion is located at the step. Similarly, the back side opening 1011 is at least partially aligned with the front side opening 1008, and preferably has an offset in the horizontal direction.

[0060] Since the sum of the depths of the back opening and the front opening can be equal to or greater than the thickness of the semiconductor substrate, a semiconductor element 1012 with steps can be formed, as shown in FIG10E. The semiconductor element 1012 can then be mounted onto the substrate 1013 to form the semiconductor device in FIG10F. It can be seen that, in FIG10F, an auxiliary structure 1015 can be attached to the steps to obtain better connectivity.

[0061] This document includes numerous illustrative diagrams illustrating the various parts of a semiconductor device and their fabrication methods. For clarity, these diagrams do not show all aspects of each example element. Any example element and / or method provided herein may share any or all features with any or all other elements and / or methods provided herein.

[0062] Various embodiments have been described herein with reference to illustrations. However, it will be apparent that various modifications and changes can be made thereto, and other embodiments can be implemented without departing from the broader scope of the invention as set forth in the appended claims. Furthermore, other embodiments will be apparent to those skilled in the art upon consideration of the practice of one or more embodiments of the invention disclosed herein. Therefore, the embodiments in this application and herein are intended to be considered exemplary only, and the true scope and spirit of the invention are indicated by the list of exemplary claims appended.

[0063] 100: Semiconductor devices 101: First semiconductor element 101a: Front 101b: Back 101c: Waveguide region 102: Second semiconductor element 103: Conductive column 104: Conductive column 105: Base 200: Semiconductor devices 201: First Semiconductor Component 201a: Front 201b: Back 202: Second semiconductor element 203: Conductive post 204: Conductive post 205: Base 206: Active Layer 207: Interconnection Layer 208: Waveguide 300: Semiconductor Devices 301: First semiconductor element 305: Base 306: Active Layer 308: Waveguide 310: Steps 400: Semiconductor Devices 401: First semiconductor element 402a: Second semiconductor element 402b: Third Semiconductor Component 404: Conductive pillar 405: Base 406: Active Layer 407: Interconnect Layer 408: Internal waveguide 411: Auxiliary Structure 412: Adhesive 413: External waveguide 500: Methods 510, 520, 530, 540, 550, 560: Boxes 600: Semiconductor Devices 601: Semiconductor substrate 601a: Front 601b: Back 602: Device Area 603: Cutting Track 604: Active Layer 604a: Active Window 605: Waveguide 606: Interconnect layer 607: Conductive post 608: Front Opening 609: Second semiconductor element 610: Conductive post 611: Opening on the back 612: Semiconductor components 613: Base 614: Bottom Filling Material 700: Semiconductor Devices 701: Semiconductor substrate 702: Device Area 703: Cutting Track 704: Active Layer 704a: Active Window 706: Active Layer 708: Front Opening 709: Second semiconductor element 711: Opening on the back 712: Semiconductor Components 713: Base 714: Steps 715: Auxiliary Structure 802: Device Area 803: Cutting Track 804: Active Layer 804a: Active Window 808: Front Opening 811: Opening on the back 811: Opening 902: Device Area 903: Cutting Track 904: Active Layer 904a: Active Window 908: Front Opening 911: Opening on the back 1000: Semiconductor Devices 1001: Semiconductor substrate 1002: Device Area 1003: Cutting Track 1004: Active Layer 1005: Waveguide 1006: Interconnection Layer 1006a: Interconnected Windows 1006a: Interconnected Windows 1008: Front opening 1011: Opening on the back 1012: Semiconductor Components 1013: Base 1014: Steps 1015: Auxiliary Structure

Claims

1. A method for separating a semiconductor substrate into individual semiconductor devices, the method comprising: A semiconductor substrate having a front side and a back side is provided, wherein the semiconductor substrate includes a plurality of device regions separated from each other by a predetermined etch path; an active layer is formed on the front side of the semiconductor substrate; the active layer is etched at the predetermined etch path to form respective active windows, the active windows exposing the front side of the semiconductor substrate, wherein a waveguide is formed in the active layer of the respective device region and adjacent to the corresponding active window to expose the waveguide from the side; an interconnect layer is formed on the front side of the semiconductor substrate. The front side of the semiconductor substrate is etched at the predetermined dicing to form a front opening, the front opening having a first depth, wherein the first depth is smaller than the thickness of the semiconductor substrate; A semiconductor element is attached to the front side of the semiconductor substrate in each device area; And etching the back side of the semiconductor substrate at the predetermined dicing to form separate back side openings, the back side openings having a second depth, wherein the front side opening is at least partially aligned with the back side opening at the same dicing to separate multiple devices of the semiconductor substrate into individual semiconductor devices.

2. The method according to request item 1, wherein, After forming the interconnect layer, the method further includes: forming a first set of conductive pillars in each device region, the first set of conductive pillars being electrically connected to the interconnect layer of the device region, wherein the height of the first set of conductive pillars is greater than the height of the semiconductor element.

3. The method according to request item 1, wherein, The semiconductor substrate includes an active layer exposed from the front side and a body layer further below the active layer, and wherein etching the front side of the semiconductor substrate includes: patterning the active layer of the semiconductor substrate at the predetermined etch path to form respective active windows exposing the body layer; and etching the front side of the semiconductor substrate at the active windows using a deep reactive ion etching process.

4. The method according to request item 1, wherein, The width of each front opening is less than the width of the corresponding predetermined cutting channel.

5. The method according to request item 4, wherein, The width of the front opening is 20% to 90% of the width of the predetermined cutting channel.

6. The method according to claim 4, wherein, Each front opening is offset relative to the corresponding predetermined cutting path.

7. The method according to request item 1 or 6, wherein, The width of each back opening is substantially equal to the width of the corresponding predetermined cut.

8. The method according to request item 1, wherein, The first width of each front opening is less than the width of the corresponding predetermined dicing, the second width of each back opening is less than the width of the corresponding predetermined dicing, and each front opening is offset relative to the back opening at the same dicing to form a step at the edge of the corresponding semiconductor device at the dicing.

9. The method according to claim 8, wherein, Etching the front side of the semiconductor substrate includes: etching the front side of the semiconductor substrate using a deep reactive ion etching process; and etching the back side of the semiconductor substrate using a deep reactive ion etching process.

10. A method for manufacturing a semiconductor device, the method comprising: A semiconductor substrate having a front side and a back side is provided, wherein the semiconductor substrate includes a plurality of device regions separated from each other by a predetermined etch path; an active layer is formed on the front side of the semiconductor substrate; and the active layer is etched at the predetermined etch path to form respective active windows, the active windows exposing the front side of the semiconductor substrate, wherein a waveguide is formed in the active layer of the respective device region and adjacent to the corresponding active window to expose the waveguide from the side; an interconnect layer is formed on the front side of the semiconductor substrate. The front side of the semiconductor substrate is etched at the predetermined etch path to form respective front openings, the front openings having a first depth and a first width, wherein the first depth is smaller than the thickness of the semiconductor substrate, and the first width is smaller than the width of the corresponding predetermined etch path; a semiconductor element is attached to the front side of the semiconductor substrate in each device area. The back side of the semiconductor substrate is etched at the predetermined dicing to form separate back side openings having a second depth and a second width, wherein the front side opening is at least partially aligned with the back side opening at the same dicing to separate multiple devices of the semiconductor substrate into individual semiconductor devices, and a step is formed at the edge of the respective semiconductor device at the dicing; the individual semiconductor devices are attached to an external substrate via a first set of conductive pillars; and an auxiliary structure is attached to the step of each semiconductor device.

11. The method according to request item 10, wherein, After forming the interconnect layer, the method further includes: forming a first set of conductive pillars in each device region, the first set of conductive pillars being electrically connected to the interconnect layer of the device region, wherein the height of the first set of conductive pillars is greater than the height of the semiconductor element.

12. The method according to request item 10, wherein, The semiconductor substrate includes an active layer exposed from the front side and a body layer further below the active layer, and wherein etching the front side of the semiconductor substrate includes: patterning the active layer of the semiconductor substrate at the predetermined etch path to form a respective active window exposing the body layer; and etching the front side of the semiconductor substrate at the active window using a deep reactive ion etching process.

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