Offset compensated differential amplifier and calibration circuit providing increased linear range and granularity of offset compensation and related method

Abstract

A offset-compensated differential amplifier employing a multi-hop circuit is disclosed, comprising differential pairs coupled in parallel to compensate for offset voltages of the output voltage in offset-compensated calibration mode. Each differential pair includes a compensation transistor coupled to a positive internal node and a reference transistor coupled to a negative internal node. Each compensation transistor receives a compensation control voltage, and each reference transistor receives a different reference voltage. The multi-hop circuit generates offset compensation voltages at the positive and negative internal nodes based on the difference between the compensation control voltage and the different reference voltages. The multi-hop circuit exhibits a larger linear range compared to the hyperbolic tangent current transfer function of a single differential pair. The offset-compensated differential amplifier provides improved linearity and finer-grained offset compensation compared to conventional differential amplifiers.

Description

Technical Field

[0001] The technique disclosed herein relates to differential amplifiers and, in particular, to compensating for offsets in the input voltage of a differential amplifier. Prior Technology

[0002] A differential amplifier is a device that receives input signals and generates an output voltage based on the voltage difference between the input signals. Ideally, the output voltage of a differential amplifier is a multiple of the voltage difference between the input signals ("differential voltage"), where the multiple depends on the gain of the differential amplifier. The gain of the differential amplifier depends on the function of the differential amplifier in the circuit in which it is employed. It is desirable for the internal components of a differential amplifier to have certain performance characteristics, but variations in the manufacturing process used to produce these components can lead to variations in component characteristics. For example, the offset voltage is an inaccuracy in the amplifier output caused by variations in the performance characteristics of the internal components. When the voltage difference between the amplifier input signals is zero, the offset voltage can be considered a non-zero output voltage. Therefore, in a differential amplifier having an offset voltage V OFFSET, a gain G, a first input V 1, and a second input V 2, the amplifier's output voltage V OUT is equal to G·(V 1 - V 2 + V OFFSET). The offset voltage V OFFSET can be a positive or negative voltage. In a multi-stage differential amplifier, the offset voltage VOFFSET is the cumulative offset voltage of the corresponding stage. In circuits requiring high accuracy in the output voltage, detecting and compensating for the offset voltage is advantageous. Summary of the Invention

[0003] The exemplary embodiments disclosed herein include an offset-compensated differential amplifier and calibration circuitry that provide increased linear range and granularity of offset compensation. A method for offset compensation calibration in an offset-compensated differential amplifier is also disclosed. The compensation calibration circuitry for calibrating the offset compensation voltage in the differential amplifier employs a successive approximation register (SAR) analog-to-digital converter (ADC) to generate a binary value based on the output voltage of the differential amplifier in offset compensation calibration mode. The compensation calibration circuitry employs a digital-to-analog converter (DAC) to generate a compensation control voltage based on the binary value. In the exemplary embodiments, the offset-compensated differential amplifier employs a multi-hop circuitry comprising a plurality of differential pairs coupled in parallel to compensate for the offset voltage of the output voltage in offset compensation calibration mode.

[0004] Each of the multiple differential pairs includes a compensation transistor coupled to a positive internal node and a reference transistor coupled to a negative internal node. Each compensation transistor receives a compensation control voltage, and each reference transistor receives one of a plurality of different reference voltages. The multi-hop circuit generates offset compensation voltages at the positive and negative internal nodes based on the difference between the compensation control voltage and the plurality of different reference voltages. In each of the multiple differential pairs, the current transfer function of the current response to the voltage is a hyperbolic tangent (tanh) function with a short linear range. However, the sum of the current responses of the multiple differential pairs is linear over a large voltage range compared to the current responses of a single differential pair among the multiple differential pairs. The sum also has a lower rate of change over the linear voltage range compared to any one of the multiple differential pairs. Therefore, the offset-compensated differential amplifier provides improved linearity and finer-grained offset compensation compared to conventional differential amplifiers.

[0005] In an exemplary embodiment, an offset-compensated differential amplifier is disclosed, comprising a first amplifier stage, a second amplifier stage, and an offset compensation circuit. The first amplifier stage is configured to generate a first output differential voltage at a positive internal node and a negative internal node based on a primary differential voltage. The second amplifier stage is coupled to the positive internal node and the negative internal node and configured to generate an output voltage based on an intermediate differential voltage at the positive internal node and the negative internal node. The offset compensation circuit includes a first resistor configured to be coupled to a supply voltage node and a positive internal node, and a second resistor configured to be coupled to the supply voltage node and the negative internal node. The offset compensation circuit also includes a multi-hop circuit comprising a plurality of constant current sources and a plurality of differential pairs. Each of the plurality of differential pairs includes a compensation transistor configured to be coupled to the positive internal node and a current input of a corresponding constant current source among the plurality of constant current sources, the compensation transistor including a compensation control input configured to receive a compensation control voltage. Each of the plurality of differential pairs also includes a reference transistor configured to be coupled to the current input of a corresponding constant current source among the negative internal node and the plurality of constant current sources. The reference transistor includes a control input configured to receive one of the plurality of different reference voltages, wherein the plurality of differential pairs supply offset compensation voltages to the positive and negative internal nodes based on the compensation control voltage and the plurality of different reference voltages, and the intermediate differential voltage is based on the first output differential voltage and the offset compensation voltage.

[0006] In another exemplary embodiment, an offset-compensated differential amplifier system including an offset-compensated differential amplifier and a compensation calibration circuit is disclosed. The offset-compensated differential amplifier includes a positive main input and a negative main input. An offset-compensated differential amplifier including a first amplifier stage, a second amplifier stage, and offset compensation circuitry is disclosed. The first amplifier stage is configured to generate a first output differential voltage at a positive internal node and a negative internal node based on the main differential voltages at the positive and negative main inputs. The second amplifier stage is coupled to the positive and negative internal nodes and configured to generate an output voltage based on an intermediate differential voltage at the positive and negative internal nodes. The offset compensation circuitry includes a first resistor configured to be coupled to a supply voltage node and a positive internal node, and a second resistor configured to be coupled to the supply voltage node and the negative internal node. The offset compensation circuitry also includes a multi-hop circuitry comprising a plurality of constant current sources and a plurality of differential pairs. Each of the plurality of differential pairs includes a compensation transistor configured to be coupled to the current input of a corresponding constant current source among the plurality of constant current sources. The compensation transistor includes a compensation control input configured to receive a compensation control voltage. Each of the plurality of differential pairs also includes a reference transistor configured to be coupled to the current input of a corresponding constant current source among the plurality of constant current sources. The reference transistor includes a control input configured to receive one of a plurality of different reference voltages. The plurality of differential pairs supply offset compensation voltages to the positive and negative internal nodes based on the compensation control voltage and the plurality of different reference voltages, and the intermediate differential voltage is based on a first output differential voltage and the offset compensation voltage. The compensation calibration circuit includes a switch configured to electrically short-circuit the positive main input to the negative main input in response to an offset compensation calibration mode. The compensation calibration circuit includes a continuous approximation register (SAR) analog-to-digital converter (ADC) coupled to a second amplifier stage and configured to generate binary values ​​based on the output voltage in response to an offset compensation calibration mode. The compensation calibration circuit includes a digital-to-analog converter (DAC) configured to generate a compensation control voltage based on binary values.

[0007] In another exemplary embodiment, a method for compensating offset voltage in a differential amplifier is disclosed. The method includes generating a binary value in a Continuous Approximation Register (SAR) analog-to-digital converter (ADC) based on the output voltage of the differential amplifier in offset compensation calibration mode. The method includes generating a compensation control voltage in a digital-to-analog converter (DAC) over a range from a lower reference voltage to a higher reference voltage based on the binary value. The method includes coupling a first resistor to a supply voltage node and a positive internal node between a first amplifier stage and a second amplifier stage of the differential amplifier. The method includes coupling a second resistor to the supply voltage node and a negative internal node between the first amplifier stage and the second amplifier stage of the differential amplifier, the positive and negative internal nodes containing an intermediate differential voltage. The method includes coupling a plurality of differential pairs to the positive and negative internal nodes. The method of coupling each of the plurality of differential pairs includes coupling a reference transistor to the negative internal node and a constant current source, receiving one of a plurality of different reference voltages from a lower reference voltage to a higher reference voltage at a control input to the reference transistor. The method includes coupling a compensation transistor to a positive internal node and a constant current source, and receiving a compensation control voltage generated in a DAC at the control input of the compensation transistor. The method also includes providing offset compensation voltages to the positive and negative internal nodes via a plurality of differential amplifiers based on the output voltage of a differential amplifier in response to an offset compensation calibration mode. Simple Explanation of the Diagram

[0008] Several aspects of this disclosure are illustrated in the accompanying drawings, which are incorporated in and form part of this specification, and together with the description, serve to explain the principles of this disclosure.

[0009] Figure 1 is a schematic diagram of a conventional automatic calibration operational amplifier system used to mitigate offset voltage;

[0010] Figure 2 is a schematic diagram providing a more detailed description of the automatic calibration operational amplifier system in Figure 1;

[0011] Figure 3 is a graph of the voltage-to-current transfer function of the differential pair over the voltage range supplied to the gate of the transistor in the differential pair;

[0012] Figure 4 is a schematic diagram of an exemplary offset-compensated differential amplifier system including a compensation calibration circuit and an offset-compensated differential amplifier employing an offset compensation circuit, which includes a multi-hop circuit to provide an increased linear range and finer granularity of offset voltage compensation compared to the system in Figure 1;

[0013] Figure 5 is a graph of the voltage-to-current transfer function of a complex number of differential pairs in a multi-hop circuit over the voltage range supplied to the gate of the transistor in the differential pair;

[0014] Figures 6A and 6B are flowcharts illustrating an exemplary process for compensating offset voltage in a differential amplifier based on the exemplary differential amplifier and offset compensation circuit of Figure 4;

[0015] Figure 7 is a schematic diagram of an exemplary offset-compensated differential amplifier system, including coupling capacitors and general-mode voltage control, as shown in Figure 4; and

[0016] Figure 8 is a block diagram of an exemplary processor-based system including a plurality of devices coupled to a system bus, and any of such devices may include an offset-compensated differential amplifier as shown in Figure 4, which includes an offset compensation circuit employing a multi-hop circuit for accumulating an increased linear range of offset voltage and finer granular compensation. Implementation

[0017] The exemplary embodiments disclosed herein include an offset-compensated differential amplifier and calibration circuitry that provide increased linear range and granularity of offset compensation. A method for offset compensation calibration in the offset-compensated differential amplifier is also disclosed. The compensation calibration circuitry for calibrating the offset compensation voltage in the differential amplifier employs a successive approximation register (SAR) analog-to-digital converter (ADC) to generate a binary value based on the output voltage of the differential amplifier in offset compensation calibration mode. The compensation calibration circuitry employs a digital-to-analog converter (DAC) to generate a compensation control voltage based on the binary value. In the exemplary embodiments, the offset-compensated differential amplifier employs a multi-hop circuitry comprising a plurality of differential pairs coupled in parallel to compensate for the offset voltage of the output voltage in offset compensation calibration mode.

[0018] Each of the multiple differential pairs includes a compensation transistor coupled to a positive internal node and a reference transistor coupled to a negative internal node. Each compensation transistor receives a compensation control voltage, and each reference transistor receives one of a plurality of different reference voltages. The multi-hop circuit generates offset compensation voltages at the positive and negative internal nodes based on the difference between the compensation control voltage and the plurality of different reference voltages. In each of the multiple differential pairs, the current transfer function of the current response to the voltage is a hyperbolic tangent (tanh) function with a short linear range. However, the sum of the current responses of the multiple differential pairs is linear over a large voltage range compared to the current responses of a single differential pair among the multiple differential pairs. The sum also has a lower rate of change over the linear voltage range compared to any one of the multiple differential pairs. Therefore, the offset-compensated differential amplifier provides improved linearity and finer-grained offset compensation compared to conventional differential amplifiers.

[0019] Figure 1 illustrates an auto-calibrating operational amplifier (op-amp) system 100 configured to compensate for the op-amp output voltage VOUT generated by op-amp 102 in order to mitigate the effect of the offset voltage VOFFSET of op-amp 102. The offset voltage VOFFSET can be attributed to a shift (e.g., uniform displacement in one direction) caused by manufacturing process variations through changes in the internal components of op-amp 102. These variations cause the op-amp output voltage VOUT to be positively or negatively offset. When the input voltage to op-amp 102 is 0 volts, the instance of offset voltage VOFFSET is a non-zero op-amp output voltage VOUT.

[0020] Op-amp 102 includes a main differential input 104 that receives the positive main input voltage VIP P and the negative main input voltage VIP N. The main differential voltage VPD (=VIP P - VIP N) is received at the main differential input 104 for amplification by op-amp 102. Figure 1 illustrates a discrete offset voltage source, VOFFPRI, at the positive main input voltage VIP P of the main differential input 104. If the main differential input 104 is the only input to op-amp 102, then the op-amp output voltage VOUT will be equal to G·(VPD + VOFFPRI) or G·(VIP P - VIP N + VOFFPRI), where G is the gain of op-amp 102. Therefore, both the offset voltage VOFFPRI and the main differential voltage VPD are amplified by the gain G.

[0021] To increase the accuracy of the op-amp output voltage VOUT, components are needed to mitigate the offset voltage VOFFPRI. In this regard, the op-amp 102 also includes a secondary differential input 106, which includes a positive secondary input voltage VIS P and a negative secondary input voltage VIS N. A secondary differential voltage VSD is received at the secondary differential input 106 to compensate for the offset voltage VOFFPRI. However, an offset voltage VOFFSEC may also exist at the secondary differential input 106. Figure 1 illustrates the offset voltage VOFFSEC as a discrete source on the positive secondary input voltage VIS P. Therefore, the op-amp output voltage VOUT is determined by: GA·(VPD+VOFFPRI)+GB·(VSD+VOFFSEC), where GA is the gain relative to the primary differential input 104 and GB is the gain relative to the secondary differential input 106. From this equation, it can be seen that the secondary differential voltage VSD can be adjusted to compensate for the offset voltage VOFFSET, which includes the effects of both the offset voltage VOFFPRI at the primary differential input 104 and the offset voltage VOFFSEC at the secondary differential input 106. The op-amp output voltage VOUT can be made more accurate (e.g., closer to GA·VPD) by supplying an appropriate secondary differential voltage VSD as the difference between the positive secondary input voltage VIS P and the negative secondary input voltage VIS N.

[0022] There exists a range of variation in the offset voltage VOFFSET based on manufacturing process variations, and a corresponding range of the secondary differential voltage VSD required for compensation. The automatic calibration op-amp system 100 to compensate for the offset voltage VOFFSET may include supplying a positive secondary input voltage VISP as a constant value and supplying a negative secondary input voltage VISN in the range between a lower reference voltage VREFL and a higher reference voltage VREFH to achieve the desired range of the secondary differential voltage VSD. An intermediate voltage between the lower reference voltage VREFL and the higher reference voltage VREFH is used as the average reference voltage VREFAVG (i.e., (VREFH-VREFL) / 2) supplied to the constant value of the positive secondary input voltage VISP. Therefore, the secondary differential voltage VSD can vary between VREFL-VREFAVG and VREFH-VREFAVG. The lower reference voltage VREFL and the higher reference voltage VREFH can be set according to the desired process variations.

[0023] The automatic calibration op-amp system 100 includes a successive approximation register (SAR) analog-to-digital converter (ADC) circuit (referred to herein as "SAR ADC") 108 and a digital-to-analog converter (DAC) 110 to automatically calibrate the negative secondary input voltage VIS N required for compensating the offset voltage VOFFSET. Before describing the operation of the SAR ADC 108 used to generate the negative secondary input voltage VIS N, details of the DAC 110 are first provided. Referring to Figure 1, the DAC 110 includes an input VHIGH for receiving a higher reference voltage VREFH and an input VLOW for receiving a lower reference voltage VREFL. The DAC 110 also includes digital inputs D0-D7 for receiving a binary value VBIN, which has multiple bits generated by the SAR ADC 108. The DAC 110 generates a compensation control voltage VCTL based on the digital inputs D0-D7 as the supply voltage for the negative secondary input voltage VIS N. In this example, the digital inputs D0-D7 indicate an eight (8)-bit binary value VBIN, where D0 is the most significant bit (MSB) and D7 is the least significant bit (LSB). Although eight (8) bits D0-D7 are used in the example in Figure 1, the DAC 110 can be operated with any number of X+1 digital inputs D0-DX, depending on the offset voltage VOFFSET, the desired compensation control voltage VCTL, and the noise in the main differential voltage VPD.

[0024] The compensation control voltage VCTL is set based on one of 28 = 256 increments in the range of digital inputs D0-D7 from the lower reference voltage VREFL to the higher reference voltage VREFH. For example, in response to the binary value "00000000" (i.e., the Arabic numeral "0") on digital inputs D0-D7, DAC 110 generates a compensation control voltage VCTL equal to the lower reference voltage VREFL. In response to the binary value "11111111" (i.e., the Arabic numeral "255") on digital inputs D0-D7, DAC 110 generates a compensation control voltage VCTL equal to the higher reference voltage VREFH. In response to the binary value "10000000" (i.e., the Arabic numeral "128") on digital inputs D0-D7, DAC 110 generates a compensation control voltage VCTL approximately equal to the average reference voltage VREFAVG.

[0025] Referring again to Figure 1, the SAR ADC 108 includes an input VCMP that receives the op-amp output voltage VOUT, which is based on a comparison of the primary differential input 104. The SAR ADC 108 also includes a CLOCK input for receiving a CLOCK signal and a VSTART input for receiving a START signal. The SAR ADC 108 generates binary values ​​VBIN for the digital inputs D0-D7 of the DAC 110. The SAR ADC 108 also includes a DONE output that generates a DONE signal, indicating the completion of the process of converting the op-amp output voltage VOUT into the binary value VBIN to compensate for the offset voltage VOFFSET.

[0026] As mentioned above, op-amp 102 generates an op-amp output voltage VOUT = GA·(VPD + VOFFPRI) + GB·(VSD + VOFFSEC). Switch 112 electrically shorts the main differential input 104, thereby setting the main differential voltage VPD to 0 volts for calibration mode. Switch 112 can be activated to the SAR ADC 108, for example, by a START signal. In this mode, the op-amp output voltage VOUT = (GA·VOFFPRI) + GB·(VSD + VOFFSEC). Therefore, although VPD = 0, the op-amp output voltage VOUT is based solely on the cumulative effect of the secondary differential voltage VSD and the offset voltages VOFFPRI and VOFFSEC (i.e., the offset voltage VOFFSET). In this respect, the secondary differential voltage VSD required to compensate the offset voltage VOFFSET during offset compensation calibration mode can be calibrated from the op-amp output voltage VOUT.

[0027] Calibrling the secondary differential voltage VSD includes setting a compensation control voltage VCTL, which in turn includes adjusting the binary value VBIN provided to the DAC 110 by the SAR ADC 108. In response to the START signal, the SAR ADC 108 calibrates the binary value VBIN to compensate for the offset voltage VOFFSET at a rate of one bit per CLOCK signal cycle over multiple consecutive cycles of the CLOCK signal.

[0028] After the START signal is activated, calibration begins without any offset voltage compensation in the first cycle of the CLOCK signal. In this regard, the SAR ADC 108 generates a binary value VBIN to set the secondary differential voltage VSD to 0 volts. As understood from the equations above, when the secondary differential voltage VSD = 0 volts (and the primary differential voltage VPD = 0), the op-amp output voltage VOUT is determined solely by the offset voltage VOFFSET. Setting the secondary differential voltage VSD to 0 volts involves setting the negative secondary input voltage VISN to the average reference voltage VREFAVG, since the positive secondary input voltage VISP was previously set to the average reference voltage VREFAVG. Setting the negative secondary input voltage VISN to the average reference voltage VREFAVG (via the compensation control voltage VCTL of DAC 110) involves the SAR ADC 108 setting the binary value VBIN to "10000000" (i.e., the Arabic numeral "128"). The binary value VBIN "10000000" is at the midpoint of the range of binary value VBIN, and therefore will cause DAC 110 to generate a compensation control voltage VCTL in the middle between the lower reference voltage VREFL and the higher reference voltage VREFH (that is, at the average reference voltage VREFAVG).

[0029] For illustrative purposes, the calibration of the automatic calibration op-amp system 100 will be further described with reference to an example, where the higher reference voltage VREFH corresponding to the binary value VBIN "11111111" is +12.8 mV, and the lower reference voltage VREFL corresponding to the binary value VBIN "00000000" is -12.8 mV. Thus, in this example, the average reference voltage VREFAVG corresponding to the binary value VBIN "10000000" is approximately 0 volts, and each increment of the binary value VBIN corresponds to an increase of 0.1 mV in the compensation control voltage VCTL. Furthermore, it is assumed that the secondary differential voltage VSD requires +4.5 mV to compensate for the offset voltage VOFFSET in this example.

[0030] In the first loop following the START signal, according to this example, the SAR ADC 108 compares the op-amp output voltage VOUT with 0 volts, which is the expected value of the op-amp output voltage VOUT when both the primary differential voltage VPD and the secondary differential voltage VSD are set to 0 volts. This comparison is used to determine whether the VOFFSET offset voltage is positive or negative in the absence of any compensation. If the SAR ADC 108 determines that the op-amp output voltage VOUT is less than 0 volts, then the SAR ADC 108 holds the first digital input D0 at "1" because a positive compensation control voltage VCTL is required. Otherwise, the first digital input D0 is set to "0". In this example, as previously mentioned, the secondary differential voltage VSD needs to be 4.5 mV to compensate for the negative offset voltage VOFFSET (less than 0 volts). Therefore, the first digital input D0 will be held at "1".

[0031] In the second cycle of the CLOCK signal following the START signal, the SAR ADC 108 sets the next digital input D1 to "1", making the binary value VBIN = "11000000". In response, the DAC 110 generates a compensation control voltage VCTL (approximately +6.4 mV) between the average reference voltage VREFAVG and the higher reference voltage VREFH. With 6.4 mV supplied to the negative secondary input voltage VISN and the 0-volt average reference voltage VREFAVG supplied to the positive secondary input voltage VISP, the secondary differential voltage VSD = +6.4 mV. The SAR ADC 108 again compares the op-amp output voltage VOUT with 0 volts to determine whether to compensate for the offset voltage VOFFSET. In this case, the 6.4 mV secondary differential voltage VSD exceeds the amount required to compensate for the negative offset voltage VOFFSET. Therefore, the SAR ADC 108 determines that the op-amp output voltage VOUT is greater than 0 volts and that the digital input D1 is reset and will remain at "0".

[0032] In the third cycle of the CLOCK signal following the START signal, the SAR ADC 108 sets the next digital input D2 to "1", making the binary value VBIN = "10100000". In response, the DAC 110 generates a compensation control voltage of approximately +3.2 mV, and the SAR ADC 108 again compares the op-amp output voltage VOUT with 0 volts to determine whether to compensate for the offset voltage VOFFSET. In this case, the 3.2 mV secondary differential voltage VSD is insufficient to compensate for the negative offset voltage VOFFSET. Therefore, the SAR ADC 108 determines that the op-amp output voltage VOUT is less than 0 volts and the digital input D2 will remain at "1".

[0033] In the fourth cycle of the CLOCK signal following the START signal, the SAR ADC 108 sets the next digital input D3 to "1", making the binary value VBIN = "10110000". In response, the DAC 110 generates a compensation control voltage of approximately +4.8 mV, and the SAR ADC 108 again compares the op-amp output voltage VOUT with 0 volts to determine whether to compensate for the offset voltage VOFFSET. In this case, the secondary differential voltage VSD of 4.8 mV exceeds the compensation required for the negative offset voltage VOFFSET. Therefore, the SAR ADC 108 determines that the op-amp output voltage VOUT is greater than 0 volts and the digital input D3 is reset and will remain at "0".

[0034] In the fifth cycle of the CLOCK signal following the START signal, the SAR ADC 108 sets the next digital input D4 to "1", making the binary value VBIN = "10101000". In response, the DAC 110 generates a compensation control voltage of approximately +4.0 mV, and the SAR ADC 108 again compares the op-amp output voltage VOUT with 0 volts to determine whether to compensate for the offset voltage VOFFSET. In this case, the secondary differential voltage VSD of 3.2 mV is insufficient to compensate for the negative offset voltage VOFFSET. Therefore, the SAR ADC 108 determines that the op-amp output voltage VOUT is less than 0 volts, and the digital input D4 will remain at "1".

[0035] In the sixth cycle of the CLOCK signal following the START signal, the SAR ADC 108 sets the next digital input D5 to "1", making the binary value VBIN = "10101100". In response, the DAC 110 generates a compensation control voltage of approximately +4.4 mV, and the SAR ADC 108 again compares the op-amp output voltage VOUT with 0 volts to determine whether to compensate for the offset voltage VOFFSET. In this case, the 4.4 mV secondary differential voltage VSD is insufficient to compensate for the negative offset voltage VOFFSET. Therefore, the SAR ADC 108 determines that the op-amp output voltage VOUT is less than 0 volts, and the digital input D5 will remain at "1".

[0036] In the seventh cycle of the CLOCK signal following the START signal, the SAR ADC 108 sets the next digital input D6 to "1", making the binary value VBIN = "10101110". In response, the DAC 110 generates a compensation control voltage of approximately +4.6 mV, and the SAR ADC 108 again compares the op-amp output voltage VOUT with 0 volts to determine whether to compensate for the offset voltage VOFFSET. In this case, the secondary differential voltage VSD of 4.6 mV exceeds the compensation required for the negative offset voltage VOFFSET. Therefore, the SAR ADC 108 determines that the op-amp output voltage VOUT is greater than 0 volts, and the digital input D6 is reset and will remain at "0".

[0037] In the eighth cycle (final calibration cycle) of the CLOCK signal following the START signal, the SAR ADC 108 sets the next digital input D7 to "1", making the binary value VBIN = "10101101". In response, the DAC 110 generates a compensation control voltage of approximately +4.5 mV, and the SAR ADC 108 again compares the op-amp output voltage VOUT with 0 volts to determine whether to compensate for the offset voltage VOFFSET. In this case, the 4.5 mV secondary differential voltage VSD is the correct amount required to compensate for the negative offset voltage VOFFSET. Therefore, the SAR ADC 108 determines that the op-amp output voltage VOUT is not less than 0 volts, and the digital input D7 will remain at "1". The SAR ADC 108 also includes a DONE output that generates a DONE signal, indicating that the process of converting the op-amp output voltage VOUT into the binary value VBIN to compensate for the offset voltage VOFFSET is complete. In other words, the offset compensation calibration mode begins with the START signal and ends with the DONE signal.

[0038] A more detailed discussion of the internal characteristics of the SAR ADC 108 and DAC 110 is beyond the scope of this disclosure and is not provided herein. However, a more detailed description of the op-amp 102 is presented with reference to the description of the automatic calibration op-amp system 100 in Figure 2. The op-amp 102 includes a first amplifier stage 202 that receives the main differential voltage VPD on the main differential input 104. The offset voltage VOFFPRI is a discrete voltage source on the positive main input voltage VIP P of the first amplifier stage 202. The first amplifier stage 202 generates an output differential voltage VOD1 at the positive internal node 204P and the negative internal node 204N, which are collectively referred to herein as internal differential nodes 206. The output differential voltage VOD1 generated by the first amplifier stage 202 at the internal differential nodes 206 is based on G1·(VPD+VOFFPRI), where G1 is the gain of the first amplifier stage 202.

[0039] Op-amp 102 includes a differential pair 208, which includes a compensation transistor 210P coupled to the positive internal node 204P and a reference transistor 210N coupled to the negative internal node 204N. Both the compensation transistor 210P and the reference transistor 210N are coupled to a constant current source 212 providing a constant current I 212. The positive secondary input voltage VIS P and the negative secondary input voltage VIS N are coupled to and control the gates 214PG and 214NG of the compensation transistor 210P and the reference transistor 210N, respectively. As mentioned above, the offset voltage VOFFSEC is a discrete voltage source on the positive secondary input voltage VIS P. The op-amp 102 also includes resistors R1, R2 and R3, which are coupled to VDD to establish the common mode voltages of the positive and negative internal nodes 204P and 204N and to provide separate current paths 216P and 216N to the compensation transistor 210P and the reference transistor 210N to the differential pair 208.

[0040] Referring again to Figure 2, op-amp 102 also includes a second amplifier stage 218, which includes inputs 220P and 220N coupled to the positive and negative internal nodes 204P and 204N, respectively. The second amplifier stage 218 generates an output differential voltage VOD2 based on an intermediate differential voltage VID2 across the inputs 220P and 220N. The output differential voltage VOD2 = G2·VID2, where G2 is the gain of the second amplifier stage 218. op-amp 102 also includes a differential-to-single-ended voltage converter 220 to convert the output differential voltage VOD2 into an op-amp output voltage VOUT. The output differential voltage VOD2 can also be used to connect to external circuitry (not shown) at the positive output voltage VOUTP and the negative output voltage VOUTN.

[0041] The output differential voltage VOD1, resistors R1, R2, R3, and each of the differential pair 208 contribute to the intermediate differential voltage VID2 on the internal differential node 206. In calibration mode, the output differential voltage VOD1 = G1·V OFFPRI, because the primary differential voltage VPO is set to 0 volts. The differential pair 208 is controlled by the secondary differential voltage VSD. The average reference voltage VREFAVG and the offset voltage VOFFSEC are constant voltages supplied to the gate 214NG of the reference transistor 210N. Therefore, the offset voltage VOFFSET in the compensated op-amp output voltage VOUT is provided by the compensation control voltage VCTL supplied to the gate 214PG of the compensation transistor 210P.

[0042] Figure 3 shows a graph of the current ID1 passing through the compensation transistor 210P in Figure 2 as a percentage of the constant current I 212 in the constant current source 212, over the range of the secondary differential voltage VSD. That is, the constant current I 212 comprises the current ID1 passing through the compensation transistor 210P and the current ID2 passing through the reference transistor 210N. The percentage of the constant current I 212 provided by current ID1 depends on the polarity and magnitude of the difference between the compensation control voltage V CTL supplied to the gate 214PG and the average reference voltage V REFAVG supplied to the gate 214NG. Depending on whether current ID1 or current ID2 provides the larger percentage of the constant current I 212, the differential pair 208 applies offset compensation to adjust the output differential voltage VOD1 to compensate for the offset voltage V OFFSET.

[0043] The curve in Figure 3 illustrates that the rate of change of current ID1 is linear when the secondary differential voltage VSD is close to a positive or negative value of 0 volts, thus indicating linear transconductance. Specifically, between points A1 and A2, the graph of current ID1 approximates a straight line with a slope SID1. However, in the nonlinear region 302, which includes voltages above point A1 and below point A2, the linearity of ID1 decreases. The absence of a linear graph of current ID1 indicates nonlinearity, meaning that the change in compensation provided to the op-amp output voltage VOUT for the change in secondary differential voltage VSD is not constant. Nonlinearity regarding the effect of the compensation control voltage VCTL reduces the accuracy of offset voltage compensation. Therefore, a wider range of linearity for offset voltage compensation is preferable. The automatic calibration op-amp system 100 in Figures 1 and 2 is limited in its linear range to the range of secondary differential voltage VSD corresponding to points A1 and A2.

[0044] Another significant feature of the ID1 curve is the slope SID1 in the linear range between points A1 and A2. The slope SID1 indicates the granularity of the compensation provided to the op-amp output voltage VOUT. That is, for each incremental change in the compensation control voltage VCTL, there is a certain amount of change in the current ID1, which in turn produces a certain amount of change in the op-amp output voltage VOUT. A finer granularity makes it possible to compensate the op-amp output voltage VOUT with respect to the offset voltage VOFFSET with higher accuracy, thereby increasing the accuracy of op-amp 102. The automatic calibration op-amp system 100 in Figures 1 and 2 is also limited in the slope of the voltage-to-current transfer function with respect to the differential pair 208 because it is better to provide offset voltage compensation in op-amp 102 with a finer granularity compared to that available in the automatic calibration op-amp system 100.

[0045] Figure 4 is a schematic diagram of an exemplary offset-compensated differential amplifier system 400 including an offset-compensated differential amplifier (“diff-amp”) 402 and a compensation calibration circuit 403. The diff-amp 402 includes an offset compensation circuit 404 that employs a multi-hop circuit 406 to provide offset voltage compensation with increased linear range and finer granularity compared to the automatic calibration op-amp system 100 of Figures 1 and 2.

[0046] The offset compensation circuit 404 includes a SAR ADC 408, a DAC 410, and a switch 412, which includes inputs and outputs corresponding to the SAR ADC 108, DAC 110, and switch 112 of the auto-calibration op-amp system 100 in Figure 1, and similarly in all other configurations. In the offset compensation differential amplifier system 400, the SAR ADC 408, DAC 410, and switch 412 operate in calibration mode to calibrate the compensation control voltage VCTL' to compensate for the offset voltage VOFFSET' included in the diff-amp output voltage VOUT' in Figure 4. The diff-amp output voltage VOUT' is the voltage difference between the positive output voltage VOUTP and the negative output voltage VOUTN. The offset voltage VOFFSET' is considered to be the response to the zero primary differential voltage VPD's non-zero voltage difference between the positive output voltage VOUTP and the negative output voltage VOUTN. Due to the difference between the offset-compensated differential amplifier system 400 in Figure 4 and the auto-calibrating operational amplifier (op-amp) system 100 in Figures 1 and 2, the compensation control voltage VCTL', offset voltage VOFFSET', and diff-amp output voltage VOUT' in Figure 4 differ from those in Figures 1 and 2. Switch 412, in response to offset-compensated calibration mode, electrically shorts the positive primary input VIPP to the negative primary input voltage VIPN. In this respect, the SAR ADC 408, DAC 410, and switch 412 operating in calibration mode operate according to the description provided above regarding the SAR ADC 108, DAC 110, and switch 112 for calibrating the compensation control voltage VCTL in Figure 1. Therefore, no further explanation is provided herein for the SAR ADC 408, DAC 410, or switch 412.

[0047] The diff-amp 402 includes a first amplifier stage 413 and a second amplifier stage 414. The diff-amp 402 may be an operational amplifier. A primary differential voltage VPD is supplied to the first amplifier stage 413. Specifically, the first amplifier stage 413 includes a positive primary input voltage VIP P and a negative primary input voltage VIP N that receive the primary differential voltage VPD. The offset voltage VOFFPRI between the positive primary input voltage VIP P and the negative primary input voltage VIP N is represented as a discrete offset voltage VOFFPRI. A compensation control voltage VCTL' is adjusted to compensate for the offset voltage VOFFSET' based on the offset voltage VOFFPRI on the positive primary input voltage VIP P and the offset voltage VOFFSEC' on the positive secondary input voltage VIS P.

[0048] The first amplifier stage 413 generates an output differential voltage VOD1 at the positive internal node 416P and the negative internal node 416N based on the primary differential voltage VPD and the first offset voltage VOFFPRI. The second amplifier stage 414 is coupled to the positive internal node 416P and the negative internal node 416N generates a diff-amp output voltage VOUT' based on the intermediate differential voltage VID2' at the positive internal node 416P and the negative internal node 416N. Due to the operation of the offset compensation circuit 404, the intermediate differential voltage VID2' in Figure 4 differs from the intermediate differential voltage VID2 in Figure 2. In the exemplary configuration, the offset compensation circuit 404 includes a multi-hop circuit 406 and resistors R1, R2, and R3 coupled to the positive internal node 416P and the negative internal node 416N. The offset voltage VOFFSEC' is based on the secondary offset voltage of the multi-hop circuit 406. Resistor R1 is coupled to the supply voltage node VDD and the positive internal node 416P. Resistor R2 is coupled to the supply voltage node VDD and the negative internal node 416N. Resistors R1 and R2 provide separate current paths 420P and 420N to the multi-hop circuit 406. Resistors R1 and R2 may have the same resistance. Depending on the situation, resistors R1 and R2 may be coupled to the supply voltage node VDD via resistor R3. Resistor R3 includes a first terminal RT1 coupled to R1 and R2 and a second terminal RT2 coupled to the supply voltage node VDD. Resistors R1, R2, and R3 together establish the common-mode voltage for the positive internal node 416P and the negative internal node 416N.

[0049] In the exemplary configuration, the offset compensation circuit 404, including the multi-hop circuit 406, improves upon the op-amp 102 of Figures 1 and 2 by providing a more uniform distribution of the final calibrated offset voltage compensation compared to that provided by the op-amp 102 in response to the compensation control voltage VCTL'. The diff-amp 402 replaces the differential pair 208 of Figure 2, which provides offset compensation to the positive inner node 206P and the negative inner node 206N, wherein the multi-hop circuit 406 provides linear transconductance over a larger range of the compensation control voltage VCTL compared to the differential pair 208 in the op-amp 102 of Figure 2. In other words, the multi-hop circuit 406 provides greater linearity or increased compensation uniformity between changes in the compensation control voltage VCTL and the effective compensation in the diff-amp 402 for the offset voltage VOFFSET'. The multi-hop circuit 406 also provides linear transconductance with finer granularity compared to the differential pair 208 in the op-amp 102.

[0050] The multi-hop circuit 406 includes three differential pairs 422A, 422B, and 422C, and constant current sources 423A, 423B, and 423C. The constant current sources 423A, 423B, and 423C include corresponding current inputs CIA, CIB, and CIC. The differential pairs 422A, 422B, and 422C each include compensating transistors 424PA, 424PB, and 424PC, which are each coupled to the positive internal node 416P and the current inputs CIA, CIB, and CIC of the constant current sources 423A, 423B, and 423C. The constant current sources 423A, 423B, and 423C conduct currents IDA, IDB, and IDC, which may all be the same first current. The compensation transistors 424PA, 424PB, and 424PC have corresponding control inputs 426GA, 426GB, and 426GC, each receiving a compensation control voltage VCTL'. The control inputs 426GA, 426GB, and 426GC are referred to herein as gates 426GA, 426GB, and 426GC. The compensation control voltage VCTL' ranges from a lower reference voltage VREFL to a higher reference voltage VREFH.

[0051] The differential pairs 422A, 422B, and 422C also include reference transistors 424NA, 424NB, and 424NC coupled to the current inputs CIA, CIB, and CIC of the negative internal node 416N and the constant current sources 423A, 423B, and 423C. The reference transistors 424NA, 424NB, and 424NC have corresponding control inputs 428GA, 428GB, and 428GC, also referred to herein as gates 428GA, 428GB, and 428GC, and each receives different reference voltages ranging from a lower reference voltage VREFL to a higher reference voltage VREFH. In the example in Figure 4, for reasons explained further below with reference to Figure 5, the gate 428GB of the second reference transistor 424NB receives the average reference voltage VREFAVG, the gate 428GA receives a lower reference voltage VREFLOW compared to the average reference voltage VREFAVG, and the gate 428GC receives a higher reference voltage VREFHIGH compared to the average reference voltage VREFAVG.

[0052] Based on the compensation control voltage VCTL' and the reference voltages VREFLOW, VREFAVG', and VREFHIGH received at the control inputs 428GA, 428GB, and 428GC of the reference transistors 424NA, 424NB, and 424NC, the differential pairs 422A, 422B, and 422C supply the offset compensation voltage VCOMP to the positive internal node 416P and the negative internal node 416N. The intermediate differential voltage VID2' is based on the output differential voltage VOD1 and the offset compensation voltage VCOMP. Due to the offset voltages VOFFPRI and VOFFSEC', the offset compensation voltage VCOMP reduces the offset in the diff-amp output voltage VOUT'.

[0053] In the example in Figure 4, the gate 428GB of the second reference transistor 424NB receives the average reference voltage VREFAVG. The average reference voltage VREFAVG is an average or intermediate value between a lower reference voltage VREFL and a higher reference voltage VREFH, which determines the range of the compensation control voltage VCTL' generated in the DAC 410. For reasons further explained below with reference to Figure 5, the gate 428GA receives a lower reference voltage VREFLOW compared to the average reference voltage VREFAVG, and the gate 428GC receives a higher reference voltage VREFHIGH compared to the average reference voltage VREFAVG.

[0054] Figure 5 is a graph of the transfer functions of the differential pairs 422A, 422B, and 422C in the multi-hop circuit 406. Specifically, Figure 5 illustrates the currents IDA, IDB, and IDC flowing through the compensation transistors 424PA, 424PB, and 424PC in response to the compensation control voltage VCTL'. The lower reference voltage VREFLOW supplied to the gate 428GA causes the differential pair 422A to begin conducting current IDA in response to the lower compensation control voltage VCTL (i.e., corresponding to the lower secondary differential voltage VSD) compared to the differential pair 422B. Similarly, the higher reference voltage VREFHIGH supplied to the gate 428GC causes the differential pair 422C to begin conducting current IDC at the higher compensation control voltage VCTL compared to the differential pair 422B. When the lower reference voltage VREFLOW and the average reference voltage VREFAVG are supplied to the gates 428GA and 428GB, the compensation transistors 424PA and 424PB in the differential pairs 422A and 422B each simultaneously conduct at least a portion of the currents IDA and IDB, but the portion of the current IDA flowing through the compensation transistor 424PA at point B2 is, for example, larger than the portion of the current IDB flowing through the compensation transistor 424PB. Similarly, the differential pairs 422B and 422C will conduct different portions of the currents IDB and IDC at point B1, for example, through the corresponding compensation transistors 424PB and 424PC.

[0055] In the exemplary configuration, as shown in the graph in Figure 5, the total current ID TTL (normalized as the magnitudes of currents IDA, IDB, and IDC) is the sum of portions of currents IDA, IDB, and IDC flowing through the corresponding compensation transistors 424PA, 424PB, and 424PC. The offset compensation voltage VCOM provided to the positive internal node 416P and the negative internal node 416N is determined by the total current ID TTL. The total current ID TTL remains linear over a larger range of compensation control voltages VCTL compared to any of the currents IDA, IDB, and IDC. Therefore, the effect of replacing the differential pair 208 in Figure 2 with the multi-hop circuit 406 in Figure 4 is in response to the increased linearity range provided by the compensation control voltage VCTL when compensating for the accumulated offset voltage VOFFSET. For comparison, the total current ID TTL is linear over a larger range of the compensated control voltage V CTL between points T1 and T2, compared to the linear range of the current IDB of the differential pair 422B between points B1 and B2.

[0056] Furthermore, the change in the magnitude of the total current ID TTL within the linear range between points T1 and T2 is smaller than the change in the magnitude of the current IDB. Therefore, the granularity of the offset compensation voltage V COMP provided by the total current ID TTL is finer compared to, for example, the granularity of a single differential pair 422B. In other words, compared to op-amp 102 in Figure 2, the offset compensation voltage V COMP provided to the positive internal node 416P and negative internal node 416N of diff-amp 402 may be adjusted less in response to changes in the compensation control voltage V CTL. In this respect, the offset compensation voltage V COMP provided by the multi-hop circuit 406 can more accurately compensate the diff-amp output voltage V OUT' of the accumulated offset voltage V OFFSET.

[0057] Although the multi-hop circuit 406 in Figure 4 includes three differential pairs 422A, 422B, and 422C, as disclosed herein, multi-hop circuits may include at least two and up to any advantageous number of differential pairs to increase the linearity of the compensation provided to the differential amplifier.

[0058] Figure 6 is a flowchart of a method 600 for compensating offset voltage in a differential amplifier. The method includes generating a binary value (VBIN) in a successive approximation register (SAR) analog-to-digital converter (ADC) (408) based on the output voltage (VOUT') of the differential amplifier (402) in offset compensation calibration mode (block 602). Method 600 includes generating a compensation control voltage (VCTL') in a digital-to-analog converter (DAC) (410) based on the binary value (VBIN) in a range between a lower reference voltage (VREFL) and a higher reference voltage (VREFH) (block 604). The method further includes coupling a first resistor (R1) to a supply voltage node VDD and a positive internal node (416P) between a first amplifier stage (413) and a second amplifier stage (414) of the differential amplifier (402) (block 606). The method further includes coupling a second resistor (R2) to the supply voltage node VDD and the negative internal node (416N) between the first amplifier stage (413) and the second amplifier stage (414) of the differential amplifier (402) (block 608). The method further includes coupling a plurality of differential pairs to positive and negative internal nodes (416P and 416N), wherein each of the plurality of differential pairs (422A, 422B, 422C) (block 610) includes coupling a reference transistor (424NA) to the negative internal node (416N) and a constant current source 423A (block 612), receiving one of a plurality of different reference voltages (e.g., VREFL, VREFAVG, VREFH) from a lower reference voltage VREFL to a higher reference voltage VREFH at the control input (428GA) of the reference transistor (424NA) (block 614), coupling a compensation transistor (424PA) to the positive internal node (426P) and a constant current source (423A) (block 616), and receiving a compensation control voltage (V) generated in the DAC (410) at the control input (426GA) of the compensation transistor (424PA). CTL' (block 618). The method also includes providing an offset compensation voltage to the positive and negative internal nodes (416P and 416N) via a plurality of differential pairs (422A, 422B, 422C) based on the output voltage (VOUT') of the differential amplifier (402) in offset compensation calibration mode (block 620).

[0059] Figure 7 is a schematic diagram of an exemplary offset-compensated differential amplifier system 700 corresponding to the offset-compensated differential amplifier system 400 in Figure 4, including diff-amp 702 and compensation calibration circuits 703A and 703B. Diff-amp 702 includes offset compensation circuitry 704, which employs multi-hop circuitry 706 to provide offset voltage compensation with finer granularity and increased linear range compared to the automatic calibration op-amp system 100 in Figures 1 and 2. The offset-compensated differential amplifier system 700 in Figure 7 includes input control circuitry 708, which includes a coupling capacitor 710P coupled to the positive primary input voltage VIP P and a coupling capacitor 710N coupled to the negative primary input voltage VIP N. Coupling capacitors 710P and 710N allow AC or time-varying primary differential voltage VPD to be passed to diff-amp 702 but block DC voltage. The input control circuit 708 also includes a resistor tree 711 that provides the common-mode voltage to the positive primary input voltage VIP P and the negative primary input voltage VIP N. The resistor tree 711 includes resistors R4 and R5. Resistor R4 is coupled to the positive primary input voltage VIP P and the supply voltage node VDD. Transistor R5 is coupled to the negative primary input voltage VIP N and the supply voltage node VDD. The input control circuit 708 also includes a positive input switch 712P and a negative input switch 712N that disconnect the positive primary input voltage VIP P and the negative primary input voltage VIP N from external circuitry in response to offset compensation calibration mode.

[0060] Figure 8 is a block diagram of an exemplary processor-based system 800 including a processor 802 (e.g., a microprocessor) that includes instruction processing circuitry 804. The processor-based system 800 may be one or more circuits included in an electronic circuit board, such as a printed circuit board (PCB), server, personal computer, desktop computer, laptop computer, personal digital assistant (PDA), notebook, mobile device, or any other device, and may represent, for example, a server or a user's computer. In this example, the processor-based system 800 includes a processor 802. Processor 802 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, processor 802 may be an EDGE instruction set microprocessor, or other processor implementing an instruction set that supports explicit consumer naming for communicating values ​​generated from executing producer instructions. Processor 802 is configured to execute processing logic in instructions for performing the operations and steps discussed herein. In this example, processor 802 includes instruction cache memory 808 for temporary fast access storage of instructions accessible by instruction processing circuitry 804. Instructions fetched or pre-fetched from memory (such as main memory 810 on system bus 812) are stored in instruction cache memory 808. Instruction processing circuitry 804 is configured to process the instructions fetched into instruction cache memory 808 and process the instructions for execution.

[0061] Processor 802 and main memory 810 are coupled to system bus 812 and can enable peripheral devices included in the processor-based system 800 to be coupled to each other. As is well known, processor 802 communicates with such other devices by exchanging address, control, and data information on system bus 812. For example, processor 802 can communicate bus transaction requests to memory controller 819 in main memory 810 as an example of a slave device. Although not shown in Figure 8, multiple system buses 812 may be provided, each with a different configuration. In this example, memory controller 819 is configured to provide memory access requests to memory array 820 in main memory 810. Memory array 820 consists of an array of storage bit cells for storing data. The main memory 810 may be read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM), etc., and static memory (e.g., flash memory, static random access memory (SRAM), etc.) as non-limiting examples.

[0062] Other devices may be connected to system bus 812. As shown in Figure 8, these devices may include, for example, main memory 810, one or more input devices 822, one or more output devices 824, modem 826, and one or more display controllers 828. Input devices 822 may include any type of input device, including but not limited to input keys, switches, sound processors, etc. Output devices 824 may include any type of output device, including but not limited to voice, video, other visual indicators, etc. Modem 826 may be any device configured to allow data exchange to and from network 830. Network 830 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), Bluetooth™ networks, and the Internet. Modem 826 may be configured to support any type of desired communication protocol. Processor 802 may also be configured to access display controller 828 on system bus 812 to control information sent to one or more displays 832. Display 832 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, etc. Any of the devices coupled to system bus 812 may include offset-compensated differential amplifier system 400 as shown in Figure 4, which includes a linear range for accumulating increased offset voltage and multi-hop circuitry for finer granular compensation.

[0063] The processor-based system 800 in Figure 8 may include a set of instructions 834 that will be executed by processor 802 for any application desired according to the instructions. Instructions 834 may be stored in main memory 810, processor 802, and / or instruction cache memory 808 as instances of non-transitory computer-readable media 836. Instructions 834 may also reside wholly or at least partially in main memory 810 and / or processor 802 during their execution. Instructions 834 may further be transmitted or received on network 830 via modem 826, such that network 830 includes computer-readable media 836.

[0064] Although computer-readable media 836 is illustrated as a single medium in the exemplary embodiments, the term "computer-readable media" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated cache and server) that store one or more instruction sets. The term "computer-readable media" should also be understood to include any medium capable of storing, encoding, or carrying instruction sets for execution by a processing device and causing the processing device to perform any one or more methodologies of the embodiments disclosed herein. The term "machine-readable media" should therefore be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0065] The embodiments disclosed herein include various steps. The steps of the embodiments disclosed herein may be formed by hardware components or may be embodied in machine-executable instructions that can be used to cause a general-purpose or special-purpose processor to perform the steps. Alternatively, the steps may be performed by a combination of hardware and software.

[0066] The embodiments disclosed herein may be provided as a computer program product or software, which may include a machine-readable medium (or computer-readable medium) having instructions stored thereon, such instructions being used to program a computer system (or other electronic device) to perform a process according to the embodiments disclosed herein. Machine-readable media includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, machine-readable media includes: machine-readable storage media (e.g., ROM, random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.); and the like.

[0067] Unless otherwise specifically stated and as will be apparent from the preceding discussion, it will be understood that throughout the description, the use of terms such as “processing,” “computing,” “determining,” “displaying,” or similar expressions refers to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data and memory representing physical (electronic) quantities in the registers of a computer system into other data representing physical quantities in the registers or other such information storage, transmission, or display devices of a computer system.

[0068] The algorithms and displays presented herein are not inherently specific to any particular computer or other device. Various systems can be used in accordance with the teachings and programs herein, or it may be proven convenient to construct more specialized devices to perform the required method steps. The necessary architecture for various such systems is apparent from the foregoing description. Furthermore, the embodiments described herein do not refer to any particular programming language. It will be understood that various programming languages ​​can be used to implement the teachings of the embodiments described herein.

[0069] Those skilled in the art will further understand that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the embodiments disclosed herein can be implemented as electronic hardware, stored in memory or on another computer-readable medium and executed by a processor or other processing device, or a combination of both. Components of the distributed antenna system described herein can be employed in any circuit, hardware component, integrated circuit (IC), or IC chip, as an example. The memory disclosed herein can be of any type and size and can be configured to store any type of desired information. To clearly illustrate this interchangeability, the various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How this functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the entire system. Those skilled in the art can implement the described functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of this embodiment.

[0070] The various illustrative logic blocks, modules, and circuits described in connection with the embodiments disclosed herein can be implemented or executed using processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, individual gate or transistor logic, individual hardware components, or any combination thereof designed to perform the functions described herein. Furthermore, the controller may be a processor. The processor may be a microprocessor, but alternatively, the processor may be any known processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, a combination of one or more microprocessors and a DSP core, or any other such configuration).

[0071] The embodiments disclosed herein can be embodied in hardware and instructions stored in hardware and may reside, for example, in RAM, flash memory, ROM, electronically programmable ROM (EPROM), electronically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable media known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from and write information to the storage medium. Alternatively, the storage medium may be integrated into the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. Alternatively, the processor and storage medium may reside as discrete components in a remote station, base station, or server.

[0072] It should also be noted that the operational steps described in any of the exemplary embodiments herein are described to provide examples and discussion. The described operations may be performed in several different sequences different from the sequences shown. Furthermore, the operation described in a single operational step may actually be performed in multiple different steps. Additionally, one or more operational steps discussed in the exemplary embodiments may be combined. Those skilled in the art will also understand that information and signals can be represented using any of a variety of methods and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that can be referenced throughout the foregoing description may be represented by voltage, current, electromagnetic waves, magnetic fields, or particles, light fields or particles, or any combination thereof.

[0073] Unless otherwise expressly stated, it is not intended to interpret any method described herein as requiring its steps to be performed in a specific order. Therefore, no particular order is intended to be inferred unless the method claim actually describes the order in which its steps are performed, or unless there is a separate specific statement in the claims or description that the steps are limited to a specific order.

[0074] As will be apparent to those skilled in the art, various modifications and variations can be made without departing from the spirit or scope of the invention. Since modifications, combinations, sub-combinations, and variations of the embodiments disclosed in accordance with the spirit and substance of the invention will be conceived by those skilled in the art, the invention should be construed as including all contents within the scope of the appended claims and their equivalents.

[0075] 100: Automatic calibration operational amplifier (op-amp) system 102:op-amp 104: Main differential input 106: Secondary Differential Input 108: Serial Approximation Register (SAR) Analog-to-Digital Converter (ADC) Circuit 110: Digital-to-Analog Converter (DAC) 112: Switch 202: First Amplifier Stage 204N: Negative internal node 204P: Positive internal node 206: Internal differential node 208: Differential Pair 210N: Reference transistor 210P: Compensating Transistor 212: Constant Current Source 214NG: Gate 214PG: Gate 216N: Current path 216P: Current path 218: Second Amplifier Stage 220: Single-ended voltage converter 220N: Input 220P: Input 302: Nonlinear region 400: Offset-compensated differential amplifier system 402: Offset-compensated differential amplifier ("diff-amp") 403: Compensation and Calibration Circuit 404: Offset Compensation Circuit 406: Multi-hop circuit 408: SAR ADC 410:DAC 412: Switch 413: First Amplifier Stage 414: Second amplifier stage 416N: Negative internal node 416P: Positive internal node 420N: Current path 420P: Current Path 422A: Differential Pair 422B: Differential Pair 422C: Differential Pair 423A: Constant Current Source 423B: Constant Current Source 423C: Constant Current Source 424NA: Reference transistor 424NB: Reference transistor 424NC: Reference transistor 424PA: Compensating Transistor 424PB: Compensating Transistor 424PC: Compensating Transistor 426GA: Control Input 426GB: Control Input 426GC: Control Input 428GA: Control Input 428GB: Control Input 428GC: Control Input 600: Method 602: Square 604: Square 606: Square 608: Square 610: Square 612: Square 614: Square 616: Square 618: Square 620: Square 700: Offset-compensated differential amplifier system 702:diff-amp 703A: Compensation and Calibration Circuit 703B: Compensation and Calibration Circuit 704: Offset Compensation Circuit 706: Multi-hop circuit 708: Input Control Circuit 710 N: Coupling capacitor 710 P: Coupling capacitor 711: Resistor Tree 712 N: Negative Input Switch 712 P: Positive Input Switch 800: System 802: Processor 804: Instruction Processing Circuit 808: Instruction Cache Memory 810: Main Memory 819: Memory Controller 820: Memory Array 822: Input device 824: Output device 826: Modem 828: Display Controller 830: Network 832: Monitor 834: Instruction 836: Non-transitory computer-readable media A1: Point A2: Point B1: Point B2: Point CI A: Current Input CI B: Current Input CI C: Current Input G: Gain I 212: Constant Current ID TTL: Total Current IDA: Current IDB: Current IDC: Current R1: Resistor R2: Resistor R3: Resistor R4: Resistor R5: Resistor RT 1: First terminal RT2: Second terminal SID1: Slope T1: point T2: Point V BIN: Binary value V CMP: Input V CTL: Compensation control voltage V CTL': Compensation control voltage VDD: Supply voltage node V OFFPRI: Offset voltage V OFFSEC: Offset voltage V OFFSEC': Offset voltage V OFFSET: Offset voltage V OFFSET': Offset voltage V OUT: Output voltage VOUT': Output voltage V OUTN: Negative output voltage V OUTP: Positive output voltage V REFAVG: Average Reference Voltage V REFH: Higher reference voltage V REFHIGH: Higher reference voltage V REFL: Lower reference voltage V REFLOW: Lower reference voltage V START: Input VID2: Intermediate Differential Voltage VID2': Intermediate differential voltage VIP N: Negative main input voltage VIP P: Positive main input voltage VIS N: Negative secondary input voltage VIS P: Positive secondary input voltage VOD1: Output differential voltage VOD2: Output differential voltage VPD: Main differential voltage VSD: Secondary differential voltage

[0076] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. An offset-compensated differential amplifier, comprising: a first amplifier stage configured to generate a first output differential voltage based on a primary differential voltage at a positive internal node and a negative internal node; a second amplifier stage coupled to the positive internal node and the negative internal node and configured to generate an output voltage based on an intermediate differential voltage at the positive internal node and the negative internal node; and an offset compensation circuit comprising: a first resistor configured to be coupled to a supply voltage node and the positive internal node; a second resistor configured to be coupled to the supply voltage node and the negative internal node; and a multi-hop circuit comprising: a plurality of constant current sources; and a plurality of differential pairs, each differential pair comprising: A compensation transistor, configured to be coupled to a current input of a corresponding constant current source among the plurality of constant current sources, the compensation transistor including a compensation control input configured to receive a compensation control voltage; and a reference transistor, configured to be coupled to the current input of the corresponding constant current source among the plurality of constant current sources, the reference transistor including a control input configured to receive one of a plurality of different reference voltages; wherein: The plurality of differential pairs supply an offset compensation voltage to the positive and negative internal nodes based on the compensation control voltage and the plurality of different reference voltages; and the intermediate differential voltage is based on the first output differential voltage and the offset compensation voltage.

2. The offset-compensated differential amplifier as described in claim 1, wherein: The compensation transistor in each of the plurality of differential pairs is configured to receive the compensation control voltage from a lower reference voltage to a higher reference voltage.

3. The offset-compensated differential amplifier as described in claim 2, wherein: Each reference transistor in the plurality of differential pairs is configured to receive one of the plurality of different reference voltages from the lower reference voltage to the higher reference voltage.

4. The offset-compensated differential amplifier as described in claim 1, wherein: Each of the plurality of constant current sources is configured to conduct a constant first current through a corresponding differential pair.

5. The offset-compensated differential amplifier as claimed in claim 1, wherein the first resistor includes a first resistance value and the second resistor includes the first resistance value.

6. The offset-compensated differential amplifier as claimed in claim 1, further comprising a third resistor, the third resistor including a first terminal coupled to the first resistor and the second resistor and a second terminal coupled to the supply voltage node.

7. The offset-compensated differential amplifier as described in claim 1, wherein: The first amplifier stage is configured to generate the first output differential voltage based on the primary differential voltage and a first offset voltage; and the second amplifier stage is configured to generate the output voltage based on the intermediate differential voltage, the offset compensation voltage, and a second offset voltage; wherein the reduction in the offset compensation voltage is attributed to an offset in the output voltage of the first offset voltage and the second offset voltage.

8. An offset-compensated differential amplifier system, comprising: an offset-compensated differential amplifier including: a positive main input and a negative main input; a first amplifier stage configured to generate a first output differential voltage at a positive internal node and a negative internal node based on a main differential voltage at the positive and negative main inputs; a second amplifier stage coupled to the positive internal node and the negative internal node and configured to generate an output voltage based on an intermediate differential voltage at the positive internal node and the negative internal node; and an offset compensation circuit including: a first resistor configured to be coupled to a supply voltage node and the positive internal node; a second resistor configured to be coupled to the supply voltage node and the negative internal node; and a multi-hop circuit including: a plurality of constant current sources; and a plurality of differential pairs, each differential pair including: A compensation transistor, configured to be coupled to a current input of a corresponding constant current source among the plurality of constant current sources, the compensation transistor including a compensation control input configured to receive a compensation control voltage; and a reference transistor, configured to be coupled to the current input of the corresponding constant current source among the plurality of constant current sources, the reference transistor including a control input configured to receive one of a plurality of different reference voltages; wherein: The plurality of differential pairs supply an offset compensation voltage to the positive and negative internal nodes based on the compensation control voltage and the plurality of different reference voltages; and the intermediate differential voltage is based on the first output differential voltage and the offset compensation voltage; and a compensation calibration circuit includes: a switch configured to electrically short-circuit the positive primary input to the negative primary input in response to an offset compensation calibration mode; a successive approximation register (SAR) analog-to-digital converter (ADC) coupled to the second amplifier stage and configured to generate a binary value based on the output voltage in response to the offset compensation calibration mode; and a digital-to-analog converter (DAC) configured to generate the compensation control voltage based on the binary value.

9. The offset-compensated differential amplifier system as described in claim 8, wherein: The compensation transistor in each of the plurality of differential pairs is configured to receive the compensation control voltage from a lower reference voltage to a higher reference voltage.

10. The offset-compensated differential amplifier system as described in claim 9, wherein: Each reference transistor in the plurality of differential pairs is configured to receive one of the plurality of different reference voltages from the lower reference voltage to the higher reference voltage.

11. The offset-compensated differential amplifier system as described in claim 10, wherein: The plurality of differential pairs includes three (3) differential pairs; the reference transistor in one of the plurality of differential pairs is configured to receive a reference voltage comprising an average voltage comprising the lower reference voltage and the higher reference voltage; the reference transistor in one of the plurality of differential pairs is configured to receive a reference voltage between the average voltage and the lower reference voltage and the higher reference voltage; and the reference transistor in one of the plurality of differential pairs is configured to receive a reference voltage between the average voltage and the higher reference voltage.

12. The offset-compensated differential amplifier system as described in claim 8, wherein: The binary value contains N bits; the DAC is further configured to generate the compensation control voltage between a lower reference voltage and a higher reference voltage; and the compensation control voltage includes one of 2N incrementing voltages from the lower reference voltage to the higher reference voltage.

13. The offset-compensated differential amplifier system as claimed in claim 8, wherein each of the plurality of constant current sources is configured to conduct a constant first current through a corresponding differential pair.

14. The offset-compensated differential amplifier system as claimed in claim 8, wherein the first resistor includes a first resistor and the second resistor includes the first resistor.

15. The offset-compensated differential amplifier system as claimed in claim 8, further comprising: a third resistor coupled to the positive primary input and the supply voltage node; and a fourth resistor coupled to the negative primary input and the supply voltage node; wherein the third and fourth resistors are configured to set a universal mode voltage on the positive primary input and the negative primary input.

16. The offset-compensated differential amplifier system as claimed in claim 8, wherein the offset-compensated differential amplifier further includes a voltage converter circuit, wherein: The second amplifier stage is configured to generate the output voltage as a differential voltage signal on a positive output and a negative output; The voltage converter circuit is coupled to the positive output and the negative output and configured to generate the output voltage on a single-ended output coupled to the SAR ADC.

17. The offset-compensated differential amplifier system of claim 8, further comprising: a positive input switch configured to disconnect the positive main input from an external circuit in response to the offset-compensated calibration mode; and a negative input switch configured to disconnect the negative main input from the external circuit in response to the offset-compensated calibration mode.

18. A method for compensating an offset voltage in a differential amplifier, the method comprising the steps of: generating a binary value in a successive approximation register (SAR) analog-to-digital converter (ADC) based on an output voltage of a differential amplifier in an offset compensation calibration mode; generating a compensation control voltage in a digital-to-analog converter (DAC) in a range from a lower reference voltage to a higher reference voltage based on the binary value; coupling a first resistor to a supply voltage node and a positive internal node between a first amplifier stage and a second amplifier stage of the differential amplifier; coupling a second resistor to the supply voltage node and a negative internal node between the first amplifier stage and the second amplifier stage of the differential amplifier, the positive and negative internal nodes comprising an intermediate differential voltage; and coupling a plurality of differential pairs to the positive and negative internal nodes, wherein the step of coupling each of the plurality of differential pairs comprises the step of: coupling a reference transistor to the negative internal node and a constant current source; The reference transistor receives one of a plurality of different reference voltages from the lower reference voltage to the higher reference voltage at a control input; a compensation transistor is coupled to the positive internal node and the constant current source; and the compensation control voltage generated in the DAC is received at a control input of the compensation transistor; and in response to the offset compensation calibration mode, an offset compensation voltage is provided to the positive and negative internal nodes via the plurality of differential pairs based on the output voltage of the differential amplifier.

19. The method of claim 18 further comprises the step of: in response to a signal indicating the offset compensation calibration mode, activating a switch to electrically short-circuit a positive main input and a negative main input to the first amplifier stage of the differential amplifier, wherein an intermediate offset voltage is based on an offset voltage in the first amplifier stage.

20. The method as described in request item 18, wherein: The binary value generated in this SAR ADC includes the response to the offset compensation calibration mode.

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