Substrate processing system and method of forming memory structure

Abstract

A substrate processing system includes a memory that stores a recipe for an electrical coupling process for electrically coupling a capacitor to an active silicon region of a memory structure. A system controller performs at least a portion of the electrical coupling process according to the recipe, including: performing a deposition and etching cycle to remove portions of one or more dielectric layers from a substrate, enlarging a trench between adjacent bit line structures of the memory structure, and providing access to a dielectric layer or a polymer layer adjacent to an upper portion of the active silicon region; performing a breakthrough operation including etching at least one of the polymer layer or the dielectric layer in the trench to expose the upper portion of the active silicon region, and performing an over-etch operation to provide access to electrically couple the capacitor to the active silicon region.

Description

Technical Field

[0001] [Cross-reference to related applications] This application claims priority to U.S. Provisional Application No. 63 / 163989, filed March 22, 2021. The entire contents of the aforementioned application are incorporated herein by reference.

[0002] This disclosure relates to the detection of partial loosening of a substrate from an electrostatic chuck in a substrate processing system. Prior Technology

[0003] The prior art description provided herein is for the purpose of generally presenting the background of this disclosure. Within the scope described in this prior art section, the works of the inventors currently listed, as well as illustrative embodiments that may not qualify as prior art at the time of application, are not expressly or implicitly acknowledged as prior art against this disclosure.

[0004] Substrate processing systems can be used to perform etching and deposition processes to form memory structures, such as dynamic random access memory (DRAM) structures. During etching, a thin film on the substrate is etched. Etching typically includes wet chemical etching or dry etching. Dry etching can be performed by generating inductively coupled plasma (ICP). ICP can be generated by coils located outside the processing chamber adjacent to a dielectric window. Process gases flowing within the processing chamber are ignited to generate ICP. Simultaneously with etching, the substrate can be placed on an electrostatic chuck (ESC) within the processing chamber of the corresponding substrate processing system. Summary of the Invention

[0005] This document provides a substrate processing system including a memory and a system controller. The memory is configured to store a recipe for at least a portion of an electrical coupling process for electrically coupling a capacitor to an active silicon region of a memory structure. The system controller is configured to perform the at least a portion of the electrical coupling process according to the recipe, including: performing multiple deposition and etching cycles to remove portions of one or more dielectric layers from a substrate, enlarging a trench between adjacent bit line structures of the memory structure, and providing access to at least one of a dielectric layer or a polymer layer adjacent to an upper portion of the active silicon region; performing a breakthrough operation including etching the polymer layer or the dielectric layer in the trench to expose the upper portion of the active silicon region; and performing an over-etch operation to remove the upper portion of the active silicon region, thereby providing access to electrically couple the capacitor to the remaining portion of the active silicon region.

[0006] Among other features, the one or more dielectric layers comprise an oxide layer and a silicon nitride layer. Among other features, the deposition cycle of the plurality of deposition and etching cycles includes a supply of argon and a supply of at least one of unsaturated hydrocarbon molecules or saturated hydrocarbon molecules. Among other features, the deposition cycle of the plurality of deposition and deposition cycles includes a supply of methane and argon.

[0007] Among other features, the deposition cycle includes supplying methane and argon at a pressure greater than or equal to 5 mT and less than or equal to 40 mT. Among other features, the substrate is processed in a processing chamber. The system controller avoids applying a bias voltage to one of the electrodes in the processing chamber during these deposition cycles.

[0008] Among other features, the etching cycle of the multiple deposition and etching cycle includes supplying a plurality of gases, the plurality of gases including at least one of (i) nitrogen fluoride, dichloro, hexafluorobutadiene, fluoromethane, difluoromethane, or carbon tetrafluoride, and (ii) helium. Among other features, the etching cycle includes supplying the plurality of gases at a pressure greater than or equal to 5 mT and less than or equal to 30 mT. Among other features, the etching cycle of the multiple deposition and etching cycle includes applying at least one of a continuous wave or a pulsed radio frequency signal to one or more electrodes.

[0009] Among other features, the breakthrough operation includes supplying carbon tetrafluoride and at least one of argon or helium. Among other features, the breakthrough operation includes supplying the carbon tetrafluoride and at least one of argon or helium at a pressure greater than or equal to 5 mT and less than or equal to 30 mT. Among other features, the breakthrough operation includes applying at least one of a continuous wave or a pulsed radio frequency signal to one or more electrodes.

[0010] Among other features, the over-etching process includes supplying a plurality of gases at a pressure greater than or equal to 200 mT and less than or equal to 400 mT. Among other features, the over-etching process includes supplying at least one of nitrogen trifluoride, hydrogen, or methane. Among other features, the over-etching process includes supplying at least one of argon or helium. Among other features, the over-etching process includes supplying nitrogen trifluoride, hydrogen, and methane. Among other features, the over-etching process includes applying at least one of a continuous wave or a pulsed radio frequency signal to one or more electrodes.

[0011] Among other features, a memory structure is provided, comprising: a first dielectric layer including an active silicon region, the active silicon region including an upper portion and a lower portion, wherein the lower portion of the active silicon region includes active silicon; a second dielectric layer disposed on the upper portion; a plurality of bit line structures, wherein one of the bit line structures is disposed on the second dielectric layer; and a trench adjacent to the active silicon region. A region between the upper portion of the active silicon region, the trench, and the plurality of bit line structures is filled with a conductive material, the conductive material electrically coupling a capacitor to the active silicon in the active silicon region.

[0012] Among other features, the upper portion of the active silicon region extends in (i) a first direction between the lower portion of the active silicon region and the second dielectric layer, and (ii) a second direction perpendicular to the first direction between the trench and the third dielectric layer. Among other features, the third dielectric layer extends at an angle along one side of the active silicon region and along a portion of the first dielectric layer.

[0013] Among other features, each of the plurality of bit line structures includes: a relative conductor layer; a respective bit line disposed on the relative conductor layer; and a protective dielectric layer disposed on a top side and a side of the relative conductor layer, and on the side of the respective bit line.

[0014] Among other features, the first dielectric layer is an oxide layer. The lower portion of the active silicon region is formed of polycrystalline silicon. Each of the multi-bit line structures includes a relative dielectric layer, a relative metal layer, and a relative alloy layer formed of silicon nitride.

[0015] Among other features, the first dielectric layer includes a second active silicon region beneath the other of the complex bit line structures. A portion of the first dielectric layer is disposed between: (i) one of the bit line structures disposed on the second dielectric layer, and (ii) the other of the complex bit line structures. Among other features, the first dielectric layer and the active silicon region are disposed on a complex layer. The complex layer includes a word line.

[0016] Among other features, the memory structure further includes multiple layers disposed on the complex bit line structure and the conductive material. These multiple layers include the capacitor.

[0017] Among other features, a dynamic random access memory is provided, comprising: a first complex layer including a word line; an electrical coupling layer disposed on the first complex layer and including the memory structure of claim 17; and a second complex layer disposed on the electrical coupling layer and including the capacitor.

[0018] Among other features, a method is provided for electrically coupling a capacitor to an active silicon region of a memory structure. The method includes: providing a substrate including the memory structure; performing multiple deposition and etching cycles to remove portions of one or more dielectric layers from the substrate, enlarging a trench between adjacent bit line structures of the memory structure, and providing access to at least one of a polymer layer or a dielectric layer adjacent to an upper portion of one of the active silicon regions; performing a breakthrough operation including etching the at least one of the polymer layer or the dielectric layer in the trench to expose the upper portion of the active silicon region; and performing an over-etching operation to remove the upper portion of the active silicon region to provide access for electrically coupling the capacitor to a remaining lower portion of one of the active silicon regions.

[0019] Among other features, the memory structure includes: a first dielectric layer containing the active silicon region; the multi-bit line structure; and the trench adjacent to the active silicon region. The lower portion of the active silicon region contains active silicon. A second dielectric layer is disposed on the upper portion. One of the multi-bit line structures is disposed on the second dielectric layer. Among other features, the method further includes: filling the trench and an open region remaining after the removal of the upper portion of the active silicon region with a conductive material for electrically coupling the capacitor to the active silicon in the active silicon region. Among other features, the one or more dielectric layers include an oxide layer and a silicon nitride layer.

[0020] Among other features, the deposition cycle of the multiple deposition and etching cycle includes the supply of methane and argon. Among other features, the deposition cycle of the multiple deposition and etching cycle includes the supply of methane and argon. Among other features, the deposition cycle includes the supply of methane and argon at a pressure greater than or equal to 5 mT and less than or equal to 40 mT.

[0021] Among other features, the method further includes avoiding applying a bias voltage to one electrode of a processing chamber during the deposition cycle, wherein the substrate is processed in the processing chamber. Among other features, the etching cycle of the multiple deposition and etching includes supplying a plurality of gases, the plurality of gases including at least one of (i) nitrogen fluoride, dichloro, hexafluorobutadiene, fluoromethane, difluoromethane, or carbon tetrafluoride, and (ii) helium. Among other features, the etching cycle includes supplying the plurality of gases at a pressure greater than or equal to 5 mT and less than or equal to 30 mT. Among other features, the etching cycle of the multiple deposition and etching cycle includes applying at least one of a continuous wave or a pulsed radio frequency signal to one or more electrodes.

[0022] Among other features, the breakthrough operation includes supplying carbon tetrafluoride and at least one of argon or helium. Among other features, the breakthrough operation includes supplying the carbon tetrafluoride and at least one of argon or helium at a pressure greater than or equal to 5 mT and less than or equal to 30 mT. Among other features, the breakthrough operation includes applying at least one of a continuous wave or a pulsed radio frequency signal to one or more electrodes.

[0023] Among other features, the over-etching process includes supplying a plurality of gases at a pressure greater than or equal to 200 mT and less than or equal to 400 mT. Among other features, the over-etching process includes supplying at least one of nitrogen trifluoride, hydrogen, or methane. Among other features, the over-etching process includes supplying at least one of argon or helium. Among other features, the over-etching process includes supplying nitrogen trifluoride, hydrogen, and methane. Among other features, the over-etching process includes applying at least one of a continuous wave or a pulsed radio frequency signal to one or more electrodes.

[0024] Among other features, the method further includes: cleaning the trench and the upper portion of the active silicon region; and filling the trench and the upper portion of the active silicon region with a conductive material to provide a conductive element electrically coupling the capacitor to the remaining lower portion of the active silicon region. Among other features, the method further includes: forming a plurality of layers on the plurality of bit lines and the conductive element, wherein the plurality of layers contain the capacitor.

[0025] Further applications of this disclosure will become apparent from the description of the embodiments, the scope of the claims, and the drawings. The embodiments and specific examples described herein are for illustrative purposes only and are not intended to limit the scope of this disclosure. Simple Explanation of the Diagram

[0026] This disclosure will be more fully understood through the section on implementation methods and the accompanying drawings, wherein:

[0027] Figure 1 shows an example memory cell of DRAM;

[0028] Figure 2 is an example process diagram showing a cross-sectional view of the memory structure at a stage of the electrical coupling process used to electrically couple the capacitor to the active silicon region;

[0029] Figure 3 is an example process diagram showing a cross-sectional view of the memory structure at multiple stages of the electrical coupling process in Figure 2;

[0030] Figure 4 is a functional block diagram of an example of a substrate processing system combined with a system controller that implements selective etching and deposition cycles, according to an embodiment of the present disclosure;

[0031] Figure 5 shows an exemplary electrical coupling method for electrically coupling a capacitor to an active silicon region according to an embodiment of the present disclosure;

[0032] Figure 6 is an example process diagram showing a cross-sectional view of the memory structure at each stage of the electrical coupling method shown in Figure 5;

[0033] Figure 7 is an illustrative process diagram showing a cross-sectional view of the memory structure during the deposition and etching cycles and breakthrough and over-etching operations of the electrical coupling method shown in Figure 5;

[0034] Figure 8 is an exemplary cross-sectional view of a memory structure containing a capacitor electrically coupled to an active silicon region layer formed according to the method of Figure 5;

[0035] Figure 9 is a functional block diagram of a wet cleaning system for implementing a portion of an electrocoupling process according to an embodiment of this disclosure; and

[0036] Figure 10 is a functional block diagram of another substrate processing system for implementing a portion of the electrical coupling process according to an embodiment of the present disclosure;

[0037] In these diagrams, reference numerals may be reused to indicate similar and / or identical elements. Implementation

[0038] Figure 1 illustrates a DRAM memory cell 100, which includes a transistor T1 and a capacitor C1. The transistor T1 includes a gate, a first terminal, and a second terminal. The gate is connected to a word line 102. The first terminal is connected to a bit line 104. The second terminal is connected to the capacitor C1, which is connected to a reference terminal 106. The voltage at the reference terminal 106 can be equal to the common-collector voltage Vcc / 2. When a bit is stored in the memory cell 100, the transistor T1 charges or discharges the capacitor C1. Charging and discharging are performed by controlling the states of the word line 102 and the bit line 104. The bit stored in the memory cell can be read through a sense amplifier (not shown). The DRAM includes an array of memory cells configured as memory cell 100.

[0039] Figure 2 illustrates a stage of the electrical coupling process for electrically coupling capacitors to active silicon regions. In the initial stage, memory structure 200A includes an oxide layer 202 (partially shown 202A, 202B, 202C) having active silicon regions 204, 205. The active silicon regions 204, 205 are conductive. The active silicon regions 204, 205 are portions of and / or electrically coupled to the respective transistors of the memory cells of a memory (e.g., DRAM). As an example, each memory cell can be configured as shown in Figure 1. Intermediate dielectric layers (IDLs) 206, 207 are disposed on the sides of the active silicon regions 204, 205, respectively. One or more IDLs (IDLs 210, 212 shown) can be disposed on IDL 207. An intermediate layer 214 can be disposed on and in direct contact with the active silicon region 204. Intermediate layer 216 can be disposed on IDL 212. Intermediate layers 214 and 216 may include polycrystalline silicon and / or silicon-germanium (SiGe). Bit line layers 218 and 220 can be formed on intermediate layers 214 and 216, respectively. Bit line layers 218 and 220 can be formed of tungsten (W). Bit line layers 218 and 220 serve as bit lines for each memory cell. Hard mask layers 219 and 221 are disposed on bit line layers 218 and 220. Hard mask layers 219 and 221 can be formed of silicon nitride (SiN). Hard mask layers 219 and 221 can be formed by plasma chemical vapor deposition (PCVD). IDL 222 is disposed above portions of layers 202, 206, 210, 212, 214, 216, 218, 219, 220, and 221 and can be formed of SiN, a non-conductive (or dielectric) material. IDL 222 can be formed by atomic layer deposition (ALD). The corresponding portions of intermediate layer 214, bit line layer 218, and IDL 222 form the first bit line structure 223. The other corresponding portion of intermediate layer 216, bit line layer 220, and IDL 222 form the second bit line structure 225.

[0040] To expose a portion of the active silicon region 205 to form an electrical coupling (or conductive element) for electrical coupling to a capacitor, portions of layers 202, 207, 210, 212, and 222 are etched during multiple etch cycles. Memory structure 200B illustrates the end of an intermediate etch cycle, while memory structure 200C illustrates the end of an etch cycle. Memory structure 200B may represent the end of a first etch cycle, showing a portion of layers 212 and 222 partially etched away. Memory structure 200C shows the final etched portions of layers 202 (or 202B), 207, 210, 212, and 222, exposing a portion 224 of the active silicon region 205. The exposed portion 224 of the active silicon region 205 is located in region 226 within trench 228 etched away during the etch cycle.

[0041] The memory structure 200D illustrates the filling of the regions between hard mask layers 219 and 221, the regions between bit line layers 218 and 220, the regions between intermediate layers 214 and 216, and other regions etched away during previous operations. A deposition operation is performed to fill these regions with a conductive filler material (e.g., polycrystalline silicon (also known as polysilicon or polycrystalline Si) 230 and / or other metal-doped versions of silicon), which contacts the exposed portions of the active silicon regions 205. Polycrystalline silicon is conductive. An example of metal-doped conductive silicon is cobalt silicide (CoSi x). Subsequent layers may then be deposited on the memory structure 200D to form capacitors that are electrically contacted with the polycrystalline silicon and thus with the active silicon regions 205.

[0042] In the aforementioned electrical coupling process, the etching is performed deep enough into the memory structure to expose the active silicon region 205. During this process, there is a risk that IDL 222 will be etched too much, resulting in partial exposure of bit line layers 218, 220. For example, if IDL 222 is etched too much in regions 240, 242, an electrical short circuit may occur between the capacitor and one of the bit lines. This electrical short circuit occurs because polysilicon (or conductive material) fills the space between one or more exposed bit line layers 218, 220 and the conductor electrically coupled to the capacitor or part of the capacitor. Furthermore, if the etching continues too deep into the memory structure in the trench region indicated by circle 243, another electrical short circuit may occur between the capacitor and the word lines due to polysilicon contacting the word lines. The word lines may be disposed in the layer below the shown portion 202B of oxide layer 202. Excessive etching of portion 202B can result in the etching of a portion of IDL 206 and / or IDL 207, which may (i) extend horizontally above the word line below portion 202B, and (ii) extend between portion 202B and the word line. Etching of IDL 206 and / or IDL 207 will expose this portion of the word line, thus causing contact between the polysilicon and the word line.

[0043] Figure 3 shows a process diagram, including memory structures 200A-200F, illustrating the stages during multiple cycles of the electrical coupling process. The initial memory structure 200A is shown, followed by memory structure 200E, illustrating the intermediate deposition steps. Following the deposition steps is an etching step, shown by memory structure 200F. Performing 4-10 cycles of deposition and etching steps produces memory structure 200C. Memory structure 200C shows the memory structure before performing a contact fill operation to fill the area between bit line structures 223, 225 and the lower area where material has been etched away.

[0044] The memory structure 200E illustrates the deposition of protective layers 300 and 302 on bit line structures 223 and 225. Protective layers 300 and 302 have a "C"-shaped cross-section and cover the top of bit line structures 223 and 225. Protective layers 300 and 302 are deposited to protect the portion below IDL 222, which is disposed above at least a portion of bit line layers 218 and 220, during subsequent etching operations. This allows portions of layers 202, 207, 210, and 212 to be etched as described above without creating an electrical short-circuit path between the capacitor and one of the bit line layers 218 and 220. The protective layers 300 and 302 may extend downward to cover and protect the sides of the hard mask layers 219 and 221, at least a portion of the sides of the bit line layers 218 and 220, and at least a portion of the IDL layer 222 on the sides of the hard mask layers 219 and 221 and on at least a portion of the sides of the bit line layers 218 and 220.

[0045] The electrocoupling process described with reference to Figure 2-3 involves etching away material to attempt to create a "U"-shaped profile to maximize the contact area of ​​the active silicon when filled with conductive material. This process can be performed simultaneously on an array of active silicon regions. Due to the incoming material variability and topographic variations, the pattern of the etching operation becomes critical to ensure that there is an exposed active silicon region for each contact formed at the corresponding active silicon region. Any poor active silicon opening can result in a complete loss of contact between the conductive filler material and the corresponding active silicon region. Due to the small critical size requirements and topographic variability of memory structures, the electrocoupling process needs to etch deep into the memory structure to ensure sufficient exposure of active silicon to provide a reliable connection interface. The connection interface lies between the conductive filler material and the active silicon region.

[0046] Examples described herein include an electrocoupling process for electrically coupling a capacitor to an active silicon region. This process involves a highly selective etching process that etches away portions of the active silicon region while minimizing the etching of the dielectric layer. The dielectric layer comprises an oxide layer and a silicon nitride layer. The regions of the active silicon region that have been partially removed are filled with a conductive material (e.g., polycrystalline silicon, CoSi x, and / or other metal-doped silicon). This provides an interface with a large contact surface area. The interface lies between the conductive material and the remaining portion of the active silicon region. This process significantly reduces the resistance of the interface compared to the active silicon region contact interface provided by the process described with reference to Figures 2-3. Examples include selectively etching the active silicon region while minimizing the etching of other adjacent layers, resulting in shallower depths of adjacent layers. This prevents the formation of conductive short-circuit paths. The active silicon region is "dug out" to an appropriate depth to increase the surface area of ​​the active silicon for the electrocoupling contact. The electrocoupling contact is created by a conductive filler material. The increased surface area improves the electrical connection with the corresponding capacitor.

[0047] Figure 4 illustrates a substrate processing system 400. While Figure 4 illustrates an inductively coupled plasma (ICP) substrate processing system, the embodiments disclosed herein are applicable to transformer-coupled plasma (TCP) systems and / or other substrate processing systems. The substrate processing system 400 incorporates a system controller 402 that implements an electrical coupling process for electrically coupling a capacitor to an active silicon region. The electrical coupling process includes etching and deposition cycles, as well as breakthrough and over-etching operations. The cycles and operations are performed to provide an electrical coupling path with minimal resistance between the active silicon region and the capacitor. The electrical coupling process is described below with reference to Figures 5-8.

[0048] The substrate processing system 400 of Figure 4 may include a back-side gas loop 406. The back-side gas loop 406 may include a system controller 402 and a first gas delivery system 410. The first gas delivery system 410 includes a gas source 412 and a valve 414. The system controller 402 controls the operation of the valve 414 to maintain a predetermined pressure of back-side gas (e.g., helium) supplied from the first gas delivery system 410 to region A between the substrate 416 and ESC 418. Although an exemplary ESC 418 is shown, the examples disclosed herein are applicable to other ESCs. The system controller 402 may adjust the position (or open) of the valve 414 based on the back-side gas pressure. The system controller 402 may adjust the back-side gas pressure and / or flow rate to adjust the temperature of the substrate 416. In one embodiment, one or more temperature sensors may be used to detect the temperature of the back-side gas. Several example temperature sensors 420, 422 are shown. The back-side gas pressure and / or flow rate may be adjusted based on the detected temperature. The system controller 402 can determine the flow rate of the back-side gas (e.g., absolute flow rate and / or mass flow rate). If the mass flow rate is determined, it can be determined based on the temperature detected by the temperature sensors 420, 422.

[0049] The substrate processing system 400 also includes a coil driving circuit 430. In some examples, the coil driving circuit 430 may include an RF source 432, a pulse circuit 434, and a tuning circuit 436. The pulse circuit 434 controls the TCP envelope of the RF signal and changes the duty cycle of the TCP envelope during operation.

[0050] Tuning circuit 436 can be directly connected to one or more induction coils 438. Alternatively, tuning circuit 436 can be connected to one or more coils 438 via optional inverting circuit 440. Tuning circuit 436 tunes the output of RF source 432 to a set frequency and / or a set phase, matches the impedance of coils 438, and distributes power among coils 438. Inverting circuit 440 is used to selectively switch the current polarity through one or more of the coils 438.

[0051] In some examples, the gas filling section 450 may be arranged between the coil 438 and the dielectric window 452 to control the temperature of the dielectric window 452 using hot and / or cold airflow. The dielectric window 452 is arranged along one side of the processing chamber 454. The processing chamber 454 includes an ESC 418. Process gases are supplied to the processing chamber 454 and plasma 456 is generated inside the processing chamber 454. The plasma 456 etches the exposed surface of the substrate 416. The substrate processing system 400 may also include an RF bias circuit 460. The RF bias circuit 460 may include an RF source 462, a pulse circuit 464, and a bias matching circuit 466, which may be used to bias the ESC 418. The bias matching circuit 466 may be connected to an electrode 467 in the ESC 418.

[0052] Gas delivery system 470 can be used to supply process gas mixtures and various gases mentioned herein to processing chamber 454. Gas delivery system 470 may include process and inert gas source 472, gas metering system 474 (e.g., valves and mass flow controllers), and manifold 476. Another gas delivery system 480 may be used to deliver gas from gas source 482 to charging section 450 via valve 484. The gas may include cooling gas (air) for cooling coil 438 and dielectric window 452. Exhaust system 486 includes valve 488 and pump 490 to remove reactants from processing chamber 454 by purging or venting.

[0053] Voltage (V) and current (I) probes (or VI probes) 492 are disposed in processing chamber 454 to detect the voltage and current of plasma 456. Additionally, a phase / amplitude detector 494 is disposed in processing chamber 454 to detect the phase and amplitude of plasma 456.

[0054] The system controller 402 can be used to control the processing of the substrate 416. The system controller 402 monitors system parameters and controls the delivery of the gas mixture, as well as activating, maintaining, and extinguishing the plasma 456, removing reactants, and supplying cooling gas, etc. In addition, the system controller 402 can control the various states of the coil drive circuit 430 and the RF bias circuit 460.

[0055] System controller 402 can control the processing of substrate 416 according to recipe 495 stored in memory 496. Recipe 495 can be used for any electro-coupling process as referred to herein. Recipe 495 defines operating parameters, such as: delivery timing of one or more gases and / or mixtures of one or more gases; valve control timing; RF power timing; RF bias timing; current power level supplied to heater (or thermal control element); RF power source activation / deactivation timing, frequency, and power level; RF bias source activation / deactivation timing, frequency, and power level; flow rate; etc. During the electro-coupling process, system controller 402 can receive feedback values ​​from one or more sensors and control one or more actuators. Examples of sensors include temperature sensors, pressure sensors, flow rate sensors, etc., at least some of which are as described above. Examples of actuators include mass flow controllers, valves, resistance heating elements, RF bias sources, RF power sources, and / or other actuators, at least some of which are as described above. The system controller 402 follows the recipe and can adjust the actuator based on feedback from the sensor.

[0056] ESC 418 may include one or more electrodes (or electrode arrays) 498. The one or more electrodes 498 may be connected to and receive power from a power source 499, which may be controlled by a system controller 402. The one or more electrodes 498 may be used to control the amount of electrostatic force generated to clamp the substrate 416 to ESC 418.

[0057] Figure 5 illustrates an electrical coupling method (or process) for electrically coupling a capacitor to an active silicon region. Although the following operations are primarily described with reference to the embodiments in Figures 4-8, the operations can be readily modified for application to other embodiments of this disclosure. These operations can be performed iteratively and are described primarily with respect to Figures 6-7, which illustrate the general sequence of operations performed at various stages of the process for memory structures 600A-600G of a single memory structure. While the following operations are described for a single memory structure comprising a finite number of bitline structures, active silicon regions, and corresponding layers, the method can be performed simultaneously for any number of memory structures, bitline structures, and active silicon regions.

[0058] This method can begin at 500 and is executed by the system controller 402 and substrate processing system 400 of FIG. 4. At 502, an initial substrate having a memory structure 600A (shown in FIG. 6) is provided and placed on ESC 418. In the initial stage, the memory structure 600A includes an oxide layer 602 (parts 602A, 602B, 602C are shown) having active silicon regions 604, 605. The active silicon regions 604, 605 are portions of and / or electrically coupled to the respective transistors of the memory cells of the memory (e.g., DRAM). As an example, after formation, each memory cell can be configured as shown in FIG. 1. IDLs 606, 607 are respectively disposed on the sides of the active silicon regions 604, 605. One or more IDLs (IDLs 610, 612 are shown) can be disposed on IDL 607. Intermediate layer 614 can be disposed on and in direct contact with active silicon region 604. Intermediate layer 616 can be disposed on IDL 612. Intermediate layers 614 and 616 can be formed of polycrystalline silicon and / or SiGe. Bit line layers 618 and 620 can be formed on intermediate layers 614 and 616, respectively. Bit line layers 618 and 620 can be formed of a metal such as tungsten (W). Bit line layers 618 and 620 serve as bit lines for each memory cell. Hard mask layers 619 and 621 are disposed on bit line layers 618 and 620. Hard mask layers 619 and 621 can be formed of SiN. Hard mask layers 619 and 621 can be formed by PCVD. IDL 622 is disposed above portions of layers 602, 606, 610, 612, 614, 616, 618, 619, 620, and 621 and can be formed of SiN. IDL 622 can be formed of ALD. The intermediate layer 614, the bit line layer 618, and the corresponding portions of IDL 622 form the first bit line structure 623. The intermediate layer 616, the bit line layer 620, and the corresponding portions of IDL 622 form the second bit line structure 625.

[0059] The initial structure may also include a substrate layer 800 (as shown in Figure 8) and a plurality of intermediate layers (e.g., intermediate layers 802, 804, 806 are shown) disposed between (i) the substrate layer and (ii) the oxide layer 602, active silicon regions 604, 605 and IDL 606, 607. One of the intermediate layers may include or be implemented as a word line, such as one of intermediate layers 804 or 806.

[0060] When etching is performed to expose the active silicon regions, the oxide and silicon nitride layers tend to be etched away at a different rate than the active silicon regions. This makes it difficult to expose large amounts of active silicon. As mentioned above, this can lead to electrical short circuits between capacitors and bit lines and / or capacitors and word lines. The process disclosed herein involves performing multiple etch and deposition cycles, similar to those described above, to expose (i) the active silicon regions and / or (ii) a thin polymer layer over the active silicon regions. A thin polymer layer can be formed due to the multiple etch and deposition cycles. After the etch and deposition cycles, the system controller 402 performs a breakout operation, followed by an over-etch operation. This is further described below with respect to the operation of Figure 5 and the structures shown in Figures 6-8.

[0061] Following operation 502, a predetermined number of deposition and etching cycles are performed as indicated by arrow 700. Each deposition cycle is performed at 504, as shown by structure 600B in FIG. 7. During each deposition cycle, a protective carbon-based polymer layer is formed over at least the top of bitline structures 623, 625 to protect at least a portion of layer 622 and thus at least the top of bitline layers 618, 620. IDL layer 622 is referred to as a top sidewall spacer. In FIG. 7, protective polymer layers 701, 702 are shown on bitline structures 623, 625. Protective layers 701, 702 may extend downward to cover and protect the sides of hard mask layers 619, 621, at least a portion of the sides of bitline layers 618, 620, and at least a portion of the IDL layer 622 on the sides of hard mask layers 619, 621 and at least a portion of the sides of bitline layers 618, 620.

[0062] As an example, the deposition operation can be performed at a chemical pressure of 5-40 mT and may involve the use of methane (CH4) and argon (Ar). For example, the duration of the deposition operation may be 4-10 seconds. The top-side electrode (e.g., one of coils 438 in Figure 4) may be 500-1500 watts (W). The bottom-side electrode, such as electrode 467, may be at zero bias and / or at a reference bias level (e.g., grounded). The deposition operation is performed at zero bias to deposit dielectric material on top of the bit line structures 623, 625 rather than at the bottom of the trench 705, or near the top of the bit line structures 623, 625 without depositing more material at the bottom of the trench 705. The deposition operation may include depositing some material at the bottom of the trench 705. The amount of material deposited at the bottom of the trench 705 may be less than the amount of material deposited at the top of the trench 705 and / or at the top of the bit line structures 623, 625. The amount of material deposited along the sides of layers 614, 616, 618, 619, 620, and 621 can decrease with increasing depth, resulting in a variation in the thickness of the deposited material from the top of trench 705 downwards to the bottom of trench 705, with the most material deposited at or near the top of trench 705 and the least material deposited at or near the bottom of trench 705. The trench is at least partially located between bit line structures 623 and 625. Deposition RF conditions are set to deposit polymer on top of bit line structures 623 and 625.

[0063] Each etch cycle is performed at 506, during which a portion of the region between the bitline structure and portions of layers 602, 610, 612, and 622 is etched. Memory structure 600C (shown in Figures 6-7) illustrates the end of an intermediate etch cycle, where a portion of layers 610, 612, and 622 has been removed. Memory structure 600D (shown in Figure 7) illustrates the end of an etch cycle. As shown in memory structure 600D, the etch cycle creates an accessible thin polymer layer 704 on the active silicon region 605. As shown in memory structure 600E (shown in Figures 6-7), a shallow etch process is performed by the etch cycle to expose a portion of the active silicon region 605. This can occur at 508 and / or 512.

[0064] Each etching cycle may include a chemical pressure between 5 and 30 mT and includes nitrogen fluoride (NF3), dichloro(Cl2), hexafluorobutadiene (C4F6), fluoromethane (CH3F), difluoromethane (CH2F2), and / or carbon tetrafluoride (CF4). The chemical may also include helium (He). The duration of each etching operation may be 5-12 seconds. The stated deposition and etching operation durations are provided as examples applicable to critical dimensions of memory structures and implemented to minimize damage to sidewall spacers (e.g., layer 622). For other structures, the times may differ. The top electrode may be 500-1500 W. The bottom electrode may be biased at 500-1500 volts (V). In synchronous operation, the top electrode and the bias (or bottom) electrode may be pulsed simultaneously, or in asynchronous operation, they may be pulsed at different times. In another embodiment, the pulses comprise two pulses greater than 0 V provided at two different non-zero voltage levels (e.g., transformer-coupled plasma (TCP) may pulse between 500 W and 1500 W, and the bias voltage may be between 500-1500 V). During synchronous and asynchronous modes, the pulses may be between a high bias voltage and a low bias voltage, where the low bias voltage may be 0 V or greater than 0 V. Synchronous mode may refer to the high and low voltage signals being in phase (or having matched phase). Asynchronous mode may refer to when the high and low voltage signals are out of phase (e.g., 180° out of phase). In another embodiment, the formulation may require continuous wave operation for both the top electrode and the bias electrode. Continuous wave operation can be performed for transformer-coupled plasma etching, while the bias voltage is provided simultaneously. At 508, system controller 402 may perform an oxygen stripping operation to remove residual polymer formed during the previous etching operation.

[0065] The durations of operations 504, 506, and 508 are very short. Example durations for the deposition and etching operations are provided above. Operations 504, 506, and 508 are performed iteratively to protect layer 622 while etching the bottom trench profile down to the active silicon region 605 and removing residual polymer formed during etching.

[0066] At 510, system controller 402 determines whether a predetermined number of deposition and etching cycles have been performed and / or whether a sufficient depth level has been reached at the site of exposed active silicon. If yes, job 512 is executed; otherwise, job 504 is executed.

[0067] At 512, system controller 402 performs a breakout operation, including etching the remaining polymer (e.g., layer 704) and / or removing a portion of the IDL layer 607 disposed above the active silicon region 605. Memory structure 600E illustrates the result of the breakout operation, exposing a portion 630 of the active silicon region 605. The portion 630 is (i) in region 631 between a portion of the active silicon region 605 and a portion of the intermediate layer 614, and (ii) within the trench region 632 formed by the previously performed etching cycle.

[0068] The breakthrough operation uses a low-voltage plasma and a chemical substance as part of a "Si punch" scheme to etch through into the active silicon region 605. For example, the chemical substance used for the breakthrough operation may include carbon tetrafluoride (CF4) and one or more of argon (Ar) and helium (He). The chemical may be at a temperature of 5-30 mT. The top electrode may be 500-1000 W. The bias voltage may be 50-200 V. The top and bottom electrodes may provide continuous wave and / or pulsed wave signals when operating in synchronous and / or asynchronous modes. In another embodiment, the pulses include providing two pulses greater than 0 V at two different voltage levels (e.g., transformer-coupled plasma (TCP) may pulse between 500 W and 1500 W, and the bias voltage may be between 500-1500 V). During synchronous and asynchronous modes, the pulses may be between a high bias voltage and a low bias voltage, where the low bias voltage may be 0 V or greater than 0 V.

[0069] At 514, system controller 402 can perform a selective over-etch operation to etch a portion of the active silicon region 605. In one embodiment, operation 514 is performed by substrate processing system 400, and system controller 402 performs selective over-etching in the same processing chamber as the previously performed operation. In another embodiment, operation 514 is performed in a different processing chamber and / or a different substrate processing system. The box for operation 514 in Figure 5 is dashed to indicate that operation 514 can be performed in a different processing chamber than the previous operation. Performing operation 514 in the same processing chamber minimizes processing time.

[0070] The result of task 514 is shown by memory structure 600F, which shows the upper portion 633 of the removed active silicon region and portions of layers 602 and 607. The upper portion 633 may refer to the upper region of the removed active silicon and / or the active silicon region where the active silicon was removed. This increases the size of the breakout region and the removed active silicon region. The removed portion of the active silicon region is below layers 610 and 612 and within circle 640. The bottom portion 635 of the active silicon region 605 below the upper portion 633 is retained. The bottom portion 635 may refer to the lower region of the remaining active silicon and / or the active silicon region in which the corresponding active silicon is disposed. Before removal, the periphery of the upper portion 633 is (i) defined on the upper side by IDL 610, (ii) defined on the side by IDL 607, and (iii) defined on the bottom side by the remaining bottom (or lower) portion 635. The upper portion 633 may be trapezoidal. Before removal, the upper portion 633 is disposed between portions of the oxide layer 602 (e.g., portions 602B and 602C) and adjacent to the trench region 632 of the enlarged trench 705'. The etched-away regions corresponding to the active silicon regions 605 of the upper portion 633 extend (i) in a first (or vertical) direction between the lower portion 635 of the active silicon region 605 and the first dielectric layer (e.g., IDL 610), and (ii) in a second (or horizontal) direction perpendicular to the first direction between the trench 705' and the second dielectric layer (e.g., IDL 607). The second dielectric layer extends along a portion of the third dielectric layer (e.g., portion 602C of the oxide layer 602).

[0071] Over-etching operations use high-voltage plasma and a chemical substance to etch silicon at a rapid etch rate without etching other materials (such as oxides and / or silicon nitrides) or minimizing the etching of other materials (such as oxides and / or silicon nitrides). The chemical substance includes gases used to "dig out" the active silicon material, such as CH4, NF3, hydrogen (H2), He, and Ar. The chemical substance may be under high pressure, such as 200-400 mT. High pressure allows for the selective etching of active silicon regions instead of dielectric layers (e.g., oxide and silicon nitride layers). At higher pressures, active silicon regions are etched at a higher rate than dielectric layers. At lower pressures, active silicon regions are etched at a similar rate to dielectric layers.

[0072] The use of CH4 allows for the formation of a thicker polymer (or protective) layer over dielectric layers such as oxides and silicon nitrides, which reduces etching of the dielectric layer. While CH4 has been described above, other similar gases can be used as an alternative, such as those comprising unsaturated and / or saturated hydrocarbon molecules (e.g., C2H4). H2 can help promote the etching of active silicon by forming silane (SiH4) byproducts, while suppressing the etching rates of silicon oxides (SiOx) and SiN. The use of H2 ensures high selectivity to minimize the etching of oxides and silicon nitrides. CH4-like gases (or gases comprising unsaturated and / or saturated hydrocarbon molecules) suppress the silicon nitride etching rate by forming a graphite (CHx) layer on top of the silicon nitride while slightly increasing the oxide etching rate. Oxygen in SiOx can react with CHx to form an active surface material for fluorine etching. NF3 is provided to etch active silicon while maintaining low SiO₂ and silicon nitride etch rates. NF3 is an etchant used to etch active silicon by forming silicon tetrafluoride.

[0073] During over-etching operations, the top electrode can be 300-1000W. The bias voltage can be 0-100V. The top and bottom electrodes can provide continuous or pulsed wave signals for synchronous or asynchronous operation modes. The signals can each transition between (i) a first non-zero state and zero, or (ii) between a first non-zero state and a second non-zero state.

[0074] In one embodiment, operations 502, 504, 506, 508, 510, 512, and 514 are part of a first sub-process of the electro-coupling process, and operations 515, 516, and 518 are part of a second and third sub-process of the electro-coupling process. The first sub-process may end after operation 514, and subsequent operations 515, 516, and 518 are performed as separate processes. Different substrate processing systems can be used to implement the separate processes. As an example, operation 515 can be performed using a wet cleaning system such as that shown in FIG. 9. As an example, operations 516 and 518 can be performed using a plasma-assisted chemical vapor deposition (PECVD) system such as that shown in FIG. 10. The boxes for operations 515, 516, and 518 in FIG. 5 are dashed lines to indicate that these operations are performed in a different substrate processing system and / or chamber than the previously performed operations. In subsequent operation 514, the substrate is transferred to the wet cleaning system shown in FIG. 9.

[0075] At 515, the controller (e.g., system controller 912 of Figure 9) can perform a cleaning operation to clean trench 705' and the corresponding exposed active silicon area. This may include cleaning other exposed surfaces. The cleaning operation may be a wet cleaning operation performed before the filling operation at 516 to clean the surfaces. The cleaning operation may include removing residual polymer formed during one or more previous etching operations.

[0076] After operation 515, the substrate can be transferred to a PECVD system (e.g., substrate processing system 1000 of FIG. 10) or other suitable deposition system. At 516, the system controller (e.g., system controller 1060 of FIG. 10) deposits conductive filler material 650 to fill the area between the etched region and the bit line structure to provide electrical coupling (or conductive element) between the lower portion of the active silicon region and the capacitor to be formed in subsequent operations. The conductive filler material 650 may include polysilicon, CoSi x, and / or other metal-doped silicon. The resulting memory structure 600G is shown in FIG. 6 and is part of the coupling layer 808 of the memory structure 600G of FIG. 8.

[0077] At 518, the system controller 1060 forms an additional layer on the memory structure 600G, which includes a capacitor layer comprising capacitors electrically coupled to a conductive filler material 650. Operation 518 can be referred to as an electrical contact operation. In the example shown, layers 810, 812, 814, 816, and 818 are shown. Although not shown, these layers can be formed during individual operations. As an example, layers 812 and 816 can be conductive layers and include conductors with capacitors. Layer 814 can be a dielectric layer and include a dielectric material with capacitors disposed between the conductors. The method can end at 520.

[0078] The above operation is intended as an illustrative example. Depending on the application, the operation may be performed as follows: sequentially, synchronously, simultaneously, continuously, during overlapping time periods, or in a different order. Furthermore, depending on the order of the implementation and / or events, any of the operations may not be performed or may be omitted.

[0079] Figure 9 shows a wet cleaning system 900, including a processing chamber 902 with a spray head 904 and a substrate support 906 supporting a substrate 908. The wet cleaning system 900 can introduce liquid chemicals via the spray head 910. A system controller 912 controls the operation of the wet cleaning system 900, including the introduction of liquid chemicals. During cleaning, the system controller 912 can rotate (or rotate) at least a portion of the substrate support 906 to rotate the substrate 908 using a motor 914.

[0080] Figure 10 shows a substrate processing system 1000, which may include an ESC 1001 or other substrate support, and a spray head 1003. Although Figure 10 shows a capacitively coupled plasma (CCP) system, the examples described below can be applied to other systems and plasma sources. The substrate processing system 1000 can be implemented as a PECVD system or a chemical vapor deposition (CVD) system.

[0081] The substrate processing system 1000 includes a processing chamber 1005. An ESC 1001 and a spray head 1003 are enclosed within the processing chamber 1005. The processing chamber 1005 may contain RF plasma. During operation, a substrate 1007 is placed on the ESC 1001 and electrostatically held in place. The spray head 1003 introduces and distributes gas. The spray head 1003 may include a rod 1011, one end of which is connected to a top surface of the processing chamber 1005. The spray head 1003 is generally cylindrical and extends radially outward from the opposite end of the rod 1011 (at a location spaced apart from the top surface of the processing chamber 1005). One of the spray heads 1003 facing the substrate surface includes holes through which the processing or purging gas flows.

[0082] An RF generation system 1020 generates and outputs an RF voltage to one or more upper electrodes 1012 in the spray head and / or one or more lower electrodes 1016 in the ESC 1001. The upper electrode 1012 or lower electrode 1016 may be DC grounded, AC grounded, or at a floating potential. By way of example only, the RF generation system 1020 may include one or more RF generators 1022 (e.g., a capacitively coupled plasma RF power generator, a bias RF power generator, and / or other RF power generators) that generate an RF voltage fed to the upper electrode 1012 and / or lower electrode 1016 by one or more matching and distribution networks 1024. As an example, a plasma RF generator 1023, a bias RF generator 1025, a plasma RF matching network 1027, and a bias RF matching network 1029 are shown. The plasma RF generator 1023 may be a high-power RF generator that produces, for example, 100 watts (W) to 10 kilowatts (kW) of power. The bias RF matching network 1029 provides power to the RF electrodes, such as RF electrode 1016.

[0083] A gas delivery system 1030 includes one or more gas sources 1032-1, 1032-2, ..., and 1032-N (collectively referred to as gas sources 1032), where N is a positive integer. Gas sources 1032 supply one or more precursors and their gaseous mixtures. Gas sources 1032 may also supply deposit gases, carrier gases, and / or purge gases. Vaporized precursors may also be used. Gas sources 1032 are connected to a manifold 1040 via valves 1034-1, 1034-2, ..., and 1034-N (collectively referred to as valves 1034) and mass flow controllers 1036-1, 1036-2, ..., and 1036-N (collectively referred to as mass flow controllers 1036). One output of manifold 1040 is fed to a processing chamber 1005. For example only, the output of manifold 1040 is fed to spray head 1003.

[0084] The substrate processing system 1000 may include a temperature controller 1042. The temperature controller 1042 controls a power supply circuit 1044. Although shown as independent of a system controller 1060, the temperature controller 1042 may be implemented as part of the system controller 1060. The power supply circuit 1044 may also provide power (including a high voltage) to the electrode 1031 to electrostatically clamp the substrate 1007 to the ESC 1001. The power supply circuit 1044 may be controlled by the temperature controller 1042 and / or the system controller 1060.

[0085] Based on parameters from other sensors (such as temperature sensor 1045 within processing chamber 1005), temperature controller 1042 may control power supply circuit 1044. Temperature sensor 1045 may include impedance temperature device, thermocouple, digital temperature sensor, and / or other suitable temperature sensor.

[0086] A valve 1056 and a pump 1058 may be used to vent reactants from the processing chamber 1005. A system controller 1060 may control components of the substrate processing system 1000, including controlling the supplied RF power level, the pressure and flow rate of the supplied gas, RF matching, etc. The system controller 1060 controls the state of valve 1056 and pump 1058. A robot 1064 may be used to transport substrates to and from ESC 1001. For example, robot 1064 may transfer substrates between ESC 1001 and a load lock 1066. Robot 1064 may be controlled by system controller 1060. System controller 1060 may control the operation of load lock 1066.

[0087] The valve, gas pump, power source, RF generator, etc. referred to herein may be called a brake. The RF generator 1023 may be called a temperature regulating element herein.

[0088] In one embodiment, the system controller 1060 can control the performance of operations 516 and 518 of the electrical coupling process in FIG5. The substrate can be transferred from processing chamber 902 to processing chamber 1005 to perform operations 516 and 518.

[0089] The examples described herein provide an electrical coupling process to provide a conduction path from the active silicon region to a capacitor with minimal resistance. Resistance is proportional to 1 / area, where area is the area of ​​a cross-section of the conductor perpendicular to the direction of current flowing through it. Because the interface area between the conductive material and the active silicon region material increases, the resistance decreases at these locations.

[0090] Shallow etching of silicon provides additional insulating (dielectric) protection on and / or near the bitline structure, preventing short circuits to capacitors and / or active silicon regions. High-voltage plasma over-etching and subsequent filling provide a wider conductive window. This window can have a square profile and include the area of ​​the etched-away active silicon region. This process solution enables shallow etching while maintaining the integrity of the protective layer positioned above the bitline structure. The etching of the exposed active silicon regions occurs while minimizing etching of other layers, increasing memory device yield and reducing corresponding manufacturing costs.

[0091] The foregoing description is illustrative in nature and is in no way intended to limit this disclosure, its application, or its uses. The broad teachings of this disclosure can be implemented in various forms. Therefore, although this disclosure contains specific examples, its true scope should not be so limited, as other modifications will become apparent upon review of the drawings, patent specifications, and accompanying claims. It should be understood that one or more steps within a method may be performed in different orders (or simultaneously) without altering the principles of this disclosure. Furthermore, although each embodiment is described above as having certain features, any one or more of these features described with respect to any embodiment of this disclosure may be implemented in, and / or combined with, features of any other embodiment, even if such combination is not explicitly described. In other words, the embodiments are not mutually exclusive, and substitution of one or more embodiments for each other remains within the scope of this disclosure.

[0092] Although the terms first, second, third, etc., may be used herein to describe various operations, elements, components, regions, areas, layers, structures, and / or portions, these steps, elements, components, regions, areas, layers, structures, and / or portions should not be limited by these terms unless otherwise stated. These terms may be used only to distinguish one step, element, component, region, area, layer, structure, or portion from another. Terms such as "first," "second," and other numerical terms used herein do not imply sequence or order unless the context clearly indicates otherwise. Therefore, a first step, element, component, region, area, layer, structure, or portion discussed herein may be referred to as a second step, element, component, region, area, layer, structure, or portion without departing from the teachings of the exemplary embodiments.

[0093] Various terms are used to describe the spatial and functional relationships between components (e.g., between modules, circuit elements, semiconductor layers, etc.), including "connection," "joint," "coupled," "adjacent," "close to," "above," "above," "below," and "configuration." Unless explicitly described as "direct," the relationship between the first and second components described in the above disclosure can be a direct relationship in which no other intermediate components exist between the first and second components, or an indirect relationship in which one or more intermediate components exist between the first and second components (spatially or functionally). As used herein, expressions such as "at least one of A, B, and C" and "at least one of A, B, or C" should be understood as meaning a logic (A or B or C) using non-exclusive OR logic, and should not be understood as meaning "at least one of A, at least one of B, and at least one of C."

[0094] In several embodiments, the controller is part of a system, which may be part of one of the examples described above. Such systems may include semiconductor processing equipment comprising: a processing tool or a plurality of processing tools; a chamber or a plurality of chambers; a processing platform or a plurality of processing platforms; and / or specific processing components (wafer pedestals, airflow systems, etc.). Such systems may be combined with electronic equipment to control their operation before, during, and after processing steps on a semiconductor wafer or substrate. Such electronic equipment may refer to a "controller" that controls various components or sub-components of the system or plurality of systems. Depending on processing requirements and / or system type, the controller may be programmable to control any process disclosed herein, including process gas delivery, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, radio frequency (RF) generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, position and operation settings, wafer transfer into and out of tools connected to or interfacing with a specific system, and other transfer tools and / or load locks.

[0095] In a broad sense, the controller may be defined as an electronic device having various integrated circuits, logic devices, memories, and / or software that receives instructions, issues instructions, controls operations, initiates cleaning operations, initiates endpoint measurements, and the like. These integrated circuits may include chips in the form of firmware storing program instructions, digital signal processors (DSPs), chips defined as application-specific integrated circuits (ASICs), and / or one or more microprocessors, or microcontrollers that execute program instructions (e.g., software). Program instructions may be instructions transmitted to the controller in the form of various independent settings (or program files), defining operational parameters on or on a semiconductor wafer or for performing specific programming on a system. In some embodiments, these operational parameters may be part of a recipe defined by a process engineer to complete one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of the wafer.

[0096] In several implementations, the controller may be coupled to or part of a computer, which may be integrated with, coupled to, or otherwise networked to the system, or a combination thereof. For example, the controller may be in the "cloud" or be all or part of a wafer fab host computer system, allowing remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of manufacturing operations, view historical records of past manufacturing operations, view trends or performance indicators from manufacturing operations, change parameters of the current process, set processing steps after the current process, or start a new process. In several examples, a remote computer (e.g., a server) may provide process recipes to the system via a network, which may include a local area network or the Internet. The remote computer may include a user interface that allows input or programming of parameters and / or settings, which are then transferred from the remote computer to the system. In several examples, the controller receives instructions in the form of data specifying parameters for each processing step to be performed during one or more operations. It should be understood that these parameters may be specific to the type of process to be implemented and the type of tool to which the controller is configured to interface with or control. Therefore, as described above, the controller may be distributed, for example, through a plurality of separate controllers that are networked together and operate toward a common purpose (e.g., the process and control described herein). An example of a distributed controller for such a purpose is a plurality of integrated circuits on a chamber that communicate with a plurality of integrated circuits located remotely (e.g., at a platform level or as part of a remote computer), which combine to control the process on the chamber. Not limited to this, the illustrated system may include plasma etching chambers or modules, deposition chambers or modules, spin-wash chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, orbital chambers or modules, and any other semiconductor processing systems that may be associated with or used in the manufacture and / or production of semiconductor wafers.

[0097] As shown above, depending on the more than one processing step to be performed by the tool, the controller may communicate with one or more of the following: other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout the plant, a host computer, another controller, or tools used for material transfer to carry wafer containers to and from tool locations and / or load ports within the semiconductor manufacturing plant.

[0098] 100: Memory Unit 102: Character Line 104: Bitline 106: Reference Terminal 200A, 200B, 200C, 200D, 200E, 200F: Memory Structure 202: Floor 202A, 202B, 202C: Partial (Layers) 204: Active silicon region 205: Active silicon region 206: Layer (IDL) 207: Layer (IDL) 210: Layer (IDL) 212: Layer (IDL) 214: Floor 216: Floor 218: Floor 219: Floor 220: Floor 221: Floor 222: Layer (IDL) 223: Bitline Structure 224: Part 225: Bitline Structure 226: Area 228: Trench 230: Polycrystalline silicon 240: Area 242: Area 243: Circle 300, 302: Protective layer 400: Substrate Processing System 402: System Controller 406: Backside Gas Circuit 410: Gas delivery system 412: Gas Source 414: Valve 416:Substrate 418:ESC 420, 422: Temperature sensors 430: Coil drive circuit 432: RF source 434: Pulse Circuit 436: Tuning Circuit 438: Coil 440: Reverse Circuit 450: Inflatable section 452: Dielectric window 454: Processing Room 456: Plasma 460: RF bias circuit 462: RF source 464: Pulse Circuit 466: Bias Matching Circuit 467: Electrode 470: Gas delivery system 472: Inert gas source 474: Gas metering system 476: manifold 480: Gas delivery system 482: Gas Source 484: Valve 486: Exhaust System 488: Valve 490: Pump 492: Probe 494: Phase / Amplitude Detector 495: Formula 496: Memory 498: Electrode 499: Power Source 500, 502, 504, 506, 508, 510, 512, 514, 515, 516, 518, 520: Homework 600A~600G: Memory Structure 602: Floor 602A, 602B, 602C: Partial (Layer) 604, 605: Active silicon regions 606: Layer (IDL) 607: Layer (IDL) 610: Layer (IDL) 612: Layer (IDL) 614: Floor 616: Floor 618: Floor 619: Floor 620: Floor 621: Floor 622: Layer (IDL) 623: Bitline Structure 625: Bitline Structure 630: Part 631: Area 632: Trench area 633: Upper part 635: Part 640: Circle 650: Conductive filler material 700: Arrow 701, 702: Floors 704: Floor 705, 705': Groove 800: Basal layer 808: Coupling layer 810, 812, 814, 816, 818: Layers 802, 804, 806: Intermediate layer 900: Wet Cleaning System 902: Processing Room 904: Spray head 906: Substrate support 908:Substrate 910: Sprayer Head 912: System Controller 914: Motor 1000: Substrate Processing System 1001:ESC 1003: Spray head 1005: Processing Room 1007:Substrate 1011: Pole section 1012: Upper electrode 1016: Electrode 1020: RF Generation System 1022: RF Generator 1023: RF Generator 1024: Matching and Distribution Networks 1025: Biased RF Generator 1027: Plasma RF Matching Network 1029: Biased RF Matching Network 1030: Gas delivery system 1031: Electrode 1032-1, 1032-2, 1032-N: Gas source 1034-1, 1034-2, 1034-N: Valve 1036-1, 1036-2, 1036-N: Mass Flow Controller 1040: Branch Pipe 1042: Temperature Controller 1044: Power Supply Circuit 1045: Temperature sensor 1056: Valve 1058: Pump 1060: System Controller 1064: Robot 1066: Load Lock

Claims

1. A substrate processing system comprising: a memory configured to store a recipe for at least a portion of an electrical coupling process for electrically coupling a capacitor to an active silicon region of a memory structure; and a system controller configured to perform the at least a portion of the electrical coupling process according to the recipe, comprising: performing multiple deposition and etching cycles to remove portions of one or more dielectric layers from a substrate, enlarging a trench between adjacent bit line structures of the memory structure, and providing access to at least one of a dielectric layer or a polymer layer adjacent to an upper portion of the active silicon region; performing a breakthrough operation comprising etching the at least one of the polymer layer or the dielectric layer in the trench to expose the upper portion of the active silicon region; and performing an over-etch operation to remove the upper portion of the active silicon region, thereby providing access to electrically couple the capacitor to the remaining portion of the active silicon region.

2. The substrate processing system of claim 1, wherein the one or more dielectric layers comprises an oxide layer and a silicon nitride layer.

3. The substrate processing system of claim 1, wherein the deposition cycle of the plurality of deposition and etching cycles includes the supply of argon and the supply of at least one of unsaturated hydrocarbon molecules or saturated hydrocarbon molecules.

4. The substrate processing system of claim 1, wherein the deposition cycle of the plurality of deposition and etching cycles includes the supply of methane and argon.

5. The substrate processing system of claim 4, wherein the deposition cycle comprises supplying the methane and argon at a pressure greater than or equal to 5 mT and less than or equal to 40 mT.

6. The substrate processing system as described in claim 4, wherein: The substrate is processed in a processing chamber; and the system controller avoids applying a bias voltage to one of the electrodes of the processing chamber during the deposition cycles.

7. The substrate processing system of claim 1, wherein the etching cycle of the plurality of deposition and etching cycles includes supplying a plurality of gases, the plurality of gases including (i) at least one of nitrogen fluoride, dichloro, hexafluorobutadiene, fluoromethane, difluoromethane, or carbon tetrafluoride, and (ii) helium.

8. The substrate processing system of claim 7, wherein the etching cycles include supplying the plurality of gases at a pressure greater than or equal to 5 mT and less than or equal to 30 mT.

9. The substrate processing system of claim 1, wherein the etching cycle of the plurality of deposition and etching cycles includes at least one of applying a continuous wave to one or more electrodes or applying a pulsed radio frequency signal.

10. The substrate processing system of claim 1, wherein the breakthrough operation includes supplying carbon tetrafluoride and at least one of argon or helium.

11. The substrate processing system of claim 10, wherein the breakthrough operation comprises: supplying at least one of the carbon tetrafluoride and the argon or helium at a pressure greater than or equal to 5 mT and less than or equal to 30 mT.

12. The substrate processing system of claim 1, wherein the breakthrough operation includes at least one of applying a continuous wave to one or more electrodes or applying a pulsed radio frequency signal.

13. The substrate processing system of claim 1, wherein the over-etching operation comprises supplying a plurality of gases at a pressure greater than or equal to 200 mT and less than or equal to 400 mT.

14. The substrate processing system of claim 13, wherein the over-etching operation includes supplying at least one of nitrogen trifluoride, hydrogen, or methane.

15. The substrate processing system of claim 14, wherein the over-etching operation includes supplying at least one of argon or helium.

16. The substrate processing system of claim 13, wherein the over-etching operation includes supplying nitrogen trifluoride, hydrogen, and methane.

17. The substrate processing system of claim 1, wherein the over-etching operation includes at least one of applying a continuous wave to one or more electrodes or applying a pulsed radio frequency signal.

18. The substrate processing system of claim 1, wherein the over-etching operation is performed but the exposed portion of the intermediate dielectric layer in the trench and on the adjacent bit line structure is not removed.

19. The substrate processing system of claim 1, wherein the breakthrough operation is performed after the multiple deposition and etching cycles are performed.

20. The substrate processing system of claim 1, wherein at least one of the polymer layer or the dielectric layer extends upward along the active silicon region toward one of the equipotential line structures.

21. The substrate processing system of claim 1, wherein the active silicon region is located below one of the equipotential line structures and is separated from the trench by at least one of the polymer layer or the dielectric layer.

22. The substrate processing system of claim 1, wherein the oxide layer is disposed below the trench and between a plurality of active silicon regions, the plurality of active silicon regions being disposed below the adjacent bit line structures.

23. The substrate processing system of claim 1, wherein the over-etching operation includes supplying a gas different from that supplied during the breakthrough operation at a pressure different from that supplied during the breakthrough operation.

24. A method for electrically coupling a capacitor to an active silicon region of a memory structure, comprising: providing a substrate including the memory structure; performing multiple deposition and etching cycles to remove portions of one or more dielectric layers from the substrate, enlarge a trench between adjacent bit line structures of the memory structure, and provide access to at least one of a polymer layer or a dielectric layer adjacent to an upper portion of the active silicon region; performing a breakthrough operation comprising etching the at least one of the polymer layer or the dielectric layer in the trench to expose the upper portion of the active silicon region; and performing an over-etching operation to remove the upper portion of the active silicon region to provide access for electrically coupling the capacitor to a remaining lower portion of the active silicon region.

25. The method of electrically coupling a capacitor to an active silicon region of a memory structure as described in claim 24, wherein: The memory structure includes: a first dielectric layer containing the active silicon region, the equipotential line structure, and the trench adjacent to the active silicon region; the lower portion of the active silicon region containing active silicon; a second dielectric layer disposed on the upper portion; and one of the equipotential line structures disposed on the second dielectric layer.

26. The method of electrically coupling a capacitor to an active silicon region of a memory structure as claimed in claim 25, further comprising: filling the trench and an open region remaining after removing the upper portion of the active silicon region with a conductive material for electrically coupling the capacitor to the active silicon in the active silicon region.

27. The method of electrically coupling a capacitor to an active silicon region of a memory structure as claimed in claim 24, wherein the more than one dielectric layer comprises an oxide layer and a silicon nitride layer.

28. The method of electrically coupling a capacitor to an active silicon region of a memory structure as claimed in claim 24, wherein the deposition cycle of the plurality of deposition and etch cycles includes the supply of methane and argon.

29. The method of electrically coupling a capacitor to an active silicon region of a memory structure as claimed in claim 28, wherein the deposition cycle comprises supplying the methane and argon at a pressure greater than or equal to 5 mT and less than or equal to 40 mT.

30. The method of electrically coupling a capacitor to an active silicon region of a memory structure as claimed in claim 28, further comprising avoiding applying a bias voltage to an electrode of a processing chamber during the deposition cycle, wherein the substrate is processed in the processing chamber.

31. The method of electrically coupling a capacitor to an active silicon region of a memory structure as claimed in claim 24, wherein the etch cycle of the plurality of depositions and etches includes supplying a plurality of gases, the plurality of gases including (i) at least one of nitrogen fluoride, dichloro, hexafluorobutadiene, fluoromethane, difluoromethane, or carbon tetrafluoride, and (ii) helium.

32. The method of electrically coupling a capacitor to an active silicon region of a memory structure as claimed in claim 31, wherein the etching cycle comprises supplying the plurality of gases at a pressure greater than or equal to 5 mT and less than or equal to 30 mT.

33. The method of electrically coupling a capacitor to an active silicon region of a memory structure as claimed in claim 24, wherein the etch cycle of the plurality of deposition and etch cycles includes at least one operation of applying a continuous wave to one or more electrodes or an operation of applying a pulsed radio frequency signal.

34. The method of electrically coupling a capacitor to an active silicon region of a memory structure as claimed in claim 24, wherein the breakthrough operation includes supplying carbon tetrafluoride and supplying at least one of argon or helium.

35. The method of electrically coupling a capacitor to an active silicon region of a memory structure as claimed in claim 34, wherein the breakthrough operation comprises supplying at least one of the carbon tetrafluoride and the argon or helium at a pressure greater than or equal to 5 mT and less than or equal to 30 mT.

36. The method of electrically coupling a capacitor to an active silicon region of a memory structure as claimed in claim 24, wherein the breakthrough operation includes at least one of applying a continuous wave or a pulsed radio frequency signal to one or more electrodes.

37. The method of electrically coupling a capacitor to an active silicon region of a memory structure as claimed in claim 24, wherein the over-etching operation comprises supplying a plurality of gases at a pressure greater than or equal to 200 mT and less than or equal to 400 mT.

38. The method of electrically coupling a capacitor to an active silicon region of a memory structure as claimed in claim 36, wherein the over-etching operation includes supplying at least one of nitrogen trifluoride, hydrogen, or methane.

39. The method of electrically coupling a capacitor to an active silicon region of a memory structure as claimed in claim 37, wherein the over-etching operation includes supplying at least one of argon or helium.

40. The method of electrically coupling a capacitor to an active silicon region of a memory structure as claimed in claim 36, wherein the over-etching operation includes supplying nitrogen trifluoride, hydrogen, and methane.

41. The method of electrically coupling a capacitor to an active silicon region of a memory structure as claimed in claim 24, wherein the over-etching operation includes at least one of applying a continuous wave to one or more electrodes or applying a pulsed radio frequency signal.

42. The method of electrically coupling a capacitor to an active silicon region of a memory structure as claimed in claim 24, further comprising: cleaning the trench and the upper portion of the active silicon region; and filling the trench and the upper portion of the active silicon region with a conductive material to provide a conductive element for electrically coupling the capacitor to the remaining lower portion of the active silicon region.

43. The method of electrically coupling a capacitor to an active silicon region of a memory structure as claimed in claim 42, further comprising: forming a plurality of layers on the equibit line structure and the conductor element, wherein the plurality of layers include the capacitor.

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