Universal hybrid bonding surface layer using an adaptable interconnect layer for interface disaggregation

Abstract

The embodiments disclosed herein include semiconductor dies having a hybrid bonding layer and multi-die modules coupled together by the hybrid bonding layer. In one embodiment, the semiconductor die includes a die substrate and a pad layer on the die substrate, wherein the pad layer includes a first pad having a first size and a first pitch and a second pad having a second size and a second pitch. In one embodiment, the semiconductor die further includes a hybrid bonding layer located on the pad layer. In one embodiment, the hybrid bonding layer includes a dielectric layer and an array of hybrid bonding pads in the dielectric layer, wherein the hybrid bonding pads include a third size and a third pitch.

Description

Technical Field

[0001] The embodiments disclosed herein relate to electronic packaging, and more specifically to electronic packaging architectures having a universal hybrid bonding surface layer. Prior Technology

[0002] Complex computing systems are increasingly based on the principle of heterogeneous integration, where many semiconductor devices / wafers using different technologies (and materials) are combined into a single functional unit to meet diverse future computing needs. Hybrid bonding is a key technology that enables continuous computing and bandwidth expansion in such systems. Heterogeneous integrated computing systems, which achieve vertical connectivity between different computing layers through hybrid bonding, consist of many individual semiconductor tiles / wafers / dies.

[0003] A key process operation in manufacturing this hybrid bonding system is creating the hybrid bonding interface. Precise chemical mechanical polishing (CMP) is required to achieve the structure and dimensions needed for high-yield hybrid bonding processes. However, CMP is highly dependent on metal density and feature size. For existing hybrid bonding interfaces, this means that the CMP process needs to be tailored for each platform (and even each product skew) to achieve optimal hybrid bonding capabilities. This is because the pad layout and dimensions may differ, and metal density and dielectric design rules will also vary. The result is that each product requires significant CMP process variations, even if the surface is on the same process node or sub-node. Summary of the Invention

[0004] and Simple Explanation of the Diagram

[0005] [Figure 1A] is a planar illustration of a hybrid bonding interface layer using an existing architecture.

[0006] [Figure 1B] is a plan view of a hybrid bonding interface having a uniform array of hybrid bonding pads according to an embodiment.

[0007] [Figure 2] is an illustration of the various layers of a uniformly mixed bonding interface provided according to an embodiment.

[0008] [Figure 3A] is a cross-sectional view of a base die coupled to a plurality of small wafers according to an embodiment using a consistent hybrid bonding interface.

[0009] [Figure 3B] is a cross-sectional view of a base grain having a hybrid bonding interface according to an embodiment, wherein the hybrid bonding interface is bonded to a small wafer having a standard bonding interface.

[0010] [Figure 4A] is a plan view of a single pad connected to a plurality of hybrid bonding pads according to an embodiment.

[0011] [Figure 4B] is a plan view of a plurality of pads connected to a single hybrid bonding pad according to an embodiment.

[0012] [Figure 5A] is a cross-sectional view of a plurality of layered polycrystalline modules coupled together by a hybrid bonding interface according to an embodiment.

[0013] [Figure 5B] is a plan view of a portion of the interface between the first layer and the second layer of a polycrystalline module according to an embodiment.

[0014] [Figure 5C] is a plan view of a portion of the interface between the second and third layers of a polycrystalline module according to an embodiment.

[0015] [Figure 5D] is a cross-sectional view illustrating a portion of a polycrystalline module with a hybrid bonding interface according to an embodiment.

[0016] [Figure 6A] is a cross-sectional view of grains to be joined together by hybrid bonding according to an embodiment, wherein the alignment is perfect.

[0017] [Figure 6B] is a cross-sectional view of grains to be joined together by hybrid bonding according to an embodiment, wherein alignment is off and adaptive lithography is used to correct alignment.

[0018] [Figures 7A-7C] are cross-sectional views depicting a process for forming grains with a uniform hybrid bonding interface according to an embodiment.

[0019] [Figures 8A-8H] are cross-sectional views depicting a process according to an embodiment of using adaptive lithography to correct alignment problems of hybrid bonding interfaces in a polydiode module.

[0020] [Figure 9] is a cross-sectional view of an electronic system having a multi-die module using a consistent hybrid bonding interface combination, according to an embodiment.

[0021] [Figure 10] is a schematic diagram of a computing device constructed according to an embodiment. Implementation

[0022] This description pertains to electronic packaging architectures with a common hybrid bonding surface layer according to various embodiments. In the following description, various illustrative embodiments will be described using terms commonly used by those skilled in the art in order to convey the nature of their operation to others skilled in the art. However, it will be apparent to those skilled in the art that the invention may be implemented with only a few of the described embodiments. Specific figures, materials, and configurations are presented for purposes of explanation to provide a thorough understanding of the illustrative embodiments. However, it will be apparent to those skilled in the art that the invention may be implemented without such specific details. In other instances, well-known features have been omitted or simplified so as not to obscure the illustrative embodiments.

[0023] Various operations will be described as multiple separate operations, sequentially in a manner most helpful for understanding the invention; however, the order of description should not be construed as meaning that these operations must be sequential. In particular, these operations do not need to be performed in the order presented.

[0024] To provide context for the embodiments disclosed herein, hybrid bonding is a process for bonding semiconductor dies (which may be referred to as dies, wafers, tiles, etc.) together without the use of solder. In a hybrid bonding (HB) process, HB layers are disposed on two dies. HB layers comprise dielectric layers having HB pads embedded in dielectric layers. The top surface of the HB pads may be substantially coplanar with the top surface of the dielectric layer. In some instances, the top surface of the HB pads may be one to several nanometers below the top surface of the dielectric layer. To initiate bonding, a pair of HB layers are brought into contact with each other. At substantially room temperature, the dielectric layers begin to bond with each other. The temperature may then be increased. As previously described, this results in a contact of metal pads (typically copper pads) that may be slightly recessed because the coefficient of thermal expansion of a metal (e.g., copper) is higher than that of the surrounding dielectric. This contact and the increased temperature result in cross-diffusion between the HB pads on the relative wafers. In some embodiments, cross-diffusion may even result in no discernible interface between the HB pads. That is, the HB pads may substantially merge to form a single conductive structure.

[0025] HB processes are particularly useful in multi-die modules because they enable extremely high-density interconnects. In some embodiments, the pitch of the HB pads can be approximately 40 μm or less, or approximately 10 μm or less. Therefore, extremely high input / output (I / O) density can be provided to increase bandwidth capabilities.

[0026] As mentioned above, the HB architecture is constrained by the need for a precise chemical mechanical polishing (CMP) process that is heavily dependent on metal density and metal size. Therefore, any change to the HB layer may require a new CMP formulation. Furthermore, designing an appropriate CMP formulation is particularly challenging when there are significant variations in the HB layer's dimensions.

[0027] An example of HB layer 110 is shown in Figure 1A. As shown, HB layer 110 includes a plurality of pads 115 embedded in dielectric layer 112. Pads 115 may include different sizes. Furthermore, different arrays 120 A-120 E have different pitches (e.g., a first pitch P1 in array 120 A or a second pitch P2 in array 120 D). Additionally, there are significant gaps 111 between different arrays 120, without pads 115. Therefore, the metal density is non-uniform. The variation in array 120 is driven by different dies that will be coupled to the underlying dies to form a polydiode module. Different dies may provide different functionalities, be located at different process nodes, come from different suppliers, or have many other differences. Therefore, it is currently impossible to provide a consistent HB layer.

[0028] Accordingly, the embodiments disclosed herein include architectures capable of using a consistent (or generic) HB layer. The advantage of a consistent HB layer is that different CMP formulations are not required for different products, as the HB layer is always the same. Furthermore, a consistent HB layer provides a consistent metal density on the HB layer, which simplifies CMP formulation. Figure 1B shows an example of a consistent HB layer.

[0029] Referring now to FIG1B, a plan view of a uniform HB layer 110 according to one embodiment is shown. As shown, a plurality of HB pads 115 are disposed in a single array 120. The HB pads 115 have a uniform first pitch P1 across the dielectric layer 112. It should be understood that, for the reasons described above, existing dies may not be directly compatible with such a uniform HB layer 110. Therefore, the embodiments disclosed herein include the use of a redistribution layer to reroute the pads on the die to be compatible with the uniform HB layer 110.

[0030] Referring now to Figure 2, a series of layers 203, 205, and 210 are shown (top) and stacked together (bottom). In one embodiment, layer 203 is an existing pad layout of the dies in dielectric layer 224. Pads 225 may have inconsistent pitch and / or size. For example, pad 225 A may be smaller and have a smaller pitch than pad 225 B. In some instances, pad 225 A may be an I / O pad, while pad 225 B may be a power pad and / or a ground pad.

[0031] Now referring to layer 205, a redistribution trace 223 in dielectric layer 222 is shown. Redistribution trace 223 reroutes the location of the underlying pad 225 to match the layout of the overlying HB pad 215 in HB layer 210. HB pad 215 may be in dielectric layer 212.

[0032] As shown in the bottom composite diagram, each pad 225 A is routed to an HB pad 215. It should be understood that, for clarity, the vertical vias connecting the layers are omitted. In some embodiments, pads 225 A and HB pads 215 can have a 1:1 ratio. Conversely, pads 225 B can have a one-to-many ratio. For example, in Figure 2, pads 225 B have a 1:6 or 1:9 ratio, but other ratios are also possible. The presence of a dummy HB pad 215 D is also illustrated in Figure 2. The dummy HB pad 215 D may not be connected to any circuitry on the die. However, the presence of the dummy HB pad 215 D keeps the metal density consistent, thus reducing the complexity of the CMP formulation.

[0033] Referring now to FIG3A, a cross-sectional view of a multi-die module 300 according to one embodiment is shown. In one embodiment, the multi-die module 300 may include a base die 301 A. A plurality of small wafers 301 B are coupled to the base die 301 A using an HB process. In one embodiment, the base die 301 A may include a back-end process (BEOL) stack 302. A first pad 325 A may be disposed on the BEOL stack 302 in dielectric layer 324 A. The first pad 325 A may be a non-uniform pad architecture. That is, the first pad 325 A may have multiple pitches, dimensions, etc.

[0034] In one embodiment, via 326 A provides a connection to redistribution layer 322 A. In redistribution layer 322 A, trace 323 A can be rerouted to the location of the underlying first pad 325 A. Traces 323 A can be connected via via 327 A to an overlying HB layer including HB pad 315 A in dielectric layer 312 A. HB pad 315 A can have a consistent pitch and size, similar to HB layer 110 in FIG. 1B. In a particular embodiment, HB pad 315 A can have a pitch of approximately 40 μm or less, or approximately 10 μm or less.

[0035] The small wafer 301 B has a similar architecture. A first pad 325 B is in dielectric layer 324 B. A via 326 B connects the first pad 325 B to a trace 323 B in redistribution layer 322 B. A via 327 B can then couple the trace 323 B to an HB pad 315 B in dielectric layer 312 B. Dielectric layers 312 A and 312 B are bonded together, and HB pads 315 A and 315 B are aligned with each other, thus bonding together.

[0036] Although each of the wafers 301 B in Figure 3A is shown to be substantially similar to one another, it should be understood that the embodiments allow for increased flexibility in using wafers with different pad designs. In particular, the addition of routing layer 322 allows substantially any incoming pad architecture to be rerouted to conform to a consistent HB pad layout. In some embodiments, wafer 301 B and / or base die 301 A may be sourced from an external supplier, and redistribution layer 322 and consistent HB layer are formed on the existing pads by combining one of the dies. In other embodiments, the supplier of wafer 301 B and / or base die 301 A may have already incorporated the consistent HB layer into the product prior to sale.

[0037] In Figure 3A, both the base die 301 A and the wafer 301 B have a consistent HB layer. However, it should be understood that in some embodiments, the consistent HB layer may only be located on one side of the interface. An example of this embodiment is shown in Figure 3B. Similar to the embodiment in Figure 3A, the multi-die module 300 includes a base die 301 A with a BEOL stack 302 A. The redistribution layer 322 reroutes the first pad 325 A to a consistent HB layer with HB pads 315 in the dielectric layer 312. However, the wafer 301 B may include a BEOL stack 302 B with non-consistent pads 325 B. The non-consistent pads 325 B can then be bonded to the HB pads 315 using a hybrid bonding process. That is, the consistent regions of the HB pads 315 can still be bonded to the discrete pad regions of the wafer 301 B. However, it should be understood that such an HB process would be more challenging and increase the design complexity of the HB pad redistribution layer 322, and may limit the choice of geometry.

[0038] Referring now to Figures 4A and 4B, enlarged illustrations of different interconnect routing schemes that can be used according to the embodiments disclosed herein are shown. As shown in Figure 4A, a single first pad 425 is shown. The single first pad 425 can be a pad that is relatively larger than other first pads 425 on a given die. For example, the first pad 425 shown can be a power pad or a ground pad. Due to the increased current that can be provided through the first pad 425, it may be necessary to connect the first pad 425 to multiple HB pads 415. In this way, a plurality of traces 423 in the redistribution layer laterally extend the first pad 425 to the HB pads 415. Although a 1:9 ratio (first pad: HB pad) is shown in Figure 4A, it should be understood that any ratio can be used according to the embodiments disclosed herein.

[0039] The ratio can also be reversed, as shown in Figure 4B. For example, a plurality of first pads 425 can be coupled to a single HB pad 415. In such an embodiment, traces 423 in the redistribution layer laterally reduce the first pads 425 to a single HB pad 415. Such an embodiment may be useful when the first pads 425 are part of a BEOL stack with typically small feature sizes. Although a 9:1 ratio is shown in Figure 4B, it should be understood that any ratio can be used according to the embodiments disclosed herein.

[0040] In the previously described embodiments, the polycrystalline module is shown to have a first layer and a second layer. However, it should be understood that embodiments can utilize HB layers to couple any number of layers together. Figure 5A shows an example of an embodiment with three layers 530 1-530 3.

[0041] Referring now to FIG5A, a cross-sectional view of a multi-die module 500 according to an embodiment is shown. As shown, the multi-die module 500 includes three layers 530 1, 530 2, and 530 3. Each layer 530 may include one or more dies 501. For example, a single die 501 A is in the first layer 530 1, a pair of dies 501 B are in the second layer 530 2, and a plurality of dies 501 C are in the third layer 530 3. In some embodiments, the die 501 may include a through-substrate via (TSV) 536 to provide electrical connectivity through the thickness of the die 501. Through-layer vias 534 or 535 through the thickness of the layer 530 may also be provided to provide electrical connectivity between the layers 530.

[0042] In one embodiment, the interfaces between layers 530 (e.g., interfaces 531 and 532) may include a consistent HB layer. In some embodiments, layers 530 at a given interface (e.g., layers 530 1 and 530 2 at interface 531) may have a consistent HB layer, similar to the embodiment shown in FIG. 3A. In other embodiments, one of the layers 530 at a given interface may have a consistent HB layer, similar to the embodiment shown in FIG. 3B. In some embodiments, interface 531 may have the same HB layer layout as interface 532. That is, interface 531 may have HB pads with a first pitch, and interface 532 may have HB pads with a first pitch.

[0043] In other embodiments, interface 531 may have a different HB layout than interface 532. Examples of such embodiments are shown in Figures 5B and 5C. As shown in Figures 5A and 5B, a consistent array of HB pads 515 is provided. However, HB pad 515 1 at interface 531 (Figure 5B) has a larger size and second pitch P2 and first pitch P1 than HB pad 515 2 at interface 532 (Figure 5C).

[0044] Referring now to FIG. 5D, an enlarged view of region 533 in FIG. 5A according to an embodiment is shown. Specifically, FIG. 5D shows that consistent HB pads 515 A and 515 B can also be used to provide interconnects to the outside of the die. For example, a through-layer via 534 in layer 530 1 is coupled to a pair of through-layer vias 535 in layer 530 2 via HB pads 515 A and 515 B. FIG. 5D also illustrates that HB pads 515 A and 515 B may be misaligned in certain situations. Misalignment between HB pads 515 may be the result of incorrect placement during assembly. That is, placing components in a high-volume manufacturing environment typically involves a degree of inaccuracy. Misalignment between HB pads 515 can be tolerated as long as the inaccuracy is within acceptable error limits.

[0045] However, as the pitch and size of HB pads continue to increase, the acceptable error range may be less than the accuracy of the pick-and-place tool. In such embodiments, adaptive patterning can be used to address component placement inaccuracies. Adaptive patterning can be implemented on the traces within the redistribution layer. For example, the traces can be lengthened, shortened, and / or rotated to accommodate component placement inaccuracies.

[0046] Referring now to FIG. 6A, a cross-sectional view of dies 601 A and 601 B to be connected to die 601 C according to an embodiment is shown. In the embodiment of FIG. 6A, alignment is shown as the ideal case with zero misalignment. As shown, the pad 625 on the BEOL stack 602 is perfectly aligned with the HB pad 615 A ​​in the dielectric 612 A. In this way, the trace 626 in the redistribution layer 624 only needs to be a via to establish a connection between the HB pad 615 A ​​and the pad 625. The HB pad 615 C and the dielectric 612 C can then be made to contact the HB pads 615 A ​​and 612 A (and the HB pad and dielectric on die 601 B) to establish a connection between dies 601.

[0047] However, when misalignment exists in the placement of dies 601 A and 601 B, the traces 626 in the redistribution layer 624 can be extended to resolve the misalignment issue. This is particularly useful when two base dies 601 are misaligned in different directions and / or sizes. For example, in Figure 6B, die 601 A is offset to the right by a distance D, and die 601 B is offset to the left by a distance D. Misalignment in different directions means that the top die 601 C cannot be moved to resolve the misalignment of the two lower dies 601 A and 601 B. This becomes more problematic as the number of multi-die modules increases. To resolve the misalignment of both dies 601 A and 601 B, the trace 626 on die 601 A extends to the left, while the trace 626 on die 601 B extends to the right. HB pad 615 A ​​can be placed above the trace 626 and properly aligned with HB pad 615 C on the top die 601 C.

[0048] It should be understood that this routing can be completed in real time as information about die placement is obtained. For example, dies 601 A and 601 B can be placed in place using a pick-and-place tool. The placement of dies 601 A and 601 B can be sensed (e.g., through imaging) to detect the offset of each die 601. The offset of each die 601 can be analyzed by software to determine the appropriate routing of trace 626 to resolve misalignment issues. An adaptive patterning tool (e.g., direct lithography) can be used to pattern the redistribution layer of the bottom dies 601 A and 601 B. Those skilled in the art will recognize that the use of adaptive patterning can be inferred from the analysis of several systems. Comparing redistribution layers will show that one or more redistribution lines are variable across different systems. That is, a given redistribution line compared across systems may have inconsistent lengths and / or rotations.

[0049] Referring now to Figures 7A-7C, according to one embodiment, a series of cross-sectional diagrams depicting a process for forming grains with a uniform HB layer are shown.

[0050] Referring now to FIG. 7A, a cross-sectional view of a die 701 according to one embodiment is shown. In one embodiment, die 701 may include a semiconductor substrate, such as a silicon substrate, a III-V semiconductor substrate, or any other semiconductor substrate. Transistor devices, etc., may be fabricated on die 701. In one embodiment, a BEOL stack 702 may provide routing between a transistor (not shown) and a first pad 725. In one embodiment, a via 726 may extend upward from the first pad 725 through a dielectric layer 724.

[0051] Referring now to FIG. 7B, a cross-sectional view of die 701 is shown after a redistribution layer 722 is patterned on dielectric layer 724 according to one embodiment. In one embodiment, redistribution layer 722 may include traces 723 that laterally reroute an underlying first pad 725. Vias 727 extend vertically upward from traces 723 to the top of redistribution layer 722. In one embodiment, traces 723 and vias 727 may be fabricated using typical processes, such as dual damascene (DD), single damascene (SD), or semi-additive (SAP) processes.

[0052] Referring now to FIG. 7C, a cross-sectional view of die 701 is shown after a uniform HB layer has been formed on redistribution layer 722 according to an embodiment. In one embodiment, the HB layer includes dielectric layer 712 and a plurality of HB pads 715. The HB pads 715 may have a uniform pitch across die 701. For example, the pitch may be approximately 40 μm or less, or approximately 10 μm or less. Furthermore, the HB pads 715 may have a uniform size. The HB pads 715 may be manufactured using typical processes such as DD, SD, or SAP.

[0053] In one embodiment, the HB pad 715 and dielectric layer 712 can then be planarized using a CMP process. Due to the consistent metal density and uniformly sized HB pad 715, the CMP process may be less complex than the process required for existing HB layers, such as those shown in FIG. 1A. In one embodiment, the top surface of the HB pad 715 may be substantially coplanar with the top surface of the dielectric layer 712. In other embodiments, the top surface of the HB pad 715 may be recessed and lie between approximately 0 nm and approximately 5 nm below the top surface of the dielectric layer 712.

[0054] Referring now to Figures 8A-8H, according to one embodiment, a series of cross-sectional diagrams depicting a process for forming a polycrystalline module with an HB layer are shown. In the illustrated embodiment, an adaptively patterned redistribution layer is used to address misalignment issues in the placement of the bottom grains.

[0055] Referring now to FIG8A, a cross-sectional view of a die 801 disposed on a carrier substrate 850 according to an embodiment is shown. When die 801 is not the bottom layer of a multi-die module, the carrier substrate 850 may also be replaced by the dies and / or components layered below. Although die 801 A is specifically mentioned, it should be understood that other bottom dies may have similar structures and features. In one embodiment, die 801 may include a BEOL stack 802 for connection to a transistor device (not shown).

[0056] After placing the die 801 on the carrier substrate 850, the actual position of the die 801 can be determined. For example, the actual position can be determined by imaging or the like. The actual position of the die 801 can provide an offset value and / or a rotation offset value for each die 801. The offset value can be used in subsequent operations to provide adaptive patterning to accommodate the offset.

[0057] Referring now to FIG8B, a cross-sectional view of the die 801 is shown according to an embodiment after the dielectric layer 861 is disposed on and around the die 801. In one embodiment, the dielectric layer 861 may be planarized such that the top surface of the BEOL stack 802 is exposed.

[0058] Referring now to FIG8C, a cross-sectional view of grain 801 after the formation of through-hole 862 is shown according to one embodiment. In one embodiment, the measured offset of grain 801 can be used to properly position the through-hole 862. In other embodiments, the through-hole 862 may be omitted.

[0059] Referring now to FIG8D, a cross-sectional view of die 801 after a redistribution layer is formed on BEOL stack 802 according to an embodiment is shown. The redistribution layer may include pads 825 and vias 826. The offset values ​​determined above can be used to modify vias 826. For example, vias may extend laterally into traces to address inaccuracies in die 801 placement. In one embodiment, one or both of pads 825 and vias 826 may be fabricated using adaptive patterning processes such as direct write lithography in combination with DD, SD, or SAP. In other embodiments, one or both of pads 825 and vias 826 may be fabricated using DD, SD, or SAP without adaptive patterning.

[0060] Referring now to FIG8E, a cross-sectional view of a die 801 is shown according to an embodiment after a uniform HB layer is disposed above a via 826. The HB layer may include a dielectric layer 812 A and a plurality of HB pads 815 A. In one embodiment, the HB pads 815 A may have a uniform pitch. For example, the pitch may be about 40 μm or less, or about 10 μm or less. In one embodiment, the HB pads 815 A may also have a uniform size.

[0061] Referring now to FIG8F, a cross-sectional view of die 801 after top die 801 B is attached to bottom die 801 A according to an embodiment is shown. Each top die 801 B may include a BEOL stack 802 and an HB layer having a dielectric 812 B and a plurality of HB pads 815 B. In one embodiment, HB pads 815 B may be aligned with an underlying HB pad 815 A on the bottom die 801 A. In one embodiment, the dielectric 812 A is attached to the dielectric 812 B and the HB pads 815 A are attached to the HB pads 815 B using an HB process.

[0062] Referring now to FIG8G, a cross-sectional view of a multi-die module after the dielectric layer 863 is disposed above and between the top die 801 B is shown according to an embodiment. In one embodiment, the dielectric layer 863 is planarized together with the back surface of the top die 801 B.

[0063] Referring now to FIG8H, a cross-sectional view of a polycrystalline module after the formation of a through-hole 864 is shown according to an embodiment. In one embodiment, and in some embodiments, the through-hole 864 may be located on the HB pad 815 B. In other embodiments, the through-hole 864 may be omitted. For example, if the second grain 801 is top-layered, the additional through-hole 864 may not be required.

[0064] Referring now to FIG9, a cross-sectional view of an electronic system 990 according to an embodiment is shown. In one embodiment, the electronic system 990 includes a substrate 991, such as a printed circuit board (PCB). In one embodiment, the substrate 991 may be coupled to a package substrate 993 via interconnects 992. Interconnects 992 may include solder balls, sockets, etc. In one embodiment, a polydie module 900 is coupled to the package substrate 993 via interconnects 994.

[0065] In one embodiment, the multi-die module 900 may be substantially similar to any multi-die module described in more detail herein. In a particular embodiment, the multi-die module 900 includes a base die 901 A. A BEOL stack 902 may be disposed on the base die 901 A. In one embodiment, a consistent HB layer comprising a dielectric 912 A and a plurality of HB pads 915 A is disposed on the base die 901 A. The HB pads 915 A may have a consistent pitch and size.

[0066] In one embodiment, the multi-die module 900 may further include a plurality of top dies 901 B. The top dies 901 B may be coupled to the bottom dies 901 A via a second HB layer. The second HB layer may include a dielectric layer 912 B and a plurality of HB pads 915 B. The HB pads 915 B may have a consistent pitch and size substantially equal to that of the HB pads 915 A. In one embodiment, dielectric 912 A is bonded to dielectric 912 B, and HB pad 915 A is bonded to HB pad 915 B (e.g., by cross-diffusion). In some embodiments, there may be no discernible seam between the HB pads 915 A and HB pad 915 B.

[0067] Figure 10 illustrates a computing device 1000 according to one embodiment of the present invention. The computing device 1000 houses a substrate 1002. The substrate 1002 may include multiple components, including, but not limited to, a processor 1004 and at least one communication chip 1006. The processor 1004 is physically and electrically coupled to the substrate 1002. In some embodiments, at least one communication chip 1006 is also physically and electrically coupled to the substrate 1002. In a further embodiment, the communication chip 1006 is part of the processor 1004.

[0068] These other components include, but are not limited to, volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, graphics processors, digital signal processors, cryptographic processors, chipsets, antennas, displays, touch screen displays, touch screen controllers, batteries, audio codecs, video codecs, power amplifiers, global positioning system (GPS) devices, compasses, accelerometers, gyroscopes, speakers, cameras, and mass storage devices (e.g., hard disk drives, optical discs (CDs), digital optical discs (DVDs), etc.).

[0069] Communication chip 1006 enables wireless communication for data transmission to or from computing device 1000. The term "wireless" and its derivatives can be used to describe circuits, devices, systems, methods, technologies, communication channels, etc., which can transmit data using modulated electromagnetic radiation that travels through a non-solid medium. This term does not imply that the associated device does not contain any wires, although this may be the case in some embodiments. Communication chip 1006 can implement any number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, and their derivatives, as well as any other wireless protocols designated for use as 3G, 4G, 5G, and later technologies. Computing device 1000 may include a plurality of communication chips 1006. For example, the first communication chip 1006 can be dedicated to short-range wireless communication, such as Wi-Fi and Bluetooth, while the second communication chip 1006 can be dedicated to long-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO and others.

[0070] The processor 1004 of the computing device 1000 includes an integrated circuit die packaged within the processor 1004. In some embodiments of the invention, according to the embodiments described herein, the processor's integrated circuit die may be a portion of an electronic package comprising a multi-die module, wherein different layers of the multi-die module are coupled together with a consistent HB layer. The term "processor" may refer to any device or portion of a device that processes electronic data from a register and / or memory to transform that electronic data into other electronic data that can be stored in the register and / or memory.

[0071] The communication chip 1006 also includes an integrated circuit die packaged within the communication chip 1006. According to another embodiment of the invention, the integrated circuit die of the communication chip may be part of an electronic package comprising a multi-die module, wherein different layers of the multi-die module are coupled together by a consistent HB layer, according to the embodiments described herein.

[0072] The above description of embodiments of the present invention, including the description in the abstract, is not intended to be exhaustive or limit the invention to the specific embodiments disclosed. The specific embodiments and examples of the present invention described herein are for illustrative purposes, and therefore those skilled in the art will recognize that various equivalent modifications may fall within the scope of the present invention.

[0073] These modifications can be made to the present invention based on the above detailed description. The terminology used in the following claims should not be construed as limiting the specific embodiments of the invention disclosed in the specification and claims. Rather, the scope of the invention is entirely determined by the following claims and is to be understood in accordance with established principles of the interpretation of the claims.

[0074] Example 1: A semiconductor die, comprising: a die substrate; a pad layer on the die substrate, wherein the pad layer includes a first pad having a first size and a first pitch and a second pad having a second size and a second pitch; and a hybrid bonding layer on the pad layer, wherein the hybrid bonding layer includes: a dielectric layer; and an array of hybrid bonding pads in the dielectric layer, wherein the hybrid bonding pads include a third size and a third pitch.

[0075] Example 2: A semiconductor die as in Example 1, wherein the entire array of the hybrid bonding pads has the third dimension and the third pitch.

[0076] Example 3: A semiconductor die such as in Example 1 or Example 2, wherein each individual first pad in the first pad is coupled to a corresponding one of the hybrid bonding pads.

[0077] Example 4: The semiconductor die as in Example 3, wherein the first pad is an input / output (I / O) pad.

[0078] Example 5: Semiconductor die as in Examples 1 to 4, wherein each individual second pad in the second pad is coupled to a plurality of the mixed bonding pads.

[0079] Example 6: The semiconductor die as in Example 5, wherein the second pad is a power pad or a ground pad.

[0080] Example 7: Semiconductor grains as in Examples 1 to 6, wherein the third pitch is about 40 μm or less.

[0081] Example 8: A semiconductor die as in Example 7, wherein the third pitch is about 10 μm or less.

[0082] Example 9: Semiconductor dies such as those in Examples 1 to 8, wherein the first surface of the hybrid bonding pad is substantially coplanar with the first surface of the dielectric layer.

[0083] Example 10: An electronic package includes: a first die, wherein the first die includes: a first die substrate; and a first hybrid bonding layer on the first die substrate, wherein the first hybrid bonding layer includes: a first dielectric layer; and an array of first hybrid bonding pads in the first dielectric layer, wherein the first hybrid bonding pads have a first pitch; and a second die coupled to the first die, wherein the second die includes: a second die substrate; and a second hybrid bonding layer on the second die substrate, wherein the second hybrid bonding layer includes: a second dielectric layer; and an array of second hybrid bonding pads in the second dielectric layer, wherein the second hybrid bonding pads have the first pitch, and wherein the second hybrid bonding pads are directly connected to the first hybrid bonding pads.

[0084] Example 11: An electronic package as in Example 10, wherein there is no seam between the first hybrid bonding pad and the second hybrid bonding pad.

[0085] Example 12: An electronic package as in Example 10 or Example 11, wherein the second dielectric layer is bonded to the first dielectric layer.

[0086] Example 13: An electronic package as in Examples 10 to 12, wherein the array of the first hybrid bonding pads is larger than the array of the second hybrid bonding pads.

[0087] Example 14: The electronic package of Example 13 further includes: a third die coupled to the first die, wherein the third die includes: a third die substrate; and a third hybrid bonding layer on the third die substrate, wherein the third hybrid bonding layer includes: a third dielectric layer; and an array of third hybrid bonding pads in the third dielectric layer, wherein the third hybrid bonding pads have the first pitch, and wherein the third hybrid bonding pads are directly connected to the first hybrid bonding pads.

[0088] Example 15: An electronic package as in Examples 10 to 14, wherein the second die further includes: a pad layer between the second die substrate and the second hybrid bonding layer, wherein the pad layer includes a first pad having a second pitch different from the first pitch; and a redistribution layer between the pad layer and the second hybrid bonding layer, wherein the redistribution layer couples each of the first pads to a corresponding of the second hybrid bonding pads.

[0089] Example 16: The electronic package of Example 15 further includes: a second pad in the pad layer, wherein the second pad has a third pitch different from the first pitch and the second pitch, and wherein the redistribution layer couples each of the second pads to a plurality of the hybrid bonding pads.

[0090] Example 17: An electronic package as in Example 16, wherein the first pad is an input / output (I / O) pad, and wherein the second pad is a power pad and / or a ground pad.

[0091] Example 18: Electronic packages as in Examples 15 to 17, wherein the redistribution layer is manufactured using an adaptive patterning process to address misalignment between the first die and the second die.

[0092] Example 19: Electronic packages as in Examples 10 to 18, wherein one or more of the first hybrid bonding pads are dummy pads that are not coupled to the active circuit.

[0093] Example 20: Electronic packages as in Examples 10 to 19, wherein the first pitch is approximately 40 μm or less.

[0094] Example 21: An electronic package as in Example 20, wherein the first pitch is approximately 10 μm or less.

[0095] Example 22: An electronic system comprising: a first layer, wherein the first layer includes: a first die; and a first hybrid bonding layer having a first pad having a first pitch; a second layer above the first layer, wherein the second layer includes: a second die; and a second hybrid bonding layer having a second pad having the first pitch, and wherein the first layer is bonded to the second layer via an interface between the first hybrid bonding layer and the second hybrid bonding layer.

[0096] Example 23: An electronic system as in Example 22, wherein the second layer further includes: a third hybrid bonding layer having a third pad having a second pitch, and wherein the electronic system further includes: a third layer above the second layer, wherein the third layer includes: a third grain; and a fourth hybrid bonding layer having a fourth pad having the second pitch, wherein the second layer is bonded to the third layer via an interface between the third hybrid bonding layer and the fourth hybrid bonding layer.

[0097] Example 24: An electronic system as in Example 23, wherein the second pitch is smaller than the first pitch.

[0098] Example 25: The electronic system of Examples 22 to 24 further includes: a substrate coupled to the first layer.

[0099] 110: HB layer 111: Gap 112: Dielectric layer 115: Pad 120: Array 120 A-120 E: Array P1: Pitch P2: Pitch 203: Floor 205: Floor 210: Floor 212: Dielectric layer 215: HB pad 222: Dielectric layer 223: Redistributed routing 224: Dielectric layer 225: Pad 225 A: Pad 225 B: Pad 225 D: Pad 300: Multi-crystal module 301 A: Basic Grain 301 B: Small chip 302: Back-end process (BEOL) stacking 302 A: BEOL stack 302 B: BEOL stacking 312: Dielectric layer 312 A: Dielectric layer 312 B: Dielectric layer 315: HB pad 315 A:HB pad 315 B:HB pad 322: Routing Layer 322 A: Redistribution Layer 322 B: Redistribution Layer 323 A: Wiring 323 B: Wiring 324 A: Dielectric layer 324 B: Dielectric layer 325 A: Pad 325 B: Pad 326 A: Through hole 326 B: Through hole 327 A: Through hole 327 B: Through hole 415: HB pad 423: Wiring 425: Pad 500: Polycrystalline module 501: Grain 515: HB pad 515 1:HB pad 515 2: HB pad 515 A:HB pad 515 B:HB pad 530: Layering 530 1: Layering 530 2: Layering 530 3: Layering 531: Interface 532: Interface 533: Area 534: Through-hole 535: Through-hole 536: Through-hole in substrate 601: Grain 601 A: Grain 601 B: Grain 601 C: Grain 602: BEOL stacking 612 A: Dielectric 612 C: Dielectric 615 A:HB pad 615 C:HB pad 624: Redistribution Layer 625: Pad 626: Wiring 701: Grain 702: BEOL stacking 712: Dielectric layer 715: HB pad 722: Redistribution Layer 723: Wiring 724: Dielectric layer 725: Pad 726: Through hole 727: Through hole 801: Grain 801 A: Grain 801 B: Grain 802: BEOL stacking 812 A: Dielectric layer 812 B: Dielectric layer 815 A:HB pad 815 B:HB pad 825: Pad 826: Through hole 850: Carrier substrate 861: Dielectric layer 862: Through-hole 863: Dielectric layer 864: Through-hole 900: Multi-crystal module 901 A: Grain 901 B: Grain 902: BEOL stacking 912 A: Dielectric 912 B: Dielectric layer 915 A:HB pad 915 B:HB pad 990: Electronic Systems 991: Board Material 992: Interconnection 993: Packaging substrate 994: Interconnection 1000: Computing device 1002: Board Material 1004: Processor 1006: Communication Chip

Claims

1. A semiconductor die, comprising: Grain substrate; A pad layer on the die substrate, wherein the pad layer includes a first pad having a first size and a first pitch and a second pad having a second size and a second pitch; and a hybrid bonding layer on the pad layer, wherein the hybrid bonding layer includes: a dielectric layer; and an array of hybrid bonding pads in the dielectric layer, wherein the hybrid bonding pads include a third size and a third pitch, wherein each individual first pad in the first pad is coupled to a corresponding one of the hybrid bonding pads, and wherein each individual second pad in the second pad is coupled to a plurality of the hybrid bonding pads.

2. The semiconductor die of claim 1, wherein the array of hybrid bonding pads has the third dimension and the third pitch.

3. The semiconductor die of claim 1, wherein the first pad is an input / output (I / O) pad.

4. The semiconductor die of claim 1, wherein the second pad is a power pad or a ground pad.

5. The semiconductor die as claimed in claim 1 or 2, wherein the third pitch is about 40 μm or less.

6. The semiconductor die of claim 5, wherein the third pitch is about 10 μm or less.

7. The semiconductor die of claim 1 or 2, wherein the first surface of the hybrid bonding pad is substantially coplanar with the first surface of the dielectric layer.

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