System and methods for dram contact formation

Abstract

This disclosure relates to dynamic random access memory (DRAM) devices and semiconductor manufacturing for DRAM devices. Certain embodiments disclosed herein provide an integrated processing system and method for forming CMOS contacts, DRAM array bit line contacts (BLC), and storage node structures. This integrated processing system and method can deposit contact and storage node layers with reduced contamination and improved quality, thereby reducing leakage current and resistance in the final contact and storage node structures.

Description

[Technical Field]

[0001] The embodiments of this disclosure are generally related to methods and apparatus for forming semiconductor element contacts and storage nodes, and more specifically, to methods and apparatus for forming bit line contacts (BLC) and storage nodes for dynamic random access memory (DRAM) arrays. [Previous Technology]

[0002] Technological advancements in semiconductor processing have led to integrated circuits reaching the physical limits of Mohr's Law. These advancements have resulted in new paradigms for components and structures in integrated circuits. For example, various three-dimensional (3D) components, such as 3D dynamic random access memory (DRAM), have been developed for integrated circuits. However, such 3D components present a series of new challenges in processing and manufacturing.

[0003] A key challenge in the design, manufacturing, and operation of 3D DRAM is contact resistance (Rc). DRAM cells operate as arrays of columns (bit lines) and rows (word lines). Bit lines propagate charge to and from sense amplifiers to perform programming (writing) or fetching (reading) data from a given cell. The speed at which data is written to and read from DRAM cells depends on the resistance of the bit lines (R in Rc); the lower the resistance, the faster the data transfer. The resistance of a conductor depends on the scattering points encountered by electrons as they move along the line. Impurities, grain boundaries, and surface roughness in the film are obstacles that slow down electron speed. The formation and relative effects of these obstacles depend on the film deposition method and / or layer thickness.

[0004] Another key challenge for 3D DRAM devices includes contact stability. Typically, bit line contacts consist of a very thin silicon layer that is subjected to high-temperature processing after deposition. Downstream thermal processing can utilize temperatures of approximately 1050°C or higher, which can lead to degradation of the silicon layer at the bit line contacts, such as agglomeration and nucleation, thus affecting the overall performance of the bit line.

[0005] Therefore, there is a need in the art for improved contact and storage node structures that reduce contact resistance and improve thermal stability. [Summary of the Invention]

[0006] The embodiments of this disclosure pertain to a system and method for forming contacts.

[0007] In one embodiment, a method is provided for forming bit line contacts within a dynamic random access memory (DRAM) element. The method includes depositing a doped semiconductive layer on an exposed surface of a doped region of a substrate in a first chamber, wherein the doped region is exposed through trenches formed in a dielectric material on the doped region. Subsequently, a metal silicate layer is deposited on the doped semiconductive layer, and a nitriding process is performed to form a nitride layer on the metal silicate layer. The formation of the semiconductive layer, the metal silicate layer, and the nitride layer is performed without disrupting the vacuum.

[0008] In another embodiment, a method for forming bit line contacts within a dynamic random access memory (DRAM) element is provided. The method includes pre-cleaning a substrate in a first chamber and depositing a doped semiconductive layer on an exposed surface of a doped region of the substrate in a second chamber, wherein the doped region is exposed through trenches formed in a dielectric material formed on the doped region. In a third chamber, a metal silicate layer is deposited on the doped semiconductive layer, and a nitriding process is performed to form a nitride layer on the metal silicate layer. The method further includes depositing a conductive layer on the nitride layer in a fourth chamber, wherein the pre-cleaning and formation of the doped semiconductive layer, the metal silicate layer, the nitride layer, and the conductive layer are performed without breaking the vacuum.

[0009] In another embodiment, a processing system is provided. The processing system includes a system controller and a first processing chamber, wherein the system controller is configured to perform a pre-cleaning process on a doped region formed at the bottom of a trench in a dielectric layer formed on a substrate disposed in the first processing chamber, and wherein the pre-cleaning process is performed on the doped region formed at the bottom of the trench in the dielectric layer. The processing system further includes a second processing chamber, wherein the system controller is configured to form a doped epitaxial layer and a metal silicate layer on an exposed surface of the doped region of the substrate disposed in the second processing chamber, and to perform a nitriding process on the metal silicate layer to form a nitride layer. The processing system also includes a third processing chamber, wherein the system controller is configured to form a conductive layer on the nitride layer, and wherein the processing system is configured to transfer a substrate between the first processing chamber, the second processing chamber, and the third processing chamber without breaking the vacuum.

Implementation Method

[0017] In the following description, numerous specific details are set forth to provide a more complete understanding of embodiments of the present disclosure. However, it will be apparent to those skilled in the art that one or more embodiments of the present disclosure may be practiced without one or more of these specific details. In other instances, well-known features have not been described to avoid obscuring one or more embodiments of the present disclosure.

[0018] The embodiments disclosed herein largely relate to dynamic random access memory (DRAM) devices and semiconductor manufacturing methods for such devices. For example, some embodiments disclosed herein provide processing systems and methods for forming DRAM array bit line contacts (BLCs) and storage node structures. Although generally described with reference to DRAM devices, the structures and methods disclosed herein can be further used to form other types of devices, such as complementary metal-oxide-semiconductor (CMOS) devices.

[0019] In various embodiments, these methods include performing various operations in a processing system without breaking the vacuum. Such operations may include performing a pre-cleaning process on exposed surfaces of source / drain regions of a transistor on a substrate, wherein the source / drain regions are exposed through trenches formed in a dielectric material formed on the source / drain regions. Such operations may further include forming an epitaxial layer on the exposed source / drain regions via an epitaxial deposition process, wherein the epitaxial layer is doped or undoped. In some embodiments, a metal silicate layer is formed on the epitaxial layer via a plasma-enhanced deposition process, followed by in-situ nitriding to form a barrier layer or capping layer. In further embodiments, a metal layer is formed on the capping layer via, for example, a deposition process, and the substrate may then be further processed.

[0020] The integrated process can form contact structures that reduce leakage current and resistance, and improve thermal stability. The embodiments disclosed herein can be used, but are not limited to, to generate DRAM bit line contacts and / or DRAM storage nodes with reduced contact resistance, thereby facilitating improved DRAM systems. The embodiments disclosed herein can also be used, but are not limited to, to generate CMOS source / drain contacts.

[0021] As used herein, the term "about" refers to a change of + / -10% in the value of the index. It should be understood that such a change may be included in any value provided herein.

[0022] Figure 1 is a partial cross-sectional view of a component contact 100 along the length of a metal layer 116 formed thereon, according to an embodiment described herein. In some embodiments, the component contact 100 is a contact formed in a DRAM bit line structure. In some embodiments, the component contact 100 is formed in a contact region of a DRAM bit line array, wherein the contact region may include the contact and any structures adjacent thereto, such as the source / drain regions of a substrate. For example, the component contact 100 may be a bit line contact with a capacitor-like structure on a three-dimensional (3D) bit. In some embodiments, the component contact 100 is a contact for a source-drain region of a CMOS logic element (e.g., an NMOS or PMOS transistor).

[0023] The component contact 100 includes a spacer layer 104 formed on the substrate 102. Generally, the substrate 102 includes any suitable type of semiconductor substrate and material. For example, the substrate 102 may include silicon (Si), germanium (Ge), silicon-germanium (SiGe), or III / V compound semiconductors such as gallium arsenide (GaAs), indium gallium arsenide (InGaAs), or similar materials. In some embodiments, the substrate 102 is a silicon-on-insulator (SOI) substrate.

[0024] The substrate 102 may be doped with p-type or n-type dopants to form doped regions 106. In one embodiment, the substrate 102 is doped with an n-type dopant, such as phosphorus (P) or arsenic (As). In another embodiment, the substrate 102 is doped with a p-type dopant, such as boron (B). The doped regions 106 may form source / drain regions 107 of a transistor. In one example, the source / drain regions 107 are either source regions or drain regions. In another example, the source / drain regions 107 include merged source / drain regions. In some embodiments, the source / drain regions 107 are epitaxially grown on the substrate 102.

[0025] Spacer layer 104 is formed on substrate 102 and may be made of any suitable insulating material. For example, spacer layer 104 may include oxides such as silicon dioxide (SiO2), or nitrides such as silicon nitride (Si3N4) and silicon carbonitride (SiCN), combinations thereof, or other dielectric materials. In some instances, spacer layer 104 includes tetraethyl orthosilicate (TES), phosphosilicate glass (PSG), borosilicate glass (BSG), or spin-on dielectrics (SOD). In some embodiments, spacer layer 104 is a single layer or multiple layers. The spacer layer 104 can be formed by deposition processes such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD) (e.g., high-density plasma chemical vapor deposition (HDPCVD) and flowable chemical vapor deposition (FCVD), or other suitable methods.

[0026] One or more trenches 108 are formed through the spacer layer 104, such that the trenches 108 penetrate the spacer layer 104 and partially expose the substrate 102 and / or the source / drain region 107. The trenches 108 can be formed by any suitable patterning and material removal process, such as lithography, followed by dry etching, wet etching, or a combination of etching processes. Furthermore, the trenches 108 can have any suitable size and shape. In some instances, the trenches 108 have a substantially circular or substantially rectangular shape (not shown) when viewed from above.

[0027] The epitaxial layer 110 is formed within the trench 108 and on the substrate 102. The epitaxial layer 110 is generally formed through a bottom-up growth process, such as selective epitaxial growth (SEG) or deposition process. Although the epitaxial layer 110 of the component contact 100 is formed on a single substrate 102, it can be formed at different times and in separate epitaxial growth processes.

[0028] The epitaxial layer 110 may comprise any suitable silicon-containing semiconducting layer, such as a polycrystalline silicon epitaxial layer. In some instances, the epitaxial layer 110 comprises Si, SiC, SiGe, or similar materials. The epitaxial layer 110 may be further doped with p-type or n-type dopants to form a doped epitaxial layer. In some instances, the epitaxial layer 110 is doped with n-type dopants, such as phosphorus, arsenic, antimony, or similar materials. In some instances, the epitaxial layer 110 is doped with carbon. Therefore, in some embodiments, the epitaxial layer 110 is a high-strain in-situ phosphorus-doped silicon (HS-Si:P) or phosphorus and carbon-doped silicon (SiP:C) epitaxial layer. In some embodiments, the epitaxial layer 110 has a phosphorus concentration of about 5 x 10²¹ atoms / cm³ or less, such as about 1 x 10²¹ or less. In some embodiments, the epitaxial layer 110 has a carbon concentration of about 5 × 10²¹ or less, such as about 2.5 × 10²¹ or less, such as about 5 × 10²⁰ or less. In some embodiments, the epitaxial layer 110 includes a gradient dopant concentration of phosphorus and / or carbon along its height.

[0029] As shown in Figures 1 and 2, a metal silicate layer 112 is formed on the epitaxial layer 110. The metal silicate layer 112 may be formed by selectively depositing a metal layer on the surface of the epitaxial layer 110 and / or on the exposed surface of the source / drain region 107, and subsequently annealing in some embodiments. In some embodiments, the metal silicate layer 112 is deposited directly on the epitaxial layer 110 and / or the source / drain region 107, but not on the spacer layer 104 (e.g., by selective epitaxial deposition). The metal silicate layer 112 may be a refractory metal layer formed using CVD, PECVD, HDPCVD, PVD, electroplating, sputtering, evaporation, epitaxial deposition, selective epitaxial deposition, or any suitable process. In some embodiments, the metal silicate layer 112 includes titanium (Ti) silicate, cobalt (Co) silicate, nickel (Ni) silicate, ruthenium (Ru) silicate, tantalum (Ta) silicate, tungsten (W) silicate, molybdenum (Mo) silicate, alloys thereof, other suitable metal silicates, or any combination thereof. Other examples of metals used for the metal silicate layer 112 include, but are not limited to, TiSi, RuSi, nickel-platinum (NiPt) alloys, nickel-palladium (NiPd), nickel-rhenium (NiRe), titanium-tantalum (TiTa), or titanium-niobium (TiNb).

[0030] In some embodiments, the metal silicate layer 112 is formed in the same processing chamber as the epitaxial layer 110. In some embodiments, the metal silicate layer 112 is formed in a different processing chamber than the epitaxial layer 110, but within the same processing system. In some instances, the metal silicate layer 112 is formed in the epitaxial deposition chamber of the processing system. Because the epitaxial layer 110 and the metal silicate layer 112 are formed in the same processing system, the vacuum is not disrupted between processes.

[0031] A capping layer 114 is formed on the component contact 100, for example, on the metal silicate layer 112 and the spacer layer 104. In some embodiments, the capping layer 114 is formed using a conformal deposition process, which allows the capping layer 114 to form along the sidewalls of the spacer layer 104, thereby forming an inner liner trench therein. The capping layer 114 acts as a barrier layer to prevent metal diffusion from subsequently formed metal layers (e.g., metal layer 116) and reaction with the underlying metal silicate layer 112 and / or the source / drain region 107. The capping layer 114 may also act as an adhesion layer to improve the adhesion between the subsequent metal layers and the metal silicate layer 112. In some embodiments, the capping layer 114 is a nitride layer. For example, the capping layer 114 may include, but is not limited to, TiN, Si3N4, or metal silicon nitrides. The capping layer 114 may include a metallic material containing a transition metal, such as iridium (Ir) or molybdenum (Mo). In some embodiments, the capping layer 114 is a nitride layer, such as a TiN layer, formed through physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), or nitriding processes. The nitriding process may include exposing the metal silicate layer 112 to a nitrogen-containing plasma or a nitrogen-containing surrounding environment, such that nitrogen (N) atoms chemically react with atoms residing on the exposed surface of the metal silicate layer 112 to form a surface nitride layer (e.g., the capping layer 114).

[0032] A metal layer 116 is formed on the surface of the capping layer 114 and can serve as a bit line and / or storage node conductor metal. Examples of suitable materials for the metal layer 116 include, but are not limited to, tungsten, cobalt, copper, aluminum, ruthenium, titanium, silver, platinum (Pt), palladium (Pa), alloys, derivatives of the above, or any combination thereof. The metal layer 116 can be deposited on the capping layer 114 using one or more deposition processes, such as CVD, PECVD, atomic layer deposition (ALD), plasma-enhanced ALD (PEALD), physical vapor deposition (PVD), electroless plating, electroplating (ECP), or other suitable deposition methods.

[0033] Figure 2A is a partial cross-sectional view of a DRAM system 200 according to an embodiment described herein, including at least a portion of the element contacts 100 of Figure 1, as seen in a plane perpendicular to the plane shown in Figure 1 (e.g., through metal layer 116a, which is the bit line in Figure 2A). In some embodiments, the DRAM system 200 is a 3D DRAM structure including a plurality of element contacts 100 and a plurality of storage nodes 201 arranged alternately. For example, the DRAM system 200 may be a 3D on-bit capacitor type structure.

[0034] As shown in Figure 2A, each contact element 100 or "contact plug" is formed on the source / drain region 107 and has a metal layer 116 formed thereon, which serves as a bit line. The storage node 201 may have a structure substantially similar to that of the element contact 100, except for its size, and therefore may be formed by a substantially similar method. For reference purposes, the bit line contact structure (such as the element contact 100 in Figure 2A) may have a cross-sectional dimension of approximately 10 nm × 4 nm or approximately 8 nm × 4 nm.

[0035] Figure 2B is a partial cross-sectional view of the DRAM system 200 of Figure 2A, as seen in the same plane shown in Figure 1 (e.g., in a plane perpendicular to the plane shown in Figure 2A, and along metal layer 116, which is a bit line). As shown in Figure 2B, the DRAM system 200 includes a plurality of contact elements 100 on which bit lines are formed, and buried word lines 224 disposed between the contact elements 100. Each buried word line 224 is disposed in a channel 208 formed in a substrate 102 between two source / drain regions 107 formed below the contact elements 100. The buried word line 224 partially fills the channel 208, which is lined with an insulating layer 226 formed conformally on its inner surface. The sealing layer 222 may be further formed on any remaining exposed surfaces of the buried word line 224 and the insulating layer 226, such that the sealing layer 206 has an upper surface flush with the upper surface of the substrate 102.

[0036] Similar to metal layer 116, the embedded word line 224 may be formed of any suitable low-resistance metallic material. In some embodiments, the embedded word line 224 is formed of W, Co, Cu, Al, Ru, Ti, Ag, platinum (Pt), palladium (Pa), alloys, derivatives, or any combination thereof. The sealing layer 222 and / or insulating layer 226 may be formed of any suitable insulating material. For example, the sealing layer 222 and / or insulating layer 226 may include oxides such as silicon dioxide (SiO2), or nitrides such as silicon nitride (Si3N4) and silicon carbonitride (SiCN), combinations thereof, or other dielectric materials. In some instances, the sealing layer 222 and / or the insulating layer 226 comprises tetraethyl orthosilicate (TEOS), phosphosilicate glass (PSG), borosilicate glass (BSG), or spin-on dielectrics (SOD). In some embodiments, the insulating layer 226 is a single layer or multiple layers.

[0037] Figure 2C is a partial cross-sectional view of a portion of a CMOS element 250 according to an embodiment described herein, including at least a portion of the element contact 100 of Figure 1. The CMOS element 250 will include suitable MOSFET device elements, such as PMOS transistors and NMOS transistors. The portion of the CMOS element 250 shown in Figure 2C is formed on a substrate 102 and includes a gate 232, an insulating layer 230, and at least two source / drain regions 107 formed in the substrate 102. In Figure 2C, the element contact 100 serves as a contact for the source / drain region 107 of the MOSFET element. Therefore, each element contact 100 (two are shown in Figure 2C) is formed on at least a portion of the source / drain region 107 and is located on either side of the transistor gate 232.

[0038] In some embodiments, the element contact 100 of at least one MOSFET element in the CMOS element 250 is formed simultaneously with the element contacts and / or storage nodes of other devices or systems, including the element contacts 100 and / or storage node 201 of the DRAM system 200. For example, the source / drain region 107, element contact 100, and contact region of the CMOS element 250 may be formed simultaneously around the periphery of the DRAM system, for example, on the same substrate 102. In some instances, the CMOS element 250 and the element contacts 100 of the DRAM system 200 are formed in or through the spacer layer 104 on the same substrate 102. In this embodiment, the element contact 100 of the CMOS element 250 may include a carbon-doped epitaxial layer 110, and in some instances, only carbon is doped to improve the thermal stability of its metal silicate layer 112. In some other instances, the element contacts 100 of the CMOS element 250 may be formed in or through a separate spacer layer on the same substrate 102 (e.g., a spacer layer on substrate 102 other than spacer layer 104).

[0039] Figure 3 is a flowchart of a method 300 for forming a contact structure (such as element contact 100) and / or a storage node (such as a DRAM storage node) according to embodiments described herein. Figures 4A-4E illustrate various views of element contact 100 during different operations of method 300 according to certain embodiments. Therefore, Figures 3 and 4A-4E are described together herein for clarity.

[0040] Although the operation of method 300 has been described in conjunction with Figures 3 and 4A-4E, those skilled in the art will understand that any system configured to perform the method operations in any order is within the scope of the embodiments described herein. Furthermore, although Figures 4A-4E illustrate method 300 applied to forming element contacts 100, those skilled in the art will understand that method 300 can also be used to form DRAM storage nodes 201. It should also be noted that method 300 can be used to form any other semiconductor structures not described herein. Those skilled in the art should recognize that the complete process for forming semiconductor elements and related structures is not shown in the figures or described herein. Contacts may be part of DRAM bit line structures, storage nodes, transistors (e.g., nMOS transistors), CMOS elements, or other semiconductor elements.

[0041] Method 300 begins with operation 302 and Figure 4A, wherein a substrate 102 on which a patterned spacer layer 104 is formed is exposed, as appropriate, to one or more pre-cleaning processes in one or more processing chambers of a processing system. As described above, substrate 102 may comprise any suitable type of semiconductor substrate and material, such as Si, Ge, SiGe, III / V compound semiconductors, or similar materials. In some embodiments, substrate 102 includes doped regions 106 which may form source / drain regions 107 of a transistor. Spacer layer 104 is formed on substrate 102 and comprises any suitable type of insulating material. Spacer layer 104 may be formed in the same or different processing chambers and / or processing systems as one or more pre-cleaning processes of operation 302 via a deposition process (not shown), such as a CVD process.

[0042] As shown in Figure 4A, trenches 108 are formed in spacer layer 104 to expose portions of the surface of doped regions 106 of substrate 102. The trenches 108 may be formed in the same or different processing chambers and / or processing systems as one or more pre-cleaning processes of operation 302, via any suitable removal process (not shown), such as an etching process using a mask pattern (not shown). In some embodiments, the removal process is a chemical dry etching process, a wet etching process, or a combination thereof. In some embodiments, the trenches 108 are formed in spacer layer 104 using a dry etching process in a processing chamber.

[0043] One or more pre-cleaning processes in operation 302 may include wet cleaning processes or dry cleaning processes. In some embodiments, one or more pre-cleaning processes are performed in one or more vacuum processing chambers using a remote plasma source. For example, one or more pre-cleaning processes may include exposing substrate 102 to hydrogen (H2) and / or chlorine (Cl2)-based plasmas, and / or nitrogen-based plasmas, such as nitrogen trifluoride (NF3) and / or ammonia (NH3) plasmas. In other instances, one or more pre-cleaning processes may include exposing substrate 102 to an inert gas containing plasma in a first processing chamber of the processing system. One or more pre-cleaning processes may remove native oxides and / or carbon from substrate 102, and any damaged layers on the substrate.

[0044] Examples of suitable first processing chambers for performing the pre-cleaning process include the AKTIV Pre-Clean™ chamber, a SiCoNi™ clean chamber available from Applied Materials, Inc., Santa Clara, California. In some other instances, pre-cleaning may be performed in an etching chamber, such as an etching chamber using an inductively coupled plasma (ICP) source. One example of an etching chamber is a modified decoupled plasma source (DPS) etching chamber, available from Applied Materials, Inc., Santa Clara, California. However, it is further envisioned that other appropriately configured chambers from other manufacturers may also be implemented to perform the pre-cleaning process described herein.

[0045] In operation 304 and Figure 4B, an epitaxial layer 110 is formed in trench 108 to fill a portion of the trench. The epitaxial layer 110 comprises any suitable silicon-containing material and can be formed by a bottom-up growth process, such as selective epitaxial deposition. For example, the epitaxial layer 110 can be formed by CVD, PECVD, low-pressure CVD (LPCVD), very low-pressure CVD (VLPCVD), ultra-high vacuum CVD (UHVCVD), rapid thermal CVD (RTCVD), atomic pressure CVD (APCVD), molecular beam epitaxy (MBE), or similar processes.

[0046] The epitaxial layer 110 can be further doped by an in-situ doping process. For example, the in-situ doping process can be performed by supplying a doping gas while growing the silicon-containing epitaxial layer 110 using a silicon source gas. In some embodiments, the epitaxial layer 110 is an in-situ doped high-strain silicon layer of phosphorus and / or carbon. In such embodiments, the epitaxial deposition and dopant immersion processes can be performed at a temperature range of about 450°C to about 550°C (e.g., about 500°C) and a pressure range of about 10 Torr to about 80 Torr (e.g., between about 30 Torr and about 60 Torr, such as about 50 Torr).

[0047] In some embodiments, the doping process includes flowing a phosphorus-based gas (such as phosphine (PH3)) into the processing chamber at a flow rate between about 500 sccm and about 1500 sccm, such as between about 750 sccm and about 1250 sccm, such as between about 900 sccm and about 1100 sccm, such as about 1000 sccm. In some embodiments, the doping process includes flowing a carbon-based gas into the processing chamber at a flow rate between about 30 sccm and about 200 sccm, such as between about 50 sccm and about 150 sccm, such as between about 75 sccm and about 125 sccm, such as about 100 sccm. In some embodiments, a silicon source gas, such as silane (SiH4), disilane (Si2H6), trisilane (Si3H8), tetrasilane (Si4H10), dichlorosilane (SiH2Cl2), or a combination thereof, flows into the processing chamber at a flow rate between about 50 sccm and about 200 sccm, such as between about 75 sccm and about 175 sccm, such as between about 100 sccm and about 150 sccm, such as about 125 sccm. In some embodiments, hydrogen chloride (HCl) gas flows into the processing chamber at a flow rate between about 50 sccm and about 500 sccm, such as between about 100 sccm and about 400 sccm, such as between about 200 sccm and about 300 sccm, such as about 250 sccm. In one instance, an epitaxial silicon layer deposition process was performed on a substrate at a deposition pressure of 40 Torr, while tetrasilane (Si4H10) flowed at 11 sccm and a hydrogen-containing carrier gas flowed at 5 SLM for approximately 712 seconds at a temperature of 450°C.

[0048] In a further embodiment, the epitaxial layer 110 may include a SiGe layer doped with an N-type dopant or a SiC layer doped with an N-type dopant.

[0049] Epitaxial deposition and doping processes can be performed in the second processing chamber of the processing system described herein. One example of a suitable chamber is a depressurized (RP) Epi chamber available from Applied Materials, Inc., Santa Clara, California. However, it is further envisioned that other appropriately configured chambers from other manufacturers can also be implemented to perform the deposition processes described herein.

[0050] In operations 306 and Figure 4C, a metal silicate layer 112 is formed above the epitaxial layer 110 and / or above the exposed surface of the source / drain region 107. In some embodiments, the metal silicate layer 112 is formed conformally on the epitaxial layer 110 and / or the exposed surface of the source / drain region 107, such that it partially fills the trench 108. The metal silicate layer 112 may be a siliconizable and refractory metal layer formed using ALD, CVD, PECVD, HDPCVD, PVD, electroplating, sputtering, evaporation, or any suitable process, followed by annealing to induce a silicate reaction. In some embodiments, the metal silicate layer 112 is a Ti layer deposited by PECVD and subsequently annealed.

[0051] In some embodiments, the metal silicate layer 112 is formed by a CVD process or an epitaxial deposition process without annealing. For example, due to a selective epitaxial deposition process, the metal silicate layer 112 may be formed on the epitaxial layer 110 and / or the source / drain region 107 of the substrate 102, but not on the spacer layer 104. The metal silicate layer 112 may include titanium silicate, cobalt silicate, ruthenium silicate, tungsten silicate, molybdenum silicate, combinations of the above, or other suitable metal silicates.

[0052] In some embodiments, the deposition of the metal silicate layer 112 is performed in the same chamber as the formation of the epitaxial layer 110, such as the second chamber of the processing system described herein. In some other embodiments, the metal silicate layer 112 is deposited in a third processing chamber. Thus, the metal silicate layer 112 can be formed in situ on the epitaxial layer 110. By performing in-situ operations 302-306, interface contamination between the substrate 102, the epitaxial layer 110, and the metal silicate layer 112 can be significantly reduced, thereby reducing the total resistance of the final component contact 100 and improving thermal stability.

[0053] In some embodiments, the deposited metal silicate layer 112 is subjected to an annealing process in a second, third, or fourth processing chamber of the processing system described herein. In some embodiments, the third or fourth processing chamber is a rapid thermal annealing (RTA) chamber. An example of a suitable RTA chamber is the Vantage® RADOXTMRTP chamber, available from Applied Materials, Inc., Santa Clara, California. However, it is further envisioned that other appropriately configured chambers from other manufacturers may also be implemented to perform the deposition process described herein.

[0054] In operation 308 and Figure 4D, a capping layer 114 is formed on the component contact 100 (e.g., the metal silicate layer 112 and the spacer layer 104). The component contact 100 may be referred to as a "contact plug". In some embodiments, the capping layer 114 is a nitride layer formed by a nitriding process. The nitriding process may be performed in the same or a different chamber as the formation of the metal silicate layer 112 and / or the epitaxial layer 110. For example, the nitriding process may be performed in situ along with the deposition of the epitaxial layer 110 and the metal silicate layer 112 in a second or third processing chamber, thereby further reducing interface contamination within the component contact 100. The nitriding process at operation 308 provides improved thermal stability to the metal silicate layer 112, thereby reducing the likelihood of degradation and / or oxidation during subsequent processing with high thermal budgets. Generally, the capping layer 114 may have a thickness of about 5 nm or less, such as about 2 nm or less.

[0055] In some embodiments, the nitriding process is a plasma nitriding process utilizing a mixture of nitrogen (N2), hydrogen (H2), and / or argon (Ar) gases. In some embodiments, the plasma nitriding process is performed using a radio frequency power between about 100 W and about 1000 W and at a pressure between about 5 Torr and about 50 Torr.

[0056] In operation 310 and Figure 4E, a metal layer 116 is formed on the capping layer 114. The metal layer 116 is formed on the surface of the capping layer 114 and can be used as a bit line conductor metal, which can be simply referred to as a bit line. In some embodiments, a seed layer (not shown) and / or a barrier layer (not shown) are formed between the capping layer 114 and the metal layer 116, which may include materials similar to or different from the metal layer 116.

[0057] Examples of materials suitable for the metal layer 116 include, but are not limited to, tungsten, cobalt, copper, aluminum, ruthenium, titanium, silver, platinum, palladium, alloys, derivatives of the foregoing, or any combination thereof. The metal layer 116 may be deposited on the capping layer 114 using one or more deposition processes, such as CVD, PECVD, ALD, PEALD, PVD, electroplating, ECP, or other suitable deposition methods. The formation of the metal layer 116 may be performed in a third, fourth, or fifth processing chamber of the processing system. In some embodiments, the metal layer 116 is formed in a CVD chamber. One example of a suitable CVD chamber is the Volta™ CVD chamber, available from Applied Materials, Inc., Santa Clara, California. However, it is further envisioned that other appropriately configured chambers from other manufacturers may also be implemented to perform the deposition processes described herein.

[0058] After the metal layer 116 is formed, further processes can be performed on the component contacts 100 to complete CMOS components and / or DRAM components (such as DRAM bit line arrays).

[0059] Examples of treatment systems that can be appropriately modified based on the teachings provided herein include the Endura®, Producer®, or Centura® integrated treatment system, or other suitable treatment systems available from Applied Materials, Inc., located in Santa Clara, California. It is conceivable that other treatment systems, including those from other manufacturers, may also be adapted to benefit from the conditions described herein.

[0060] Figure 5 shows a schematic top view of a multi-chamber processing system 500 according to one embodiment. The multi-chamber processing system 500 is configured to perform various semiconductor processing methods, such as method 300 described above, on one or more substrates. As shown, the multi-chamber processing system 500 includes a plurality of processing chambers 502, 514, 516, a first transfer chamber 504, a passage chamber 506, a second transfer chamber 510, a loading gate chamber 512, a factory interface 520, one or more cassettes 530, and a system controller 580.

[0061] Each processing chamber 502 is coupled to a first transfer chamber 504. The first transfer chamber 504 is also coupled to a first pair of through chambers 506. A transfer robot (not shown) is centrally located in the first transfer chamber 504 for transferring substrates between the through chambers 506 and the processing chambers 502. The through chambers 506 are coupled to a second transfer chamber 510, which is coupled to processing chambers 514 and 516, which are configured to perform a pre-cleaning process (operation 302) and / or, if applicable, an annealing process. A transfer robot (not shown) is centrally located in the second transfer chamber 510 for transferring substrates between the loading gate chamber 512, the through chambers 506, and the processing chambers 514 and / or 516. A factory interface 520 is connected to the second transfer chamber 510 via the loading gate chamber 512. The plant interface 520 is coupled to one or more pods 530 on the opposite side of the loading gate chamber 512. The pods 530 are typically front-opening unified pods (FOUPs) that can be accessed from the cleaning chamber.

[0062] In some embodiments, the substrate is transferred from the cassette 530 to processing chambers 514 and / or 516, where a pre-cleaning process (e.g., operation 302) is performed to remove contaminants, such as carbon or oxide contaminants, from exposed surfaces of the source / drain regions of the substrate's transistors. Subsequently, the substrate is transferred to one or more processing chambers 502, where epitaxial layers are deposited (e.g., operation 304, such as SEG of SiCP or SiP), silicate layers are deposited (e.g., operation 306, such as PECVD of Ti or Mo), optional capping layers are formed (e.g., operation 308, such as Ti layer nitriding to form TiN), and metal layers are deposited (e.g., operation 310, such as CVD of W). Because all these operations 302-310 are performed within the same processing system, the vacuum is not disrupted as the substrate is transferred to the respective chambers. This reduces the chance of contamination and improves the quality of the deposited epitaxial film, thereby reducing the contact resistance of any formed contact structures.

[0063] System controller 580 is coupled to processing system 500. System controller 580 controls processing system 500 or its components. For example, system controller 580 controls the operation of processing system 500 by directly controlling chambers 502, 504, 506, 510, 512, 514, 516 and / or factory interface 520 and / or cassette 530, or by controlling controllers associated with chambers 502, 504, 506, 510, 512, 514 and / or factory interface 520 and / or cassette 530. In operation, system controller 580 enables the collection and feedback of data from each chamber to coordinate the performance of processing system 500.

[0064] As shown in the figure, the system controller 580 includes a central processing unit (CPU) 582, memory 584, and support circuitry 586. The CPU 582 may be one of any type of general-purpose processor used in an industrial environment. The memory 584 may include non-transitory computer-readable media and / or machine-readable storage devices. The memory 584 is accessible by the CPU 582 and may be one or more types of memory, such as random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, or any other form of local or remote digital memory. The support circuitry 586 is coupled to the CPU 582 and may include cache memory, clock circuitry, input / output subsystems, power supply, etc. The system controller 580 is configured to perform the operations of method 300 stored in memory 584. The various embodiments disclosed in this disclosure can generally be implemented under the control of CPU 582 by executing computer instructions stored in memory 584 (or memory of a specific processing chamber), for example, as a computer program product or software routine. In other words, the computer program product is tangibly contained in memory 584 (or a non-transitory computer-readable medium or machine-readable storage device). When the computer instructions are executed by CPU 582, CPU 582 controls the chamber to perform operations according to the various embodiments.

[0065] As described above, this document provides a method and processing system for forming semiconductor device contacts. In some cases, the method and system provided herein can be used to form bit line contacts (BLCs) of dynamic random access memory (DRAM) arrays, storage nodes, and CMOS device contacts with reduced thickness.

[0066] The processing system includes a plurality of processing chambers configured to clean, deposit, etch, and / or anneal a substrate on which semiconductor element contact structures are formed. These chambers are integrated into a single integrated system, an operation previously considered challenging due to the high sensitivity of epitaxial chambers to contamination. Integrating at least one epitaxial chamber with a metal deposition chamber enables various operations of the contact formation method described herein to be performed within the same processing system. Therefore, the vacuum is not disrupted when the substrate is transferred between the various processing chambers, reducing the chance of interface contamination and improving the quality of the deposited layer. Furthermore, the processing system and method provide a highly nitrided metal silicate layer, which improves its thermal stability and reduces degradation during subsequent thermal processing. Therefore, the integrated process described herein can form contact structures with reduced resistance. Example Embodiments

[0067] Example 1: A method for forming element contacts, comprising: depositing a doped semiconductive layer on an exposed surface of a first doped region of a substrate in a first chamber, wherein the first doped region is exposed through trenches formed in a dielectric material formed on the first doped region; depositing a metal silicate layer on the doped semiconductive layer; and performing a nitriding process on the metal silicate layer to form a nitride layer on the metal silicate layer, wherein the semiconductive layer, the metal silicate layer and the nitride layer are formed without breaking the vacuum, and wherein the doped semiconductive layer and the metal silicate layer form bit line contact plugs for a dynamic random access memory (DRAM) element, the DRAM element comprising: word lines formed between a first doped region and a second doped region of the substrate; and bit lines formed on the bit line contact plugs.

[0068] Example 2: The method of Example 1 above, wherein the doped semiconducting layer is a high strain in-situ phosphorus-doped silicon (HS-Si:P) layer or a phosphorus and carbon-doped silicon (SiP:C) layer.

[0069] Example 3: The method of Example 2 above, wherein the phosphorus concentration of the semiconducting layer is about 1×1021 atoms / cm3 or lower.

[0070] Example 4: The method of Example 1 above, wherein the metal silicate layer is deposited in the first chamber through a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a high density plasma chemical vapor deposition (HDPCVD) process, a physical vapor deposition (PVD) process, an electroplating process, a sputtering process, or an evaporation process.

[0071] Example 5: The method of Example 4 above, wherein the metal silicate layer includes titanium (Ti), cobalt (Co), nickel (Ni), ruthenium (Ru), tantalum (Ta), tungsten (W), molybdenum (Mo) or an alloy of the above.

[0072] Example 6: The method of Example 1, wherein the nitride layer is a titanium nitride (TiN) layer.

[0073] Example 7: The method of Example 1 further includes: pre-cleaning the substrate in a second chamber before depositing the doped semiconducting layer, wherein the pre-cleaning and formation of the doped semiconducting layer, the metal silicate layer and the nitride layer are performed without breaking the vacuum.

[0074] Example 8: The method of Example 1 further includes: depositing a conductive layer on a nitride layer in a second chamber, wherein the formation of the doped semiconducting layer, the metal silicate layer, the nitride layer and the conductive layer is performed without breaking the vacuum, and wherein the conductive layer forms a bit line on the bit line contact plug.

[0075] Example 9: The method of Example 8, wherein the conductive layer is deposited through a chemical vapor deposition (CVD) process, a plasma-enhanced chemical vapor deposition (PECVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or a plasma-enhanced ALD (PEALD) process.

[0076] Example 10: The method of Example 9, wherein the conductive layer comprises tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), titanium (Ti), silver (Ag), platinum (Pt), palladium (Pa) or alloys thereof.

[0077] Example 11: A method for forming component contacts, comprising: pre-cleaning a substrate in a first chamber; depositing a doped semiconductive layer on exposed surfaces of a plurality of doped regions of the substrate in a second chamber, wherein the doped regions are exposed through trenches formed in a dielectric material formed on the plurality of doped regions; and depositing a metal silicide layer on the doped semiconductive layer in a third chamber, wherein the doped semiconductive layer and the metal silicide layer form dynamic random access memory; The DRAM element includes a bit line contact plug; a metal silicate layer is nitrided to form a nitride layer on the metal silicate layer; and a conductive layer is deposited on the nitride layer in a fourth chamber, the conductive layer forming bit lines on the bit line contact plug, wherein pre-cleaning and formation of the doped semiconducting layer, the metal silicate layer, the nitride layer and the conductive layer are performed without breaking the vacuum, and wherein the DRAM element further includes: word lines disposed within a portion of a substrate and formed between a first doped region and a second doped region of a plurality of doped regions.

[0078] Example 12: The method of Example 11, wherein the doped semiconducting layer is a high-strain in-situ phosphorus-doped silicon (HS-Si:P) layer or a phosphorus and carbon-doped silicon (SiP:C) layer.

[0079] Example 13: The method of Example 12, wherein the phosphorus concentration of the semiconducting layer is about 1×1021 atoms / cm3 or lower.

[0080] Example 14: The method of Example 11, wherein the metal silicate layer is deposited through a chemical vapor deposition (CVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a high density plasma chemical vapor deposition (HDPCVD) process, a physical vapor deposition (PVD) process, an electroplating process, a sputtering process, or an evaporation process.

[0081] Example 15: The method of Example 14, wherein the metal silicate layer comprises titanium (Ti), cobalt (Co), nickel (Ni), ruthenium (Ru), tantalum (Ta), tungsten (W), molybdenum (Mo) or an alloy thereof.

[0082] Example 16: The method of Example 11, wherein the nitride layer is a titanium nitride (TiN) layer.

[0083] Example 17: A processing system includes: a system controller; a first processing chamber, wherein the system controller is configured to perform a pre-cleaning process on a doped region at the bottom of a trench formed in a dielectric layer above a substrate; a second processing chamber, wherein the system controller is configured such that: a doped epitaxial layer and a metal silicate layer are formed on the exposed surface of the doped region of the substrate, the doped epitaxial layer and the metal silicate layer forming bit line contact plugs for dynamic random access memory (DRAM) elements; and a nitriding process is performed on the metal silicate layer to form a nitride layer; and a third processing chamber, wherein the system controller is configured such that a conductive layer is formed on the nitride layer, the conductive layer forming bit lines on the bit line contact plugs, wherein the processing system is configured to transfer a substrate between the first processing chamber, the second processing chamber and the third processing chamber without breaking the vacuum.

[0084] Example 18: The processing system of Example 17, wherein the doped epitaxial layer is a high strain in-situ phosphorus-doped silicon (HS-Si:P) layer or a phosphorus and carbon-doped silicon (SiP:C) layer.

[0085] Example 19: The processing system of Example 17, wherein the phosphorus concentration of the doped epitaxial layer is about 1×1021 atoms / cm3 or lower.

[0086] Example 20: The processing system of Example 17, wherein the metal silicate layer comprises titanium (Ti), cobalt (Co), nickel (Ni), ruthenium (Ru), tantalum (Ta), tungsten (W) or alloys thereof.

[0087] Example 21: A processing system includes: a transfer chamber; a plurality of processing chambers coupled to the transfer chamber; and a system controller configured to perform a process in the processing system, the process including: performing a pre-cleaning process on a substrate; forming a doped epitaxial semiconducting layer on a doped region on the substrate; forming a metal silicide layer on the doped epitaxial semiconducting layer; performing a nitriding process on the metal silicide layer to form a nitride layer on the metal silicide layer; and depositing a conductive layer on the nitride layer, wherein the pre-cleaning and the formation of the doped epitaxial semiconducting layer, the metal silicide layer, and the nitride layer are performed without disrupting the vacuum.

[0088] Example 22: The processing system of Example 21, wherein the doped epitaxial semiconducting layer is a high strain in-situ phosphorus-doped silicon (HS-Si:P) layer or a phosphorus and carbon-doped silicon (SiP:C) layer, and wherein the metal silicide layer comprises titanium (Ti), cobalt (Co), nickel (Ni), ruthenium (Ru), tantalum (Ta), tungsten (W), molybdenum (Mo) or alloys thereof.

[0089] Example 23: The processing system of Example 22, wherein the phosphorus concentration of the doped epitaxial semiconducting layer is about 1×1021 atoms / cm3 or lower.

[0090] Although the foregoing content pertains to embodiments of the present disclosure, other and further embodiments of the present disclosure are conceivable without departing from the basic scope of the present invention, the scope of which is determined by the appended claims. [Simplified Explanation of the Diagram]

[0010] To facilitate a detailed understanding of the above-described features of this disclosure, the invention briefly summarized above can be described in more detail with reference to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only show exemplary embodiments and should not be considered as limiting its scope, and other equivalent embodiments are permissible.

[0011] Figure 1 is a cross-sectional view of a component contact according to an embodiment of the present disclosure.

[0012] Figures 2A-2C are cross-sectional views of element contacts in various elements according to embodiments of the present disclosure.

[0013] Figure 3 is a flowchart of a method for forming element contacts according to an embodiment of the present disclosure.

[0014] Figures 4A-4E illustrate the element contacts of Figure 1 in various operations of the method of Figure 3 according to embodiments of the present disclosure.

[0015] Figure 5 shows a schematic top view of a multi-chamber processing system for performing the method of Figure 3 according to an embodiment of the present disclosure.

[0016] For ease of understanding, the same element symbols are used as much as possible to represent the same elements in the figures. It is contemplated that elements and features of one embodiment may be advantageously incorporated into other embodiments without further description. [Biomaterial Storage]

[0092] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A method for forming a dynamic random access memory (DRAM) device, comprising the steps of: forming a plurality of bit line contact regions in an array on the DRAM device, wherein the step of forming each of the bit line contact regions comprises the steps of: forming a plurality of source / drain contact regions; depositing a doped semiconducting layer on a first doped region, and simultaneously depositing the doped semiconducting layer on each of the source / drain contact regions, the first doped region being exposed through a trench in a dielectric material formed on the first doped region on a substrate; depositing a metal silicate layer on the doped semiconducting layer; and forming a nitride layer on the metal silicate layer, wherein the doped semiconducting layer, the metal silicate layer, and the nitride layer are formed in a single processing system without breaking a vacuum, the single processing system comprising a plurality of processing chambers, wherein the doped semiconducting layer comprises a silicon layer doped only with carbon, the carbon concentration being about 5 × 10²¹ atoms / cm³ or lower.

2. The method of claim 1, wherein the doped semiconducting layer is deposited through an epitaxial deposition process.

3. The method as described in request item 1, wherein: The metal silicate layer is deposited through a chemical vapor deposition (CVD) process, a plasma-enhanced CVD (PECVD) process, a high-density plasma CVD (HDPCVD) process, a physical vapor deposition (PVD) process, an electroplating process, a sputtering process, or an evaporation process, and the metal silicate layer includes at least one of titanium (Ti), cobalt (Co), nickel (Ni), ruthenium (Ru), tantalum (Ta), molybdenum (Mo), and tungsten (W).

4. The method of claim 1, further comprising the steps of: performing a pre-cleaning process on the first doped region prior to depositing the doped semiconductive layer, wherein the pre-cleaning process, and the formation of the doped semiconductive layer, the metal silicate layer, and the nitride layer are performed in the single processing system without breaking the vacuum; and depositing a conductive layer on the nitride layer, wherein the conductive layer forms a bit line on the bit line contact region.

5. The method of claim 4, wherein the formation of the doped semiconducting layer, the metal silicate layer, the nitride layer and the conductive layer is performed in the single processing system without breaking the vacuum.

6. The method of claim 1, wherein the nitride layer is formed by performing a nitriding process on the metal silicate layer.

7. A method of forming a dynamic random access memory (DRAM) device, comprising the steps of: forming a plurality of bit line contact regions in an array on the DRAM device, wherein the step of forming each of the bit line contact regions comprises the steps of: depositing a doped semiconductive layer on a first doped region, the first doped region being exposed through a trench in a dielectric material formed on the first doped region on a substrate; depositing a metal silicate layer on the doped semiconductive layer; and forming a nitride layer on the metal silicate layer, wherein the doped semiconductive layer, the metal silicate layer and the nitride layer are formed in a single processing system without breaking a vacuum, the single processing system comprising a plurality of processing chambers, wherein the doped semiconductive layer comprises a silicon layer doped only with carbon, the carbon concentration being about 5 × 10²¹ atoms / cm³ or lower.

8. The method of claim 7, wherein the doped semiconducting layer is deposited through an epitaxial deposition process.

9. The method as described in request item 7, wherein: The metal silicate layer is deposited through a chemical vapor deposition (CVD) process, a plasma-enhanced CVD (PECVD) process, a high-density plasma CVD (HDPCVD) process, a physical vapor deposition (PVD) process, an electroplating process, a sputtering process, or an evaporation process, and the metal silicate layer includes at least one of titanium (Ti), cobalt (Co), nickel (Ni), ruthenium (Ru), tantalum (Ta), molybdenum (Mo), and tungsten (W).

10. The method of claim 7 further includes the step of: performing a pre-cleaning process on the first doped region prior to depositing the doped semiconducting layer, wherein the pre-cleaning process, and the formation of the doped semiconducting layer, the metal silicate layer, and the nitride layer are performed in the single processing system without breaking the vacuum.

11. The method of claim 10, further comprising the steps of: depositing a conductive layer on the nitride layer, wherein the conductive layer forms a bit line on the bit line contact region; wherein the formation of the doped semiconducting layer, the metal silicate layer, the nitride layer and the conductive layer is performed in the single processing system without breaking the vacuum.

12. A method of forming a dynamic random access memory (DRAM) device, comprising the steps of: forming a plurality of bit line contact regions in an array on the DRAM device, wherein the step of forming each bit line contact region comprises the steps of: performing a pre-cleaning process on a first doped region in a first chamber, the first doped region being exposed through a trench formed in a dielectric material formed above the first doped region on a substrate; depositing a doped semiconducting layer on the first doped region in a second chamber; depositing a metal silicon layer on the doped semiconducting layer in a third chamber; performing a nitriding process on the metal silicon layer to form a nitride layer on the metal silicon layer; and depositing a conductive layer on the nitride layer in a fourth chamber, wherein the pre-cleaning process and the formation of the doped semiconducting layer, the metal silicon layer, and the nitride layer are performed without disrupting the vacuum. The doped semiconducting layer includes a silicon layer doped only with carbon, with a carbon concentration of about 5 × 10²¹ atoms / cm³ or lower.

13. The method of claim 12, wherein the pre-cleaning process, and the formation of the doped semiconducting layer, the metal silicate layer, the nitride layer, and the conductive layer are performed without disrupting the vacuum.

14. The method of claim 12, wherein the metal silicate layer is deposited through a chemical vapor deposition (CVD) process, a plasma-enhanced CVD (PECVD) process, a high-density plasma CVD (HDPCVD) process, a physical vapor deposition (PVD) process, an electroplating process, a sputtering process, or an evaporation process.

15. The method of claim 14, wherein the metal silicate layer comprises titanium (Ti), cobalt (Co), nickel (Ni), ruthenium (Ru), tantalum (Ta), tungsten (W), molybdenum (Mo), or an alloy thereof.

16. The method of claim 12, wherein the doped semiconducting layer is deposited through an epitaxial deposition process.

17. A processing system, comprising: One transfer to the chamber; A plurality of processing chambers are coupled to the transfer chamber; A system controller is configured to execute a process in the processing system, the process comprising the following steps: exposing a first doped region to a pre-cleaning process in a first chamber, the first doped region being exposed through a trench in a dielectric material formed on the first doped region on a substrate; depositing a doped semiconducting layer on the first doped region in a second chamber; depositing a metal silicide layer on the doped semiconducting layer in a third chamber; performing a nitriding process on the metal silicide layer to form a nitride layer on the metal silicide layer; and depositing a conductive layer on the nitride layer in a fourth chamber, wherein the pre-cleaning process and the formation of the doped semiconducting layer, the metal silicide layer, and the nitride layer are performed without breaking the vacuum, wherein the doped semiconducting layer comprises a silicon layer doped only with carbon at a concentration of about 5 × 10²¹ atoms / cm³ or less.

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