Switching regulator and power management integrated circuit

Abstract

This invention provides a switching regulator, comprising: an inductor connected to a switching node; a power switch connected to the switching node and configured to apply a first voltage to the switching node in response to a first control signal and to apply a second voltage to the switching node in response to a second control signal; and a controller configured to generate the first control signal and the second control signal. After a first pause following a transition from low to high in the first control signal, the second control signal transitions from low to high; after a second pause following a transition from a high level to a low level in the second control signal, the first control signal transitions from high to low; and an inductor current flowing through the inductor flows in a first direction during the first pause and in a second direction different from the first direction during the second pause.

Description

Technical Field

[0001] Embodiments of the inventive concept generally relate to a switching regulator that converts an input voltage into an output voltage. Embodiments of the inventive concept also relate to a power management integrated circuit (PMIC) including the switching regulator. [Cross - Reference to Related Applications]

[0002] This application claims the priority of Korean Patent Application No. 10 - 2021 - 0139386, filed on October 19, 2021, with the Korean Intellectual Property Office, the subject matter of which is incorporated herein by reference in its entirety under 35 U.S.C.§ 119. Background Art

[0003] A PMIC can be used to generate one or more supply voltages that are typically provided to an electronic system, circuit, component, and / or element (hereinafter generally referred to as an "electronic device"), where the respective levels of the supply voltages are referenced for determining the performance of the electronic device. The PMIC can include one or more regulators for generating (or defining) the supply voltage levels.

[0004] In this regard, a regulator can be a circuit that converts an externally provided input power signal into an internal direct current (DC) power signal compatible with an intended electronic device (e.g., a system including a power switch). Assuming the input power signal is a DC power signal, the regulator can be operated as a DC - DC converter, for example, to increase or decrease the level of the input DC power signal. Here, the DC - DC converter can include a boost converter (e.g., a type of boost converter) capable of increasing the level of the input DC power signal, a buck converter (e.g., a type of buck converter) capable of decreasing the level of the DC input power signal, and / or a buck - boost converter capable of increasing or decreasing the level of the input DC power signal. Summary of the Invention

[0005] Embodiments of the inventive concept provide a switching regulator capable of performing flexible switching. Embodiments of the inventive concept also provide a power management integrated circuit (PMIC) including the switching regulator capable of performing flexible switching.

[0006] According to an embodiment, a switching regulator may include: an inductor connected to a switching node; a power switch connected to the switching node and configured to apply a first voltage to the switching node in response to a first control signal and apply a second voltage to the switching node in response to a second control signal; and a controller configured to generate the first control signal and the second control signal, wherein after a first dead time after the first control signal transitions from low to high, the second control signal transitions from low to high, after a second dead time after the second control signal transitions from a high level to a low level, the first control signal transitions from high to low, and the inductor current flowing through the inductor flows in a first direction during the first dead time and in a second direction different from the first direction during the second dead time.

[0007] According to an embodiment, a switching regulator for converting an input power supply voltage into an output power supply voltage may include: an inductor connected to a switching node; a power switch including a first transistor configured to apply the input power supply voltage to the switching node in response to a first control signal and a second transistor configured to apply a ground voltage to the switching node in response to a second control signal; a peak current detector configured to provide a peak current sensing signal when the inductor current flowing through the inductor reaches a peak current; a zero current detector configured to provide a zero current sensing signal when the inductor current is an offset current; a feedback controller configured to compare the output power supply voltage with a target voltage and provide a corresponding feedback signal; a pulse frequency modulation generator configured to provide a pulse frequency modulation signal based on the peak current sensing signal, the zero current sensing signal, the feedback signal, and a reference voltage; and a gate driver configured to provide the first control signal and the second control signal based on the pulse frequency modulation signal, wherein the first transistor and the second transistor are turned off during a first dead time after the inductor current reaches the peak current, the first transistor and the second transistor are turned off during a second dead time after the inductor current reaches the offset current, and the direction of the peak current and the direction of the offset current are opposite to each other.

[0008] According to an embodiment, a power management integrated circuit may include a switching regulator configured to convert an input power supply voltage to an output power supply voltage. Here, the switching regulator may include: an inductor connected to a switching node; a power switch connected to the switching node and configured to apply a first voltage to the switching node in response to a first control signal and to apply a second voltage to the switching node in response to a second control signal; and a controller configured to generate the first control signal and the second control signal. After a first dead time after the first control signal transitions from low to high, the second control signal may transition from low to high, and after a second dead time after the second control signal transitions from high to low, the first control signal may transition from high to low, and the inductive current flowing through the inductor may flow in a first direction during the first dead time and in a second direction different from the first direction during the second dead time. Brief Description of the Drawings

[0009] After considering the following detailed description and the accompanying drawings, various advantages, benefits, features, and related aspects of the inventive concept may be understood, where: FIG. 1 is a block diagram of an electronic device showing an embodiment according to the inventive concept. FIG. 2 is a block diagram further showing the switching regulator of FIG. 1 in one example (100). FIG. 3 is a block diagram further showing the switching regulator of FIG. 1 in another example (100a), and FIG. 4 is a timing diagram showing the operation of the switching regulator 100a of FIG. 3. FIG. 5 is a block diagram further showing the switching regulator of FIG. 1 in yet another example (100b), and FIG. 6 is a timing diagram showing the operation of the switching regulator 100b of FIG. 5. FIG. 7 is a graph showing the change in power efficiency with respect to the load current of the switching regulator 100a of FIG. 3 and the switching regulator 100b of FIG. 5. FIG. 8 is a block diagram of a system 20 including a PMIC showing an embodiment according to the inventive concept. FIG. 9 is a block diagram of an electronic device 1000 having a controller 1700 including a PMIC showing an embodiment according to the inventive concept. Embodiments

[0010] Throughout the written description and the drawings, the same reference numerals and marks are used to denote the same or similar systems, components, circuits, elements, features, and / or method steps.

[0011] FIG. 1 is a block diagram showing an electronic device 10 according to an embodiment of the concepts of the present invention. Referring to FIG. 1, the electronic device 10 may generally include a central processing unit (CPU) 11, a memory 12, a power management integrated circuit (PMIC) 13, a user interface 14, a storage device 15, and a communication device 16.

[0012] In some embodiments, the electronic device 10 may include various semiconductor wafers, semiconductor devices, semiconductor packages, semiconductor modules, semiconductor systems, and / or system-on-chip (SOC) devices. As selected examples, the electronic device 10 is a smart phone, a tablet personal computer (PC), a mobile phone, a video phone, an e-book reader, a desktop personal computer (PC), a laptop personal computer (PC), a netbook, a workstation, a server, a personal digital assistant (PDA), a portable multimedia player (PMP), an MP3 player, a mobile medical device, a digital TV, a camera, a wearable device, an Internet of Things (IoT) device, an Internet of Everything (IoE) device, a virtual reality (VR) device, an augmented reality (AR) device, a data center, or an LED driving device.

[0013] The CPU 11 may perform various operations / calculations necessary to operate the electronic device 10. For example, the CPU 11 may execute software, firmware, instruction sequences, and / or code (e.g., an operating system and / or an application running on the operating system) loaded into the memory 12. In addition, the CPU 11 may store the results of such calculations / operations in the memory 12.

[0014] Accordingly, the memory 12 may be used to store data and code associated with the operation of the CPU 11. In some embodiments, the memory 12 may operate as a main memory device for the electronic device 10. Alternatively or additionally, the memory 12 may operate as a buffer memory, a cache memory, and / or a working memory.

[0015] Memory 12 may include one or more volatile memories (e.g., static random access memory (SRAM) or dynamic RAM (DRAM)) and / or one or more non-volatile memories (e.g., flash memory, phase-change RAM (PRAM), magneto-resistive RAM (MRAM), resistive RAM (ReRAM), and ferro-electric RAM (FRAM)). Memory 12 may be physically implemented as two or more memories or memory systems. Memory 12 may be implemented as an external memory device capable of communicating with electronic device 10 and / or one or more internal memories.

[0016] PMIC 13 may be used to generate one or more power supply voltages and / or currents (hereinafter, singularly or collectively referred to as "power supply voltage / current") necessary to operate electronic device 10. This power supply voltage / current may be provided differently to components of electronic device 10 (e.g., CPU 11, memory 12, user interface 14, storage device 15, and / or communication device 16). Accordingly, each of the components of electronic device 10 may be understood to perform one or more functions in response to the power supply voltage / current provided by PMIC 13. In some embodiments, PMIC 13 may be implemented as an external circuit of electronic device 10.

[0017] PMIC 13 may include various circuits capable of defining and generating power supply voltage / current. For example, PMIC 13 may include one or more reference voltage generators, one or more regulators (e.g., linear regulators and / or switching regulators), and one or more converters (e.g., boost converters, buck converters, and / or buck-boost converters).

[0018] In the illustrated example of FIG. 1, it is assumed that PMIC 13 includes switching regulator 100.

[0019] In this regard, the switching regulator 100 can provide (or output) an output power signal (e.g., output power supply voltage VOUT) by regulating (or converting) an input power signal (e.g., input power supply voltage VIN). Thus, it is assumed that the switching regulator 100 functions as a DC-DC converter. In some embodiments, the switching regulator 100 can be understood as a switching mode power supply (SMPS) or a circuit included in an SMPS. The switching regulator 100 can perform power conversion using at least one of, for example, a power switch, an inductor, and a capacitor.

[0020] In some embodiments, the switching regulator 100 can be selectively operated in a heavy load operation mode or a light load operation mode, as determined and controlled by the CPU 11. For example, when the operating load (e.g., the number of a type of operation) of any one of the components in the electronic device 10 increases (e.g., when the CPU 11 performs one or more operations, the computational load placed on the CPU 11 increases, and / or data is written to and / or read from the memory 12 and / or the storage device 15), the CPU 11 can determine that the switching regulator 100 will operate in the heavy load operation mode. In the heavy load operation mode, the switching regulator 100 can output a corresponding output power supply voltage defined using, for example, a pulse width modulation mode. Alternatively, when the electronic device 10 enters the standby mode or when the CPU 11 enters the idle state, the CPU 11 can determine that the switching regulator 100 will operate in the light load operation mode. In the light load operation mode, the switching regulator 100 can output a corresponding output power supply voltage defined using, for example, a pulse frequency modulation mode, a burst mode, or a turn-on / turn-off mode.

[0021] In some embodiments, the switching regulator 100 may include an inductor L connected to a switching node, where the output terminal of the power switch is connected to the switching node. Here, the power switch may apply a first voltage to the switching node in response to a first control signal, or apply a second voltage to the switching node in response to a second control signal, where the controller is available to generate the first control signal and the second control signal. The second control signal may transition from a low level (hereinafter "low") to a high level (hereinafter "high") after a first dead time. (Here, the term "dead time" may refer to the period between the disconnection of one transistor and the connection of another transistor - for example, the time when the first control signal transitions from high to low). Similarly, the first control signal may transition from high to low after a second dead time (e.g., the time when the second control signal transitions from high to low). Thus, the current flowing through the inductor L may reverse in one direction (i.e., the first direction) during the first dead time and flow through the inductor L in another direction (i.e., the second direction) during the second dead time.

[0022] The user interface 14 may be available to communicate with the user of the electronic device 10 under the control of the CPU 11. For example, the user interface 14 may provide the user with data stored in the memory 12 or the storage device 15. In this regard, the user interface 14 may receive data from the user or requests for data processing. In some embodiments, the user interface 14 may include at least one of the following: such as a microphone, a keyboard, a mouse, a touch screen, a display device (e.g., a monitor), and a speaker.

[0023] The storage device 15 may be provided as a storage medium related to the electronic device 10. The storage device 15 may store data generated by the CPU 11 (e.g., data that needs to be stored long - term), files to be operated on by the CPU 11, and various software, firmware, code, and executable instructions. The storage device 15 may be used as an auxiliary memory device related to the electronic device 10. In some embodiments, the storage device 15 may be differently implemented as a memory card (e.g., MMC, eMMC, SD, microSD, etc.). Alternatively or additionally, the storage device 15 may include non - volatile memory such as NAND flash memory, NOR flash memory, PRAM, MRAM, ReRAM, or FRAM. In some embodiments, the electronic device 10 may include two or more than two storage devices 15. In some embodiments, the storage device 15 may be external to the electronic device 10.

[0024] The communication device 16 can be used to communicate with various devices external to the electronic device 10 using one or more wired communication protocols and / or wireless communication protocols. For example, under the control of the CPU 11, the communication device 16 can receive data from an external device and / or transmit data retrieved from the memory 12 or the storage device 15 to an external device.

[0025] FIG. 2 is a block diagram further showing the switching regulator 100 of FIG. 1 in one example. Referring to FIGS. 1 and 2, the switching regulator 100 may include a power switch 101, a controller 110 that controls the power switch 101, an inductor L, a resistor DCR, and an output capacitor Cout. For the purpose of clarity, the parasitic capacitor Cpar and the switching node NSW are also indicated in FIG. 2. The input power supply voltage VIN can be applied (or provided) to the input terminal IN of the switching regulator 100, and the output power supply voltage VOUT can be provided (manifested) at the output terminal OUT of the switching regulator 100.

[0026] It is assumed hereinafter that the switching regulator 100 operates in a pulse frequency modulation (PFM) mode. However, the switching regulator 100 can operate in one or more additional modes, such as a pulse width modulation (PWM) mode. It is further assumed that the switching regulator 100 includes various DC-DC converters, such as a boost converter, a buck converter, and / or a buck-boost converter.

[0027] The power switch 101 can be switched (e.g., turned on or off) under the control of the controller 110. When the power switch 101 is switched, the voltage manifested at the switching node NSW can be pulled up or pulled down in response to the input power supply voltage VIN. Accordingly, the magnitude of the inductive current IL flowing through the inductor L from the switching node NSW can be adjusted.

[0028] The parasitic capacitor Cpar can be understood as being connected between the switching node NSW and ground. The parasitic capacitor Cpar can be further understood as a modeled (or mathematically derived) capacitance associated with the switching node NSW, the power switch 101, and / or elements and characteristics related to the switching node NSW and the power switch 101. Thus, when the voltage manifested at the switching node NSW is pulled up, charge can be stored in the parasitic capacitor Cpar.

[0029] When the voltage of the switching node NSW is pulled up, the inductance current IL flowing into the inductor L can be increased. The inductance current IL can supply charge to the output capacitor Cout via the resistor DCR. The resistor DCR can be understood as a modeled DC resistance associated with the inductor L.

[0030] The level of the output power supply voltage VOUT can be referenced to the change in the amount of charge stored in the output capacitor Cout.

[0031] Here, the output power supply voltage VOUT can be fed back to the controller 110 together with the input power supply voltage VIN, the reference voltage VREF, and the voltage presented at the switching node NSW. In response, the controller 110 can generate a control signal for switching the power switch 101. For example, the controller 110 can detect (or monitor) the inductance current IL, compare the output power supply voltage VOUT with the reference voltage VREF, and generate a switching control signal for the power switch 101 related to the input power supply voltage VIN. Therefore, the power switch 101 can be switched in response to the switching control signal generated by the controller 110 to adjust the level of the output power supply voltage VOUT.

[0032] In some embodiments, the switching regulator 100 can be a synchronous switching regulator, but the scope of the inventive concept is not limited thereto.

[0033] FIG. 3 is a block diagram further showing the switching regulator 100 of FIG. 1 in another example (100a). Referring to FIGS. 1, 2, and 3, the switching regulator 100 of FIG. 2 can alternatively be implemented as the switching regulator 100a of FIG. 3.

[0034] The switching regulator 100a of FIG. 3 can include a controller 110a, a power switch 101, an inductor L, and an output capacitor Cout. The load device LOAD can be connected to the output terminal OUT of the switching regulator 100a.

[0035] The controller 110a may include a PFM generator 111a, a gate driver 112, inverters 112-1 and 112-2, an inductor current detector 113a, and a feedback controller 114. The PFM generator 111a may generate a signal PFMa that controls the gate driver 112 in response to a reference voltage VREF, an inductor current sensing signal CS, and a feedback signal FB. In some embodiments, the PFM generator 111a may include a comparator that compares the reference voltage VREF with the feedback signal FB. The generator 111a may receive the inductor current sensing signal CS from the inductor current detector 113a. The PFM generator 111a may receive the feedback signal FB from the feedback controller 114. The PFM generator 111a may use PFM technology to generate the signal PFMa in response to the inductor current sensing signal CS, the feedback signal FB, and the comparison between the reference voltage VREF and the feedback signal FB. The generator 111a may apply the generated signal PFMa to the gate driver 112.

[0036] In some embodiments, the number of pulses in the signal PFMa per unit time (e.g., the frequency of the signal PFMa) may be adjusted by the PFM generator 111a. For example, to increase the load current ILOAD, the PFM generator 111a may increase the frequency of the signal PFMa. Thus, the power switch 101 may be turned on / off more quickly (or more frequently during a unit time period, thereby increasing the PFMa signal frequency). Thus, the output power voltage VOUT may be increased, and the magnitude of the load current ILOAD may also be increased.

[0037] The gate driver 112 may generate a control signal that switches the power switch 101 in response to the signal PFMa output by the PFM generator 111a. The gate driver 112 may generate a control signal in response to the signal PFMa output from the PFM generator 111a. For example, based on the signal PFMa, the gate driver 112 may generate a first control signal applied to the gate of the transistor M1 via the inverter 112-1, and a second control signal applied to the gate of the transistor M2 via the inverter 112-2. The gate driver 112 may control the period during which the first control signal is high, the period during which the second control signal is high, and the dead time of the power switch 101 in response to the signal PFMa. In some embodiments, the gate driver 112 may further include a controller (e.g., a microcontroller) that controls the period of the dead time of the power switch 101.

[0038] The gate driver 112 can apply control signals to the gates of the transistor M1 and the transistor M2 of the power switch 101 via the inverter 112-1 and the inverter 112-2, respectively. Therefore, the control signals generated by the gate driver 112 can be inverted by the inverter 112-1 and the inverter 112-2, and then provided to the gates of the transistor M1 and the transistor M2 as the control signal PDRV and the control signal NDRV, respectively.

[0039] The inductor current detector 113a can detect the magnitude of the inductor current IL. The inductor current detector 113a can compare the magnitude of the inductor current IL with the magnitude of the peak current (e.g., the peak current in FIG. 4). Alternatively, the inductor current detector 113a can compare the magnitude of the inductor current IL with the magnitude of the minimum current. The magnitudes of the peak current and the minimum current can be determined in advance. If the magnitude of the inductor current IL is greater than or equal to the magnitude of the peak current, or if the magnitude of the inductor current IL is less than or equal to the magnitude of the minimum current, then the inductor current detector 113a can output the current sensing signal CS to the PFM generator 111a. For example, if the magnitude of the inductor current IL is greater than or equal to the magnitude of the peak current, then the current sensing signal CS can have a first level indicating this first relationship. However, if the magnitude of the inductor current IL is less than or equal to the magnitude of the minimum current, then the current sensing signal CS can have a second level different from the first level indicating this second relationship.

[0040] The feedback controller 114 can sense the output power supply voltage VOUT. That is, the feedback controller 114 can output the feedback signal FB based on the determination of whether the output power supply voltage VOUT is greater than or less than the target voltage. For example, if the output power supply voltage VOUT is less than the target voltage, then the feedback controller 114 can output the feedback signal FB indicating an increase in the level of the output power supply voltage VOUT to the PFM generator 111a. However, if the output power supply voltage VOUT is greater than the target voltage, then the feedback controller 114 can output the feedback signal FB indicating a decrease in the level of the output power supply voltage VOUT to the PFM generator 111a.

[0041] The power switch 101 may include a transistor M1 and a transistor M2. Here, the transistor M1 may be implemented as a P-channel Metal-Oxide-Semiconductor (PMOS) transistor, and the transistor M2 may be implemented as an N-channel Metal Oxide Semiconductor (NMOS) transistor. The parasitic diode Dpar1 and the parasitic diode Dpar2 may be modeled components corresponding to the parasitic diodes (e.g., body diodes) of the transistor M1 and the transistor M2, respectively.

[0042] The transistor M1 may include a first terminal (e.g., source) receiving an input power supply voltage VIN, a gate receiving a control signal PDRV, and a second terminal (e.g., drain) connected to a switch node NSW. The parasitic diode Dpar1 may be connected between the first terminal and the second terminal of the transistor M1. The transistor M2 may include a first terminal (e.g., drain) connected to the switch node NSW, a gate receiving a control signal NDRV, and a second terminal (e.g., source) receiving an applied ground voltage. The parasitic diode Dpar2 may be connected between the first terminal and the second terminal of the transistor M2.

[0043] The transistor M1 may be turned on in response to a low control signal PDRV. In this case, the input power supply voltage VIN may be transmitted to the switch node NSW via the transistor M1, and thus the switch voltage VSW may be increased. The transistor M1 may be turned off in response to a high control signal PDRV.

[0044] The transistor M2 may be turned on in response to a high control signal NDRV. In this case, the switch voltage VSW of the switch node NSW may be decreased toward the ground voltage. The transistor M2 may be turned off in response to a low control signal NDRV. And in this case, the switch node NSW may be electrically disconnected from the second terminal of the transistor M2 receiving the ground voltage.

[0045] A load device LOAD may be connected to the output terminal OUT of the switching regulator 100a such that a load current ILOAD flows from the output terminal OUT of the switching regulator 100a through the load device LOAD in response to the level of an output power supply voltage VOUT. However, when the load current ILOAD flows, the magnitude of the output power supply voltage VOUT may decrease over time, and the switching regulator 100a may sense the decrease in the output power supply voltage VOUT and adjust the output power supply voltage VOUT to a target voltage. Here, the target voltage may be defined according to the specific operating characteristics and requirements of the load device LOAD.

[0046] FIG. 4 is a timing diagram showing the operation of the switching regulator 100a of FIG. 3. The variations in the inductor current IL, the switch voltage VSW, the control signal PDRV, and the control signal NDRV depend on the operation of the switching regulator 100a.

[0047] The various signal waveforms in FIG. 4 are assumed to use a switching regulator related to the switching regulators described in FIGS. 1, 2, and 3. Here, for the purpose of this description, it is assumed that the pulse waveform of the inductor current IL includes two triangular pulses.

[0048] At time t0, it is assumed that the magnitude of the inductor current IL is approximately 0. When the transistor M1 turns on in response to a low control signal PDRV level, the magnitude of the switch voltage VSW can be substantially the same as the magnitude of the input power supply voltage VIN. That is, the magnitude of the switch voltage VSW can be approximated to the magnitude of the input power supply voltage VIN. (Here, it is further assumed that the parasitic capacitor Cpar has been fully charged by the input power supply voltage VIN before time t0). After time t0, the inductor current IL flowing through the inductor L can increase in response to the switch voltage VSW.

[0049] At time t1, the magnitude of the inductor current IL can be the same as the peak current. The inductor current detector 113a can detect the magnitude of the inductor current IL and can output an inductor current sensing signal CS to the PFM generator 111a, where the inductor current sensing signal CS indicates that the magnitude of the inductor current IL is the same (or approximate) as the peak current Ipeak. The PFM generator 111a can generate a signal PFMa for disconnecting the power switch 101 and can apply the generated signal PFMa to the gate driver 112. The control signal PDRV provided by the gate driver 112 to the gate of the transistor M1 can change from low to high in response to the signal PFMa.

[0050] Transistor M1 can be turned off in response to a high control signal PDRV. After time t1, the inductor current IL and the switch voltage VSW can decrease in response to the power consumption y of the load device LOAD connected to the output terminal OUT of the switch regulator 100a. That is, the power consumption of the load device LOAD can reduce the switch voltage VSW to a level lower than the ground voltage. For example, when power is consumed by the load device LOAD, the charge associated with the parasitic capacitor Cpar can be discharged. Subsequently, the parasitic diode Dpar2 of transistor M2 can be turned on due to the positive inductor current IL (i.e., the current flowing from the switch node NSW to the output terminal OUT via the inductor L and the resistor DCR). Therefore, the switch voltage VSW can be reduced below the ground voltage, dropping by up to the threshold voltage of the parasitic diode Dpar2 associated with transistor M2.

[0051] At time t2, the control signal NDRV provided to the gate of transistor M2 by the gate driver 112 can transition from low to high. For example, the gate driver 112 can be operated such that the high control signal NDRV is applied to the gate of transistor M2 after a first dead time DT1a after time t1. Transistor M2 can be turned on in response to the high control signal NDRV, and the ground voltage can be applied to the switch node NSW via transistor M2. Therefore, the switch voltage VSW can increase to the ground voltage, and the inductor current IL can decrease. Here, the rate at which the inductor current IL decreases can be proportional to the magnitude of the output supply voltage VOUT.

[0052] At time t3, the control signal NDRV can transition from high to low. And once the magnitude of the inductor current IL becomes approximately the same as the minimum current (e.g., approximately), then the inductor current detector 113a can detect the magnitude of the inductor current IL and output an inductor current sensing signal CS to the PFM generator 111a. The PFM generator 111a can generate a signal PFMa for turning off the power switch 101 and can apply the generated signal PFMa to the gate driver 112. The control signal NDRV provided to the gate of transistor M2 by the gate driver 112 can transition from high to low in response to the signal PFMa.

[0053] Transistor M2 can be turned off in response to the low control signal NDRV, and the parasitic diode Dpar2 of transistor M2 can be turned on due to the positive inductor current IL. Therefore, the magnitude of the switch voltage VSW can be reduced, thereby reducing the ground voltage. For example, the switch voltage VSW is reduced below the ground voltage, dropping by up to the threshold voltage of the parasitic diode Dpar2 associated with transistor M2.

[0054] At time t4, the control signal PDRV provided by the gate driver 112 to the gate of the transistor M1 may transition from high to low. For example, the gate driver 112 may be operable to apply the low control signal PDRV to the gate of the transistor M1 after a second dead time DT2a after time t3. The transistor M1 may turn on in response to the low control signal PDRV, and the input power supply voltage VIN may be applied to the switching node NSW via the transistor M1. Accordingly, the switching voltage VSW may increase to the input power supply voltage VIN, and the inductor current IL may also increase.

[0055] At time t5, the magnitude of the inductor current IL may be approximately the same as (e.g., approximate) the peak current. And as described with respect to time t1, the control signal PDRV provided by the gate driver 112 to the gate of the transistor M1 may transition from low to high, and the transistor M1 may turn off in response to the high control signal PDRV. Then, the inductor current IL and the switching voltage VSW may decrease in response to the power consumption of the load device LOAD connected to the output terminal OUT of the switching regulator 100a. When power is consumed by the load device LOAD, the parasitic capacitor Cpar may be discharged, the parasitic diode Dpar2 may be turned on, and the switching voltage VSW may be reduced below the ground voltage. For example, the switching voltage VSW may be reduced below the voltage by up to the threshold voltage of the parasitic diode Dpar2 associated with the transistor M2.

[0056] At time t6, the control signal NDRV provided by the gate driver 112 to the gate of the transistor M2 may transition from low to high. For example, the gate driver 112 may be operable to apply the high control signal NDRV to the gate of the transistor M2 after a third dead time DT3a after time t5. The transistor M2 may turn on in response to the high control signal NDRV, and the ground voltage may be applied to the switching node NSW via the transistor M2. Accordingly, the switching voltage VSW may increase to the ground voltage, and the inductor current IL may also decrease.

[0057] At time t7, the control signal NDRV provided by the gate driver 112 to the gate of the transistor M2 can transition from high to low. For example, in response to the feedback signal FB, the PFM generator 111a can determine that the output power voltage VOUT of the switching regulator 100a is the same as (or approximately) the target voltage. The power switch 101 can be controlled by the gate driver 112 according to the determination result and no longer maintain the switching state. That is, the transistors M1 and M2 can remain off. Therefore, the inductor current IL can be reduced to a value of 0, and the switch voltage VSW can also be reduced or converge. An example of the temporary convergence of the switch voltage VSW is shown in FIG. 4, but depending on the power consumption of the load device LOAD, the switch voltage VSW can be temporarily reduced in other ways (e.g., gradually reduced). Subsequently, the power switch 101 can switch again when the output power voltage VOUT drops below the target voltage.

[0058] Therefore, the transistors M1 and M2 can be turned off during the first dead time DT1a (e.g., the period from t1 to t2), the second dead time DT2a (e.g., the period from t3 to t4), and the third dead time DT3a (e.g., the period from t5 to t6). And thus, the transistors M1 and M2 cannot be turned on simultaneously. Therefore, the first terminal of the transistor M1 receiving the input power voltage VIN and the second terminal of the transistor M2 receiving the ground voltage will not be electrically connected under conditions that could potentially damage the power switch 101.

[0059] Here, it should be noted that at discrete moments along the time period shown in FIG. 4 (e.g., from time t0 to time t7), the switching operation of the switching regulator 100a can result in power losses. For example, due to the switching operation of the switching regulator 100a, the transistors M1 and M2 of the power switch 101 will be turned on / off differently. Whenever the transistors M1 and M2 of the power switch 101 are alternatively turned on / off, power losses can occur due to the presence of the parasitic capacitor Cpar associated with the switch node NSW and the presence of the parasitic diode Dpar2 associated with the transistor M2.

[0060] For example, as described above, before turning on any transistor, both the transistors M1 and M2 of the power switch 101 can be turned off during the first dead time DT1a, the second dead time DT2a, and / or the third dead time DT3a. When both the transistors M1 and M2 are turned off, due to the positive inductor current IL, the parasitic capacitor Cpar of the switch node NSW can be discharged, and the parasitic diode Dpar2 can be turned on. Therefore, power losses can occur due to the conduction of the parasitic diode Dpar2.

[0061] In addition, as another example, when the transistor M1 is turned on again, the discharged parasitic capacitor Cpar can be charged again by the input power supply voltage VIN. The loss current supplied to the parasitic capacitor Cpar based on the input power supply voltage VIN can be inversely proportional to the period of time taken by the input power supply voltage VIN with respect to the switching voltage VSW of the switch node NSW.

[0062] As the periods of the first dead time DT1a, the second dead time DT2a, and the third dead time DT3a increase, and as the switching frequency of the power switch 101 increases, the power loss due to the conduction of the parasitic diode Dpar2 and the power loss due to the recharing of the parasitic capacitor Cpar can increase.

[0063] FIG. 5 is a block diagram further showing the switch regulator 100 of FIG. 2 in another example (100b). Referring to FIGS. 1, 2, and 5, the switch regulator 100 of FIG. 2 can alternatively be implemented as the switch regulator 100b of FIG. 5.

[0064] Similar to the switch regulator 100a in FIG. 3, the switch regulator 100b in FIG. 5 can include a power switch 101, a parasitic capacitor Cpar, an inductor L, a resistor DCR, and an output capacitor Cout, and the load device LOAD can be connected to the output terminal OUT of the switch regulator 100b. Different from the switch regulator 100a in FIG. 3, the switch regulator 100b in FIG. 5 can include a controller 110b instead of the controller 110a. Hereinafter, the material differences between the switch regulator 100a in FIG. 3 and the switch regulator 100b in FIG. 5 will be described in some additional details.

[0065] The controller 110b in FIG. 5 can include a PFM generator 111b, a gate driver 112, a zero current detector 113b, a feedback controller 114, and a spike current detector 115. Different from the PFM generator 111a in FIG. 3, the PFM generator 111b in FIG. 5 can generate a signal PFMb that controls the gate driver 112 in response to a spike current sensing signal PCS, a zero current sensing signal ZCS, a feedback signal FB, and a reference voltage VREF.

[0066] For example, the PFM generator 111b may receive a zero current sensing signal ZCS from the zero current detector 113b. The PFM generator 111b may receive a feedback signal FB from the feedback controller 114. The PFM generator 111b may receive a peak current sensing signal PCS from the peak current detector 115. The PFM generator 111b may compare the feedback signal FB with a reference voltage VREF. The PFM generator 111b may determine whether to increase the switching frequency of the power switch 101 based on the comparison result. The PFM generator 111b may output a PFM signal PFMb to the gate driver 112 based on the zero current sensing signal ZCS, the feedback signal FB, the peak current sensing signal PCS, and the comparison result. The switching (or switching frequency) of the power switch 101 may be controlled via the gate driver 112 depending on the PFM signal PFMb.

[0067] The gate driver 112 may generate a first control signal and a second control signal that respond to the signal PFMb output from the PFM generator 111b and control the switching of the power switch 101. The first control signal and the second control signal generated from the gate driver 112 may be provided as a control signal PRDV and a control signal NDRV to the gates of the transistor M1 and the transistor M2 via the inverter 112-1 and the inverter 112-2, respectively.

[0068] The zero current detector 113b may detect the magnitude of the inductor current IL flowing across the inductor L. For example, the zero current detector 113b may detect the magnitude of the inductor current IL based on the magnitude of the switching voltage VSW of the switch node NSW. The zero current detector 113b may include a comparator 113b-1 and an offset controller 113b-2.

[0069] The comparator 113b-1 may include a first input terminal connected to the switch node NSW, a second input terminal to which a ground voltage is applied, and an output terminal that outputs a zero current sensing signal ZCS. The comparator 113b-1 may receive an offset signal OFS from the offset controller 113b-2. The comparator 113b-1 may compare the switching voltage VSW with the ground voltage based on the offset signal OFS. By comparing the switching voltage VSW with the ground voltage, the comparator 113b-1 may determine whether the inductor current IL is lower than "0" by up to the magnitude of an offset current corresponding to the offset signal OFS (e.g., the offset current in FIG. 6). In response to the inductor current IL being lower than "0" by up to the magnitude of the offset signal OFS, the comparator 113b-1 may output a zero current sensing signal ZCS.

[0070] The offset controller 113b-2 can provide an offset signal OFS to the comparator 113b-1 based on a control signal NDRV applied to the transistor M2 and the zero current sensing signal ZCS. The offset signal OFS can be a current signal. The magnitude of the offset current corresponding to the offset signal OFS (or the magnitude of the offset signal OFS when the offset signal OFS is a current signal) can be determined in consideration of the capacitance of the parasitic capacitor Cpar, the input power supply voltage VIN, the duration of the dead time, etc. in advance. A method for determining the magnitude of the offset current corresponding to the offset signal OFS will be described in some additional details below.

[0071] The feedback controller 114 can output a feedback signal FB to the PFM generator 111b based on the magnitude of the output power supply voltage VOUT using the method described with respect to FIG. 3.

[0072] Different from the switching regulator 100a of FIG. 3, the switching regulator 100b of FIG. 5 can further include a spike current detector 115. The spike current detector 115 can be connected to the power switch 101. For example, the spike current detector 115 can be connected to the first terminal of the transistor M1 of the power switch 101. The spike current detector 115 can sense the magnitude of the inductor current IL provided from the input terminal IN to the switch node NSW via the transistor M1. The spike current detector 115 can sense that the magnitude of the inductor current IL is the same (or approximate) as the spike current (e.g., the spike current Ipeak of FIGS. 4 and 6). If the magnitude of the inductor current IL is the same (or approximate) as the spike current Ipeak, the spike current detector 115 can output a spike current sensing signal PCS to the PFM generator 111b.

[0073] FIG. 6 is a timing diagram showing the operation of the switching regulator 100b of FIG. 5. The changes in the inductor current IL, the switch voltage VSW, the control signal PDRV, and the control signal NDRV depend on the operation of the switching regulator 100b of FIG. 5.

[0074] Referring to FIGS. 1, 2, 5, and 6, at time t8, the magnitude of the inductor current IL can be approximately 0. When the transistor M1 turns on in response to the low control signal PDRV, the magnitude of the switch voltage VSW can be substantially the same as the magnitude of the input power supply voltage VIN. That is, the magnitude of the switch voltage VSW can be approximated to the magnitude of the input power supply voltage VIN. (Here, it is assumed that the parasitic capacitor Cpar has been fully charged by the input power supply voltage VIN before time t8). Thereafter, the inductor current IL flowing through the inductor L can increase in response to the switch voltage VSW.

[0075] At time t9, the magnitude of the inductor current IL can be the same as the peak current Ipeak. The peak current detector 115 can detect the magnitude of the inductor current IL and can output a peak current detection signal PCS to the PFM generator 111b when the magnitude of the inductor current IL is the same as (or approximately the same as) the peak current Ipeak. The PFM generator 111b can generate a signal PFMb for turning off the power switch 101 and can apply the generated signal PFMb to the gate driver 112. The control signal PDRV provided by the gate driver 112 to the gate of the transistor M1 can transition from low to high in response to the signal PFMb.

[0076] The transistor M1 can turn off in response to the high control signal PDRV. Thereafter, the inductor current IL and the switch voltage VSW can decrease in response to the power consumption of the load device LOAD connected to the output terminal OUT of the switch regulator 100b. The power consumption of the load device LOAD can cause the switch voltage VSW to drop below the ground voltage.

[0077] Different from the embodiment shown in FIG. 4, in the embodiment shown in FIG. 6, the control signal NDRV can transition from low to high before the parasitic diode Dpar2 of the transistor M2 turns on due to the discharge of the parasitic capacitor Cpar. Therefore, the duration of the first dead time DT1b in FIG. 6 can be determined according to Equation 1 below: [Equation 1]

[0078] In Equation 1, can be the duration of the dead time DT1b, can be the capacitance of the parasitic capacitor Cpar, can be the magnitude of the input power supply voltage VIN, and can be the magnitude of the peak current Ipeak. Referring to Equation 1, the duration of the dead time DT1b can be the period for discharging the charge stored in the parasitic capacitor Cpar sufficiently. At the same time, the duration of the dead time DT1b This may be a period insufficient to turn on the parasitic diode Dpar2 of the transistor M2. That is, the first dead time DT1b may end before the parasitic diode Dpar2 of the transistor M2 is turned on. Therefore, after the charge associated with the parasitic capacitor Cpar is discharged and before the parasitic diode Dpar2 of the transistor M2 is turned on, the transistor M2 may be turned on. In this case, all the charge associated with the parasitic capacitor Cpar can be discharged and supplied to the output terminal OUT. Therefore, power loss due to the parasitic capacitor Cpar can be avoided, and power loss due to the conduction of the parasitic diode Dpar2 can also be avoided.

[0079] At time t10, the control signal NDRV provided by the gate driver 112 to the gate of the transistor M2 may transition from low to high. For example, the gate driver 112 may be operated to apply a high control signal NDRV to the gate of the transistor M2 after the first dead time DT1b after time t9. The transistor M2 may be turned on in response to the high control signal NDRV, and the ground voltage may be applied to the switch node NSW via the transistor M2. Therefore, the switch voltage VSW may increase to the ground voltage, and the inductor current IL may decrease. The rate at which the inductor current IL decreases may be proportional to the magnitude of the output supply voltage VOUT.

[0080] At time t11, the control signal NDRV may transition from high to low. For example, the zero current detector 113b may detect that the switch voltage VSW is the same (or approximately the same) as the ground voltage. In response to this detection result, the zero current detector 113b may detect that the inductor current IL has a negative direction (i.e., the inductor current IL flows from the output terminal OUT to the switch node NSW via the resistor DCR and the inductor L due to the charge stored in the output capacitor Cout), and the magnitude of the inductor current IL is the same (or approximately the same) as the offset current Iofs. In response to determining that the inductor current IL has a negative direction and simultaneously determining that the magnitude of the inductor current IL is the same (or approximately the same) as the offset current Iofs, the zero current detector 113b may output a zero current sense signal ZCS to the PFM generator 111b. The PFM generator 111b may generate a signal PFMb for switching the power switch 101 and may apply the generated signal PFMb to the gate driver 112. The control signal NDRV applied from the gate driver 112 to the gate of the transistor M2 may transition from high to low in response to the signal PFMb. Therefore, different from the embodiment shown in FIG. 4, in the embodiment shown in FIG. 6, the control signal NDRV may transition from high to low after the inductor current IL has a negative direction.

[0081] Transistor M2 can be turned off in response to a low control signal NDRV. Different from the embodiment shown in FIG. 4, in the embodiment shown in FIG. 6, due to the negative inductor current IL, the parasitic diode Dpar2 associated with transistor M2 may not conduct. At the same time, due to the negative inductor current IL, charge can be stored in the parasitic capacitor Cpar of the switching node NSW during the second dead time DT2b. Here, the duration of the second dead time DT2b in FIG. 6 can be determined according to Equation 2 below: [Equation 2]

[0082] In Equation 2, can be the duration of the second dead time DT2b, can be the capacitance of the parasitic capacitor Cpar, can be the magnitude of the input power supply voltage VIN, and can be the magnitude of the offset current Iofs. Referring to Equation 2, the duration of the second dead time DT2b can be sufficient to electrically charge the parasitic capacitor Cpar in response to the inductor current IL, such that the switching voltage VSW of the switching node NSW increases to approximately the input power supply voltage VIN.

[0083] During the second dead time DT2b, based on the charge stored in the output capacitor Cout, the inductor current IL can have a negative direction. That is, in response to the energy stored in the output capacitor Cout, the inductor current IL can flow from the output terminal OUT to the switching node NSW. Therefore, when the duration of the second dead time DT2b is too long, since transistor M1 can conduct, the time required to charge the output capacitor Cout can become longer, thereby reducing the efficiency of the switching regulator 100b. In contrast, when the duration of the second dead time DT2b is too short, the parasitic capacitor Cpar may not be fully charged.

[0084] In some embodiments, in response to a pre-determined magnitude of the input power supply voltage VIN and the capacitance of the parasitic capacitor Cpar , the duration of the second dead time DT2b and the magnitude of the offset current Iofs . Based on these possible combinations, the duration of the second dead time DT2b and the magnitude of the offset current Iofs It can be determined through conventional experiments and / or simulation experiments.

[0085] At time t12, the control signal PDRV provided by the gate driver 112 to the gate of the transistor M1 can transition from high to low. For example, the gate driver 112 can be operated such that the low control signal PDRV is applied to the gate of the transistor M1 after a second dead time DT2b after time t11. The transistor M1 can turn on in response to the low control signal PDRV, and the input power supply voltage VIN can be applied to the switching node NSW through the transistor M1.

[0086] Different from the embodiment shown in FIG. 4, in the embodiment shown in FIG. 6, the parasitic capacitor Cpar can be charged during the second dead time DT2b, such that the switching voltage VSW of the switching node NSW is approximately equal to the input power supply voltage VIN. Therefore, the power loss due to the recharing of the parasitic capacitor Cpar when the transistor M1 turns on can be avoided.

[0087] At time t13, the magnitude of the inductor current IL can be the same (or approximate) as the peak current Ipeak. Consistent with the description regarding time t8, the control signal PDRV provided by the gate driver 112 to the gate of the transistor M1 can transition from low to high. The transistor M1 can turn off in response to the high control signal PDRV. Thereafter, the inductor current IL and the switching voltage VSW can decrease in response to the power consumption of the load device LOAD connected to the output terminal OUT of the switching regulator 100b. The power consumption of the load device LOAD can cause the switching voltage VSW to drop below the ground voltage.

[0088] Similar to the duration of the first dead time DT1b, the duration of the third dead time DT3b can be determined according to Equation 1. Therefore, similar to the first dead time DT1b, all the charges associated with the parasitic capacitor Cpar can be discharged during the third dead time DT3b, and at the same time, the parasitic diode Dpar2 of the transistor M2 can be prevented from turning on. Therefore, the power loss due to the power loss of the parasitic capacitor Cpar and the conduction of the parasitic diode Dpar2 can be avoided.

[0089] At time t14, the control signal NDRV provided by the gate driver 112 to the gate of the transistor M2 transitions from low to high. For example, the gate driver 112 can be operated to apply the high control signal NDRV to the gate of the transistor M2 after a third dead time DT3b after time t13. The transistor M2 can turn on in response to the high control signal NDRV, and the ground voltage can be applied to the switch node NSW via the transistor M2. Therefore, the switch voltage VSW can increase to the ground voltage, and the inductor current IL can decrease.

[0090] At time t15, the control signal NDRV provided by the gate driver 112 to the gate of the transistor M2 can transition from high to low. For example, in response to the feedback signal FB, the PFM generator 111b can determine that the output power voltage VOUT of the switching regulator 100b is the same (or approximately the same) as the target voltage. Based on the determination result, the power switch 101 can be controlled by the gate driver 112 to avoid further switching. For example, after time t15, the transistors M1 and M2 can remain in the off state. Therefore, the inductor current IL can decrease to a value of 0, and the switch voltage VSW can also temporarily converge. Thereafter, the power switch 101 can switch again when the output power voltage VOUT is lower than the target voltage.

[0091] In some embodiments, the switching regulator 100b of FIG. 5 can be understood to perform flexible switching. For example, when switching the power switch 101 (e.g., when the transistors M1 and M2 are turned on / off), the parasitic capacitor Cpar of the switch node NSW can be charged / discharged by the inductor current IL flowing through the inductor L rather than the current based on the input power voltage VIN.

[0092] FIG. 7 is a graph showing the power efficiency varying with the load current ILOAD for each of the switching regulator 100a of FIG. 3 and the switching regulator 100b of FIG. 5. Here, the power efficiency can be understood as the ratio of the input power voltage supplied to each of the switching regulator 100a and the switching regulator 100b to the output power voltage provided by each of the switching regulator 100a and the switching regulator 100b, respectively.

[0093] As the magnitude of the load current ILOAD increases, the amount of power required by the load device LOAD also increases. For the purpose of increasing the magnitude of the load current ILOAD, the power switch 101 can perform switching operations at a higher frequency.

[0094] As described above, in the switching regulator 100a, when the transistors M1 and M2 of the power switch 101 are turned off and then turned on again, power losses may occur due to the discharge and recharge of the parasitic capacitor Cpar and due to the conduction of the parasitic diode Dpar2. Therefore, as shown in FIG. 7, as the magnitude of the load current ILOAD increases, the switching frequency of the power switch 101 may increase, thereby causing a decrease in the power efficiency of the switching regulator 100a. In contrast, in the switching regulator 100b, since power losses due to the discharge and recharge of the parasitic capacitor Cpar and the conduction of the parasitic diode Dpar2 are avoided when performing the switching of the power switch 101, the power efficiency of the switching regulator 100b may not decrease despite the increase in the magnitude of the load current ILOAD.

[0095] FIG. 8 is a block diagram showing a system 20 according to an embodiment of the concept of the present invention. Referring to FIG. 8, the system 20 may include a power supply 21 and a PMIC 22, as well as any number (e.g., 4) and types of functional blocks (e.g., 23-1, 23-2, 23-3, and 23-4).

[0096] The power supply 21 may supply an input power supply voltage to the PMIC 22 in response to an externally provided voltage VEXT. The PMIC 22 may supply one or more output power supply voltages to each of the functional blocks 23-1, functional block 23-2, functional block 23-3, and functional block 23-4 in response to the input power supply voltage received from the power supply 21. In some embodiments, the system 20 may include a battery, and the externally provided voltage VEXT supplied to the power supply 21 may be a battery supply voltage. Alternatively, in some embodiments, the system 20 may be powered from a power line, and the externally provided voltage VEXT may be a voltage generated by the power supply via the power line. For example, the externally provided voltage VEXT may be the voltage of the power line, or may be a DC voltage generated by rectifying an AC voltage supplied from a power line.

[0097] The PMIC 22 may include the switching regulator 100b of FIG. 5. Therefore, the PMIC 22 may use the switching regulator 100b to convert the input power supply voltage received from the power supply 21, and may supply the converted voltage to at least one of the functional blocks 23-1, functional block 23-2, functional block 23-3, and functional block 23-4.

[0098] Each of functional blocks 23-1, 23-2, 23-3, and 23-4 may operate in response to power supplied from PMIC 22. For example, one of functional blocks 23-1, 23-2, 23-3, and 23-4 may be a digital circuit that processes digital signals, such as an application processor (AP), an analog circuit that processes analog signals, such as an amplifier, or a circuit that processes mixed signals, such as an analog-to-digital converter (ADC).

[0099] FIG. 9 is a block diagram showing an electronic device 1000 according to an embodiment of the inventive concept. Referring to FIG. 9, the electronic device 1000 may include an image processing unit 1100, a wireless transceiver unit 1200, an audio processing unit 1300, a battery 1400, a non-volatile memory device 1500, a user interface 1600, and a controller 1700. The electronic device 1000 may operate under the control of the controller 1700.

[0100] The image processing unit 1100 may include a lens 1110, an image sensor 1120, an image processor 1130, and a display unit 1140. The image processor 1130 may convert a real image into image data via the lens 1110 and the image sensor 1120. The display unit 1140 may display an image data signal generated by the image processor 1130 or image data to be provided to the user. The display unit 1140 may be implemented by a liquid crystal display (LCD) or organic light emitting diodes (OLED). In the case where the LCD or OLED is implemented in a touch screen manner, the display unit 1140 may operate together with the user interface 1600.

[0101] The wireless transceiver unit 1200 includes an antenna 1210, a transceiver 1220, and a modulator / demodulator (modem) 1230. The wireless transceiver unit 1200 may perform a wireless communication function. The transceiver 1220 may adjust the frequency of a signal to be transmitted via the antenna 1210 or may amplify the signal to be transmitted; the transceiver 1220 may adjust the frequency of a signal received via the antenna 1210 or amplify the received signal. The modem 1230 may include a transmitter that encodes and modulates a signal to be transmitted, and a receiver that decodes and demodulates a signal received via the antenna 1210.

[0102] The audio processing unit 1300 includes an audio processor 1310, a microphone 1320, and a speaker 1330. The audio processing unit 1300 can constitute an encoder / decoder, and the encoder / decoder can include a data encoder / decoder and an audio encoder / decoder. The data encoder / decoder can process packet data, and the audio encoder / decoder can process audio signals such as voice and multimedia files. Similarly, the audio processing unit 1300 can perform the function of converting a digital audio signal received via the modem 1230 into an analog signal via the audio encoder / decoder and reproducing the analog signal or converting an analog audio signal generated by the microphone 1320 into a digital audio signal for transmission to the modem 1230. The encoder / decoder can be provided separately or can be included in the controller 1700.

[0103] According to an embodiment of the inventive concept, the non-volatile memory device 1500 can be implemented by a memory card (e.g., a multimedia card (MMC), an embedded MMC (eMMC), a secure digital (SD) card, or a micro SD card) and the like. In addition, the controller 1700 can be provided as a system-on-chip (SOC) that drives application programs, operating systems, etc. The controller 1700 can include a PMIC 1710. The PMIC 1710 can supply voltage from the battery 1400 and can convert the level of the supplied voltage. The PMIC 1710 can include the switching regulator 100b of FIG. 6.

[0104] The switching regulator according to an embodiment of the inventive concept can include a power switch that provides a switching voltage to a switching node in response to an input power supply voltage and a ground voltage. When switching the power switch, the charge stored in a parasitic capacitor can be at least partially used to perform the switching in order to prevent the parasitic diode associated with the power switch from turning on. Accordingly, a switching regulator exhibiting reduced switching loss and better power efficiency can be provided.

[0105] Although the inventive concept has been described with reference to embodiments of the inventive concept, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the inventive concept as set forth in the following claims.

[0106] 10, 1000: Electronic device 11: Central processing unit 12: Memory 13, 22, 1710: Power management integrated circuit 14: User interface 15: Storage device 16: Communication device 20: System 21: Power supply 23-1, 23-2, 23-3, 23-4: Functional block 100, 100a, 100b: Switching regulator 101: Power switch 110, 110a, 110b: Controller 111a, 111b: PFM generator 112: Gate driver 112-1, 112-2: Inverter 113a: Inductor current detector 113b: Zero current detector 113b-1: Comparator 113b-2: Offset controller 114: Feedback controller 115: Spike current detector 1100: Image processing unit 1110: Lens 1120: Image sensor 1130: Image processor 1140: Display unit 1200: Wireless transceiver 1210: Antenna 1220: Transceiver 1230: Modem 1300: Audio processing unit 1310: Audio processor 1320: Microphone 1330: Speaker 1400: Battery 1500: Non-volatile memory device 1600: User interface 1700: Controller 1710: Power management integrated circuit Cout: Output capacitor Cpar: Parasitic capacitor CS: Current sensing signal DCR: Resistor Dpar1, Dpar2: Parasitic diode DT1a, DT1b: First dead time DT2a, DT2b: Second dwell time DT3a, DT3b: Third dwell time FB: Feedback signal IL: Inductor current ILOAD: Load current IN: Input terminal Iofs: Offset current Ipeak: Peak current L: Inductor LOAD: Load device M1, M2: Transistors NDRV, PDRV: Control signals NSW: Switching node OFS: Offset signal OUT: Output terminal PCS: Peak current sensing signal PFMa, PFMb: Signals t0, t1, t2, t3, t4, t5, t6, t7, t8, t9, t10, t11, t12, t13, t14, t15: Time VEXT: External voltage VIN: Input power supply voltage VOUT: Output power supply voltage VREF: Reference voltage VSW: Switching voltage ZCS: Zero current sensing signal

Claims

1. A switching regulator, comprising: Inductor, connected to the switching node; A power switch, connected to the switching node and configured to apply a first voltage to the switching node in response to a first control signal, and to apply a second voltage to the switching node in response to a second control signal; A zero-current detector is configured to provide a zero-current sensing signal when the inductor current flowing through the inductor is an offset current; a controller is configured to generate the first control signal and the second control signal based on a pulse frequency modulation signal and to control the first duration of the first pause time and the second duration of the second pause time; a spike current sensor is configured to provide a spike current sensing signal when the inductor current reaches a spike current; a pulse frequency modulation generator is configured to output a pulse frequency modulation signal to the controller based on the spike current sensing signal, the zero-current sensing signal, and a reference voltage; The zero-current detector includes: a comparator configured to compare the switching voltage of the switching node with the ground voltage based on an offset signal and provide the zero-current sensing signal; And an offset controller, configured to output the offset signal to the comparator based on the zero-current sensing signal and the second control signal; wherein the magnitude of the offset current is based on the offset signal, wherein the second control signal transitions from low to high after a first pause time following the transition of the first control signal from low to high, and the first control signal transitions from high to low after a second pause time following the transition of the second control signal from high to low, and the inductor current flows in a first direction during the first pause time and in a second direction different from the first direction during the second pause time.

2. The switching regulator as claimed in claim 1, wherein the first control signal transitions from low to high when the inductor current reaches the peak current, and the first duration of the first pause time is based on the capacitance of the parasitic capacitor associated with the switching node, the magnitude of the first voltage, and the magnitude of the peak current.

3. The switching regulator as claimed in claim 1, wherein the power switch comprises: The first transistor includes a first terminal for receiving the first voltage, a gate for receiving the first control signal, and a second terminal connected to the switching node. And a second transistor, including a first terminal connected to the switching node, a gate for receiving the second control signal, and a second terminal for receiving the second voltage, wherein the controller is configured to control the first duration of the first pause time such that the first pause time ends before the parasitic diode associated with the second transistor is turned on.

4. The switching regulator as claimed in claim 1, wherein the second control signal transitions from high to low when the inductor current is the offset current, and the second duration of the second pause time is based on the capacitance of the parasitic capacitor associated with the switching node, the magnitude of the first voltage, and the magnitude of the offset current.

5. The switching regulator as claimed in claim 1, wherein after the second pause time following the transition of the second control signal from high to low, the magnitude of the voltage at the switching node is the same as the magnitude of the first voltage.

6. The switching regulator as described in claim 1, further comprising: The output capacitor is charged in response to the inductor current, wherein, during the second pause time, the inductor current flows from the output capacitor to the parasitic capacitor associated with the switching node via the inductor and the switching node.

7. A switching regulator that converts an input power supply voltage into an output power supply voltage, the switching regulator comprising: An inductor connected to a switching node; a power switch including a first transistor that applies the input power supply voltage to the switching node in response to a first control signal, and a second transistor that applies a ground voltage to the switching node in response to a second control signal; and a spike current sensor configured to provide a spike current sensing signal when the inductor current flowing through the inductor reaches a spike current. A zero-current detector is configured to provide a zero-current sensing signal when the inductor current is an offset current. A feedback controller, configured to compare the output power supply voltage with a target voltage and provide a corresponding feedback signal; a pulse frequency modulation generator, configured to provide a pulse frequency modulation signal based on the peak current sensing signal, the zero current sensing signal, the feedback signal, and a reference voltage; and a gate driver, configured to provide the first control signal and the second control signal based on the pulse frequency modulation signal, wherein the first transistor and the second transistor are off during a first pause time after the inductor current reaches the peak current, and the first transistor and the second transistor are off during a second pause time after the inductor current reaches the offset current, and the directions of the peak current and the offset current are opposite to each other, wherein the zero current detector includes: a comparator, configured to compare the switching voltage of the switching node with the ground voltage based on the offset signal and provide the zero current sensing signal; And an offset controller, configured to output the offset signal to the comparator based on the zero current sensing signal and the second control signal; wherein the magnitude of the offset current is based on the offset signal.

8. The switching regulator as claimed in claim 7, wherein the first duration of the first pause time corresponds to the ratio of the product of the capacitance of the parasitic capacitor associated with the switching node and the magnitude of the input power supply voltage to the magnitude of the spike current.

9. The switching regulator as claimed in claim 7, wherein during the first stagnation time, the inductor current flows to the inductor via the switching node.

10. The switching regulator as claimed in claim 7, wherein the first stagnation time ends before the parasitic diode associated with the second transistor is turned on.

11. The switching regulator as claimed in claim 7, wherein the second duration of the second pause time corresponds to the ratio of the product of the capacitance of the parasitic capacitor associated with the switching node and the magnitude of the input power supply voltage to the magnitude of the offset current.

12. The switching regulator as claimed in claim 7, wherein after the second pause time following the inductor current reaching the offset current, the magnitude of the voltage at the switching node is the same as the magnitude of the input power supply voltage.

13. A power management integrated circuit, comprising: A switching regulator configured to convert an input power supply voltage into an output power supply voltage, wherein the switching regulator includes: an inductor connected to a switching node; and a power switch connected to the switching node and configured to apply a first voltage to the switching node in response to a first control signal and to apply a second voltage to the switching node in response to a second control signal. and a controller configured to generate the first control signal and the second control signal based on a pulse frequency modulation signal and configured to control the first duration of the first pause time and the second duration of the second pause time; and a spike current sensor configured to provide a spike current sensing signal when the inductor current reaches a spike current. A zero-current detector, configured to provide a zero-current sensing signal when the inductor current flowing through the inductor is an offset current; a feedback controller, configured to compare the output power supply voltage with a target voltage and provide a feedback signal based on the comparison result of the output power supply voltage and the target voltage; and a pulse frequency modulation generator, configured to output a pulse frequency modulation signal to the controller based on the spike current sensing signal, the zero-current sensing signal, the feedback signal, and a reference voltage; wherein after a first pause time following a transition from low to high of the first control signal, the second control signal transitions from low to high; after a second pause time following a transition from high to low of the second control signal, the first control signal transitions from high to low; and the inductor current flowing through the inductor flows in a first direction during the first pause time and in a second direction different from the first direction during the second pause time, wherein the zero-current detector includes: a comparator, configured to compare the switching voltage of the switching node with the ground voltage based on the offset signal and provide the zero-current sensing signal; And an offset controller, configured to output the offset signal to the comparator based on the zero current sensing signal and the second control signal, wherein the magnitude of the offset current is based on the offset signal.

14. The power management integrated circuit of claim 13, wherein the first control signal transitions from low to high when the inductor current reaches a peak current, and the first duration of the first pause time corresponds to the ratio of the product of the capacitance of the parasitic capacitor associated with the switching node and the magnitude of the first voltage to the magnitude of the peak current.

15. The power management integrated circuit of claim 13, wherein the power switch comprises: a first transistor including a first terminal receiving the first voltage, a gate receiving the first control signal, and a second terminal connected to the switching node; and a second transistor including a first terminal connected to the switching node, a gate receiving the second control signal, and a second terminal receiving the second voltage, wherein the controller is configured to control the first duration of the first pause time such that the first pause time ends before the parasitic diode associated with the second transistor is turned on.

16. The power management integrated circuit of claim 13, wherein the second control signal transitions from high to low when the inductor current is the offset current, and the second duration of the second pause time corresponds to the ratio of the product of the capacitance of the parasitic capacitor associated with the switching node and the magnitude of the first voltage to the magnitude of the offset current.

17. The power management integrated circuit as claimed in claim 13, wherein after the second pause time following the transition of the second control signal from high to low, the magnitude of the voltage at the switching node is the same as the magnitude of the first voltage.

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