Semiconductor device

Abstract

The electric fuse element has a first portion, a second portion disposed at one end of the first portion, and a third portion disposed at the other end of the first portion. A resistor element is disposed separately from the electric fuse element. Each of the electric fuse element and the resistor element is made of silicon or nickel-chromium. The electric fuse element and the resistor element are disposed in an upper layer of the first wiring and a lower layer of the second wiring. The wiring width of the second portion and the wiring width of the third portion are greater than the wiring width of the first portion.

Description

[Technical Field]

[0001] [Cross-reference to related applications] The entire disclosure of Japanese Patent Application No. 2021-143192, filed on September 2, 2021, including the specification, drawings and abstract, is incorporated herein by reference. [Previous Technology]

[0002] This embodiment relates to a semiconductor device and a method for manufacturing the same.

[0003] The disclosed technologies are listed below.

[0004] [Patent File 1] Japanese Patent Application Publication No. 2011-155192. For example, Patent File 1 discloses a semiconductor device having a configuration in which the resistivity does not change even when subjected to stress. In Patent File 1, a metal resistor element layer is formed in the region between the passivation film and the uppermost aluminum wiring. Therefore, a high-precision resistor element with small resistance value fluctuations due to mold stress after the packaging process can be realized, and a high-precision analog circuit can be formed. [Summary of the Invention]

[0005] However, in semiconductor devices where various components are mixed, further stabilization and miniaturization of features are required.

[0006] Other objects and novel features will become apparent from the description and drawings in this specification.

[0007] According to one embodiment of a semiconductor device, a first metal film includes: a first portion, a second portion, and a third portion; the second portion is disposed on one end of the first portion; and the third portion is disposed on the other end of the first portion. The second metal film is disposed separately from the first metal film. The material of each of the first and second metal films includes silicon metal or nickel-chromium. The first and second metal films are disposed in an upper layer of a first wiring and a lower layer of a second wiring. At least a portion of the second portion and at least a portion of the third portion each have a wiring width greater than the wiring width of the first portion.

[0008] In semiconductor devices according to other embodiments, the materials of the electric fuse element that can become the target of fuse removal when a redundant circuit portion is used to replace a specific circuit portion include silicon metal film or nickel-chromium.

[0009] A method of manufacturing a semiconductor device according to one embodiment includes the following steps: forming a first wiring; forming a first metal film in an upper layer of the first wiring, the first metal film having a first portion, a second portion, and a third portion, the second portion being disposed at one end of the first portion and the third portion being disposed at the other end of the first portion; forming a second metal film in an upper layer of the first wiring, the second metal film being separate from the first metal film; forming a second wiring in an upper layer of the first metal film and the second metal film; each of the first metal film and the second metal film being made of silicon metal or nickel-chromium; the first metal film being formed such that at least a portion of the second portion and at least a portion of the third portion each have a wiring width greater than the wiring width of the first portion; the first metal film and the second metal film being formed simultaneously.

[0010] According to the above embodiments, a semiconductor device and its manufacturing method that have stable characteristics and are suitable for miniaturization can be realized.

Implementation Method

[0024] In the following, embodiments of this disclosure will be described in detail with reference to the accompanying drawings. In the specification and drawings, identical or corresponding elements are denoted by the same reference numerals, and repeated descriptions will not be repeated. In the drawings, configuration or manufacturing methods may be omitted or simplified for ease of explanation. Moreover, at least some embodiments and each modified example can be arbitrarily combined with each other.

[0025] The semiconductor device described in the embodiments below is not limited to a semiconductor wafer, but can be a semiconductor wafer before it is divided into semiconductor wafers, or a semiconductor package in which the semiconductor wafer is sealed with resin. Furthermore, the plan views in this specification refer to a viewpoint viewed from a direction perpendicular to the surface of the semiconductor substrate. Configuration of the semiconductor device in wafer state

[0026] First, the configuration in the wafer state will be described with reference to FIG1 as the configuration of the semiconductor device in this embodiment.

[0027] As shown in FIG1, the semiconductor device SC in this embodiment is, for example, a microcomputer. The semiconductor device SC is, for example, in a wafer state and has a semiconductor substrate. Electrical components are arranged on and above the semiconductor substrate. The semiconductor device SC includes, for example, a RAM (Random Access Memory) region RA, a redundant circuit region RB, a power supply circuit region RC, a CPU (Central Processing Unit) region RD, and a peripheral circuit region RE. The power supply circuit region RC has, for example, an oscillation circuit region RF. The semiconductor device SC has a plurality of pad electrodes PD. Each of the plurality of pad electrodes PD is electrically connected to an electrical component arranged in the semiconductor device SC.

[0028] An oscillation circuit is arranged in the oscillation circuit region RF. For example, the oscillation circuit generates an output signal with a predetermined oscillation period through the oscillation operation of the repeated charging and discharging of the capacitor element. The oscillation circuit is, for example, a HOCO (high-speed on-chip oscillator) circuit, but it can also be a LOCO (low-speed on-chip oscillator) circuit, and may include both HOCO and LOCO circuits.

[0029] The oscillation circuit has a constant current circuit for outputting a signal with a constant voltage level, and this constant current circuit includes a resistive element. The oscillation circuit has a differential amplifier circuit, which also includes a resistive element. The resistive element is also included in other circuits.

[0030] A spare redundant circuit section is arranged in the redundant circuit area RB. The spare redundant circuit section has the same function as a specific circuit section with a predetermined function. An electric fuse is provided to be melted and removed in order to replace the specific circuit section in the redundant circuit section. Configuration and function of the redundant circuit section and the electric fuse.

[0031] Next, the configuration and function of the redundant circuit section and the electric fuse will be described with reference to Figures 2 and 3.

[0032] As shown in Figure 2, multiple blocks (specific circuit portions) N1, N2, ..., Nm are arranged in the semiconductor device SC. Each of the multiple blocks N1, N2, ..., Nm has the same function. Each of the multiple blocks N1, N2, ..., Nm is configured, for example, by multiple memory cells in the RAM region RA (Figure 1).

[0033] Fuse H1, H2, ..., Hm are formed to deactivate each of the multiple blocks N1, N2, ..., Nm. A spare redundant block RED with the same function is arranged so as to be able to replace any of the unactivated blocks N1, N2, ..., Nm. The redundant block RED is arranged in the redundant circuit region RB shown in Figure 1.

[0034] The potential of the ground power supply GD is applied to the gate electrode of the MOS (metal-oxide-semiconductor) transistor TR via the fuse Hs. Therefore, the MOS transistor TR is kept in a non-conducting state. Thus, the redundant block RED is electrically disconnected in the semiconductor device SC.

[0035] In addition, the test pad electrodes PDa and PDb are arranged to detect defects in each of the multiple blocks N1, N2, ..., Nm.

[0036] Next, the functional testing of the semiconductor device configured as described above will be described. Here, the case where the fuse is melted and removed by energizing will be described.

[0037] First, an electrical signal from a functional test device (not shown, also referred to below as a tester) is applied via test pad electrodes PDa and PDb. If the semiconductor device SC is functioning correctly, the expected signal for the applied electrical signal is output from the test pad electrodes PDa and PDb. At this time, the tester determines whether the semiconductor device SC is good or defective based on the relationship between the electrical signal applied to the semiconductor device SC and the electrical signal output. If any of the blocks N1, N2, ..., Nm is determined to be defective, the defective block and the redundant block RED are replaced. This ensures that the semiconductor device SC meets the functions it should perform, thereby creating the possibility that the semiconductor device SC will become a good product.

[0038] The replacement of the defective block and the redundant block RED is performed as follows. For example, when a defect in block N1 is detected by the above functional test, fuses H1 and Hs are blown and removed by energizing. Due to the blown fuse H1, the defective block N1 is electrically separated in the semiconductor device SC.

[0039] On the other hand, through the blown fuse Hs, the voltage of the power supply PV is applied to the gate electrode of the MOS transistor TR via the resistor RR. This causes the MOS transistor TR to become on, and the defective block N1 is replaced by the redundant block RED.

[0040] Next, the melting and removal of an electric fuse element that is melted and removed by energizing will be described with reference to FIG3.

[0041] As shown in Figure 3, the electric fuse element EH is a fuse that is cut off by allowing current to flow rather than by irradiating a laser beam. A cutting transistor CT is provided as a switching element for directing current to the electric fuse element EH.

[0042] One end of the fuse element EH is electrically connected to the power supply voltage (Vdd). The other end of the fuse element EH is electrically connected to the drain D of the cutoff transistor CT. The source S of the cutoff transistor CT is connected to the ground potential (GND).

[0043] The level shifter LS is electrically connected to the gate G of the cutoff transistor CT. The level shifter LS inputs the signal used to turn the cutoff transistor CT on and off to the gate G of the cutoff transistor CT. The core part CO is electrically connected to the other end of the fuse element EH and each of the drains of the cutoff transistor CT.

[0044] If any of the blocks N1, N2, ..., Nm (Figure 2) is determined to be defective, the cutoff transistor CT is turned on by the level shifter LS. Therefore, current flows through the fuse element EH, which is then melted and removed. The core part CO is a determining circuit for determining the state of the fuse element EH, and if it is determined that the fuse element EH has been melted and removed, then the operation is performed based on the determination result. Configuration of resistor elements and fuse elements.

[0045] Next, the configuration of the resistor element and the fuse element included in the semiconductor device of this embodiment will be described with reference to FIGS. 4A to 8B. As described above, the resistor element is arranged, for example, in the oscillation circuit region RF in FIG. 1, but the resistor element is not limited thereto and may be arranged in another region.

[0046] As shown in Figures 4A and 4B, a first wiring FI is arranged on an interlayer dielectric layer (not shown). The first wiring FI is made of a conductor such as a metal (including alloys). The first wiring FI is made of, for example, aluminum (Al), copper (Cu), aluminum-copper (AlCu), etc. The first wiring FI is a wire that transmits electrical signals. However, the first wiring FI can be a dummy wiring. A dummy wiring is a wiring that is electrically isolated from other electrical components and does not transmit electrical signals.

[0047] As shown in FIG4A, an interlayer dielectric layer I1 is arranged to cover the first wiring FI. The upper surface of the interlayer dielectric layer I1 is planarized. A via Va1 is disposed in the interlayer dielectric layer I1. The via Va1 extends from the upper surface of the interlayer dielectric layer I1 to the first wiring FI. A via conductive layer Vca1 is embedded in the via Va1. The via conductive layer Vca1 is made of, for example, tungsten (W).

[0048] The resistor element RS (second metal film) is disposed on the upper surface of the interlayer dielectric layer I1. The resistor element RS is made of metal (including alloys), such as silicon metal, nickel-chromium (NiCr), etc. Silicon metal is, for example, silicon-chromium (SiCr) or carbon-doped silicon-chromium (SiCrC).

[0049] Each of the resistor element RS at one end and the other end is electrically connected to the first wiring FI via the via conductive layer Vca1. Specifically, one end of the resistor element RS is electrically connected to the first wiring FI1 via the via conductive layer Vca1, and the other end of the resistor element RS is electrically connected to the first wiring FI4 via the via conductive layer Vca1.

[0050] An interlayer dielectric layer I2 is arranged to cover a resistor element RS. The upper surface of the interlayer dielectric layer I2 is planarized. A via V2 is provided to access the first wiring FI from the upper surface of the interlayer dielectric layer I2 through the interlayer dielectric layers I2 and I1. A via conductive layer Vc2 is embedded in the via V2. The via conductive layer Vc2 is made of, for example, tungsten.

[0051] The second wiring SI is disposed on the upper surface of the interlayer dielectric layer I2. The second wiring SI is made of a conductor, such as a metal (including alloys). The second wiring SI is made of, for example, aluminum, copper, aluminum-copper, etc. The second wiring SI is a wire for transmitting electrical signals. However, the second wiring SI may be a dummy wiring that is electrically isolated from other electrical components and does not transmit electrical signals.

[0052] One of the plurality of second wirings SI is electrically connected to the first wiring FI via a via conductive layer Vc2. Specifically, the second wiring SI1 is electrically connected to the first wiring FI4 via the via conductive layer Vc2. An interlayer dielectric layer I3 is arranged to cover the second wiring SI. The upper surface of the interlayer dielectric layer I3 is planarized.

[0053] As shown in Figure 4B, a via Vb1 is disposed in the interlayer dielectric layer I1. The via Vb1 extends from the upper surface of the interlayer dielectric layer I1 to the first wiring FI. A via conductive layer Vcb1 is embedded in the via Vb1. The via conductive layer Vcb1 is made of, for example, tungsten.

[0054] An electric fuse element EH (first metal film) is disposed on the upper surface of the interlayer dielectric layer I1. The electric fuse element EH is made of, for example, a metal (including alloys), and is made of, for example, silicon metal, nickel-chromium, etc. The silicon metal is, for example, silicon-chromium or silicon-chromium in which carbon is introduced.

[0055] Each of one end and the other end of the electric fuse element EH is electrically connected to the first wiring FI via the via conductive layer Vcb1. Specifically, one end of the electric fuse element EH is electrically connected to the first wiring FI6 via the via conductive layer, and the other end of the electric fuse element EH is electrically connected to the first wiring FI7 via the via conductive layer Vcb1.

[0056] An interlayer dielectric layer I2 is arranged to cover the fuse element EH. The upper surface of the interlayer dielectric layer I2 is planarized. A second wiring SI can be arranged on the upper surface of the interlayer dielectric layer I2. However, preferably, the second wiring SI is not arranged in the area directly above the fuse element EH. This is because if the fuse element EH is blown and removed, the second wiring SI located directly above the fuse element EH may be damaged due to the blown and removed. An interlayer dielectric layer I3 is arranged on the interlayer dielectric layer I2. As described above, the upper surface of the interlayer dielectric layer I3 is planarized.

[0057] As shown in Figures 4A and 4B, each of the resistor element RS and the fuse element EH is arranged in the upper layer of the first wiring FI and the lower layer of the second wiring SI. The resistor element RS and the fuse element EH are arranged in the same layer and have the same composition.

[0058] As shown in Figure 5A, the resistor element RS may include, for example, multiple resistor portions RSa, RSb, RSc, and RSd (multiple metal portions). Each of the multiple resistor portions RSa to RSd is made of, for example, a metal (including alloys), and is made of, for example, silicon metal, nickel-chromium, etc. Silicon metal is, for example, silicon-chromium or silicon-chromium in which carbon has been introduced. The resistor element RS is not limited to four resistor portions RSa to RSd, and may have two, three, five, or more resistor portions.

[0059] Multiple resistor sections RSa to RSd can be connected in series. In this case, the multiple resistor sections RSa to RSd are connected in the order of resistor section RSa, resistor section RSb, resistor section RSc, and resistor section RSd.

[0060] Specifically, one end of resistor portion RSa in the longitudinal direction is electrically connected to one end of resistor portion RSb in the longitudinal direction via a first wiring FI1. The other end of resistor portion RSb in the longitudinal direction is electrically connected to one end of resistor portion RSc in the longitudinal direction via a first wiring FI2. The other end of resistor portion RSc in the longitudinal direction is electrically connected to one end of resistor portion RSd in the longitudinal direction via a first wiring FI3.

[0061] Preferably, the resistor element RS is arranged to be bent in a plan view. The longitudinal direction of each of the plurality of resistor portions RSa to RSd is, for example, along the same direction and parallel to each other. In this arrangement, the resistor element RS is configured to be bent in a plan view by electrically connecting the ends of the resistor portions that are adjacent to each other in the longitudinal direction via the aforementioned first wiring FI1 to FI3.

[0062] If the resistor element RS is bent in the plan view, the longitudinal direction of each of the multiple resistor sections RSa to RSd may not be along the same direction as each other.

[0063] In the plan view, the other end of the resistor portion RSa in the longitudinal direction is electrically connected to the second wiring SI1 via the first wiring FI4. And in the plan view, the other end of the resistor portion RSd in the longitudinal direction is electrically connected to the second wiring SI2 via the first wiring FI5.

[0064] As shown in Figure 5B, the fuse element EH and the resistor element RS are arranged separately. The fuse element EH has a first part P1, a second part P2, and a third part P3. The second part P2 is arranged at one end of the first part P1. The third part P3 is arranged at the other end of the first part P1. The first part P1 is sandwiched between the second part P2 and the third part P3.

[0065] At least a portion of each of the second part P2 and the third part P3 has a wiring width W2, W3 that is greater than the wiring width W1 of the first part P1. In this embodiment, each of the maximum wiring widths W2 of the second part P2 and W3 of the third part P3 is greater than the wiring width W1 of the first part P1.

[0066] The second part P2 has a tapered portion TP2 and a pad portion PD2 in the plan view. The tapered portion TP2 is connected to the first part P1. The pad portion PD2 is connected to the tapered portion TP2. The tapered portion TP2 is arranged between the first part P1 and the pad portion PD2. The tapered portion TP2 is configured such that the wiring width gradually increases from the first part P1 toward the pad portion PD2 in the plan view. The pad portion PD2 has, for example, a rectangular shape in the plan view.

[0067] The third part P3 has a tapered portion TP3 and a pad portion PD3 in the plan view. The tapered portion TP3 is connected to the first part P1. The pad portion PD3 is connected to the tapered portion TP3. The tapered portion TP3 is arranged between the first part P1 and the pad portion PD3. The tapered portion TP3 is configured such that the wiring width gradually increases from the first part P1 toward the pad portion PD3 in the plan view. The pad portion PD3 has, for example, a rectangular shape in the plan view. The pad portions PD2 and PD3 can be directly connected to the first part P1 without the tapered portions TP2 and TP3.

[0068] Pad portion PD2 is electrically connected to the first wiring FI6 via via Vb1. Pad portion PD3 is electrically connected to the first wiring FI7 via via Vb1.

[0069] As shown in Figures 5A and 5B, the wiring width W1 of the first portion P1 in the fuse element EH is less than the wiring width WB of each of the plurality of resistor portions RSa to RSd. Preferably, the wiring width WB of the plurality of resistor portions RSa to RSd is the same, but they may also be different from each other.

[0070] As shown in Figures 4A and 4B, the wiring length LB of the fuse element EH is less than the wiring length LA of the resistor element RS. As shown in Figures 5A and 5B, when the resistor element RS is formed by multiple resistor sections RSa to RSd connected in series, the wiring length LB of the fuse element EH is less than the sum of the wiring lengths LA of the multiple resistor sections RSa to RSd.

[0071] In the plan view shown in Figure 6B, the area of ​​the overlapping region (shaded area in the figure) of the first wiring FI and the fuse element EH is smaller than the area of ​​the overlapping region (shaded area in the figure) of the first wiring FI and the resistor element RS in the plan view shown in Figure 6A. By reducing the area of ​​the first wiring FI8 overlapping with the fuse element EH in the plan view, the fuse element EH is less likely to be radiated and more likely to be melted.

[0072] Incidentally, as shown in Figure 6A, when there are multiple overlapping regions between the resistor element RS and the first wiring FI, the sum of the areas of the multiple overlapping regions is compared with the area of ​​the overlapping region between the first wiring FI and the fuse element EH. Similarly, when there are multiple overlapping regions between the first wiring FI and the fuse element EH, the sum of the areas of the multiple overlapping regions is compared with the area of ​​the overlapping region between the first wiring FI and the resistor element RS.

[0073] Further, in FIG6B, to illustrate the overlapping area between the fuse element EH and the first wiring FI, a configuration in which the first wiring FI8 is disposed below the fuse element EH is shown. However, in the area directly below the fuse element EH, the first wiring FI8 may not be disposed, as shown in FIG4B and 5B.

[0074] As shown in Figure 7, when the resistor element RS is formed by multiple resistor portions RSa to RSd, the multiple resistor portions RSa to RSd can be connected in parallel with each other. In this case, the longitudinal directions of each resistor portion among the multiple resistor portions RSa to RSd are parallel to each other, for example, along the same direction. In this arrangement, one end of the multiple resistor portions RSa to RSd is electrically connected to each other via a via V1 through a first wiring FI11. The other end of the multiple resistor portions RSa to RSd is electrically connected to each other via a via V1 through another first wiring FI12. A second wiring SI11 is electrically connected to the first wiring FI11 via a via V2. A second wiring SI12 is electrically connected to the first wiring FI12 via a via V2.

[0075] If multiple resistor sections RSa to RSd are connected in parallel with each other, the longitudinal directions of the multiple resistor sections RSa to RSd may not be along the same direction.

[0076] As shown in Figures 8A and 8B, each of the resistor element RS and the fuse element EH can be electrically connected to the second wiring SI. In this case, the resistor element RS is electrically connected to the second wiring SI through a via conductive layer Vca3 embedded in a via Va3, which is disposed in the interlayer dielectric layer I2. The fuse element EH is electrically connected to the second wiring SI through a via conductive layer Vcb3 embedded in a via Vb3, which is disposed in the interlayer dielectric layer I2. Method for manufacturing a semiconductor device

[0077] Next, the method of manufacturing a semiconductor device according to this embodiment will be described with reference to FIG4A and 9A to 13B.

[0078] First, a semiconductor substrate (not shown) is prepared. An electrical component (not shown), such as a MOS transistor (not shown), is formed on the surface of the semiconductor substrate. An interlayer dielectric layer is formed on the surface of the semiconductor substrate to cover the electrical component formed on the surface of the semiconductor substrate. Wiring is formed on the interlayer dielectric layer. By repeatedly forming the interlayer dielectric layer and wiring, a multilayer wiring structure is formed.

[0079] As shown in Figures 9A and 9B, a first wiring FI is formed as a wiring in a multilayer wiring structure. The first wiring FI is formed, for example, by forming a metal (aluminum, copper, aluminum-copper, etc.) on an interlayer dielectric layer and patterning it using photolithography, etching, or other techniques.

[0080] As shown in Figures 10A and 10B, an interlayer dielectric layer I1 is formed to cover the first wiring FI. The interlayer dielectric layer I1 is made of silicon oxide (SiO2), for example. Subsequently, CMP (chemical mechanical polishing) is performed. As a result, the upper surface of the interlayer dielectric layer I1 is planarized.

[0081] Subsequently, vias Va1 and Vb1 are formed in the interlayer dielectric layer I1 by photolithography. Each via in Va1 and Vb1 is formed to extend from the upper surface of the interlayer dielectric layer I1 to the first wiring FI.

[0082] Subsequently, a conductive layer for embedding is formed on the upper surface of the interlayer dielectric layer I1 to embed each of the vias Va1 and Vb1. The conductive layer for embedding is, for example, tungsten. A barrier metal layer may be formed between the conductive layer for embedding and the interlayer dielectric layer. The barrier metal layer is, for example, titanium nitride (TiN).

[0083] Subsequently, CMP is performed on the upper surface of the conductive layer for embedding. Therefore, the upper surface of the interlayer dielectric layer I1 is exposed, and the conductive layer for embedding is retained inside each of the vias Va1 and Vb1. The via conductive layers Vca1 and Vcb1 are formed from the conductive layer for embedding retained inside each of the vias Va1 and Vb1.

[0084] As shown in Figures 11A and 11B, the metal layer SM is formed on the upper surface of the interlayer dielectric layer I1, for example, by sputtering. The metal layer SM is formed, for example, from metallic silicon (SiCr, SiCrC), nickel-chromium, etc.

[0085] As shown in Figures 12A and 12B, a photoresist (organic photosensitive film) PR is applied to a metal layer SM. The photoresist PR is patterned into a predetermined shape through exposure and development. The patterned photoresist PR is used as a mask to etch the metal layer SM.

[0086] The metal layer SM is patterned by this etching, and the resistor element RS and the fuse element EH from the metal layer SM are formed simultaneously. The resistor element RS and the fuse element EH are formed separately from each other. Therefore, the resistor element RS and the fuse element EH are arranged in the same layer and have the same composition.

[0087] Resistor element RS is formed to be electrically connected to the first wiring FI via a via conductive layer Vca1 embedded in via Va1. Fuse element EH is formed to be electrically connected to the first wiring FI via a via conductive layer Vcb1 embedded in via Vb1. Thereafter, photoresist PR is removed by ashing or the like.

[0088] As shown in Figures 13A and 13B, an interlayer dielectric layer I2 is then formed on the interlayer dielectric layer I1 to cover the resistor element RS and the fuse. The interlayer dielectric layer I2 is formed, for example, from silicon oxide. CMP is then performed on the upper surface of the interlayer dielectric layer I2. The upper surface of the interlayer dielectric layer I2 is then planarized.

[0089] Subsequently, via V2 is formed in the interlayer dielectric layers I1 and I2 using photolithography and etching techniques. Via V2 is formed to extend from the upper surface of the interlayer dielectric layer I2 to the first wiring FI.

[0090] Subsequently, due to the embedding of via V2, a conductive layer for embedding is formed on the upper surface of the interlayer dielectric layer I2. The conductive layer for embedding is, for example, tungsten. A barrier metal layer may be formed between the conductive layer for embedding and the interlayer dielectric layer. The barrier metal layer is, for example, titanium nitride.

[0091] Subsequently, CMP is performed on the upper surface of the conductive layer for embedding. Therefore, the upper surface of the interlayer dielectric layer I2 is exposed, while the conductive layer for embedding remains inside the via V2. The via conductive layer Vc2 is formed from the conductive layer for embedding retained within the via V2.

[0092] As shown in Figures 4A and 4B, as a wiring in a multilayer wiring structure, a second wiring SI is formed on the upper surface of the interlayer dielectric layer I2. The second wiring SI is formed by forming a metal (aluminum, copper, aluminum-copper, etc.) on the interlayer dielectric layer I2 and patterning it using photolithography, etching, or other techniques.

[0093] An interlayer dielectric layer I3 is formed to cover the second wiring SI. The interlayer dielectric layer I3 is formed, for example, from silicon oxide. Then, CMP is performed on the upper surface of the interlayer dielectric layer I3. Thus, the upper surface of the interlayer dielectric layer I3 is planarized.

[0094] As described above, the semiconductor device of this embodiment shown in Figures 4A and 4B is manufactured. Effects

[0095] In this embodiment, the metallic silicon (silicon-chromium) used as the material for the metal films EH and RS has a sheet resistance of 300 to 1300 Ω / sq. and a melting point of 1306°C. The nickel-chromium used as the material for the metal films EH and RS has a sheet resistance of 5 to 200 Ω / sq. and a melting point of 1400°C. On the other hand, polycrystalline silicon has a sheet resistance of 360 Ω / sq. and a melting point of 1414°C. Due to these characteristics, silicon metal (silicon-chromium) and nickel-chromium can be melted using a cutting current smaller than that used for polycrystalline silicon.

[0096] According to this embodiment, as shown in FIG5B, each of the second portion P2 and the third portion P3 of the metal film EH has a width wider than the first portion P1. Therefore, the metal film EH can be used, for example, as an electric fuse element EH. As described above, silicon or nickel-chromium metal can be melted with a lower cutting current than polycrystalline silicon. Therefore, by using the metal film EH as an electric fuse element EH, for example, the cutting transistor CT (FIG. 3) can be miniaturized. Therefore, the semiconductor device SC of this embodiment is suitable for miniaturization.

[0097] As also shown in Figures 5A and 5B, the metal film RS is separated from the metal film EH. Therefore, the metal film RS can be used as a component other than the fuse element EH. Compared with polycrystalline silicon, metallic silicon or nickel-chromium has a lower temperature dependence of resistance. Therefore, for example, by using the metal film RS as a resistor element RS, characteristics such as resistance are stabilized.

[0098] Metallic silicon has a larger sheet resistance than polycrystalline silicon. Therefore, a large resistance can be obtained with a short wiring length, for example, by using a metal film RS as the resistor element RS, which allows for miniaturization.

[0099] Metal films EH and RS are arranged between the first wiring FI and the second wiring SI. During resin sealing, although stress acts on metal films EH and RS due to the difference in the coefficients of thermal expansion between the sealing resin and the semiconductor substrate, the first wiring FI and the second wiring SI act as buffers to relieve stress. Therefore, the stress caused by the difference in the coefficients of thermal expansion between the sealing resin and the semiconductor substrate during resin sealing is almost negligible on metal films RS and EH. For this reason, changes in the characteristics of the element formed by metal film RS and the element formed by metal film EH due to stress can be suppressed, thereby obtaining stable characteristics.

[0100] Therefore, it is possible to realize a semiconductor device with stable characteristics and suitable for miniaturization.

[0101] According to this embodiment, the metal film EH is an electric fuse element EH, and the metal film RS is a resistor element RS. Therefore, in the semiconductor device SC having the electric fuse element EH and the resistor element RS, stable characteristics and miniaturization can be achieved.

[0102] Further, according to this embodiment, as shown in FIG5A or FIG7, the resistor element RS has a plurality of resistor portions RSa to RSd, and the plurality of resistor portions RSa to RSd are connected in series or in parallel.

[0103] Further, according to this embodiment, as shown in FIG5A, multiple resistor portions RSa to RSd are connected in series, and the resistor element RS is arranged to be bent in the planar view. Therefore, a long resistor length can be ensured in a small planar area while reducing the wiring width.

[0104] Further, according to this embodiment, as shown in Figures 6A and 6B, in the plan view, the area overlapping the first wiring FI8 and the fuse element EH is smaller than the area overlapping the first wirings FI9 and FI10 and the resistor element RS. The fuse element EH is the part to be melted and removed. Therefore, by reducing the area of ​​the first wiring FI8 overlapping with the fuse element EH in the plan view, the fuse element EH is less likely to be radiated, and it is more likely to be melted.

[0105] Further, according to this embodiment, as shown in Figures 4A and 4B, the wiring length LB of the fuse element EH is less than the wiring length LA of the resistor element RS. This makes it easier to increase the wiring resistance of the resistor element RS. Additionally, it becomes easier to specify the portion to be melted and removed in the fuse element EH.

[0106] Further, according to this embodiment, as shown in Figures 5A and 5B, the wiring length W1 of the electric fuse element EH is less than the wiring length WB of the resistor element RS. This facilitates the removal of the electric fuse element EH after it has melted.

[0107] According to this embodiment, as shown in Figures 5A and 5B, the fuse element EH and the resistor element RS are arranged in the same layer and have the same composition. Therefore, the fuse element EH and the resistor element RS can be formed simultaneously from the same layer. Therefore, the manufacturing process can be simplified compared to the case where each of the fuse element EH and the resistor element RS is formed separately.

[0108] Although the present invention made by the inventors has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and needless to say, various modifications can be made without departing from its spirit. [Simplified Explanation of the Diagram]

[0011] FIG1 is a plan view showing the configuration of a semiconductor device in a wafer state according to one embodiment.

[0012] Figure 2 is a schematic plan view showing the configuration of a semiconductor wafer in which redundant circuitry is formed.

[0013] Figure 3 is a diagram showing the circuit configuration with an electric fuse.

[0014] Figure 4A is a cross-sectional view along line IVA-IVA of Figure 5A, and Figure 4B is a cross-sectional view along line IVB-IVB of Figure 5B.

[0015] Figure 5A is a plan view showing the configuration of the resistor elements, and Figure 5B is a plan view showing the configuration of the fuse elements.

[0016] Figure 6A is a plan view showing the configuration of the resistor elements, and Figure 6B is a plan view showing the configuration of the fuse elements, wherein the second wiring is omitted and the first wiring FI8 is added.

[0017] Figure 7 is a plan view showing the configuration in which the resistor elements are connected in parallel.

[0018] FIG8A is a cross-sectional view showing a configuration in which a resistor element is electrically connected to a second wiring, and FIG8B is a cross-sectional view showing a configuration in which an electric fuse element is electrically connected to a second wiring.

[0019] FIG9A is a cross-sectional view showing a first step in a method of manufacturing a semiconductor device including a resistor element according to an embodiment, and FIG9B is a cross-sectional view showing a first step in a method of manufacturing a semiconductor device including an electric fuse element according to an embodiment.

[0020] FIG10A is a cross-sectional view showing a second step in a method of manufacturing a semiconductor device including a resistor element according to an embodiment, and FIG10B is a cross-sectional view showing a second step in a method of manufacturing a semiconductor device including an electric fuse element according to an embodiment.

[0021] FIG11A is a cross-sectional view showing the third step in a method of manufacturing a semiconductor device including a resistor element according to an embodiment, and FIG11B is a cross-sectional view showing the third step in a method of manufacturing a semiconductor device including an electric fuse element according to an embodiment.

[0022] FIG12A is a cross-sectional view showing the fourth step in a method of manufacturing a semiconductor device including a resistor element according to an embodiment, and FIG12B is a cross-sectional view showing the fourth step in a method of manufacturing a semiconductor device including an electric fuse element according to an embodiment.

[0023] FIG13A is a cross-sectional view showing the fifth step in a method of manufacturing a semiconductor device including a resistor element according to an embodiment, and FIG13B is a cross-sectional view showing the fifth step in a method of manufacturing a semiconductor device including an electric fuse element according to an embodiment.

Claims

1. A semiconductor device, comprising: First wiring; Second wiring; Third wiring; A first metal film has a first part, a second part and a third part, the second part being disposed on one end of the first part and the third part being disposed on the other end of the first part; A second metal film is arranged separately from the first metal film; a fourth wiring is electrically connected to the second portion of the first metal film via a first via conductive layer; a fifth wiring is electrically connected to the third portion of the first metal film via a second via conductive layer; and a sixth wiring is electrically connected to one end of the second metal film via a third via conductive layer. And a seventh wiring, electrically connected to the other end of the second metal film via a fourth via conductive layer, wherein the material of each of the first and second metal films includes silicon metal or nickel-chromium, wherein the first and second metal films are disposed above the first wiring and above the third wiring and below the second wiring, and wherein at least a portion of the second portion and at least a portion of the third portion each have a wiring width greater than the wiring width of the first portion, the first wiring overlaps with the first metal film, the third wiring overlaps with the second metal film, and in a plan view, the area of ​​overlap between the first wiring and the first metal film is smaller than the area of ​​overlap between the third wiring and the second metal film.

2. The semiconductor device as claimed in claim 1, wherein the first metal film is a fuse element and the second metal film is a resistor element.

3. The semiconductor device as claimed in claim 2, wherein the resistor element has a plurality of resistor portions, and wherein the plurality of resistor portions are connected in series or in parallel.

4. The semiconductor device as claimed in claim 3, wherein the plurality of resistor portions are connected in series and arranged such that the resistor elements are bent in a plan view.

5. The semiconductor device of claim 1, wherein the wiring length of the first metal film is less than the wiring length of the second metal film.

6. The semiconductor device of claim 1, wherein the wiring width of the first metal film is smaller than the wiring width of the second metal film.

7. The semiconductor device of claim 1, wherein the first metal film and the second metal film are disposed in the same layer and have the same composition.

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