Semiconductor integrated circuit and method for testing semiconductor integrated circuit

Abstract

A semiconductor integrated circuit for receiving test scan input, test clock, and test mode signals and outputting a secure scan output signal, the integrated circuit comprising: a secure key circuit that generates a delayed input signal with a different delay from the test scan input and generates an input key signal by capturing the delayed input signal in response to the test clock; a key comparator that generates a verification result indicating whether the input key of the input key signal is the same as a preset reference key; a chip that generates a scan output signal based on the test scan input; a scan output remapper that obfuscates the scan output signal according to the verification result and outputs the obfuscated scan output signal as a secure scan output signal; and a secure scan controller for controlling the secure key circuit, the key comparator, the chip, and the remapper.

Description

Technical Field

[0001] The present inventive concept relates to an electronic device, and more particularly to a semiconductor integrated circuit, a method for testing the semiconductor integrated circuit, and a semiconductor system. [Cross-reference to Related Applications]

[0002] This application claims the priority of Korean Patent Application No. 10-2021-0128350, filed on September 28, 2021, and Korean Patent Application No. 10-2021-0178879, filed on December 14, 2021, with the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety. Background Art

[0003] Design For Test (DFT) techniques support the testing of complex integrated circuits (ICs) and system on chips (SOCs) because the DFT techniques provide simple and effective means for reading, changing, and accessing components inside the device. Access to these devices is provided via scan chains. However, after the product is sold / set up, this access during testing can lead to many security issues. For example, the same type of access can be used for malicious reasons, such as changing the product, manipulating the product, decompiling the product, or imitating or performing malicious actions.

[0004] A typical solution to prevent the use of the scan chain after testing is to ensure that the input key embedded in the test scan input signal provided from outside the device corresponds to a preset authentication key. Generally, in order to capture the test scan input signal provided from outside the device in response to a clock signal, flip-flops connected in series are used. However, when receiving the authentication key input using flip-flops connected in series, the flip-flops need to be further connected in series to increase security, which increases the complexity of the preset authentication key. This method not only increases the size of the chip, but also does not greatly contribute to further improving the security of the product. Summary of the Invention

[0005] Embodiments of the present inventive concept provide a semiconductor integrated circuit, a method for testing the semiconductor integrated circuit, and a semiconductor system that can further enhance the security of a product without adding components such as flip-flops.

[0006] According to an embodiment of the present invention concept, a semiconductor integrated circuit is provided. The semiconductor integrated circuit is configured to receive a test scan input signal, a test clock signal, and a test mode signal from the outside and output a secure scan output signal. The semiconductor integrated circuit includes: a security key circuit configured to generate a plurality of delayed input signals that are differently delayed from the test scan input signal based on the test scan input signal, and generate an input key signal by capturing the plurality of delayed input signals in response to the test clock signal; a key comparator configured to generate a verification result signal indicating whether an input key of the input key signal is the same as a preset reference key; a chip configured to generate a scan output signal based on the test scan input signal; a scan output remapper configured to scramble the scan output signal according to the verification result signal and output the scrambled scan output signal as the secure scan output signal; and a secure scan controller configured to control the security key circuit, the key comparator, the chip, and the scan output remapper.

[0007] According to an embodiment of the present invention concept, a semiconductor integrated circuit is provided. The semiconductor integrated circuit is configured to receive a test scan input signal, a test clock signal, and a test mode signal and output a secure scan output signal. The semiconductor integrated circuit includes: a security key circuit including N delay circuits and N flip-flops, where the N delay circuits are configured to receive the test scan input signal and output N delayed input signals that are differently delayed from the test scan input signal (where N is an integer greater than or equal to 1), and the N flip-flops are configured to latch logical values of the N delayed input signals and output an input key signal including the latched logical values; a key comparator configured to output a verification result signal indicating whether an input key of the input key signal is the same as a preset reference key; a chip configured to generate a scan output signal based on the test scan input signal; a scan output remapper configured to scramble the scan output signal in response to the verification result signal and output the scrambled scan output signal as the secure scan output signal; and a secure scan controller configured to control the security key circuit, the key comparator, the chip, and the scan output remapper.

[0008] According to an embodiment of the present invention concept, a method for testing a semiconductor integrated circuit is provided. The method includes: changing a test scan input signal into a plurality of delayed input signals having different delay values; generating an input key signal by obtaining values of the plurality of delayed input signals in response to a test clock signal; verifying whether an input key according to the input key signal is the same as a preset reference key; and scrambling a scan output signal output from a wafer under test according to a result of the verification.

[0009] According to an embodiment of the present invention concept, a semiconductor system is provided. The semiconductor system includes: a test device configured to output a test scan input signal, a test clock signal, and a test mode signal; and a semiconductor integrated circuit configured to receive the test scan input signal, the test clock signal, and the test mode signal and output a secure scan output signal. The semiconductor integrated circuit includes: N delay circuits configured to receive the test scan input signal and output N (where N is an integer greater than or equal to 1) delayed input signals differently delayed from the test scan input signal; and N flip-flops respectively connected in parallel to the N delay circuits and configured to latch logical values of the N delayed input signals in response to the test clock signal. Brief Description of the Drawings

[0010] Embodiments of the present invention concept will be more clearly understood by reading the following detailed description in conjunction with the accompanying drawings, in which: FIG. 1 is a view illustrating a semiconductor system according to an exemplary embodiment of the present invention concept. FIG. 2 is a view illustrating a semiconductor integrated circuit according to an exemplary embodiment of the present invention concept. FIG. 3 is a view illustrating a secure key injection unit according to an exemplary embodiment of the present invention concept. FIG. 4 is a view illustrating an example of implementing a secure key injection unit according to an exemplary embodiment of the present invention concept. FIG. 5 is a timing diagram illustrating a method of generating an input key signal according to an exemplary embodiment of the present invention concept. FIG. 6 is a view illustrating an example of an implementation scheme of a secure scan controller for controlling a key comparator according to an exemplary embodiment of the present invention concept. FIG. 7 is a view illustrating an example of an implementation scheme of a key selector shown in FIG. 6. FIG. 8 is a view illustrating a scan output remapper according to an exemplary embodiment of the present invention concept. FIG. 9 is a view illustrating an example of implementing a scan output remapper according to an exemplary embodiment of the present invention concept. FIG. 10 is a view illustrating an implementation example of a remapping controller according to an exemplary embodiment of the inventive concept. FIG. 11 is a view illustrating a security scan output signal output in a test mode. FIG. 12 is a view illustrating a security scan output signal output in a scan dump mode. FIG. 13 is a view illustrating a semiconductor integrated circuit according to another exemplary embodiment of the inventive concept. FIG. 14 is a view illustrating a semiconductor integrated circuit according to another exemplary embodiment of the inventive concept. FIG. 15 is a flowchart illustrating a method for testing a semiconductor integrated circuit according to an exemplary embodiment of the inventive concept. Embodiments

[0011] Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0012] FIG. 1 is a view illustrating a semiconductor system according to an exemplary embodiment of the inventive concept.

[0013] Referring to FIG. 1, the semiconductor system 10 may include a tester 100 and a semiconductor integrated circuit 200.

[0014] The tester 100 can be any device suitable for testing the semiconductor integrated circuit 200. The tester 100 may include a plurality of pins. Referring to FIG. 1, for example, the tester 100 may include a first pin P1', a second pin P2', and a third pin P3'. However, the exemplary embodiments are not limited thereto. For example, the tester 100 may include more than three pins. The tester 100 can transmit specific signals to the semiconductor integrated circuit 200 via each pin. For example, the tester 100 can output a test scan input signal via the first pin P1', can output a test clock signal via the second pin P2', and can output a test mode signal via the third pin P3'. The test scan input signal can be a signal that a user who will perform the test can optionally input to perform the test. As an alternative, the test scan input signal can be a signal for identifying whether the user who will perform the test is eligible to test the semiconductor integrated circuit 200. The test clock signal can be a clock signal used in the test mode. The test clock signal can continuously bistate toggle according to a specific period. In this case, when the specific period includes a preset cycle, the test clock signal can repeatedly bistate toggle within each cycle of the specific period. As an alternative, the test clock signal can bistate toggle only in at least one specific cycle among the multiple cycles included in one period. For example, when one period of the test clock signal includes 100 cycles, the test clock signal can bistate toggle at the 70th cycle, the 81st to 83rd cycles, and the 99th cycle among the 100 cycles. However, the exemplary embodiments are not limited thereto. The test mode signal can be a signal for implementing the test mode. When the logical value of the test mode signal is a first value (or a first bit value, logical high level), the test mode signal can indicate implementing the test mode. In contrast, when the logical value of the test mode signal is a second value (or a second bit value, logical low level), the test mode signal can indicate implementing the normal mode. However, the exemplary embodiments are not limited thereto. The tester 100 in this specification can be referred to as a test device, a tester, etc.

[0015] In an embodiment of the inventive concept, the tester 100 as a computer system can be set up as, for example, a personal computer, etc., and can include a debugging program for testing.

[0016] The semiconductor integrated circuit 200 may include a plurality of pins that receive signals output from the tester 100. For example, the semiconductor integrated circuit 200 may include a first pin P1, a second pin P2, and a third pin P3 and may receive a test scan input signal, a test clock signal, and a test mode signal via each pin. For example, the first pin P1 of the semiconductor integrated circuit 200 may receive a test scan input signal. However, the exemplary embodiments are not limited thereto. The semiconductor integrated circuit 200 may further include a pin for outputting a scan output signal generated due to performing a test. For example, the semiconductor integrated circuit 200 may include a fourth pin P4.

[0017] In an embodiment of the inventive concept, the semiconductor integrated circuit 200 may include a secure scan controller 210, a secure key injection unit 220, a key comparator 230, a scan output remapper 240, a circuit under test 250, and a one-time programmable memory (hereinafter referred to as OTP) 260.

[0018] FIG. 2 is a view illustrating a semiconductor integrated circuit according to an exemplary embodiment of the inventive concept.

[0019] Referring to FIG. 2, the semiconductor integrated circuit 200 may receive a test scan input signal TSI via the first pin P1, a test clock signal TCK via the second pin P2, and a test mode signal TMS via the third pin P3 to output a secure scan output signal SSO. To achieve this, the semiconductor integrated circuit 200 may include a secure scan controller 210, a secure key injection unit 220, a key comparator 230, a scan output remapper 240, a circuit under test 250, and an OTP 260.

[0020] The security scan controller 210 can control each of the security key injection unit 220, the key comparator 230, the scan output remapper 240, and the circuit under test 250. The security scan controller 210 can receive a test scan input signal TSI, a test clock signal TCK, and a test mode signal TMS via a first pin P1, a second pin P2, and a third pin P3. In an embodiment of the inventive concept, when the test mode signal TMS has a first value, the security scan controller 210 can transmit the test scan input signal TSI as a test key signal TSI_KEY to the security key injection 220 and can transmit a test clock signal TCK_SKI for the security key injection unit 220 to the security key injection unit 220. In an embodiment of the inventive concept, the security scan controller 210 can transmit a test clock signal TCK_KC for the key comparator 230 to the key comparator 230 and can transmit a pre-stored reference key signal KEY_REF to the key comparator 230. In an embodiment of the inventive concept, the security scan controller 210 can transmit a test clock signal TCK_SR for the scan output remapper 240 to the scan output remapper 240. In an embodiment of the inventive concept, the security scan controller 210 can transmit a scan control signal SC, a test data TSI_TD, and a test clock signal TCK_CHIP for the circuit under test 250 to the circuit under test 250.

[0021] In another embodiment of the inventive concept, the security scan controller 210 can receive a key selection signal KEY_SEL from the OTP 260 and can output a key selected from among a plurality of pre-stored keys as the reference key signal KEY_REF according to the key selection signal KEY_SEL.

[0022] In another embodiment of the inventive concept, the security scan controller 210 can receive a scan dump enable signal SDE and a configuration signal CFG from the circuit under test 250 and transmit a dump mode signal DUMP_MODE to the scan output remapper 240 to switch from a normal mode to a scan dump mode. The scan dump enable signal SDE can be a signal indicating that the scan dump mode is being entered. The configuration signal CFG can be a signal indicating internal information of the circuit under test 250 in the scan dump mode.

[0023] In another embodiment of the inventive concept, the security scan controller 210 can transmit a mapping selection signal MAP_SEL that allows an authorized user to decrypt the security scan output signal SSO to the scan output remapper 240.

[0024] The security key injection unit 220 can generate a plurality of delayed input signals based on the test scan input signal TSI. The plurality of delayed input signals can be signals that are differently delayed from the test scan input signal TSI. The security key injection unit 220 can generate an input key signal KEY_CAP by capturing the plurality of delayed input signals in response to the test clock signal TCK. The security key injection unit 220 can provide the input key signal KEY_CAP to the key comparator 230.

[0025] The key comparator 230 can verify whether the input key according to the input key signal KEY_CAP is the same as the reference key according to the reference key signal KEY_REF. Then, the key comparator 230 can generate a verification result signal P / F indicating the verification result. For example, the key comparator 230 can compare the value of the input key signal KEY_CAP with the value of the reference key signal KEY_REF in response to the test clock signal TCK_KC for the key comparator 230 and can output a verification result signal P / F indicating a pass state or a fail state.

[0026] In an embodiment of the inventive concept, the key comparator 230 can additionally provide a comparison key signal KEY_COMP to the scan output remapper 240. The comparison key signal KEY_COMP can be, for example, a signal indicating that the input key and the reference key are compared in the cycle of the last bistate transition of the test clock signal TCK_KC for the key comparator 230.

[0027] The scan output remapper 240 can scramble the scan output signal PSO using the verification result signal P / F according to the verification result and can output the scrambled scan output signal as a secure scan output signal SSO.

[0028] In an embodiment of the inventive concept, when the verification result is a pass, the scan output remapper 240 can output the scan output signal PSO via the fourth pin P4 without change. In other words, when the verification result is a pass, the scan output remapper 240 can not scramble the scan output signal PSO and can output the unscrambled scan output signal PSO via the fourth pin P4 as the secure scan output signal SSO without change.

[0029] In an embodiment of the inventive concept, when the verification result is a failure, the scan output remapper 240 may generate scrambling information for scrambling the scan output signal PSO based on the comparison key signal KEY_COMP. The scan output remapper 240 may scramble the scan output signal PSO according to the scrambling information.

[0030] In another embodiment of the inventive concept, the scan output remapper 240 may generate scrambling information for scrambling the scan output signal PSO based on the dump mode signal DUMP_MODE and the mapping selection signal MAP_SEL.

[0031] The circuit under test 250 may be a circuit or chip to be tested or debugged. The circuit under test 250 may include a plurality of synchronized circuits connected via a single scan chain. The circuit under test 250 may perform a scan operation based on the scan control signal SC and the test data TSI_TD received from the self-secure scan controller 210, and the circuit under test 250 may generate a scan output signal PSO and may transmit the scan output signal PSO to the scan output remapper 240. The circuit under test 250 in this specification may be referred to as a chip, a circuit, core logic, on-chip logic, etc.

[0032] The OTP 260 may store authentication key data. The authentication key data may be data indicating the number of authentication keys generated by a manufacturer or the like. The OTP 260 may output the authentication key data as a key selection signal KEY_SEL to the self-secure scan controller 210. The self-secure scan controller 210 may output a pre-stored key selected from the plurality of pre-stored keys according to the key selection signal KEY_SEL as a reference key signal KEY_REF. The OTP 260 in this specification may be implemented using fuses, antifuses, or electrofuses.

[0033] FIG. 3 is a view illustrating a secure key infusion unit according to an exemplary embodiment of the inventive concept.

[0034] Referring to FIG. 3, the security key injection unit 220 may include N delay circuits and N flip - flops. N can be an integer greater than or equal to 1. Referring to FIG. 3, for example, the security key injection unit 220 may include a first delay circuit 221_1, a second delay circuit 221_2, a third delay circuit 221_3, a fourth delay circuit 221_4, a fifth delay circuit 221_5, and a sixth delay circuit 221_6, as well as a first flip - flop (KFF) 222_1, a second flip - flop 222_2, a third flip - flop 222_3, a fourth flip - flop 222_4, a fifth flip - flop 222_5, and a sixth flip - flop 222_6. However, the exemplary embodiments are not limited thereto. For example, there may be more than six or less than six delay circuits in the security key injection unit 220, and there may be more than six or less than six flip - flops in the security key injection unit 220. Hereinafter, for the sake of convenience of explanation, it is assumed that the number of delay circuits and the number of flip - flops included in the security key injection unit 220 are six.

[0035] The security scan controller 210 may transmit the test scan input signal TSI as the test key signal TSI_KEY to the first delay circuit 221_1, the second delay circuit 221_2, the third delay circuit 221_3, the fourth delay circuit 221_4, the fifth delay circuit 221_5, and the sixth delay circuit 221_6. In this case, the first delay circuit 221_1, the second delay circuit 221_2, the third delay circuit 221_3, the fourth delay circuit 221_4, the fifth delay circuit 221_5, and the sixth delay circuit 221_6 may delay the test key signal TSI_KEY to output a first delayed input signal D0, a second delayed input signal D1, a third delayed input signal D2, a fourth delayed input signal D3, a fifth delayed input signal D4, and a sixth delayed input signal D5. For example, the first delay circuit 221_1 may delay the test key signal TSI_KEY to output the first delayed input signal D0. The delay value of the first delayed input signal D0, the delay value of the second delayed input signal D1, the delay value of the third delayed input signal D2, the delay value of the fourth delayed input signal D3, the delay value of the fifth delayed input signal D4, and the delay value of the sixth delayed input signal D5 may be different from each other. The first delayed input signal D0, the second delayed input signal D1, the third delayed input signal D2, the fourth delayed input signal D3, the fifth delayed input signal D4, and the sixth delayed input signal D5 may be respectively transmitted to the first flip - flop 222_1, the second flip - flop 222_2, the third flip - flop 222_3, the fourth flip - flop 222_4, the fifth flip - flop 222_5, and the sixth flip - flop 222_6.

[0036] The security scan controller 210 can transmit the test clock signal TCK_SKI for the security key injection unit 220 to the first flip-flop 222_1, the second flip-flop 222_2, the third flip-flop 222_3, the fourth flip-flop 222_4, the fifth flip-flop 222_5, and the sixth flip-flop 222_6. In this case, the first flip-flop 222_1, the second flip-flop 222_2, the third flip-flop 222_3, the fourth flip-flop 222_4, the fifth flip-flop 222_5, and the sixth flip-flop 222_6 can latch the logical values of the first delay input signal D0, the second delay input signal D1, the third delay input signal D2, the fourth delay input signal D3, the fifth delay input signal D4, and the sixth delay input signal D5 in response to the test clock signal TCK_SKI, and can transmit the latched values to the key comparator 230. Referring to FIG. 3, for example, in response to the test clock signal TCK_SKI, the first flip-flop 222_1 can latch the logical value of the first delay input signal D0, the second flip-flop 222_2 can latch the logical value of the second delay input signal D1, and the third flip-flop 222_3 can latch the logical value of the third delay input signal D2. Similarly, the fourth flip-flop 222_4, the fifth flip-flop 222_5, and the sixth flip-flop 222_6 can latch the logical values of the fourth delay input signal D3, the fifth delay input signal D4, and the sixth delay input signal D5 respectively in response to the test clock signal TCK_SKI.

[0037] FIG. 4 is a view illustrating an example of implementing a security key injection unit according to an exemplary embodiment of the inventive concept.

[0038] Referring to FIG. 4, at least one of the first delay circuit 221_1, the second delay circuit 221_2, the third delay circuit 221_3, the fourth delay circuit 221_4, the fifth delay circuit 221_5, and the sixth delay circuit 221_6 can include one or more buffers. In this case, the number of buffers included in the i-th (where i is an integer less than or equal to N, such as 1 to 6) delay circuit among the six delay circuits of the first delay circuit 221_1, the second delay circuit 221_2, the third delay circuit 221_3, the fourth delay circuit 221_4, the fifth delay circuit 221_5, and the sixth delay circuit 221_6 can be different from the number of buffers included in the j-th (where j is different from i and is an integer less than or equal to N) delay circuit among the six delay circuits of the first delay circuit 221_1, the second delay circuit 221_2, the third delay circuit 221_3, the fourth delay circuit 221_4, the fifth delay circuit 221_5, and the sixth delay circuit 221_6.

[0039] Referring to FIG. 4, for example, the second delay circuit 221_2 may include four buffers 223, the third delay circuit 221_3 may include two buffers 223, the fourth delay circuit 221_4 may include one buffer 223, the fifth delay circuit 221_5 may include three buffers 223, and the sixth delay circuit 221_6 may include five buffers 223. The first delay circuit 221_1 may not include a buffer 223. However, the exemplary embodiments are not limited thereto, and the number of buffers included in each delay circuit may be different from the number shown in FIG. 3. The larger the number of buffers 223, the larger the delay value. In other words, when the number of buffers 223 increases, the test key signal TSI_KEY may be delayed more.

[0040] In an embodiment of the inventive concept, one of the six delay circuits, i.e., the first delay circuit 221_1, the second delay circuit 221_2, the third delay circuit 221_3, the fourth delay circuit 221_4, the fifth delay circuit 221_5, and the sixth delay circuit 221_6, may not include a buffer. In such a case, one of the first delay circuit 221_1, the second delay circuit 221_2, the third delay circuit 221_3, the fourth delay circuit 221_4, the fifth delay circuit 221_5, and the sixth delay circuit 221_6 may transmit the test key signal TSI_KEY to the corresponding flip-flop. Referring to FIG. 4, for example, the first delay circuit 221_1 may not include a buffer, and the first delay circuit 221_1 may input the test key signal TSI_KEY to the first flip-flop 222_1. However, the exemplary embodiments are not limited thereto.

[0041] FIG. 5 is a timing diagram illustrating a method of generating an input key signal according to an exemplary embodiment of the inventive concept.

[0042] Referring to FIGS. 4 and 5, the test clock signal TCK_SKI and the test key signal TSI_KEY may be transmitted to the security key injection unit 220. The test clock signal TCK_SKI may be bistable only in a specific cycle within one period. From one specific time point to another specific time point, the test key signal TSI_KEY may have a first logic value (e.g., a logic high level). Each of the test clock signal TCK_SKI and the test key signal TSI_KEY may have a first logic value or a second logic value. Hereinafter, for convenience, it is assumed that the first logic value is a logic high level or 1 bit, and the second logic value is a logic low level or 0 bit.

[0043] The first delayed input signal D0, the second delayed input signal D1, the third delayed input signal D2, the fourth delayed input signal D3, the fifth delayed input signal D4, and the sixth delayed input signal D5 may be signals in which the test key signal TSI_KEY is delayed. Each of the first delayed input signal D0, the second delayed input signal D1, the third delayed input signal D2, the fourth delayed input signal D3, the fifth delayed input signal D4, and the sixth delayed input signal D5 may have a first logic value or a second logic value. When assuming that the number of buffers 223 included in each delay circuit is as shown in FIG. 4, the delay values may increase in order from the first delayed input signal D0, the fourth delayed input signal D3, the third delayed input signal D2, the fifth delayed input signal D4, the second delayed input signal D1, and the sixth delayed input signal D5. In other words, the sixth delayed input signal D5 may have the maximum delay.

[0044] In an embodiment of the inventive concept, the first flip-flop 222_1, the second flip-flop 222_2, the third flip-flop 222_3, the fourth flip-flop 222_4, the fifth flip-flop 222_5, and the sixth flip-flop 222_6 may latch the logical value of the first delay input signal D0, the logical value of the second delay input signal D1, the logical value of the third delay input signal D2, the logical value of the fourth delay input signal D3, the logical value of the fifth delay input signal D4, and the logical value of the sixth delay input signal D5 at the rising edge of the test clock signal TCK_SKI in response to the rising edge of the test clock signal TCK_SKI. Referring to FIG. 5, for example, in the first stage STG1, a rising edge of the test clock signal TCK_SKI may be generated. In this case, the logical value of the first delay input signal D0 may be a first logical value (or a logical high level or 1 bit), the logical value of the second delay input signal D1 may be a second logical value (or a logical low level or 0 bit), and the logical values of the third delay input signal D2 to the fifth delay input signal D4 may be the first logical value, and the logical value of the sixth delay input signal D5 may be the second logical value. The first flip-flop 222_1, the second flip-flop 222_2, the third flip-flop 222_3, the fourth flip-flop 222_4, the fifth flip-flop 222_5, and the sixth flip-flop 222_6 may capture the input key KEY_CAP [D0:D5] including the latched logical values, and at this time, the input key KEY_CAP [D0:D5] may be "101110". Referring to FIG. 5, in another example, in the second stage STG2, a rising edge of the test clock signal TCK_SKI may be generated. In this case, the logical value of the first delay input signal D0 may be the second logical value, the logical values of the second delay input signal D1 and the third delay input signal D2 may be the first logical value, the logical value of the fourth delay input signal D3 may be the second logical value, and the logical values of the fifth delay input signal D4 and the sixth delay input signal D5 may be the first logical value. In this case, the input key KEY_CAP [D0:D5] including the latched logical values may be "011011". Referring to FIG. 5, in another example, in the third stage STG3, a rising edge of the test clock signal TCK_SKI may be generated. In this case, the logical values of the first delay input signal D0, the second delay input signal D1, the third delay input signal D2, the fourth delay input signal D3, and the fifth delay input signal D4 may be the first logical value, and the logical value of the sixth delay input signal D5 may be the second logical value. In this case, the input key KEY_CAP [D0:D5] may be "111110".

[0045] The security key injection unit 220 can generate the logical values of the first delay input signal D0, the second delay input signal D1, the third delay input signal D2, the fourth delay input signal D3, the fifth delay input signal D4, and the sixth delay input signal D5 at the rising edge of the test clock signal TCK_SKI during testing as the input key signal KEY_CAP and can provide the input key signal KEY_CAP to the key comparator 230.

[0046] When the test clock signal TCK_SKI toggles between two states for the first flip-flop 222_1, the second flip-flop 222_2, the third flip-flop 222_3, the fourth flip-flop 222_4, the fifth flip-flop 222_5, and the sixth flip-flop 222_6, the number of cases of the input key KEY_CAP [D0:D5] that can be captured by the first flip-flop 222_1, the second flip-flop 222_2, the third flip-flop 222_3, the fourth flip-flop 222_4, the fifth flip-flop 222_5, and the sixth flip-flop 222_6 can be 2^6. Therefore, in order to obtain the same input key as the reference key input to the key comparator 230, the user needs to know the individual time when the transition of the test key signal TSI_KEY reaches each of the first flip-flop 222_1, the second flip-flop 222_2, the third flip-flop 222_3, the fourth flip-flop 222_4, the fifth flip-flop 222_5, and the sixth flip-flop 222_6 and needs to accurately input the skew between the transitions of the test key signal TSI_KEY to capture the desired key value and the test clock signal TCK_SKI. Therefore, according to the exemplary embodiments of the present invention, malicious users may not be able to accurately input the skew between the transitions of the test key signal TSI_KEY and the test clock signal TCK_SKI, so as to enhance the security.

[0047] As described above, the encryption level can be increased without adding flip-flops, which is generally used to achieve higher security and reliability.

[0048] FIG. 6 is a view illustrating an implementation example of a security scan controller for controlling a key comparator according to an exemplary embodiment of the concept of the present invention.

[0049] Referring to FIG. 6, the security scan controller 210 can provide a reference key signal KEY_REF and a test clock signal TCK_KC for the key comparator 230 to the key comparator 230. Whenever multiple delayed input signals are captured, the security scan controller 210 can count the stage corresponding to the number of times the multiple delayed input signals are captured. Referring to FIGS. 4 and 6, for example, when the first delayed input signal D0, the second delayed input signal D1, the third delayed input signal D2, the fourth delayed input signal D3, the fifth delayed input signal D4, and the sixth delayed input signal D5 are captured at the first stage STG1, the security scan controller 210 can count the first stage STG1. When the first delayed input signal D0, the second delayed input signal D1, the third delayed input signal D2, the fourth delayed input signal D3, the fifth delayed input signal D4, and the sixth delayed input signal D5 are captured at the second stage STG2, the security scan controller 210 can count the second stage STG2. When the first delayed input signal D0, the second delayed input signal D1, the third delayed input signal D2, the fourth delayed input signal D3, the fifth delayed input signal D4, and the sixth delayed input signal D5 are captured at the third stage STG3, the security scan controller 210 can count the third stage STG3. The security scan controller 210 can provide the key corresponding to the counted stage among the multiple pre-stored keys as a reference key to the comparator 230.

[0050] In an exemplary embodiment of the inventive concept, the security scan controller 210 can include a key selector 211, a stage counter 212, a first AND gate 213, a first OR gate 214, a second OR gate 215, and a second AND gate 216.

[0051] The key selector 211 can select one key among the multiple pre-stored keys as a reference key according to the counted stage in response to the stage signal STG, so as to transmit the reference key signal KEY_REF to the comparator 230. In an exemplary embodiment of the inventive concept, the key selector 211 can transmit the reference key signal KEY_REF to the key comparator 230 in response to the key selection signal KEY_SEL received from the OTP 260.

[0052] The stage counter 212 can output a stage corresponding to the number of times the logical values of the N delayed input signals are latched, so as to output a stage signal STG indicating the counted stage. Referring to FIGS. 5 and 6, for example, the stage counter 212 can output a stage signal STG that sequentially indicates a first stage STG1, a second stage STG2, and a third stage STG3. Each time a stage is counted, the stage counter 212 can output a comparison signal COMP indicating a comparison operation. The comparison signal COMP can have a first logical value or a second logical value, and when counting the stage, the comparison signal COMP can have a first logical value. When the comparison operation of the key comparator 230 is completed or a preset stage count number is satisfied, the stage counter 212 can output a comparison completion signal COMP_DONE to the first logical AND gate 214. The comparison completion signal COMP_DONE can have a first logical value or a second logical value. When the comparison operation of the key comparator 230 is completed, the comparison signal COMP can have a second logical value, and the comparison completion signal COMP_DONE can have a first logical value.

[0053] The first logical AND gate 213 can perform a logical AND operation on the comparison signal COMP and the test clock signal TCK to provide the result of the logical AND operation as a test clock signal TCK_KC for the key comparator 230 to the key comparator 230. The first logical AND gate 213 can be an AND gate.

[0054] The first logical OR gate 214 can perform a logical OR operation on the comparison completion signal COMP_DONE and the dump mode signal DUMP_MODE, so as to provide the result of the logical OR operation as a system reset signal SYS_nRESET to the circuit under test 250. The dump mode signal DUMP_MODE can have a first logical value or a second logical value. When the dump mode signal DUMP_MODE has a first logical value, this can mean that the scan dump mode is being entered. The system reset signal SYS_nRESET can be a signal indicating that the circuit under test 250 is reset.

[0055] The second logical AND gate 215 can perform a logical OR operation on the comparison completion signal COMP_DONE and the dump mode signal DUMP_MODE, so as to provide the result of the logical OR operation to the second logical AND gate 216.

[0056] The second logical AND gate 216 can perform a logical AND operation on the output of the second logical OR gate 215 and the test clock signal TCK provided from the outside, so as to output the result of the logical AND operation as a test clock signal TCK_CHIP for the circuit under test 250.

[0057] When the input key according to the input key signal KEY_CAP is the same as the reference key according to the reference key signal KEY_REF, the key comparator 230 can output a signal indicating a pass state as the verification result signal P / F. In such a case, for example, the signal indicating the pass state can be a signal having a first logic value. On the other hand, when the input key signal KEY_CAP is different from the reference key signal KEY_REK, the key comparator 230 can output a signal indicating a failure state as the verification result signal P / F. In such a case, for example, the signal indicating the failure state can be a signal having a second logic value. However, the exemplary embodiments are not limited thereto.

[0058] FIG. 7 is a view illustrating an implementation example of the key selector shown in FIG. 6.

[0059] Referring to FIGS. 5, 6, and 7, the key selector 211 can pre-store a stage key 211_1 corresponding to a stage and a set of authentication keys 211_2 corresponding to the number of authentication keys. The set of authentication keys 211_2 can be referred to as a predefined key set. The key selector 211 can include a first multiplexer 211_3 and a second multiplexer 211_4. The number of stage keys 211_1 can be m, however, the number of stage keys 211_1 is not limited thereto. Here, m can be an integer greater than or equal to 2.

[0060] The first multiplexer 211_3 can output one stage key selected among the stage keys 211_1 according to the stage signal STG. Referring to FIGS. 5 and 7, for example, when the stage signal STG indicates the first stage STG1, the first multiplexer 211_3 can output the first stage key KEY_0.

[0061] The second multiplexer 211_4 can select one key among the set of authentication keys 211_2 according to the stage key selected by the first multiplexer 211_3 and the key selection signal KEY_SEL (or authentication key data) to output the reference key signal KEY_REF.

[0062] FIG. 8 is a view illustrating a scan output remapper according to an exemplary embodiment of the inventive concept.

[0063] Referring to FIG. 8, the scan output remapper 240 can include a remapping controller 241, a first register bank 242, a second register bank 243, a first selector 244, and a second selector 245.

[0064] The remapping controller 241 may receive a test clock signal TCK_SR, a scan output signal PSO, a verification result signal P / F, a dump mode signal DUMP_MODE, and a comparison key signal KEY_COMP. According to an exemplary embodiment of the inventive concept, the remapping controller 241 may further receive a mapping selection signal MAP_SEL. The remapping controller 241 may transmit the scan output signal PSO to the first register bank 242 and the second register bank 243. Based on the test clock signal TCK_SR and the comparison key signal KEY_COMP, the remapping controller 241 may output a first clock signal TCK_1 to the first register bank 242 and may output a second clock signal TCK_2 to the second register bank 243. The remapping controller 241 may output a first scan enable signal SE_1 to the first register bank 242 and may provide and output a second scan enable signal SE_2 to the second register bank 243. According to an exemplary embodiment of the inventive concept, the second scan enable signal SE_2 may be a signal in which the first scan enable signal SE_1 is inverted.

[0065] The first register bank 242 may latch the scan output signal PSO in response to the first scan enable signal SE_1 and the first clock signal TCK_1 and may output the latched first scan output signal OSO1. The first register bank 242 may be connected to ground GND.

[0066] The second register bank 243 may latch the scan output signal PSO in response to the second scan enable signal SE_2 and the second clock signal TCK_2 and may output the latched second scan output signal OSO2. The second register bank 243 may be connected to ground GND.

[0067] The first selector 244 may select one of the first scan output signal OSO1 and the second scan output signal OSO2 according to the second scan enable signal SE_2.

[0068] The second selector 245 may output one of the scan output signal OSO_SEL selected by the first selector 244 and the scan output signal PSO as a secure scan output signal SSO according to the verification result signal P / F.

[0069] FIG. 9 is a view illustrating an example of implementing a scan output remapper according to an exemplary embodiment of the inventive concept.

[0070] Referring to FIG. 9, the first register bank 242 may include r first flip - flops connected in series (where r is an integer greater than or equal to 1). The flip - flops connected in series may be shaped such that the output terminal of the current flip - flop is connected to the input terminal of the next flip - flop. Referring to FIG. 9, for example, the first register bank 242 may include four first flip - flops 242_1, 242_2, 242_3, and 242_4, where the output of the current flip - flop is connected to the input of the next flip - flop. However, the exemplary embodiments are not limited to this. For example, there may be more than four flip - flops in the first register bank 242. Hereinafter, it is assumed that the number of first flip - flops is four. Each of the first flip - flops 242_1, 242_2, 242_3, and 242_4 may latch the scan output signal PSO in response to the rising edges of the four first clock signals TCK_11, TCK_12, TCK_13, and TCK_14. The first flip - flop 242_1 among the first flip - flops 242_1, 242_2, 242_3, and 242_4 may receive GND from the scan input terminal SI, and in the three first flip - flops 242_2, 242_3, and 242_4, the scan output terminal SO of the previous flip - flop may be connected to the scan input terminal SI of the next flip - flop. The first flip - flop 242_4 may correspond to the most significant bit (MSB), and the first flip - flop 242_1 may correspond to the least significant bit (LSB).

[0071] The second register bank 243 may include r second flip - flops connected in series. Referring to FIG. 9, for example, the second register bank 243 may include four second flip - flops 243_1, 243_2, 243_3, and 243_4, where the output of the current flip - flop is connected to the input of the next flip - flop. However, the exemplary embodiments are not limited to this. For example, the second register bank 243 may include more than four flip - flops. Hereinafter, it is assumed that the number of second flip - flops is four. Each of the second flip - flops 243_1, 243_2, 243_3, and 243_4 may latch the scan output signal PSO in response to the rising edges of the four second clock signals TCK_21, TCK_22, TCK_23, and TCK_24. The second flip - flop 243_1 among the second flip - flops 243_1, 243_2, 243_3, and 243_4 may receive GND from the scan input terminal SI, and in the three second flip - flops 243_2, 243_3, and 243_4, the scan output terminal SO of the previous flip - flop may be connected to the scan input terminal SI of the next flip - flop. The second flip - flop 243_4 may correspond to the MSB, and the second flip - flop 243_1 may correspond to the LSB.

[0072] The remapping controller 241 can output four first clock signals TCK_11, TCK_12, TCK_13, and TCK_14 to the first register bank 242. The remapping controller 241 can output four second clock signals TCK_21, TCK_22, TCK_23, and TCK_24 to the second register bank 243. The remapping controller 241 can output a first scan enable signal SE_1 to the first register bank 242.

[0073] The scan output remapper 240 may further include an inverter 246. The inverter 246 can invert the first scan enable signal SE_1 to output a second scan enable signal SE_2 to the second register bank 243.

[0074] In an exemplary embodiment of the inventive concept, the first selector 244 may be implemented as a first multiplexer 244_1. However, the exemplary embodiment is not limited thereto. The first multiplexer 244_1 can select and output a first scan output signal OSO1 or a second scan output signal OSO2 according to the logical value of the second scan enable signal SE_2. For example, when the logical value of the second scan enable signal SE_2 is a first logical value (e.g., logical high level), the first multiplexer 244_1 can output the second scan output signal OSO2. In another example, when the logical value of the second scan enable signal SE_2 is a second logical value (e.g., logical low level), the first multiplexer 244_1 can output the first scan output signal OSO1.

[0075] In an exemplary embodiment of the inventive concept, the second selector 245 may be implemented as a second multiplexer 245_1. However, the exemplary embodiment is not limited thereto. The second multiplexer 245_1 can select and output the scan output signal OSO_SEL selected by the first multiplexer 244_1 or the scan output signal PSO selected according to the logical value of the verification result signal P / F. For example, when the logical value of the verification result signal P / F is a first logical value (e.g., pass state or logical high level), the second multiplexer 245_1 can output the scan output signal PSO as the secure scan output signal SSO. In another example, when the logical value of the verification result signal P / F is a second logical value (e.g., fail state or logical low level), the second multiplexer 245_1 can output the selected scan output signal OSO_SEL as the secure scan output signal SSO.

[0076] FIG. 10 is a view illustrating an implementation example of a remapping controller according to an exemplary embodiment of the inventive concept.

[0077] Referring to FIG. 10, the remapping controller 241 can generate scrambling information for scrambling the scan output signal PSO based on the comparison key signal KEY_COMP and can scramble the scan output signal PSO according to the scrambling information. The scrambling information can be indicated as the rising edge timings of r first clock signals TCK_1[r - 1:0] or the rising edge timings of r second clock signals TCK_2[r - 1:0].

[0078] The remapping controller 241 can include a linear feedback shift register 241_1, a one-hot encoder 241_2, a first multiplexer (MUX1) 241_3, a second multiplexer (MUX2) 241_4, a third multiplexer (MUX3) 241_5, r first AND gates 241_6, and r second OR gates 241_7.

[0079] The linear feedback shift register 241_1 can output r linear signals LO based on the comparison key signal KEY_COMP. Here, the number of linear signals LO can be the same as the number of flip-flops included in the first register bank 242 and the second register bank 243.

[0080] The one-hot encoder 241_2 can output r encoded signals EO based on the mapping selection signal MAP_SEL. Here, the number of encoded signals EO can be the same as the number of flip-flops included in the first register bank 242 and the second register bank 243.

[0081] The r linear signals LO and the r encoded signals EO can correspond to the above scrambling information.

[0082] The first multiplexer 241_3 can output r linear signals LO or r encoded signals EO according to the logical value of the dump mode signal DUMP_MODE. For example, when the logical value of the dump mode signal DUMP_MODE is the first logical value, the first multiplexer 241_3 can output r encoded signals EO. In another example, when the logical value of the dump mode signal DUMP_MODE is the second logical value, the first multiplexer 241_3 can output r linear signals LO.

[0083] The second multiplexer 241_4 can output the first data 241_8 with a pre-stored first logic value or the output signal of the first multiplexer 241_3 according to the logic value of the first scan enable signal SE_1. For example, when the logic value of the first scan enable signal SE_1 is the first logic value, the second multiplexer 241_4 can output the first data 241_8. In another example, when the logic value of the first scan enable signal SE_1 is the second logic value, the second multiplexer 241_4 can output the output signal of the first multiplexer 241_3.

[0084] The third multiplexer 241_5 can output the second data 241_9 with a pre-stored first logic value or the output signal of the first multiplexer 241_3 according to the logic value of the first scan enable signal SE_1. For example, when the logic value of the first scan enable signal SE_1 is the first logic value, the third multiplexer 241_5 can output the output signal of the first multiplexer 241_3. In another example, when the logic value of the first scan enable signal SE_1 is the second logic value, the third multiplexer 241_5 can output the second data 241_9.

[0085] According to an exemplary embodiment of the inventive concept, the first data 241_8 and the second data 241_9 can be stored as one data in the same storage space or can be stored in different storage spaces.

[0086] r first logic AND gates 241_6 can perform a logic AND operation on the test clock signal TCK_SR for the scan output remapper 240 and the output signal of the second multiplexer 241_4, respectively.

[0087] r second logic AND gates 241_7 can perform a logic AND operation on the test clock signal TCK_SR for the scan output remapper 240 and the output signal of the third multiplexer 241_5, respectively.

[0088] FIG. 11 is a view illustrating a secure scan output signal output in a test mode.

[0089] Referring to FIGS. 9, 10, and 11, for convenience, it is assumed that the number of cycles of the test clock signal TCK_SR for the scan output remapper 240 is 12, r is 4, and the logical values (or bit values) of the linear signal LO in each cycle are sequentially "0011", "0001", "1000", "0100", "0010", "1001", "1100", "0110", "1011", "0101", "1010", and "1101", and "-" indicates that the first clock signals TCK_11, TCK_12, TCK_13, and TCK_14 and the second clock signals TCK_21, TCK_22, TCK_23, and TCK_24 are gated. It is assumed that "En" indicates the first clock signals TCK_11, TCK_12, TCK_13, and TCK_14 and has been enabled, has a rising edge, or is input to each flip-flop for the second clock signals TCK_21, TCK_22, TCK_23, and TCK_24, and "SR_A [3:0]" is the first scan output signal OSO1 and "SR_B [3:0]" is the second scan output signal OSO2.

[0090] It is assumed that the logical value of the first scan enable signal SE_1 and the logical value of the second scan enable signal SE_2 alternate with each other in each cycle. For example, the logical value of the first scan enable signal SE_1 from the first cycle to the fourth cycle (e.g., counting from the zero cycle to the third cycle) can be a logical low level, and the logical value of the second scan enable signal SE_2 from the first cycle to the fourth cycle can be a logical high level. In this case, the secure scan output signal SSO can be the signal output from the four second flip-flops 243_1, 243_2, 243_3, and 243_4. From the fifth cycle to the eighth cycle (e.g., counting from the fourth cycle to the seventh cycle), the logical value of the first scan enable signal SE_1 can be a logical high level, and the logical value of the second scan enable signal SE_2 can be a logical low level. In this case, the secure scan output signal SSO can be the signal output from the four first flip-flops 242_1, 242_2, 242_3, and 242_4.

[0091] When the first cycle (e.g., cycle count is 0), the value of the scan output signal PSO is "p0" and only the first clock signals TCK_11 and TCK_12 are enabled. The first flip-flops 242_1 and 242_2 can latch "p0" in response to the rising edges of the first clock signals TCK_13 and TCK_14. When the second cycle (e.g., cycle count is 1), the value of the scan output signal PSO is "p1" and only the first clock signal TCK_11 is enabled. The first flip-flop 242_1 can latch "p1" in response to the rising edge of the first clock signal TCK_11. When the third cycle (e.g., cycle count is 2), only the first clock signal TCK_14 is enabled, and the first flip-flop 242_4 can latch "p2" in response to the rising edge of the first clock signal TCK_14. When the cycle count is 3, only the first clock signal TCK_13 can be enabled, and the first flip-flop 242_3 can latch "p3" in response to the rising edge of the first clock signal TCK_13.

[0092] When the cycle count is from 4 to 7, the secure scan output signal SSO can sequentially output the output values of each flip-flop from the first flip-flop 242_4 corresponding to the MSB to the first flip-flop 242_1 corresponding to the LSB. When the cycle count is 4, the secure scan output signal SSO can be "p2", when the cycle count is 5, the secure scan output signal SSO can be "p3", when the cycle count is 6, the secure scan output signal SSO can be "p0", and when the cycle count is 7, the secure scan output signal SSO can be "p1".

[0093] When the cycle count is 4, only the second clock signal TCK_22 is enabled. The second flip-flop 243_2 can latch "p4" in response to the rising edge of the second clock signal TCK_22. When the cycle count is 5, the second flip-flops 243_1 and 243_4 can latch "p5" in response to the rising edges of the second clock signals TCK_21 and TCK_24. Similarly, when the cycle count is 6, the second flip-flops 243_3 and 243_4 can latch "p6". When the cycle count is 7, the second flip-flops 243_2 and 243_3 can latch "p7".

[0094] When the cycle count is from 8 to 11, the secure scan output signal SSO with "p6", "p7", "p7", and "p5" can be output sequentially from the second flip-flop 243_4 corresponding to the MSB to the second flip-flop 243_1 corresponding to the LSB.

[0095] Figure 12 is a view illustrating the secure scan output signal output in the scan dump mode.

[0096] Referring to FIGS. 9, 10, 11, and 12, similar to FIG. 11, for convenience, assume that the number of cycles of the test clock signal TCK_SR is 8, r is 4, and the values of the mapping selection signal MAP_SEL are {2'b00, 2'b10, 2'b11, 2'b01} (or "00101101"). In this case, {A, B, C, D} indicating the values of the mapping selection signal MAP_SEL can indicate the priority from the flip-flop corresponding to the MSB to the flip-flop corresponding to the LSB. For example, the first bit digit in {A, B, C, D} (e.g., "A") can indicate the priority of the flip-flop corresponding to the MSB (e.g., the first flip-flop 242_4 and the second flip-flop 243_4), the second bit digit in {A, B, C, D} (e.g., "B") can indicate the priority of the flip-flop corresponding to the MSB-1 (e.g., the first flip-flop 242_3 and the second flip-flop 243_3), the third bit digit in {A, B, C, D} (e.g., "C") can indicate the priority of the flip-flop corresponding to the MSB-2 (e.g., the first flip-flop 242_2 and the second flip-flop 243_2), and the fourth bit digit in {A, B, C, D} (e.g., "D") can indicate the priority of the flip-flop corresponding to the LSB (e.g., the first flip-flop 242_1 and the second flip-flop 243_1). Then, the lower the value in the parentheses "{}", the higher the order of the latches. For example, in the case of {2'b00, 2'b10, 2'b11, 2'b01}, the latch order can be in the order of the flip-flop corresponding to the MSB, the flip-flop corresponding to the LSB, the flip-flop corresponding to the MSB-1, and the flip-flop corresponding to the MSB_2. In this case, within each cycle, the logical value of the encoded signal EO can repeatedly be "1000", "0001", "0100", and "0010".

[0097] As shown in FIG. 11, assume that the logical value of the first scan enable signal SE_1 and the logical value of the second scan enable signal SE_2 alternate with each other within each cycle. For example, when the cycle count is 0, the logical value of the first scan enable signal SE_1 is 0 and the logical value of the second scan enable signal SE_2 is 1.

[0098] When the loop count is 0, the first flip-flop 242_4 can latch "p0". When the loop count is 1, the first flip-flop 242_1 can latch "p1". When the loop count is 2, the first flip-flop 242_3 can latch "p2". When the loop count is 3, the first flip-flop 242_2 can latch "p3". The value of the safety scan output signal SSO can be "0".

[0099] When the loop count is 4, the second flip-flop 243_4 can latch "p4". When the loop count is 5, the second flip-flop 243_1 can latch "p5". When the loop count is 6, the second flip-flop 243_3 can latch "p6". When the loop count is 7, the second flip-flop 243_2 can latch "p7". The values of the safety scan output signal SSO can be "p0", "p2", "p3", and "p1" in sequence.

[0100] FIG. 13 is a view illustrating a semiconductor integrated circuit according to another exemplary embodiment of the present invention concept.

[0101] Referring to FIG. 13, the semiconductor integrated circuit 400 may include first to fourth pins P1, P2, P3, and P4, as described above with reference to FIG. 1. The semiconductor integrated circuit 400 may include a single lock key (SLK) circuit 410 and a plurality of chips 420_1, 420_2,..., and 420_n. Here, n may be an integer greater than or equal to 2.

[0102] The single lock key circuit 410 may include the safety scan controller 210, the safety key infusion unit 220, the key comparator 230, the scan output remapper 240, the circuit under test 250, and the OTP 260 shown in FIG. 1.

[0103] Each of the plurality of chips 420_1, 420_2,..., and 420_n may correspond to the circuit under test 250 shown in FIG. 1. The plurality of chips 420_1, 420_2,...., and 420_n may include a plurality of test interfaces 421_1, 421_2,..., and 421_n. The plurality of test interfaces 421_1, 421_2,..., and 421_n may be interfaces that communicate with the single lock key circuit 410 in test mode or scan dump mode. According to an exemplary embodiment of the present invention concept, the plurality of chips 420_1, 420_2,...., and 420_n may be implemented with a plurality of circuits.

[0104] FIG. 14 is a view of a semiconductor integrated circuit illustrating another exemplary embodiment according to the concepts of the present invention.

[0105] Referring to FIG. 14, the semiconductor integrated circuit 500 may include a first pin P1' and a second pin P2'. The semiconductor integrated circuit 500 may receive a test scan input signal TSI or a test clock signal TCK via the first pin P1'. The semiconductor integrated circuit 500 may output a secure scan output signal SSO via the second pin P2'.

[0106] The semiconductor integrated circuit 500 may include a single-lock key circuit group 510, a plurality of chips 520_1, 520_2,..., and 520_n, and a demultiplexer 530.

[0107] The single-lock key circuit group 510 may include a plurality of single-lock key circuits 510_1, 510_2,..., and 510_n. Each of the plurality of single-lock key circuits 510_1, 510_2,..., and 510_n may correspond to the single-lock key circuit 410 described above with reference to FIG. 13.

[0108] The plurality of chips 520_1, 520_2,..., and 520_n may correspond to the plurality of chips 420_1, 420_2,..., and 420_n described above with reference to FIG. 13.

[0109] In an exemplary embodiment of the concepts of the present invention, the first single-lock key circuit 510_1 may communicate with a first test interface 521_1 included in the first chip 520_1. The second single-lock key circuit 510_2 may communicate with a second test interface 521_2 included in the second chip 520_2. The nth single-lock key circuit 510_n may communicate with the nth test interface 521_n included in the nth chip 520_n.

[0110] The demultiplexer 530 may transmit a signal received from the outside to the plurality of single-lock key circuits 510_1, 510_2,..., and 510_n via the first pin P1'.

[0111] FIG. 15 is a flowchart illustrating a method for testing a semiconductor integrated circuit according to an exemplary embodiment of the concepts of the present invention.

[0112] Referring to FIG. 15, a method for testing a semiconductor integrated circuit may include changing a test scan input signal into a plurality of delayed input signals having different delay values (S310); generating an input key signal by capturing the plurality of delayed input signals in response to a test clock signal (S320); verifying whether an input key according to the input key signal is the same as a preset reference key (S330); obtaining a scan output signal from the chip (S340); and scrambling the scan output signal output from the chip to be tested according to the verification result (S350, S360, S370, S380).

[0113] When scrambling the scan output signal output from the chip to be tested according to the verification result (S350, S360, S370, S380), the method includes checking whether the verification result passes (S350). When the verification result passes (yes in S350), the scan output signal is output to the outside via an output pin (S360). When the verification result fails (no in S350), the scan output signal is scrambled (S370) and the scrambled scan output signal is output to the outside via an output pin (S380).

[0114] In an exemplary embodiment of the inventive concept, each of the plurality of delayed input signals may have a first logic value and a second logic value, and the second logic value is different from the first logic value. In such a case, when generating the input key signal (S320), the logic values of the plurality of delayed input signals may be generated as the input key signal at the rising edge of the test clock signal.

[0115] In an exemplary embodiment of the inventive concept, when verifying whether an input key according to the input key signal is the same as a preset reference key (S330), when the input key is the same as the reference key, a signal indicating a pass state may be output. When the input key is different from the reference key, a signal indicating a fail state may be output.

[0116] In an exemplary embodiment of the inventive concept, when outputting the scan output signal to the outside via an output pin (S360), the unscrambled scan output signal may be output as a secure scan output signal.

[0117] In an exemplary embodiment of the inventive concept, when outputting the scrambled scan output signal to the outside via an output pin (S380), the scrambled scan output signal may be output as a secure scan output signal.

[0118] As described above, the circuit used to perform the test can be prevented from being maliciously used, so that the reliability and security can be improved.

[0119] In addition, as described above, the test scan input is input to the flip-flop in a parallelized input manner so that the number of input cases of the security key can be exponentially increased and thus the security can be further improved.

[0120] Furthermore, as described above, the test scan input to be input to the flip-flop can be further input in a parallelized input manner instead of adding flip-flops implemented in the serialized input method, so that the manufacturing cost can be reduced and the product can be further integrated.

[0121] Although the present inventive concept has been shown and described with reference to embodiments of the present inventive concept, it will be understood that various changes in form and detail may be made to the embodiments of the present inventive concept without departing from the spirit and scope of the present inventive concept as set forth in the following claims.

[0122] 10: Semiconductor system 100: Tester 200, 400, 500: Semiconductor integrated circuit 210: Security scan controller 211: Key selector 211_1: Phase key 211_2: Authentication key set 211_3, 241_3, 244_1: First multiplexer 211_4, 241_4, 245_1: Second multiplexer 212: Phase counter 213, 241_6: First AND gate 214: First OR gate 215: Second OR gate 216, 241_7: Second AND gate 220: Security key injection unit 221_1: First delay circuit 221_2: Second delay circuit 221_3: Third delay circuit 221_4: Fourth delay circuit 221_5: Fifth delay circuit 221_6: Sixth delay circuit 222_1, 242_1, 242_2, 242_3, 242_4: First flip-flop (KFF) 222_2, 243_1, 243_2, 243_3, 243_4: Second flip-flop 222_3: Third flip-flop 222_4: Fourth flip-flop 222_5: Fifth flip-flop 222_6: Sixth flip-flop 223: Buffer 230: Key comparator / comparator 240: Scan output remapper 241: Remapping controller 241_1: Linear feedback shift register 241_2: One-hot encoder 241_5: Third multiplexer 241_8: First data 241_9: Second data 242: First register bank 243: Second register bank 244: First selector 245: Second selector 246: Inverter 250: Circuit under test 260: One-time programmable memory 410: Single-lock key (SLK) circuit 420_1, 420_2, 420_n: Chip 421_1, 421_2, 421_n: Test interface 510: Single-lock key circuit group 510_1: Single-lock key circuit / First single-lock key circuit 510_2: Single-lock key circuit / Second single-lock key circuit 510_n: Single-lock key circuit / nth single-lock key circuit 520_1: Chip / First chip 520_2: Chip / Second chip 520_n: Chip / nth chip 521_1: First test interface 521_2: Second test interface 521_n: nth test interface 530: Demultiplexer COMP: Comparison signal COMP_DONE: Comparison completed signal CFG: Configuration signal D: Fourth-bit digit D0: First delay input signal D1: Second delay input signal D2: Third delay input signal D3: Fourth delay input signal D4: Fifth delay input signal D5: Sixth delay input signal DUMP_MODE: Dump mode signal EO: Encoding signal GND: Ground KEY_0: First-stage key KEY_CAP: Input key signal KEY_CAP [D0:D5]: Input key KEY_COMP: Comparison key signal KEY_REF: Reference key signal KEY_SEL: Key selection signal LO: Linear signal MAP_SEL: Mapping selection signal OSO1, SR_A [3:0]: First scan output signal OSO2, SR_B [3:0]: Second scan output signal OSO_SEL, PSO: Scan output signal P1, P1': First pin P2, P2': Second pin P3, P3': Third pin P4: Fourth pin P / F: Verification result signal S310, S320, S330, S340, S350, S360, S370, S380: Operations SC: Scan control signal SDE: Scan dump enable signal SE_1: First scan enable signal SE_2: Second scan enable signal SI: Scan input terminal SO: Scan output terminal SSO: Secure scan output signal STG: Step signal STG1: First stage STG2: Second stage STG3: Third stage SYS_nRESET: System reset signal TCK, TCK_CHIP, TCK_KC, TCK_SKI, TCK_SR: Test clock signal TCK_1, TCK_1 [r-1:0], TCK_11, TCK_12, TCK_13, TCK_14: First clock signal TCK_2, TCK_2 [r-1:0], TCK_21, TCK_22, TCK_23, TCK_24: Second clock signal TMS: Test mode signal TSI: Test scan input signal TSI_KEY: Test key signal TSI_TD: Test data

Claims

1. A semiconductor integrated circuit configured to receive a test scan input signal, a test clock signal, and a test mode signal from an external source and to output a safe scan output signal, the semiconductor integrated circuit comprising: A secure key circuit is configured to generate multiple delayed input signals, each delayed differently from the test scan input signal, based on the test scan input signal, and to generate an input key signal by capturing the multiple delayed input signals in response to the test clock signal; a key comparator is configured to generate a verification result signal indicating whether the input key of the input key signal is the same as a preset reference key; a chip is configured to generate a scan output signal based on the test scan input signal; and a scan output remapping unit is configured to obfuscate the scan output signal according to the verification result signal and output the obfuscated scan output signal as the secure scan output signal. And a security scan controller, configured to control the security key circuit, the key comparator, the chip, and the scan output remapping unit.

2. The semiconductor integrated circuit of claim 1, wherein the secure scan controller is further configured to provide the test scan input signal and the test clock signal to the secure key circuit, and each of the plurality of delayed input signals has a first logic value or a second logic value different from the first logic value, and the secure key circuit is further configured to generate the logic value of the plurality of delayed input signals as the input key signal at the rising edge of the test clock signal.

3. The semiconductor integrated circuit of claim 1, wherein the security scan controller is further configured to provide a reference key signal and the test clock signal to the key comparator, and the key comparator is further configured to provide a signal indicating a pass status as the verification result signal to the scan output remainder when the input key is the same as the preset reference key, and to provide a signal indicating a failure status as the verification result signal to the scan output remainder when the input key is different from the preset reference key.

4. The semiconductor integrated circuit of claim 3, wherein the security scan controller is further configured to count a phase corresponding to the number of times the plurality of delayed input signals are captured when the plurality of delayed input signals are captured, and to provide one of a plurality of pre-stored keys corresponding to the counted phase as the preset reference key to the key comparator.

5. The semiconductor integrated circuit of claim 3, wherein the key comparator is further configured to provide a comparison key signal to the scan output remapping unit when the input key is different from the preset reference key, and the scan output remapping unit is further configured to generate obfuscation information for obfuscating the scan output signal based on the comparison key signal and obfuscate the scan output signal according to the obfuscation information.

6. The semiconductor integrated circuit of claim 1, wherein the scan output remapper is further configured to output an unobfuscated scan output signal as the secure scan output signal when the verification result corresponding to the verification result signal is passed.

7. A semiconductor integrated circuit configured to receive a test scan input signal, a test clock signal, and a test mode signal, and to output a safe scan output signal, the semiconductor integrated circuit comprising: A secure key circuit includes N delay circuits and N flip-flops, wherein the N delay circuits are configured to receive the test scan input signal and output N delayed input signals that are delayed differently from the test scan input signal, and the N flip-flops are configured to latch the logic values ​​of the N delayed input signals and output an input key signal including the latched logic values, where N is an integer greater than or equal to 1; a key comparator is configured to output a verification result signal indicating whether the input key of the input key signal is the same as a preset reference key; a chip is configured to generate a scan output signal based on the test scan input signal; and a scan output remapping unit is configured to obfuscate the scan output signal in response to the verification result signal and output the obfuscated scan output signal as the secure scan output signal. And a security scan controller, configured to control the security key circuit, the key comparator, the chip, and the scan output remapping unit.

8. The semiconductor integrated circuit of claim 7, wherein the secure scan controller is further configured to provide the test scan input signal to the N delay circuits and the test clock signal to the N flip-flops, and each of the N flip-flops is further configured to latch the logic value of the N delay input signals at the rising edge of the test clock signal.

9. The semiconductor integrated circuit of claim 8, wherein at least one of the N delay circuits includes one or more buffers, and the number of buffers included in the i-th delay circuit of the N delay circuits is different from the number of buffers included in the j-th delay circuit of the N delay circuits, where i is an integer less than or equal to N, and j is different from i and is an integer less than or equal to N.

10. The semiconductor integrated circuit of claim 9, wherein one of the N delay circuits does not include a buffer and is configured to input the test scan input signal to a flip-flop among the N flip-flops corresponding to the one delay circuit.

11. The semiconductor integrated circuit of claim 7, wherein the security scan controller comprises: A stage counter is configured to output the counted stage by counting the number of times the logic values ​​of the N delayed input signals are latched, and to output a comparison signal indicating a comparison operation when the stage is being counted; a key selector is configured to provide the key comparator with a key selected from a plurality of pre-stored keys according to the counted stage in response to the stage signal. And a first logic product gate, configured to perform a logic product operation on the comparison signal and the test clock signal and provide the result of the logic product operation to the key comparator.

12. The semiconductor integrated circuit as claimed in claim 11, further comprising: A programmable memory is configured to provide a key selection signal indicating a pre-stored number of authentication keys to the key selector, wherein the plurality of pre-stored keys includes stage keys corresponding to stages and a set of authentication keys corresponding to the number of pre-stored authentication keys, and the key selector includes: a first multiplexer configured to output a stage key selected from the stage keys according to the stage signal; and a second multiplexer configured to output the selected stage key and a key selected from the set of authentication keys according to the key selection signal as the preset reference key.

13. The semiconductor integrated circuit of claim 7, wherein the security scan controller is further configured to provide the test clock signal to the scan output remapping unit, and the key comparator is further configured to provide a comparison key signal to the scan output remapping unit, wherein the scan output remapping unit comprises: The remapping controller is configured to transmit the scan output signal to output a first clock signal and a second clock signal based on the test clock signal and the comparison key signal, and to output a first scan enable signal. An inverter is configured to invert the first scan enable signal to output a second scan enable signal; a first register group is configured to latch the scan output signal in response to the first scan enable signal and the first clock signal, and output the latched first scan output signal; a second register group is configured to latch the scan output signal in response to the second scan enable signal and the second clock signal, and output the latched second scan output signal; a first selector is configured to select one of the latched first scan output signal and the latched second scan output signal according to the second scan enable signal; And a second selector, configured to output, based on the verification result signal, one of the scan output signal selected by the first selector and the scan output signal from the remapping controller as the security scan output signal.

14. The semiconductor integrated circuit of claim 13, wherein the first register group comprises r first flip-flops cascaded in series, and the first register group comprises r second flip-flops cascaded in series, wherein r is an integer greater than or equal to 1.

15. The semiconductor integrated circuit as claimed in claim 13, wherein the first selector is a multiplexer and the second selector is a multiplexer.

16. A method for testing semiconductor integrated circuits, the method comprising: The test scan input signal is changed into multiple delayed input signals with different delay values; An input key signal is generated by obtaining the values ​​of the plurality of delayed input signals in response to the test clock signal; the input key signal based on the input key signal is verified to be the same as a preset reference key; and the scan output signal output from the chip under test is obfuscated based on the verification result.

17. The method of claim 16, wherein each of the plurality of delayed input signals has a first logic value or a second logic value different from the first logic value, and generating the input key signal includes generating the logic value of the plurality of delayed input signals as the input key signal at the rising edge of the test clock signal.

18. The method of claim 16, wherein the verification includes outputting a signal indicating a pass status when the input key is the same as the preset reference key, and outputting a signal indicating a failure status when the input key is different from the preset reference key.

19. The method of claim 18 further includes outputting an unobfuscated scan output signal as a security scan output signal when the signal indicating the pass status is output.

20. The method of claim 18, further comprising, when outputting the signal indicating the failure state, outputting an obfuscated scan output signal as a secure scan output signal.

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