Transistors with reduced epitaxial source / drain span via etch-back for improved cell scaling

Abstract

Regarding the reduced lateral source-drain span in the manufactured transistors, methods, transistors, and systems related to anisotropic etch-back deposition of epitaxial source and drain semiconductor materials are discussed. This reduction in the lateral width of the source and drain materials results in improved transistor scaling and perturbation reduction in the resulting source and drain semiconductor materials.

Description

Technical Field

[0001] This disclosure relates to a transistor with reduced epitaxial source / drain span that improves cell scaling via etchback. Prior Technology

[0002] Transistor cell density is a crucial characteristic in integrated circuits because increased cell density improves device capabilities. Due to the ever-increasing demand for higher transistor densities, there is a need to reduce the lateral spacing between transistors for closer N-to-P (NP), N-to-N (NN), and P-to-P (PP) transistor spacing. This increase in transistor density necessitates a reduction in the lateral epitaxial span between the transistor source and drain (EPI S / D). Furthermore, such a reduction in spacing requires a manufacturable process flow to achieve. Ideally, this process flow should, for example, eliminate the need for barriers or molds to restrict the epitaxial source and drain of the scaled-down transistors. The desired outcome is to increase transistor cell density while providing high-quality epitaxial sources and drains in a manufacturable process flow. Existing improvements regarding these and other considerations are needed. Such improvements can become critical to increasing cell density in higher-performance integrated circuit electronic components. Summary of the Invention

[0003] and Simple Explanation of the Diagram

[0004] The materials described herein are illustrated in the accompanying drawings as examples, not as limitations. For simplicity and clarity of illustration, the elements shown are not necessarily drawn to scale. For instance, the dimensions of some elements may be exaggerated relative to others for clarity. Furthermore, reference numerals in the drawings have been repeated where deemed appropriate to indicate corresponding or similar elements. In the figures: [Figure 1A] provides a visual diagram of an example transistor with reduced-width source and drain semiconductors; [Figure 1B] provides a visual representation of the transistor structure of Figure 1A obtained at the interface between the example source and drain materials and the channel semiconductor; [Figure 2] A flowchart illustrating the process of fabricating a transistor structure with etch-back epitaxial source and drain materials; [Figures 3, 4, 5, 6, 7, 8, 9, and 10] illustrate cross-sectional side views of exemplary transistor structures in which specific manufacturing operations are performed to produce reduced-width source and drain semiconductors; [Figure 11] is a schematic diagram of a mobile computing platform employing a device with an epitaxial (Epi) source and / or drain (S / D) transistor; and [Figure 12] is a functional block diagram of a computing device configured according to at least some embodiments of the present disclosure. Implementation

[0005] One or more embodiments or implementations are described with reference to the accompanying drawings. Although specific configurations and arrangements are discussed, it is understood that they are for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of this description. It will be apparent to those skilled in the art that the techniques and / or arrangements described herein can also be used in a wide variety of other systems and applications besides those described herein. References to the following detailed description of the accompanying drawings are made in connection with this point, wherein similar numerals indicate similar portions throughout to indicate corresponding or similar elements. It should be understood that, for the sake of simplicity and / or clarity of the examples, the elements shown in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be enlarged relative to others for clarity. Furthermore, it is understood that other embodiments may be used, and structural and / or logical changes may be made without departing from the scope of the claimed subject matter. It should also be noted that directions and references, such as up, down, top, bottom, above, below, etc., may be used to enhance the discussion of the drawings and embodiments, and are not intended to limit the application of the claimed subject matter. Therefore, the following detailed description is not intended to limit the concepts and scope of the claimed subject matter as defined by the appended claims and their equivalents. In the following description, numerous details are set forth. However, it will be apparent to those skilled in the art that the invention may be practiced without these specific details. In some instances, known methods and apparatus are shown in block diagram form rather than in detail to avoid obscuring the invention. Throughout this specification, reference to "embodiment" or "an embodiment" means that a particular feature, structure, function, or characteristic described in connection with an embodiment is included in at least one embodiment of the invention. Therefore, the phrase "in an embodiment" or "in an embodiment" appearing throughout this specification does not necessarily refer to the same embodiment of the invention. Furthermore, a particular feature, structure, function, or characteristic may be combined in any suitable form in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere, and the particular features, structures, functions, or characteristics associated with these two embodiments are not mutually exclusive. The singular forms such as “a,” “an,” and “the” used in the description of this invention and the appended claims are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein means and covers any and all possible combinations of one or more related listed items. The terms “coupled” and “connected,” and their derivatives, are used herein to describe structural relationships between components. It should be understood that these terms are not intended to be synonymous with each other. Rather, in certain embodiments, “connected” can be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” can be used to indicate that two or more elements are in physical or electrical contact with each other, either directly or indirectly (with other intermediate elements between them), and / or that two or more elements cooperate or interact with each other (e.g., in a causal relationship, an electrical relationship, a functional relationship, etc.). As used herein, the terms "over," "under," "between," and "on" refer to the relative position of a material layer or component with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with the other layers or may have one or more intermediate layers. Furthermore, a layer disposed between two layers may be in direct contact with the two layers or have one or more intermediate layers. In contrast, a first layer "on" a second layer is in direct contact with the second layer. Similarly, unless explicitly stated otherwise, a feature disposed between two features may be in direct contact with an adjacent feature or have one or more intermediate features. The term "directly adjacent" indicates that these features are in direct contact. Furthermore, the terms "substantially," "near," "proximately," "close to," and "about" generally refer to within + / - 10% of the target value. The term "layer" as used herein may include a single material or multiple materials. Throughout this specification and the claims, a series of terms beginning with "at least one of..." or "one or more of..." may refer to any combination of the listed terms. For example, the phrase "at least one of A, B or C" may refer to A; B; C; A and B; A and C; B and C; or A, B and C. The transistor structures, component structures, devices, integrated circuits, computing platforms, and methods described herein relate to transistors that reduce the epitaxial source and / or drain spans of scaling units. These transistors have source and / or drain widths that are reduced by etch-back after epitaxial deposition of the source and / or drain. The desired outcome of this discussion is to increase transistor cell density by maintaining high-quality transistors, including high-quality epitaxial source and drain electrodes, throughout the manufacturing process. Specifically, this increase in cell density is achieved by reducing the epitaxial source and / or drain span (e.g., lateral width) while maintaining source and / or drain height (e.g., vertical height). Thus, while maintaining low contact resistance, high drive current, and other transistor characteristics, the transistor cell density can be increased when the transistors can be packaged more tightly laterally (e.g., perpendicular to the fin direction). This transistor structure can be achieved by performing anisotropic etchback after epitaxial deposition (or growth) of the source and drain electrodes. This etchback can be performed after the entire source and drain material has been deposited, or in a multi-stage manner, such as partial deposition of source and drain material, first etchback performed, another portion of source and drain material deposited, second etchback performed, etc. Such processing can be performed, for example, two, three, four, or more etchbacks. The deposition before and between etch can utilize different source and drain materials, the same material, or these materials can be altered during the etch. In some embodiments, the techniques discussed herein utilize in-situ epitaxial deposition and etch-back, developed to provide anisotropic etching that etches the vertical (110) planes (e.g., sidewall surfaces) of the source and drain semiconductor materials at a faster rate than horizontal (001) planes (e.g., top and bottom surfaces, if exposed). Furthermore, this etch-back trims the {111} facets of the semiconductor source and drain materials to provide smoother sidewall surfaces. This etch-back can be performed immediately after the deposition (e.g., epitaxial growth of the source and drain materials) in the same processing chamber. Figure 1A is a visual diagram of an example transistor structure 100 with reduced-width source and drain semiconductors provided according to at least some embodiments of the present disclosure. Figure 1A illustrates a first cross-sectional view 131 of the transistor structure 100 cut along the fins, such that the source 112 and the isolation spacer layer 102 on the substrate 101 are visible. A second cross-sectional view 132 of the transistor structure 100 is cut along the gate, such that the channel semiconductor 109, the source 112, and the drain 113 are visible, along with other components of the transistor structure 100 discussed below. For example, the second cross-sectional view 132 is provided as a view cut through the first cross-sectional view 131 along A-A'. Furthermore, numerous fin structures (e.g., including a dummy gate 104, an isolation layer 103, a dummy gate oxide 110, a channel semiconductor 109, a sacrificial layer 108, etc.) may be provided along an x-axis having a shared source 112 and / or drain 113. As the lateral widths of the source 112 and drain 113 are reduced, the technique discussed herein provides a reduced gap along the y-axis of the transistor structure 100. Transistor structure 100 includes a substrate 101, an isolation spacer layer 102, an isolation layer 103, a dummy gate 104, source and drain materials 105 constituting source 112 and drain 113, a channel semiconductor 109, a sacrificial layer 108, and a dummy gate oxide 110. As shown, the source and drain materials 105 include a doped epitaxial nucleation layer 107 and a doped epitaxial host layer 106. The source and drain materials 105 may further include a capping layer as discussed below. The substrate 101 may comprise any suitable material or multiple materials, and in some embodiments, the substrate 101 comprises one or more materials having the same or similar composition as respect to the channel semiconductor 109. In some embodiments, the substrate 101 and the channel semiconductor 109 comprise Group IV materials (e.g., silicon). In some embodiments, the substrate 101 and the channel semiconductor 109 comprise substantially single-crystal materials. In some embodiments, the substrate 101 comprises, for example, a semiconductor-on-insulator (SOI) substrate and / or an insulating region and a buried insulating layer (e.g., silicon dioxide). The channel semiconductor 109 may comprise a plurality of channel semiconductors, strips, or layers, such as three, four, or more layers, on the substrate 101. The channel semiconductor 109 is separated by a sacrificial layer 108, which will subsequently be removed and replaced by one or more gate structures comprising, for example, a gate dielectric material and a gate electrode material. Similarly, the dummy gate oxide 110, dummy gate 104, and isolation layer 103 can be removed last and replaced by gate dielectric and gate electrode materials. In particular, FIG. 1A shows a transistor structure 100 that can be further processed to form a functional element, as discussed below. As shown, the transistor structure 100 includes source and drain materials 105, which include a doped epitaxial nucleation layer 107 and a doped epitaxial host layer 106. The source and drain materials 105 may also include a doped capping layer on the doped epitaxial host layer 106 (see FIG. 9). The source and drain materials 105 are epitaxially oriented onto the channel semiconductor 109 such that they are epitaxially deposited on or grown from the channel semiconductor 109 and have epitaxial crystallinity to the channel semiconductor 109. For example, the source and drain materials 105 and the channel semiconductor 109 can share the crystal lattice structure from which the source and drain materials 105 are epitaxially grown. As discussed, the source and drain materials 105 may comprise a single layer, a double layer (as shown in FIG. 1A), or a triple layer (as shown in FIG. 9), or an additional layer of doped semiconductor material coupled to the channel semiconductor 109. In some embodiments, the source and drain materials 105 comprise a double layer of doped epitaxial nucleation layer 107 and doped epitaxial host layer 106. Such a layer may also be simply characterized as a doped epitaxial material or a material layer. In some embodiments, both the doped epitaxial nucleation layer 107 and the doped epitaxial host layer 106 are phosphorus- and / or arsenic-doped silicon (e.g., (P,As):Si N-Epi). In some embodiments, the doped epitaxial nucleation layer 107 is silicon doped with phosphorus and arsenic concentrations in the range of 1E19 to 1E21 cm⁻³. As discussed, either or both of phosphorus and arsenic may be used advantageously in some environments. In some embodiments, the doped epitaxial host layer 106 is silicon doped with phosphorus and arsenic concentrations ranging from 1E19 to 5E21 cm⁻³. In some embodiments, the doped epitaxial host layer 106 is silicon doped with phosphorus and arsenic concentrations ranging from 3E21 to 5E21 cm⁻³ (e.g., with concentrations exceeding 5E21 cm⁻³). In some embodiments, the source and drain materials 105 include a doped epitaxial nucleation layer 107, a doped epitaxial host layer 106, and a doped epitaxial capping layer on the doped epitaxial host layer 106. In some embodiments, such as a bilayer example, both the doped epitaxial nucleation layer 107 and the doped epitaxial host layer 106 are phosphorus- and / or arsenic-doped silicon (e.g., (P,As):Si N-Epi). In some embodiments, the doped epitaxial nucleation layer 107 is silicon doped with phosphorus and arsenic concentrations in the range of 1E19 to 1E21 cm⁻³, and the doped epitaxial host layer 106 is silicon doped with phosphorus and arsenic concentrations in the range of 1E21 to 5E21 cm⁻³, and in some environments, a concentration range of 3E21 to 5E21 cm⁻³ is advantageous. In some embodiments, the doped epitaxial capping layer is silicon doped only with phosphorus (e.g., lacking arsenic) at a concentration not less than 3E21 cm⁻³. In some embodiments, the doped epitaxial capping layer is silicon doped only with phosphorus (e.g., lacking arsenic) at a concentration of about 5E21 cm⁻³ (e.g., within 10% of 5E21 cm⁻³). In some embodiments, a monolayer of doped epitaxial source and drain materials is used. For example, the monolayer may comprise silicon doped with phosphorus and arsenic concentrations in the range of 1E19 to 1E21 cm⁻³. In some embodiments, the layers in question of the source and drain materials 105 are not separate layers but are configured with similar slopes. In this context, the layers in question may be clearly seen as sampling layers or regions detached from the channel semiconductor in the source and drain materials 105. For example, the concentrations in question may be found within the regions or portions of the source and drain materials 105 represented by the illustrated layers. In some embodiments, the source and drain materials 105 include a doped epitaxial nucleation layer 107 (or corresponding portion or region) on or adjacent to the channel semiconductor 109, and a doped epitaxial host layer 106 (or corresponding portion or region) on or adjacent to the doped epitaxial nucleation layer 107, such that the doped epitaxial nucleation layer region or portion has a lower doping concentration than the doped epitaxial host layer region or portion. For example, the channel semiconductor 109 (such as [phosphorus] or [arsenic] or both) moving toward the channel semiconductor 109 in the positive or negative x direction may be reduced in the source and drain materials 105. Figure 1B is a visual diagram 111 of a transistor structure 100 provided according to at least some embodiments of the present disclosure, taking its contents from the interface between the source and drain materials 105 and the channel semiconductor 109. As shown in Figure 1B, for clarity, the source and drain materials 105 are depicted as a single material. As shown, the visual diagram 111 is along a transverse dimension or axis 114 aligned with the y-axis. Clearly, the transverse axis 114 is substantially perpendicular to the dimension or axis 115, which extends along the channel semiconductor 109 between the source 112 and drain 113 and is aligned with the x-axis (see Figure 1A). For example, axis 115 may be along the current flowing through the transistor structure 100 during operation and may be along a predetermined channel length of the transistor structure 100. Clearly, the transverse axis 114 is substantially perpendicular to axis 115 and parallel to the surface 133 of the substrate 101. The horizontal axis can also be perpendicular to the stacking direction of the transistor structure 100, which has an establishment direction defined along the z-axis. This surface 133 is substantially parallel to the xy-plane established here, and the establishment direction is substantially perpendicular to the xy-plane. The techniques discussed below describe anisotropic etchback and / or modifications to the deposited source and drain materials to provide the source and drain materials 105 illustrated in Figures 1A and 1B, as well as other source and drain material examples shown herein. Clearly, anisotropic etchback reduces the lateral width of the deposited source and drain materials and reduces disturbance along the vertical sidewalls with minimal or no etchback to provide the vertical height of the deposited source and drain materials. This technique can provide one or more of an increased aspect ratio of the source and drain materials 105, a reduced dimensional difference in the width of the source and drain materials 105, and a reduced wingspan of the source and drain materials 105. Clearly, the wingspan of the source and drain materials 105 can be defined as the lateral width of the source and drain materials 105 measured relative to the lateral width of the channel semiconductor 109, such that these lateral widths are along the lateral axis 114 as defined above. For example, as discussed, transistor structure 100 (and other transistor structures discussed herein) includes a channel semiconductor 109 on substrate 101 and between source 112 and drain 113, such that source 112 and drain 113 are epitaxial to channel semiconductor 109. As shown, channel semiconductor 109 has a lateral width X1. As defined herein, lateral width is a lateral dimension along a substantially perpendicular axis 115 extending between the source and drain of the transistor, and the term lateral also indicates that axis 115 is substantially parallel to surface 133, the xy plane, and the established add-on plane (e.g., a plane perpendicular to the add-on direction along the z-axis). Lateral width X1 can be any suitable dimension, for example, a lateral width in the range of 10 to 50 nm. Lateral width X1 can be shared by sacrificial layer 108 and ultimately by gate structures replacing sacrificial layer 108. The lateral width X1 and other measurements discussed herein may be performed using any suitable technique, such as a single measurement (e.g., located at the vertical midpoint of a single channel semiconductor 109) or an average of several measurements (e.g., located at several points along a single channel semiconductor 109, at a single point of several or all channel semiconductors 109, or at several points along several or all channel semiconductors 109). As shown, source 112 and / or drain 113 have a lateral width X3, such that the lateral width is defined as described above. Furthermore, source 112 and / or drain 113 include a portion 116 extending further from the lateral width X1 of channel semiconductor 109. This portion 116 can be defined as a wing or similar. One or both portions 116 have a lateral width X2, such that the lateral width X2 defines the dimension by which source 112 and / or drain 113 extend further from the lateral width of channel semiconductor 109. This lateral width X3 can be defined, for example, by vertical sidewall surfaces 121, 122, and then the lateral width X2 can be defined as half the difference between lateral width X3 and lateral width X1 (e.g., (X3-X1) / 2) or a measurement of either vertical sidewall surface 121, 122 to channel semiconductor 109. The lateral width X3 can be any suitable dimension, for example, a lateral width in the range of 20 to 60 nm. In some embodiments, the lateral width X3 is in the range of 30 to 50 nm. In some embodiments, the lateral width X3 is in the range of 30 to 40 nm. In some embodiments, the lateral width X3 is in the range of 20 to 30 nm. As discussed, to increase the cell density of transistor structure 100, the source 112 and / or drain 113 have reduced lateral widths. In some embodiments, the wingspan (or lateral span or simple span) can be defined as the ratio of lateral width X2 to lateral width X1 (e.g., X2 / X1), characterized by the ratio of the lateral width of the source and / or drain extending outward from channel semiconductor 109 to the lateral width of channel semiconductor 109. This parameter is characterized by the wingspan ratio described herein. In some embodiments, without etch-back as discussed below, the wingspan ratio is approximately 60%, which is disadvantageous for transistor cell scaling along the lateral axis 114. In contrast, transistor structure 100 has a significantly reduced wingspan ratio. In some embodiments, the wingspan ratio (e.g., X2 / X1) of transistor structure 100 is no more than one-half. In some embodiments, the wingspan ratio (e.g., X2 / X1) of transistor structure 100 is no more than one-third. In some embodiments, the wingspan ratio (e.g., X2 / X1) of the transistor structure 100 is no more than one-quarter. In some embodiments, the wingspan ratio (e.g., X2 / X1) of the transistor structure 100 is no more than one-fifth. In some embodiments, the wingspan ratio (e.g., X2 / X1) of the transistor structure 100 is in the range of 0.15 to 0.5 (e.g., 20% to 50%). In some embodiments, the wingspan ratio (e.g., X2 / X1) of the transistor structure 100 is in the range of 0.15 to 0.35. In some embodiments, the wingspan ratio (e.g., X2 / X1) of the transistor structure 100 is in the range of 0.15 to 0.25. Other wingspan ratios below approximately 50-60% may be configured. Alternatively, source 112 and / or drain 113 may have an increased aspect ratio relative to source and drain material 105 deposited by anisotropic etchback not discussed herein. In some embodiments, the vertical height Y1 (e.g., along the z-axis) of source 112 and / or drain 113 may be defined or measured as discussed above with respect to lateral widths X1, X2, X3. In some embodiments, the ratio of vertical height Y1 to lateral width X3 of source 112 and / or drain 113 is not less than 2. In some embodiments, the ratio of vertical height Y1 to lateral width X3 of source 112 and / or drain 113 is not less than 2.1. In some embodiments, the ratio of vertical height Y1 to lateral width X3 of source 112 and / or drain 113 is not less than 2.25. Other aspect ratios of source 112 and / or drain 113 of not less than 2.0 may be used. Furthermore, or alternatively, the source 112 and / or drain 113 may have reduced variability in the lateral width X3 along the z-dimensional dimension due to the smoothed surfaces formed during epitaxial growth during the etch-back process. For example, significant perturbations along sidewall surfaces 121, 122 may be removed during this etch-back process. In some embodiments, any measurement of the lateral width X3 between sidewall surfaces 121 and 122 (e.g., along the lateral dimension or axis 114) is indistinguishable at a value not exceeding 12 nm. In some embodiments, any measurement of the lateral width X3 between sidewall surfaces 121 and 122 (e.g., along the lateral dimension or axis 114) is indistinguishable at a value not exceeding 10 nm. In some embodiments, any measurement of the lateral width X3 between sidewall surfaces 121 and 122 (e.g., along the lateral dimension or axis 114) is indistinguishable at a value not exceeding 8 nm. In some embodiments, any measurement of the lateral width X3 between sidewall surfaces 121 and 122 (such as measurements along the lateral dimension or axis 114) is indistinguishable at a value not exceeding 5 nm. Other measurements of variability may also be implemented. In some embodiments, the variability of measurements of the lateral width X3 between sidewall surfaces 121 and 122 that are not less than 5 is not more than 20% of the average of the lateral width X3 measurements. In some embodiments, the variability of measurements of the lateral width X3 between sidewall surfaces 121 and 122 that are not less than 5 is not more than 15% of the average of the lateral width X3 measurements. In some embodiments, the variability of measurements of the lateral width X3 between sidewall surfaces 121 and 122 that are not less than 5 is not more than 10% of the average of the lateral width X3 measurements. Figure 2 is a flowchart illustrating a configuration according to at least some embodiments of the present disclosure, showing an exemplary process 200 for fabricating a transistor having etch-back epitaxial source and drain materials. For example, process 200 can be implemented to fabricate transistor structure 100 or any other transistor structure discussed herein. In the example embodiment, process 200 includes one or more operations as shown in operations 201-207. However, embodiments herein may include additional operations, specific operations that are omitted, or operations in a sequence other than those provided herein. In one embodiment, process 200 may fabricate transistor structure 100 or a similar transistor structure having different etch-back epitaxial source and drain materials discussed herein with respect to Figures 3-10. Figures 3, 4, 5, 6, 7, 8, 9, and 10 show cross-sectional side views of exemplary transistor structures configured according to at least some embodiments of this disclosure as being performed to produce specific manufacturing operations for reducing the width of the source and drain semiconductors. In particular, the numbers for Figures 3, 4, 5, 6, 7, 8, 9, and 10 are generated within process 200. Process 200 begins at operation 201, where a transistor structure working piece is received for processing. For example, NMOS and / or PMOS transistor structures may be formed within, on, and / or on a substrate. The substrate may include any suitable substrate such as a silicon substrate or the like. The NMOS and PMOS transistor structures may be planar, multi-gate, or gate-around transistor structures formed using known techniques. In the gate-around example, a multilayer structure including alternating layers of channel semiconductors and sacrificial material layers may be deposited and patterned. Sidewall structures and sacrificial gate structures (such as those including sacrificial gate oxide, sacrificial or dummy gates, and isolation layers) may then be formed as known. Referring now to Figure 3, the exemplary receiving transistor structure 300 (such as a transistor structure workpiece) includes a substrate 101, an isolation spacer layer 102 (including portions on the sacrificial layer 108 and optional portions between the substrate 101 and the remaining material of the structure), an isolation layer 103, a dummy gate 104, a dummy gate oxide 110, the sacrificial layer 108, and a channel semiconductor 109. The transistor structure 300 can be fabricated using any suitable one or more techniques. As shown in both cross-sectional views 131 and 132, portions of the channel semiconductor 109 are exposed for the growth of epitaxial source and drain materials. Returning to Figure 2, the process continues in operation 202, where the epitaxial source and drain materials are deposited by growth from exposed sites on the channel semiconductor. The epitaxial source and drain materials can be deposited using any suitable one or more techniques, such as chemical vapor deposition including doped materials. As shown with respect to in-situ operation 211, operations 202-205 can be performed sequentially in the same processing chamber such that, for example, the workpiece (e.g., a wafer) is not removed from the chamber during these operations. Furthermore, operation 211 shows that deposition and etch-back can each be performed once (e.g., following operation 202 with operation 203, then proceeding directly to operation 206) or multiple times (e.g., following operation 202 with operation 203, then operation 204 is followed by operation 205, then any number of repetitions of this operation before proceeding to operation 206). In some embodiments, operation 202 includes the deposition of one, two, three, or more layers of doped epitaxial source and drain materials prior to etchback. In some embodiments, two layers are deposited or grown: a doped epitaxial nucleation layer and a doped epitaxial host layer, as depicted in FIG4. For example, the doped epitaxial nucleation layer may be formed on the channel semiconductor and the doped epitaxial host layer may be formed on the doped epitaxial nucleation layer, such that the doped epitaxial host layer has a higher doping concentration than the doped epitaxial nucleation layer. In some embodiments, three layers are deposited or grown: a doped epitaxial nucleation layer, a doped epitaxial host layer, and a doped epitaxial capping layer. For example, the doped epitaxial nucleation layer may be formed on the channel semiconductor, the doped epitaxial host layer may be formed on the doped epitaxial nucleation layer such that the doped epitaxial host layer has a higher doping concentration than the doped epitaxial nucleation layer, and the doped epitaxial capping layer may be formed on the doped epitaxial host layer such that the doped epitaxial capping layer has a unique phosphorus doping concentration. Figure 4 shows an exemplary transistor structure 400 configured according to at least some embodiments of the present disclosure, illustrating a transistor structure 300 after epitaxial growth similar to the source and drain materials 401. As shown, the source and drain materials 401 include a doped epitaxial nucleation layer 107 and a doped epitaxial host layer 402 with perturbations, such that the source and drain materials 401 have relatively non-uniform outer surfaces. In particular, the source and drain materials 401 discussed are doped epitaxial semiconductors, such as silicon doped with phosphorus and arsenic having a top surface 404 (and a bottom surface, unlabeled) along a crystal (001) plane, side surfaces 403, 413 along a crystal (110) plane, and {111} planes 405 intersecting the crystal planes. For example, a plane formed at an angle of approximately 55 degrees between the (111) plane and the (001) plane and at an angle of approximately 35 degrees between the (111) plane and the (110) plane. As shown, the source and drain materials 401 have a maximum lateral width X4 and a maximum lateral height Y2. Returning to Figure 2, the process continues to operation 203, where the deposited or grown epitaxial material is etched back using anisotropic gas chemical etching. Specifically, the gas chemical etching is configured to provide anisotropy such that vertical surfaces (e.g., the crystal (110) plane) are etched at a much faster rate than horizontal surfaces (e.g., the crystal (001) plane). This reduces the width of the deposited epitaxial material at a rate much greater than its height. Furthermore, faces (e.g., the {111} face) are etched at a higher rate, particularly smoothing out the vertical sidewalls. For example, these faces are high-energy etch points or locations that are etched more rapidly than the crystal (110) plane. As discussed, operation 203 can be performed in place with respect to operation 202. To achieve this anisotropic etching characteristic of the phosphorus and / or arsenic-doped epitaxial silicon, etching chemicals including hydrochloric acid (HCl) and one or more of silanes, phosphanes, and germanes are prepared at elevated temperatures, such as those in the range of 500 to 800°C. In some embodiments, the etching is performed at a temperature not lower than 700°C. In particular, chlorine is a necessary etchant, which can be advantageously prepared with gaseous HCl, while silanes, phosphanes, and germanes can be used in any combination. In some embodiments, all three of the silanes, phosphanes, and germanes are prepared. In some embodiments, when germanes are prepared alone or in combination with one or both of silanes and phosphanes, germanes can act as an etchant that reduces the etching rate, thereby lowering the temperature. In some embodiments, when germanes are prepared, the etching temperature is in the range of 500 to 650°C. As discussed, any combination of silane, phosphine, and germane can be used with gaseous HCl. In some embodiments, gas chemical etching is performed using HCl with silane lacking both phosphine and germane. In some embodiments, gas chemical etching is performed using HCl with phosphine lacking both silane and germane. In some embodiments, gas chemical etching is performed using HCl with silane lacking both germane and phosphine. For example, such etching can be performed at temperatures ranging from 600 to 800°C, for example, within the range of 650 to 750°C. In some embodiments, gas chemical etching is performed using HCl with germane lacking both silane and phosphine. In some embodiments, gas chemical etching is performed using HCl with germane comprising either silane or phosphine. For example, such etching can be performed at temperatures ranging from 500 to 650°C, for example, within the range of 600 to 650°C. Furthermore, in the use of any combination of silane, phosphine, and germane with HCl, the flow rate can be controlled to achieve and / or enhance the desired anisotropy. In some embodiments, the ratio of HCl flow rate to hydride (such as one or more of silane, phosphine, and germane) is in the range of 1 to 10. In particular, an HCl to hydride flow rate ratio of not more than 10 can achieve the desired anisotropy and surface etching to achieve high uniformity and near-cubic source and drain semiconductors. Furthermore, it should be noted that this gas chemical etching can be performed at low or high temperatures while maintaining the desired anisotropy and surface etching characteristics. Figure 5 shows an exemplary transistor structure 500 configured according to at least some embodiments of this disclosure, illustrating a transistor structure 400 after etch-back similar to epitaxially grown source and drain materials 401. As shown, the source and drain materials 401 are etched back to provide source and drain materials 501 comprising a doped epitaxial nucleation layer 107 and a doped epitaxial host layer 106. In particular, the transistor structure 500 may have any of the features discussed with respect to transistor structure 100. As discussed, the anisotropic etching of the source and drain materials 401 is achieved by using chlorine (e.g., prepared as gaseous HCl) and one or more of silanes, phosphines, and germanes in a gas chemical etching process using temperatures in the range of 600 to 800°C at flow rates, for example, those discussed herein. As shown, the source and drain materials 501 have a reduced lateral width X5 relative to the lateral width X4 of the source and drain materials 401; however, due to the anisotropy of gas chemical etching, they have a vertical height Y2 that is substantially the same as the vertical height Y2 of the source and drain materials 401 (see Figure 4). Furthermore, the surfaces of the source and drain materials 401 and other disturbances in the formation of the source and drain materials 501 have been substantially removed. Returning to Figure 2, as discussed, in some embodiments, a single deposition (such as in operation 202) followed by a single etch-back deposition (such as in operation 203) can be used. In this embodiment, operations 204 and 205 can be bypassed. In other examples, repeated deposition / etch cycles can be implemented as shown with respect to optional deposition operation 204 and optional etch-back operation 205. In particular, operations 204 and 205 can be implemented using any of the techniques discussed with respect to operations 202 and 203. In some embodiments, epitaxial material deposition increases the doping concentration of a single material, etch-back is performed, and a second material deposition increases the doping concentration of another material, followed by optional etch-back, optionally followed by a third material deposition, followed by another optional etch-back. For example, it is advantageous to perform a back etching after the deposition of the doped epitaxial nucleation layer. For example, the deposition of the doped epitaxial nucleation layer can be highly non-uniform and the back etching can provide a conformal material layer so that the subsequent doped epitaxial layer does not need to be etched back. Figure 6 illustrates an exemplary transistor structure 600 after epitaxial growth, similar to a doped epitaxial nucleation layer 602, configured according to at least some embodiments of this disclosure. As shown, the doped epitaxial nucleation layer 602 can be formed epitaxially to the channel semiconductor 109 in a highly non-conformal manner. The doped epitaxial nucleation layer 602 can have any of the characteristics discussed herein related to the doped epitaxial nucleation layer 107. For example, the doped epitaxial nucleation layer 602 can be doped with one or both of phosphorus and arsenic at a concentration in the range of 1E19 to 1E21 cm⁻³, such as 5E20 cm⁻³. Furthermore, the doped epitaxial nucleation layer 602 can have a lower doping concentration than the subsequently formed doped epitaxial body layer. Similar to the source and drain materials 401, the doped epitaxial nucleation layer 602 is a doped epitaxial semiconductor, such as silicon doped with phosphorus and arsenic, having a top surface 604 (and a bottom surface, unlabeled) along the crystal (001) plane, side surfaces 603 and 613 along the crystal (110) plane, and a {111} plane 605 located at the intersection of the (111) plane and the crystal (110) plane. As also shown, the doped epitaxial nucleation layer 602 has a maximum lateral width X6 and a maximum lateral height Y3. As discussed in process 200, the deposition or growth of the epitaxial nucleation layer system utilizes anisotropic gas chemical etching followed by etch-back to provide anisotropy. Anisotropic etching etches vertical surfaces (e.g., sidewall surfaces) at a rate much faster than horizontal surfaces (e.g., top and bottom surfaces), causing the width of the synthesized doped epitaxial nucleation layer to be reduced at a rate much greater than its height. Furthermore, faces (e.g., the {111} face) are etched at a greater rate to their elimination. Figure 7 illustrates an exemplary transistor structure 700, configured according to at least some embodiments of the present disclosure, similar to a post-etch-back transistor structure 600 of a doped epitaxial nucleation layer 602. As shown, the doped epitaxial nucleation layer 602 is etched back to provide a doped epitaxial nucleation layer 702 such that the doped epitaxial nucleation layer 702 has a larger aspect ratio, smoother sidewalls, and a more cubic structure relative to the doped epitaxial nucleation layer 602. In particular, the doped epitaxial nucleation layer 702 can provide a conformal layer for the subsequent growth of the doped epitaxial body layer. Furthermore, the anisotropic etching of the doped epitaxial nucleation layer 602 is achieved by using chlorine (e.g., prepared as gaseous HCl) and one or more of silanes, phosphines, and germanes in a gas chemical etching process at a temperature in the range of 600 to 800°C and a flow rate, for example, that discussed herein. The anisotropic etching of the doped epitaxial nucleation layer 602 can be performed using any such gas chemical etching technique. As shown, the doped epitaxial nucleation layer 702 has a reduced lateral width X7 relative to the lateral width X6 of the doped epitaxial nucleation layer 602; however, due to the anisotropy of gas chemical etching, it has a vertical height Y3 substantially the same as the vertical height Y3 of the doped epitaxial nucleation layer 702 (see Figure 6). Furthermore, the surfaces of the doped epitaxial nucleation layer 602 and other disturbances have been substantially removed. As discussed in process 200, the second epitaxial growth or deposition may be performed using any suitable one or more techniques discussed in process 202. Figure 8 illustrates an exemplary transistor structure 800 after epitaxial growth, similar to a doped epitaxial body layer 802, configured according to at least some embodiments of this disclosure. As shown, due to the refinement of the doped epitaxial nucleation layer 702, the doped epitaxial body layer 802 can be formed in a highly conformal manner to provide substantially cubic material. The doped epitaxial body layer 802 may have any of the features discussed herein with respect to the doped epitaxial body layer 106. For example, the doped epitaxial body layer 802 may have a higher doping concentration than the doped epitaxial nucleation layer 702. In some embodiments, the doped epitaxial body layer 802 may be an etch-back as discussed herein to provide a greater aspect ratio, a smaller span, and / or to remove disturbances caused by the deposition of the doped epitaxial body layer 802. As discussed herein, a three-layer configuration of doped epitaxial source and drain materials can be constructed. This material can be deposited without etch-back between layers or between any of these deposited materials. Furthermore, additional doped epitaxial source and drain material layers can be used. Figure 9 illustrates an exemplary transistor structure 900 after epitaxial growth, similar to a doped epitaxial capping layer 902, according to at least some embodiments of this disclosure. The doped epitaxial capping layer 902 is shown to be deposited over the doped epitaxial body layer 802 and the doped epitaxial nucleation layer 702; however, the doped epitaxial capping layer 902 can be deposited over any suitable material layer. In some embodiments, the doped epitaxial capping layer 902 is deposited over the doped epitaxial body layer 106 of Figure 5. Optional etch-back may then be performed. In some embodiments, the doped epitaxial capping layer 902 is deposited over the doped epitaxial body layer 402 of Figure 4, and etch-back of the epitaxial capping layer is then performed. In any case, the combined source and drain semiconductor materials may include the epitaxial capping layer on the epitaxial body layer, which may subsequently be on the epitaxial nucleation layer. As shown, in some embodiments, due to the refinement of the doped epitaxial nucleation layer 702 and / or the doped epitaxial body layer 802, the doped epitaxial capping layer 902 can be formed in a highly conformal manner to provide substantially cubic material. In some embodiments, the doped epitaxial capping layer 902 is phosphorus-doped silicon (e.g., at a concentration exceeding 3E21 cm⁻³, for example, about 5E21 cm⁻³). In some embodiments, the doped epitaxial capping layer 902 can be etched back as discussed herein to provide a greater aspect ratio, a smaller span, and / or to remove disturbances. Returning to Figure 2, after such a single deposition / etch or multiple-cycle deposition / etch process, the process continues to operation 206, where the sacrificial layer adjacent to the channel semiconductor virtual gate material can be replaced by a gate structure using any suitable one or more known techniques. For example, the sacrificial layer can be selectively etched, and the necessary structure can be formed via deposition and optional patterning techniques. The process continues to operation 207, where the source and drain semiconductors and the gate structure are contacted via metal contacts using any suitable one or more known patterning and metal deposition processes. Figure 10 illustrates an exemplary transistor structure 1000 configured according to at least some embodiments of this disclosure, showing a transistor structure 500 after the formation of a gate structure and source, drain, and gate contacts. In the example of Figure 10, the source and drain material structures of the transistor structure 500 are used for illustrative purposes. However, any such source and drain material structure may be used as in transistor structure 800, transistor structure 900, or any other source and drain material structure discussed herein. As shown, the sacrificial layer 108, dummy gate oxide 110, dummy gate 104, and isolation layer 103 are removed and at least partially replaced by gate dielectric 1007, gate electrode 1001, source contact 1002, drain contact 1003, gate contact 1004, and spacers 1005 (which may include some or all of the isolation gap wall layers 102). Such processing can be performed using known operations. Furthermore, these components may include any suitable materials. For example, the gate dielectric 1007 may be a high-k material such as hafnium oxide, the gate electrode 1001 may include a work function material such as metal, and the source contact 1002, drain contact 1003, and gate contact 1004 may include metal contacts. In particular, the transistor structure 1000 includes a channel semiconductor 109 on a substrate 101 and between a source 112 and a drain 113, which can be epitaxially plotted to the channel semiconductor 109. Furthermore, as discussed here with respect to FIG. 1B, the channel semiconductor 109 has a lateral width X1 along a lateral dimension (e.g., the y-axis) substantially perpendicular to the axis extending between the source 112 and the drain 113. The source 112 and the drain 113 have portions extending along this dimension with a lateral width X2 exceeding the lateral width of the channel semiconductor 109, such that the lateral width X2 does not exceed, for example, one-third of the lateral width X1. The transistor structure 1000 further includes a gate electrode 1001 coupled to the channel semiconductor 109, a source contact 1002 coupled to the source 112, and a drain contact 1003 coupled to the drain 113. Figure 11 is a schematic diagram of a mobile computing platform 1100 configured according to at least some embodiments of the present disclosure, using transistors having etch-back epitaxial (Epi) source and / or drain (S / D) transistors. Any device with a transistor structure including any of the components, materials, or features discussed herein can be implemented by any component of the mobile computing platform 1100. The mobile computing platform 1100 can be any portable device for electronic data display, electronic data processing, wireless electronic data transmission, or the like. For example, the mobile computing platform 1100 can be any of a tablet computer, smartphone, notebook computer, laptop computer, etc., and may include, in exemplary embodiments, a touch screen (such as a capacitive, inductive, resistive, etc. touch screen), a chip-level (System-on-a-Chip) or package-level integrated system 1110, and a battery 1115. The battery 1115 may include any suitable means for providing electrical power, such as means consisting of one or more electrochemical cells and electrodes coupled to an external device. The mobile computing platform 1100 further includes a power supply that converts power from the power supply voltage into one or more voltages used by other devices of the mobile computing platform 1100. The package-level integrated system 1110 is further shown in the unfolded figure 1120. In an example embodiment, the package device 1150 (labeled "Memory / Processor" in FIG11) includes at least one memory chip (such as memory) and / or at least one processor chip (such as a microprocessor, a multi-core microprocessor, or a graphics processor or the like). In one embodiment, the package device 1150 is a microprocessor including static random access memory (SRAM) cache. As shown, the package device 1150 may use a die or device having any of the transistor structures and / or related features discussed herein. Package 1150 may be further coupled (e.g., communicationally coupled) to a board, substrate, or an interposer 1160 comprising power management integrated circuitry (PMIC) 1130, RF (wireless) transmitters and / or receivers (TX / RX) (e.g., including digital baseband and analog front-end modules, further including power amplifiers on the transmit path and low-noise amplifiers on the receive path), and controller 1135 itself. Generally, package 1150 may also be coupled (e.g., communicationally coupled) to a display screen 1105. As shown, one or both of PMIC 1130 and / or RFIC 1125 may use chips or devices having any of the transistor structures and / or related features discussed herein. Functionally, PMIC 1130 can perform battery power regulation, DC-DC conversion, etc., and therefore has an input coupled to battery 1115 and an output supplying current to other functional modules. In one embodiment, PMIC 1130 can perform high-voltage operation. As further shown, in an example embodiment, RFIC 1125 has an output coupled to an antenna (not shown) to implement any number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, their derivatives, and any other wireless protocols referred to as 3G, 4G, 5G, and above. In alternative implementations, each of these board-level modules may be incorporated into a package substrate coupled to the package device 1150 or a discrete integrated circuit within a single integrated circuit (SoC) coupled to the package substrate of the package device 1150. Figure 12 is a functional block diagram of a computing device 1200 configured according to at least some embodiments of the present disclosure. For example, the computing device 1200 may be found within a platform 700, and the computing device 1200 further includes a motherboard 1102 that controls some components, such as (but not limited to) a processor 1201 (e.g., an application processor) and one or more communication chips 1204, 1205. The processor 1201 may be physically and / or electrically coupled to the motherboard 1202. In some examples, the processor 1201 includes an integrated circuit die packaged within the processor 1201. Generally, the term "processor" may refer to any device or part of a device that processes electronic data from a register and / or memory to convert the electronic data into other electronic data that can be stored in the register and / or memory. Any one or more devices or components of the computing device 1200 may include a die or device having any of the transistor structures and / or related features discussed herein. In various examples, one or more communication chips 1204, 1205 are also physically and / or electrically coupled to the motherboard 1202. In a further embodiment, communication chip 1204 is part of processor 1201. Depending on the application, computing device 1200 may include other components that may or may not be physically and electrically coupled to motherboard 1202. These other components include (but are not limited to) volatile memory (e.g., DRAM) 1207, 1208 as shown, non-volatile memory (e.g., ROM) 1210, graphics processor 1212, flash memory, global positioning system (GPS) device 1213, compass 1214, chipset 1206, antenna 1216, power amplifier 1209, touch screen controller 1211, touch screen display 1217, speaker 1215, camera 1203, battery 1218, and power supply 1219, as well as digital signal processors, crypto processors, audio codecs, video codecs, accelerometers, gyroscopes, and mass storage devices (such as hard disk drives, solid-state drives (SSDs), compact disks (CDs), digital versatile disks (DVDs), etc.) or similar. Communication chips 1204 and 1205 enable wireless communication for transmitting data to and from computing device 1200. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, technologies, communication channels, etc., that communicate data using electromagnetic rays modulated through a non-solid-state medium. This term does not imply that the associated device does not contain any wires, although they may be absent in some embodiments. Communication chips 1204 and 1205 may implement any number of wireless standards or protocols, including (but not limited to) those described herein. As discussed, computing device 1200 may include a plurality of communication chips 1204 and 1205. For example, a first communication chip may be dedicated to shorter-range wireless communication, such as Wi-Fi and Bluetooth, while a second communication chip may be dedicated to longer-range wireless communication, such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others. Furthermore, power supply 1219 can convert power from a power supply voltage to one or more voltages used by other devices of mobile computing platform 1200. In some embodiments, power supply 1219 converts AC power to DC power. In some embodiments, power supply 1219 converts DC power to one or more different (lower) DC voltages. In some embodiments, multiple power supplies are adapted to convert from AC to DC and then from a higher DC voltage to a lower DC voltage specified by components of computing device 1200. Although specific features relating to the various embodiments have been described herein, this description is not intended to be construed as limiting. Therefore, various modifications and other embodiments of the embodiments described herein will be apparent to those skilled in the art as being within the spirit and scope of this disclosure. In one or more of the first embodiments, a transistor structure is included on a substrate and between a source and a drain, such that the source and drain are epitaxially connected to the channel semiconductor, the channel semiconductor having a first lateral width along a lateral dimension substantially perpendicular to an axis extending between the source and the drain, one of the source or drain having a portion extending beyond the lateral width of the channel semiconductor along the dimension with a second lateral width not greater than one-third of the first lateral width, a gate electrode coupled to the channel semiconductor, and a source contact coupled to the source and a drain contact coupled to the drain. In one or more second embodiments, following the first embodiment, the second lateral width is no greater than one-quarter of the first lateral width. In one or more third embodiments, following the first or second embodiment, one of the source or drain comprises a doped epitaxial nucleation layer on the channel semiconductor and a doped epitaxial body layer on the doped epitaxial nucleation layer, the doped epitaxial nucleation layer having a lower doping concentration than the doped epitaxial body layer. In one or more fourth embodiments, following any of the first to third embodiments, the doped epitaxial nucleation layer and the doped epitaxial body layer are doped with phosphorus and / or arsenic, and the source or drain is further included in a phosphorus-doped capping layer on the doped epitaxial body layer. In one or more fifth embodiments, following any of the first to fourth embodiments, one of the source or drain electrodes includes a first sidewall and a second sidewall relative to the first sidewall, wherein any measurement difference between the first and second sidewalls along the lateral dimension is no greater than 8 nanometers. In one or more sixth embodiments, following any of the first to fifth embodiments, the aspect ratio of the height to the width of the source or drain is not less than 2. In one or more seventh embodiments, a system includes a power supply and an integrated circuit die coupled to the power supply, the integrated circuit die including a transistor structure according to any one of the first to sixth embodiments. In one or more of the eighth embodiments, the method of manufacturing a transistor structure includes receiving a transistor structure comprising a channel semiconductor contained on a substrate, epitaxially depositing source and drain materials on the channel semiconductor, performing gas chemical etching back on the deposited source and drain materials via at least one of chlorine, silane, phosphine, or germane at a temperature in the range of 500°C to 800°C to provide a horizontal etching of the deposited source and drain materials at a faster rate than vertical etching of the deposited source and drain materials, coupling a gate electrode to the channel semiconductor, and coupling source contacts and drain contacts to the source and drain materials. In one or more ninth embodiments, following the eighth embodiment, the method further includes, after the back etching of the deposited source and drain materials, epitaxially depositing second source and drain materials on the etched source and drain materials, and back etching the deposited second source and drain materials via a second gas chemical etching comprising at least one of chlorine and silane, phosphine or germane. In one or more tenth embodiments, following the eighth or ninth embodiment, the source and drain materials include a doped epitaxial nucleation layer and the second source and drain materials include a doped epitaxial body layer, the doped epitaxial nucleation layer having a lower doping concentration than the subsequent doped epitaxial body layer. In one or more eleventh embodiments, following any of the eighth to tenth embodiments, the epitaxial deposition of the source and drain materials and the etchback of the deposited source and drain materials are performed in a common processing chamber. In one or more twelfth embodiments, following any of the eighth to eleventh embodiments, prior to the etchback, the epitaxial deposition of the source and drain materials comprises depositing a doped epitaxial nucleation layer and a doped epitaxial host layer, the epitaxial nucleation layer having a lower doping concentration than the subsequent epitaxial host layer. In one or more thirteenth embodiments, following any of the eighth to twelfth embodiments, the doped epitaxial nucleation layer and the doped epitaxial host layer are doped with phosphorus and / or arsenic, and prior to the etching back, the epitaxial deposition of the source and drain materials further comprises depositing a phosphorus-doped capping layer on the doped epitaxial host layer. In one or more of the fourteenth embodiments, following any of the eighth to thirteenth embodiments, the gas chemical etching comprises germane at a temperature not exceeding 650°C. In one or more fifteenth embodiments, following any of the eighth to fourteenth embodiments, the gas chemical etching comprises silanes and phosphines without germanane at a temperature of not less than 700°C. In one or more sixteenth embodiments, following any of the eighth to fifteenth embodiments, the deposited source material includes a first lateral width variation and the etched source material includes a second lateral width variation smaller than the first lateral width variation. In one or more of the seventeenth embodiments, following any of the eighth to sixteenth embodiments, the gas chemical etching comprises a first gas flow rate of hydrogen chloride and a second gas flow rate of a hydride comprising one or more of silane, phosphine, or germane, wherein the ratio of the first gas flow rate to the second gas flow rate is in the range of 1 to 10. It is understood that the present invention is not limited to the embodiments described, but can be implemented with modifications and alterations without departing from the scope of the appended claims. For example, the above embodiments may include specific combinations of features. However, the above embodiments are not limited to this matter, and in various implementations, the above embodiments may include performing only a subset of these features, performing different orders of these features, performing different combinations of these features, and / or performing other features not expressly listed. Therefore, the scope of the present invention should be determined with reference to the full scope of the appended claims and their equivalents.

[0006] 100: Transistor Structure 101:Substrate 102: Isolation gap wall layer 103: Isolation layer 104: Virtual Gate 105: Source and Drain Materials 106: Doped epitaxial host layer 107: Doped epitaxial nucleation layer 108: Sacrifice Layer 109: Channel Semiconductor 110: Virtual gate oxide 111: Noodles 112: Source 113: Jiji 114: Axis 115: Axis 116: Location 121: Sidewall surface 122: Sidewall surface 131: Cross-sectional view 132: Cross-sectional view 133: Surface 200: Process 201: Operation 202: Operation 203: Operation 204: Operation 205: Operation 206: Operation 207: Operation 211: In-place operation 300: Transistor Structure 400: Transistor Structure 401: Source and Drain Materials 402: Doped epitaxial host layer 403: Side surface 404: Top surface 405: Noodles 413: Side surface 500: Transistor Structure 501: Source and Drain Materials 600: Transistor Structure 602: Doped epitaxial nucleation layer 603: Side surface 604: Top surface 605: Noodles 613: Side surface 700: Transistor Structure 702: Doped epitaxial nucleation layer 800: Transistor Structure 802: Doped epitaxial bulk layer 900: Transistor Structure 902: Doped epitaxial capping layer 1000: Transistor Structure 1001: Gate electrode 1002: Source Contact 1003: Dust Contact 1004: Gate Contact 1005: Spacers 1100: Mobile Computing Platform 1105: Display screen 1110: Package-level integrated system 1115: Battery 1120: Unfolded diagram 1125: Radio Frequency Integrated Circuit 1130: Power Management Integrated Circuit 1135: Controller 1150: Packaging device 1160: Intermediary Layer 1200: Computing device 1201: Processor 1202: Motherboard 1203: Camera 1204: Communication Chip 1205: Communication Chip 1206: Chipset 1207: Volatile Memory 1208: Volatile Memory 1209: Power Amplifier 1210: Non-volatile memory 1211: Touchscreen controller 1212: Graphics Processor 1213: Global Positioning System (GPS) device 1214: Compass 1215: Speaker 1216: Antenna 1217: Touchscreen Display 1218: Battery 1219: Power Supply

Claims

1. A transistor structure comprising: a channel semiconductor, the channel semiconductor being disposed on a substrate and between a source and a drain, wherein, The source and the drain are epitaxially connected to the channel semiconductor, the channel semiconductor having a first lateral width along a lateral dimension, which is substantially perpendicular to the axis extending between the source and the drain, and one of the source or drain having a portion that extends beyond the lateral width of the channel semiconductor along the dimension with a second lateral width, and the second lateral width is not greater than one-third of the first lateral width. The gate electrode is coupled to the semiconductor of the channel; And the source contact coupled to the source and the drain contact coupled to the drain.

2. The transistor structure of claim 1, wherein the second lateral width is not greater than one-quarter of the first lateral width.

3. The transistor structure of claim 1, wherein the source or drain comprises a doped epitaxial nucleation layer on the channel semiconductor and a doped epitaxial body layer on the doped epitaxial nucleation layer, the doped epitaxial nucleation layer having a lower doping concentration than the doped epitaxial body layer.

4. The transistor structure of claim 3, wherein the doped epitaxial nucleation layer and the doped epitaxial body layer are doped with phosphorus and / or arsenic, and wherein one of the source or drain is further included in the phosphorus-doped capping layer on the doped epitaxial body layer.

5. A transistor structure as claimed in any one of claims 1 to 4, wherein the source or drain comprises a first sidewall and a second sidewall relative to the first sidewall, wherein any measurement difference between the first and second sidewalls along the lateral dimension is not greater than 8 nanometers.

6. A transistor structure as claimed in any one of claims 1 to 4, wherein the aspect ratio of the height to the width of the source or drain is not less than 2.

7. A semiconductor system comprising: a power supply; and an integrated circuit die coupled to the power supply, the integrated circuit die including a transistor structure, the transistor structure including: a channel semiconductor, the channel semiconductor being on a substrate and disposed between a source and a drain, wherein... The source and the drain are epitaxially connected to the channel semiconductor, the channel semiconductor having a first lateral width along a lateral dimension that is substantially perpendicular to an axis extending between the source and the drain, one of the source or drain having a portion that extends beyond the lateral width of the channel semiconductor along the dimension with a second lateral width, and the second lateral width is not greater than one-third of the first lateral width. The gate electrode is coupled to the semiconductor of the channel; And the source contact coupled to the source and the drain contact coupled to the drain.

8. The semiconductor system of claim 7, wherein the second lateral width is not greater than one-quarter of the first lateral width.

9. The semiconductor system of claim 7 or 8, wherein one of the source or drain comprises a doped epitaxial nucleation layer on the channel semiconductor and a doped epitaxial body layer on the doped epitaxial nucleation layer, the doped epitaxial nucleation layer having a lower doping concentration than the doped epitaxial body layer.

10. The semiconductor system of claim 7 or 8, wherein the doped epitaxial nucleation layer and the doped epitaxial body layer are doped with phosphorus and / or arsenic, and wherein one of the source or drain is further comprised of a phosphorus-doped capping layer on the doped epitaxial body layer.

11. A method of manufacturing a transistor structure, the method comprising: receiving a transistor structure comprising a channel semiconductor on a substrate; epitaxially depositing source and drain materials on the channel semiconductor; chemically etching back the deposited source and drain materials via a gas chemical etching process of at least one of chlorine, silane, phosphine, or germane at a temperature in the range of 500°C to 800°C to provide a horizontal etching of the deposited source and drain materials at a faster rate than vertical etching of the deposited source and drain materials; coupling a gate electrode to the channel semiconductor; and coupling source contacts and drain contacts to the source and drain materials.

12. The method of claim 11 further comprises: epitaxially depositing a second source and drain material on the etched source and drain material after the etched back etching; and etching back the deposited second source and drain material via a second gas chemical etching comprising at least one of chlorine and silane, phosphine or germane.

13. The method of claim 12, wherein the source and drain materials comprise a doped epitaxial nucleation layer and the second source and drain materials comprise a doped epitaxial body layer, the doped epitaxial nucleation layer comprising a lower doping concentration than the subsequent doped epitaxial body layer.

14. The method of claim 11, wherein the epitaxial deposition of the source and drain materials and the etchback of the deposited source and drain materials are performed in a common processing chamber.

15. The method of claim 11, wherein prior to the etchback, the epitaxial deposition of the source and drain materials comprises depositing a doped epitaxial nucleation layer and a doped epitaxial host layer, the epitaxial nucleation layer comprising a lower doping concentration than the subsequent epitaxial host layer.

16. The method of claim 15, wherein the doped epitaxial nucleation layer and the doped epitaxial host layer are doped with phosphorus and / or arsenic, and wherein prior to the etching back, the epitaxial deposition of the source and drain materials further comprises depositing a phosphorus-doped capping layer on the doped epitaxial host layer.

17. The method of any one of claims 11 to 16, wherein the gas chemical etching comprises germane at a temperature not exceeding 650°C.

18. The method of any one of claims 11 to 16, wherein the gas chemical etching comprises silane and phosphine without germanane at a temperature of not less than 700°C.

19. The method of any one of claims 11 to 16, wherein the deposited source material includes a first lateral width variation and the etched source material includes a second lateral width variation smaller than the first lateral width variation.

20. The method of any one of claims 11 to 16, wherein the gas chemical etching comprises a first gas flow rate of hydrogen chloride and a second gas flow rate of a hydride comprising one or more of silane, phosphine, or germane, and wherein the ratio of the first gas flow rate to the second gas flow rate is in the range of 1 to 10.

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