Semiconductor device and method of manufacturing semiconductor device

Abstract

The present invention provides a semiconductor device that can reduce the resistance of the gate electrode and a method for manufacturing the semiconductor device. The semiconductor device of the present invention comprises: a substrate; a semiconductor layer disposed on the substrate; an insulating layer disposed on the semiconductor layer and having a first opening; a gate electrode disposed on the insulating layer and contacting the semiconductor layer through the first opening; and a source electrode and a drain electrode, which are in ohmic contact with the semiconductor layer; and the gate electrode comprises: a crystallinity control film disposed on the insulating layer and having a second opening, the second opening being formed such that its inner wall is connected to the inner wall of the first opening when viewed from a direction perpendicular to the upper surface of the substrate; a first metal film disposed on the crystallinity control film and in Schottky contact with the semiconductor layer through the inner walls of the second opening and the first opening respectively; and a second metal film disposed on the first metal film and having a lower resistance than the first metal film.

Description

Semiconductor devices and methods for manufacturing semiconductor devices This invention relates to a semiconductor device and a method for manufacturing the semiconductor device. A semiconductor device exists in which a gate electrode is in Schottky contact with a semiconductor layer. In this semiconductor device, an insulating layer is formed on the semiconductor layer to mitigate electric field concentration near the gate electrode, and a portion of the gate electrode is disposed on the insulating layer (Patent Documents 1, 2). [Prior Art Documents] [Patent Documents] [Patent Document 1] Japanese Patent Application Publication No. 2013-207086 [Patent Document 2] Japanese Patent Application Publication No. 2019-216188 [The problem the invention aims to solve] The semiconductor device described in Patent Documents 1 and 2 can achieve the intended purpose, but in order to obtain higher characteristics, it is desirable to reduce the resistance of the gate electrode. The purpose of this invention is to provide a semiconductor device that can reduce the resistance of the gate electrode and a method for manufacturing the semiconductor device. [Technical Means for Solving the Problem] The semiconductor device of the present invention comprises: a substrate; a semiconductor layer disposed on the substrate; an insulating layer disposed on the semiconductor layer and having a first opening; a gate electrode disposed on the insulating layer and in contact with the semiconductor layer through the first opening; and a source electrode and a drain electrode, which are in ohmic contact with the semiconductor layer; and the gate electrode comprises: a crystallinity control film disposed on the insulating layer and having a second opening, the second opening being formed such that its inner wall is connected to the inner wall of the first opening when viewed from a direction perpendicular to the upper surface of the substrate; a first metal film disposed on the crystallinity control film and in Schottky contact with the semiconductor layer through the inner walls of the second opening and the first opening respectively; and a second metal film disposed on the first metal film and having a lower resistance than the first metal film. [Effects of the Invention] According to the present invention, the resistance of the gate electrode can be reduced. [Description of Embodiments of the Invention] First, embodiments of the present invention will be listed and described. [1] A semiconductor device according to one aspect of the present invention includes: a substrate; a semiconductor layer disposed on the substrate; an insulating layer disposed on the semiconductor layer and having a first opening; a gate electrode disposed on the insulating layer and in contact with the semiconductor layer through the first opening; and a source electrode and a drain electrode, which are in ohmic contact with the semiconductor layer; and the gate electrode includes: a crystallinity control film disposed on the insulating layer and having a second opening, the second opening being formed such that its inner wall is connected to the inner wall of the first opening when viewed from a direction perpendicular to the upper surface of the substrate; a first metal film disposed on the crystallinity control film and in Schottky contact with the semiconductor layer through the inner walls of the second opening and the first opening respectively; and a second metal film disposed on the first metal film and having a lower resistance than the first metal film. A first metal film is formed on top of a crystallinity control film. Therefore, compared to the case where the first metal film is formed on the insulating layer in contact with it, the crystallinity of the first metal film is improved. The crystallinity of the second metal film is influenced by the crystallinity of the first metal film, thus the crystallinity of the second metal film is also improved. Therefore, the resistance of the gate electrode can be reduced. By reducing the resistance of the gate electrode, the signal loss input to the gate electrode can be reduced, and the degradation of high-frequency gain can be reduced. Therefore, the characteristics and reliability of the semiconductor device can be improved. [2] As in [1], the semiconductor layer includes a nitride semiconductor layer, the first metal film is a Ni film, and the atomic arrangement at the interface between the crystallinity control film and the first metal film can be six-fold symmetrical. In this case, the crystallinity of the Ni film is easily improved. [3] As in [1] or [2], the crystallinity control film may include ZnO film, GaN film, Ti film, TiN film, Al film, AlSiCu film or AlN film. In this case, the crystallinity of the Ni film is easily improved. [4] As in [1] to [3], the gate electrode, viewed from a direction perpendicular to the upper surface of the substrate, has: a first region that overlaps with the first opening; a second region that is horizontally connected to the first region on the source electrode side; and a third region that is horizontally connected to the first region on the drain electrode side; and the crystallinity control film may be disposed at least in a portion of the second region and a portion of the third region. In this case, the electric field concentration near the gate electrode is easily mitigated. Furthermore, the reduction in crystallinity of the first and second metal films in the second and third regions can be suppressed. [5] As in [4], the half-width of the electron beam diffraction pattern of the second metal film in the second region and the half-width of the electron beam diffraction pattern of the second metal film in the third region can be less than 45 times the half-width of the electron beam diffraction pattern of the second metal film in the first region. In this case, it is particularly easy to reduce the resistance of the gate electrode. [6] As in [4] or [5], the average grain size of the second metal film in the second region and the average grain size of the second metal film in the third region can be 60% or more of the average grain size of the second metal film in the first region. In this case, it is particularly easy to reduce the resistance of the gate electrode. [7] As in [1] to [6], the thickness of the crystallinity control film can be 10 nm or more and 30 nm or less. In this case, side etching can be suppressed during etching when the crystallinity control film is formed, and the crystallinity of the first metal film can be easily improved. [8] As in [1] to [7], the portion of the gate electrode that is higher than the upper surface of the insulating layer may have a tapered shape that becomes wider as it approaches the insulating layer when viewed in cross-section from a direction perpendicular to the direction in which the source electrode and the drain electrode are arranged and parallel to the upper surface of the substrate. This shape is easily achieved when the gate electrode is formed by a deposition method with a resist mask. [9] As in [1] to [8], the insulating layer described above may be an amorphous layer. In this case, leakage current between the gate electrode and the semiconductor layer is easily suppressed.

[10] Another aspect of the semiconductor device of the present invention includes: a substrate; a semiconductor layer disposed on the substrate; an insulating layer disposed on the semiconductor layer and having a first opening formed thereon; a gate electrode disposed on the insulating layer and in contact with the semiconductor layer through the first opening; and a source electrode and a drain electrode, which are in ohmic contact with the semiconductor layer; and the gate electrode includes: a ZnO film disposed on the insulating layer and having a second opening formed thereon by its inner wall being connected to the inner wall of the first opening; a Ni film disposed on the ZnO film and in Schottky contact with the semiconductor layer through the inner walls of the second opening and the first opening being connected to each other; and an Au film disposed on the Ni film and having a lower resistance than the Ni film. Because a Ni film is formed on top of the ZnO film, the crystallinity of the Ni film is improved compared to the case where the Ni film is formed on top of the insulating layer in contact with it. The crystallinity of the Au film is affected by the crystallinity of the Ni film, thus the crystallinity of the Au film is also improved. Therefore, the resistance of the gate electrode can be reduced. By reducing the resistance of the gate electrode, the signal loss input to the gate electrode can be reduced, and the degradation of high-frequency gain can be minimized. Therefore, the characteristics and reliability of the semiconductor device can be improved.

[11] Another aspect of the present invention describes a method for manufacturing a semiconductor device comprising the following steps: forming a semiconductor layer on a substrate; forming a source electrode and a drain electrode in ohmic contact with the semiconductor layer; forming an insulating layer on the semiconductor layer; forming a crystallinity control film on the insulating layer; forming a second opening on the crystallinity control film; forming a first opening on the insulating layer such that the inner wall of the second opening is connected to the inner wall of a first opening; forming a resist mask having a third opening having an opening width larger than the opening width of the second opening and the first opening; forming a first metal film in Schottky contact with the semiconductor layer on the crystallinity control film through the third opening and through the inner walls of the second opening and the first opening, which are respectively connected to each other; forming a second metal film with a lower resistance than the first metal film on the first metal film through the third opening; and removing the resist mask. Because a first metal film is formed on top of the crystallinity control film, the crystallinity of the first metal film is improved compared to the case where the first metal film is formed on top of the insulating layer in contact with it. The crystallinity of the second metal film is affected by the crystallinity of the first metal film, thus the crystallinity of the second metal film is also improved. Therefore, the resistance of the gate electrode can be reduced. By reducing the resistance of the gate electrode, the signal loss input to the gate electrode can be reduced, and the degradation of high-frequency gain can be reduced. Therefore, the characteristics and reliability of the semiconductor device can be improved.

[12] As in

[11] , in the step of forming the crystallinity control film, the temperature of the substrate can be above 150°C and below 500°C.

[13] As in

[11] or

[12] , wherein the first metal film and the second metal film can be formed by vapor deposition.

[14] As in

[11] to

[13] , the temperature of the substrate in the step of forming the first metal film and the step of forming the second metal film may be below 80°C. [Details of Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described in detail, but the present invention is not limited thereto. Furthermore, in this specification and drawings, constituent elements that have substantially the same functional configuration are omitted by using the same symbols to avoid repetitive descriptions. The present invention relates to a semiconductor device comprising a high electron mobility transistor (HEMT) using a nitride semiconductor. FIG1 is a cross-sectional view showing the semiconductor device of the embodiment. The semiconductor device 1 of the embodiment includes a substrate 10 and a semiconductor stacking section 20 comprising a plurality of nitride semiconductor layers disposed on the substrate 10. The substrate 10 is, for example, a SiC substrate having a (0001) surface, and the stacking direction of the semiconductor stacking section 20 is, for example, the

[0001] direction. The semiconductor stacking section 20 includes a nucleation layer 12, a channel layer 14, a barrier layer 16, and a capping layer 18 sequentially formed from the substrate 10 side. The nucleation layer 12 functions as a seed layer for the channel layer 14. For example, the nucleation layer 12 is an AlN layer, and the thickness of the nucleation layer 12 is 5 nm to 20 nm. The channel layer 14 is epitaxially grown on the nucleation layer 12 and functions as an electron transfer layer. For example, the channel layer 14 is an undoped GaN layer, and the thickness of the channel layer 14 is 500 nm. The semiconductor stacking section 20 is an example of a semiconductor layer. Barrier layer 16 is epitaxially grown on channel layer 14 and functions as an electron supply layer. For example, barrier layer 16 can be an AlGaN layer, an InAlN layer, or an InAlGaN layer, and its thickness is 5 nm to 30 nm. The band gap of barrier layer 16 is larger than that of channel layer 14. When barrier layer 16 is an AlGaN layer, its Al composition is, for example, 0.15 to 0.35. The conductivity of barrier layer 16 can be n-type, and barrier layer 16 can be undoped. Barrier layer 16 and channel layer 14 can be connected to each other, or a spacer layer (not shown) can be placed between barrier layer 16 and channel layer 14. Strain occurs in barrier layer 16 and channel layer 14 due to the difference in their lattice constants. By means of this strain, a two-dimensional electron gas (2DEG) from piezoelectric charge is generated in the region near the interface between the barrier layer 16 and the channel layer 14 and on the side of the channel layer 14, forming a channel region. The capping layer 18 is epitaxially grown on the barrier layer 16. For example, the capping layer 18 is a GaN layer, and the thickness of the capping layer 18 is 5 nm. For example, the conductivity type of the capping layer 18 is n-type. The semiconductor device further includes a source electrode 22 and a drain electrode 24. The source electrode 22 and drain electrode 24 are arranged along the upper surface of the substrate 10. The source electrode 22 and drain electrode 24 are disposed on the capping layer 18 and form ohmic contacts with the semiconductor stack 20. The source electrode 22 and drain electrode 24 are formed by heat treatment (alloying) a tantalum (Ta) layer, an aluminum (Al) layer, and a Ta layer sequentially disposed from the semiconductor stack 20 side. Alternatively, a Ti layer may be disposed instead of a Ta layer. The semiconductor device 1 further includes a SiN passivation film 26. For example, the thickness of the SiN passivation film 26 is 20 nm to 100 nm. The SiN passivation film 26 is an amorphous film. The SiN passivation film 26 is disposed on the source electrode 22, the drain electrode 24, and the capping layer 18, covering the source electrode 22, the drain electrode 24, and the capping layer 18. An opening 26G is formed in the SiN passivation film 26, through which the capping layer 18 is exposed from the SiN passivation film 26. The SiN passivation film 26 is an example of an insulating layer. The opening 26G is an example of a first opening. The semiconductor device 1 further includes a gate electrode 28. The gate electrode 28 is disposed on a SiN passivation film 26 between the source electrode 22 and the drain electrode 24. Here, the gate electrode 28 will be described in detail. FIG2 is an enlarged cross-sectional view of the gate electrode 28. The gate electrode 28 covers the opening 26G and is in contact with the semiconductor stack 20 through the opening 26G. The gate electrode 28 has a zinc oxide (ZnO) film 52, a nickel (Ni) film 54, and a gold (Au) film 56. A ZnO film 52 is disposed on the SiN passivation film 26, and an opening 52G is formed in the ZnO film 52. The inner wall portion of the opening 52G and the inner wall portion of the opening 26G are smoothly and continuously formed from the opening 52G to the opening 26G when viewed from a direction perpendicular to the upper surface of the substrate. That is, the opening 52G is formed such that its inner wall is connected to the inner wall of the opening 26G. For example, the thickness of the ZnO film 52 is 10 nm to 30 nm. The ZnO film 52 is an example of a crystallinity control film. A Ni film 54 is disposed on a ZnO film 52 and is in Schottky contact with the semiconductor stack 20 through openings 52G and 26G. The Ni film 54 is in contact with the ZnO film 52. The Ni film 54 covers openings 52G and 26G. The Ni film 54 extends from the upper surface of the semiconductor stack 20 within opening 26G, passing through the interconnected inner wall surfaces of openings 26G and 52G, and sits atop the ZnO film 52. For example, the thickness of the Ni film 54 is 1 nm to 200 nm. The Ni film 54 is an example of a first metal film. An Au film 56 is disposed on top of the Ni film 54, extending from the inner sides of openings 26G and 52G and over the SiN passivation film 26. The Au film 56 is in contact with the Ni film 54. For example, the thickness of the Au film is 300 nm to 800 nm. The resistance of the Au film 56 is lower than that of the Ni film 54. The Au film 56 is an example of a second metal film. Viewed from a direction perpendicular to the upper surface of the substrate, the gate electrode 28 has a first region 62 overlapping the opening 26G, a second region 64 horizontally connected to the first region 62 on the source electrode 22 side, and a third region 66 horizontally connected to the first region 62 on the drain electrode 24 side. The second region 64 and the third region 66 are disposed on the SiN passivation film 26. One pair of side surfaces 28A and 28B of the gate electrode 28 on the SiN passivation film 26 are inclined relative to the upper surface of the SiN passivation film 26, and become closer to each other the further away from the semiconductor stack portion 20. Therefore, the portion of the gate electrode 28 that is higher than the upper surface of the SiN passivation film 26 is generally trapezoidal. That is, the portion of the gate electrode 28 that is higher than the upper surface of the SiN passivation film 26, when viewed in cross-section perpendicular to the direction in which the source electrode 22 and the drain electrode 24 are arranged and parallel to the upper surface of the substrate 10, has a tapered shape that becomes wider as it gets closer to the SiN passivation film 26. One pair of side surfaces 28A and 28B of the gate electrode 28 are mainly composed of an Au film 56. Side surface 28A is the side surface on the source electrode 22 side, and side surface 28B is the side surface on the drain electrode 24 side. The semiconductor device 1 further includes an insulating layer 30. The insulating layer 30 covers the gate electrode 28. The insulating layer 30 contains an insulating material containing Si, such as a SiN layer or SiO2 layer. Two layers or SiON layers. For example, the thickness of the insulating layer 30 is 20 nm to 400 nm. Openings 32 and 34 are formed in the SiN passivation film 26 and the insulating layer 30. The source electrode 22 is exposed through opening 32, and the drain electrode 24 is exposed through opening 34. Wiring (not shown) connected to the source electrode 22 is disposed in opening 32, and wiring (not shown) connected to the drain electrode 24 is disposed in opening 34. Here, the manufacturing method of the semiconductor device 1 according to the embodiment will be described. Figures 3 to 14 are cross-sectional views showing the manufacturing method of the semiconductor device 1 according to the embodiment. First, as shown in Figure 3, a semiconductor stack 20 comprising a plurality of nitride semiconductor layers is formed on a substrate 10 using metal-organic chemical vapor deposition (MOCVD). Specifically, a nucleation layer 12 is first grown on the substrate 10. When the nucleation layer 12 is an AlN layer, for example, the feed gas is TMA (trimethylaluminum) and NH4+. 3 (ammonia), the temperature of substrate 10 during the formation of nucleation layer 12 is set to 1100°C. Next, channel layer 14 is grown on nucleation layer 12. When channel layer 14 is a GaN layer, for example, the feed gas is TMG (trimethylgallium) and NH3. 3. The temperature of the substrate 10 during the formation of the channel layer 14 is set to 1050°C. Next, a barrier layer 16 is grown on the channel layer 14. When the barrier layer 16 is an AlGaN layer, for example, the feed gas is TMA, TMG, or NH4+. 3. The temperature of the substrate 10 during the formation of the barrier layer 16 is set to 1050°C. Next, the capping layer 18 is grown on the barrier layer 16. When the capping layer 18 is a GaN layer, for example, the feed gases are TMG and NH4+. 3. The temperature of the substrate 10 when forming the cover layer 18 is set to 1050°C. Next, as shown in Figure 4, source electrode 22 and drain electrode 24 are formed on the capping layer 18 by vapor deposition using photolithography and evaporation techniques. Subsequently, alloying is performed by heat treatment at a temperature of 500°C to 600°C. Next, as shown in FIG5, a SiN passivation film 26 is formed covering the source electrode 22, the drain electrode 24, and the semiconductor stack 20. The SiN passivation film 26 can be formed, for example, by plasma CVD or sputtering. For example, when the SiN passivation film 26 is formed by plasma CVD, the temperature of the substrate 10 is set to 250°C or higher and 350°C or lower. Next, as shown in Figure 6, a ZnO film 52 is formed on the SiN passivation film 26. The ZnO film 52 can be formed, for example, by sputtering, plasma CVD, or atomic layer deposition (ALD). The temperature (growth temperature) of the substrate 10 during the formation of the ZnO film 52 is set, for example, to 150°C or higher and 500°C or lower. By setting the growth temperature to 150°C or higher and 500°C or lower, the c-axis orientation of the ZnO film 52 is easily improved. The growth temperature is preferably 200°C or higher and 450°C or lower, and more preferably 250°C or higher and 400°C or lower. Next, as shown in Figure 7, a resist mask 72 with an opening 72A in a predetermined area where the opening 26G is formed is formed on the ZnO film 52. The resist mask 72 can be formed, for example, by coating, exposing and developing a resist. Secondly, as shown in Figure 8, an opening 52G is formed in the ZnO film 52 by etching the portion exposed from the opening 72A. The etching of the ZnO film 52 is preferably performed using anisotropic dry etching with a chlorine-based gas. Although there is a risk of side etching, HCl or HNO3 can also be used. 3. CH Wet etching is performed using 3COOH and other methods. Furthermore, the ZnO film 52 can also be etched using a developer solution used to form the resist mask 72, such as tetramethylammonium hydroxide (TMAH). Next, as shown in Figure 9, an opening 26G is formed in the SiN passivation film 26 by etching the portions exposed from openings 72A and 52G. The opening 26G is formed such that its inner wall is connected to the inner wall of the opening 52G. The etching of the SiN passivation film 26 is preferably performed using anisotropic dry etching with a fluorine-based gas. Next, as shown in FIG10, the resist mask 72 is removed. Next, a resist mask 74 having an opening 74A and a resist mask 76 having an opening 76A are formed on the ZnO film 52. In the cross-sectional shape shown in FIG10, the horizontal opening width of opening 76A is larger than the horizontal opening widths of openings 52G and 26G. Also, the horizontal opening width of opening 74A is larger than the horizontal opening width of opening 76A. In the formation of resist masks 74 and 76, resist for resist mask 74 is applied, followed by resist for resist mask 76. Next, the resist for resist mask 76 forms opening 76A with an opening width larger than that of openings 52G and 26G. Subsequently, the resist used in the resist mask 74 forms the opening 74A such that its opening width is larger than that of the opening 76A. The resist mask 74 and the resist mask 76 are included in the resist mask 78, and the openings 74A and 76A are included in the opening 78A. The opening 78A is an example of the third opening. Next, as shown in Figure 11, a Ni film 54 and an Au film 56 are sequentially formed through openings 76A and 74A by vapor deposition. To avoid degradation of the resist mask 76 and the resist mask 74, the temperature of the substrate 10 during the formation of the Ni film 54 and the Au film 56 is preferably below 80°C, and more preferably below 70°C. The Ni film 54 is formed on the ZnO film 52 and makes Schottky contact with the semiconductor stack 20 through openings 52G and 26G. The Au film 56 is formed on the Ni film 54 from the inside of openings 26G and 52G, extending over the SiN passivation film 26. When forming the Ni film 54, a Ni film 54A is formed on the resist mask 76, and when forming the Au film 56, an Au film 56A is formed on the Ni film 54A. Next, as shown in Figure 12, resist mask 76 and resist mask 74 are removed. With the removal of resist mask 76 and resist mask 74, the Ni film 54A and Au film 56A are also removed. This is called separation. Next, as shown in Figure 13, the portion of the ZnO film 52 exposed from the Au film 56 and Ni film 54 is removed. The removal of the ZnO film 52 is performed, for example, by wet etching. The removal of the ZnO film 52 can be performed using, for example, a diluted solution of hydrochloric acid or sulfuric acid. As a result, a gate electrode 28 is formed having the ZnO film 52, the Ni film 54, and the Au film 56. Since the Ni film 54 and the Au film 56 are formed using resist mask 74 and resist mask 76, the portion of the gate electrode 28 that is higher than the upper surface of the SiN passivation film 26 becomes approximately trapezoidal. That is, the portion of the gate electrode 28 that is higher than the upper surface of the SiN passivation film 26, when viewed in cross-section perpendicular to the direction in which the source electrode 22 and the drain electrode 24 are arranged and parallel to the upper surface of the substrate 10, has a tapered shape that becomes wider as it approaches the SiN passivation film 26. Next, as shown in FIG14, an insulating layer 30 is formed covering the gate electrode 28 and the SiN passivation film 26. The insulating layer 30 can be formed, for example, by plasma CVD or sputtering. The temperature of the substrate 10 during the formation of the insulating layer 30 is set, for example, to be above 250°C and below 350°C. Next, openings 32 and 34 are formed in the insulating layer 30 and the SiN passivation film 26. The source electrode 22 is exposed through opening 32, and the drain electrode 24 is exposed through opening 34. The semiconductor device 1 of the embodiment can be manufactured in this manner. In this embodiment, a Ni film 54, which is in Schottky contact with the semiconductor stack 20, is formed on the ZnO film 52, which serves as a crystallinity control film. Therefore, compared to the case where the Ni film 54 is formed on the SiN passivation film 26 in contact with it, the crystallinity of the Ni film 54 is improved. Furthermore, the crystallinity of the Au film 56 is affected by the crystallinity of the Ni film 54. Therefore, according to this embodiment, compared to the case where the Ni film 54 is formed on the SiN passivation film 26 in contact with it, the crystallinity of the Au film 56 is also improved. Therefore, according to this embodiment, the resistance of the gate electrode 28 can be reduced. By reducing the resistance of the gate electrode 28, the signal loss input to the gate electrode 28 can be reduced, and the degradation of high-frequency gain can be minimized. Therefore, the characteristics and reliability of the semiconductor device 1 can be improved. In this embodiment, the semiconductor stack 20 includes a nitride semiconductor layer, and the Ni film 54 is in Schottky contact with the nitride semiconductor layer. Furthermore, the atomic arrangement at the interface between the Ni film 54 and the ZnO film 52 is six-fold symmetrical, and the atomic arrangement at the interface between the ZnO film 52 and the Ni film 54 is also six-fold symmetrical. Therefore, it is easier to improve the crystallinity of the Ni film 54. The ZnO film used as a crystallinity control film may or may not be doped with impurities. When doped, the concentration is, for example, between 1 atomic% and 10 atomic%. Examples of impurities doped in ZnO films include B, Al, Ga, and In. The crystallinity control film is not limited to ZnO; it may also include GaN, Ti, TiN, Al, AlSiCu, or AlN films. The atomic arrangement at the interface between these films and the first metal film is also hexagonal symmetry. The GaN film may or may not be doped with impurities. Examples of impurities doped in GaN films include Si and Ge. The gate electrode 28 includes a first region 62, a second region 64, and a third region 66, which can alleviate the electric field concentration near the gate electrode 28. Furthermore, a ZnO film 52 is provided in the second region 64 and the third region 66, which can suppress the decrease in crystallinity of the Ni film 54 and the Au film 56 in the second region 64 and the third region 66. The SiN passivation film 26 is an amorphous film, which makes it easy to suppress leakage current between the gate electrode 28 and the semiconductor stack 20. Furthermore, a barrier metal film such as a Pd film, Pt film, or Ru film can also be disposed between the Ni film 54 and the Au film 56. The thickness of the barrier metal film is, for example, 5 nm to 100 nm. Also, a Ta film, TaN film, Hf film, HfN film, Zr film, ZrN film, W film, or WN film can also be disposed on the Au film 56. In this invention, the half-width at half-maximum (WWHM) of the electron beam diffraction pattern of the second metal film in the second region and the half-width at half-maximum (WWHM) of the electron beam diffraction pattern of the second metal film in the third region are preferably 45 times or less, more preferably 30 times or less, and even more preferably 20 times or less. The smaller the WWHM of the electron beam diffraction pattern of the second metal film in the second region and the half-width at half-maximum (WWHM) of the electron beam diffraction pattern of the second metal film in the third region, the easier it is to reduce the resistance of the gate electrode. The half-width at half-maximum (WHM) of the electron beam diffraction pattern of the second metal film can be determined as follows: A thin sheet is fabricated using a focused ion beam (FIB) to expose the cross-section of the gate electrode 28. The ideal thickness of the sheet is approximately 50 nm to 200 nm. An electron beam is incident perpendicularly onto the cross-section of the gate electrode 28 using a transmission electron microscope (TEM). Due to the crystalline nature of the second metal film, the electron beam passing through the sample (sheet) reinforces each other along a specific direction corresponding to the periodicity of the crystals, forming a point-like image on the detector, thus obtaining the electron beam diffraction pattern. The intensity distribution of the 111 diffraction points or -1-1-1 diffraction points within the electron beam diffraction pattern is extracted, and its WHM is measured. In region 1, the first metal film is in contact with the nitride semiconductor film. In regions 2 and 3, a SiN passivation film 26 exists between the first metal film and the nitride semiconductor layer. Electron beam diffraction patterns are obtained for the second metal film in regions 1, 2, and 3, and the half-width is measured. This allows for the quantification and comparison of the (111) orientation of different regions of the substrate. In this invention, the average grain size of the second metal film in the second region and the average grain size of the second metal film in the third region are preferably 60% or more, more preferably 70% or more, and even more preferably 80% or more of the average grain size of the second metal film in the first region. The larger the average grain size of the second metal film in the second region and the average grain size of the second metal film in the third region, the easier it is to suppress the interdiffusion between the first and second metal films, thereby reducing the resistance of the gate electrode. The average crystal grain size of the second metal film can be determined, for example, using an atomic force microscope. In this invention, the thickness of the crystallinity control film is preferably 10 nm to 30 nm, and more preferably 15 nm to 25 nm. If the crystallinity control film is too thin, it may be difficult to improve the crystallinity of the first metal film. Furthermore, if the crystallinity control film is too thick, side etching may occur during the etching of the crystallinity control film. The above describes the implementation methods in detail, but is not limited to a specific implementation method. Various changes and modifications can be made within the scope of the claims. 1: Semiconductor device 4A: Opening 10: Substrate 12: Nucleation layer 14: Channel layer 16: Barrier layer 18: Capping layer 20: Semiconductor stack 22: Source electrode 24: Drain electrode 26: SiN passivation film 26G: Opening 28: Gate electrode 28A: Side side 28B: Side side 30: Insulating layer 32: Opening 34: Opening 52: ZnO film 52G: Opening 54: Ni film 54A: Ni film 56: Au film 56A: Au film 62: Region 1 64: Region 2 66: Region 3 72: Resist mask 72A: Opening 74: Resist mask 74A: Opening 76: Resist mask 76A: Opening 78: Resist mask 78A: Opening Figure 1 is a cross-sectional view of a semiconductor device according to an embodiment. Figure 2 is a cross-sectional view showing the gate electrode magnified. Figure 3 is a cross-sectional view (1) of a method for manufacturing the semiconductor device according to an embodiment. Figure 4 is a cross-sectional view (2) of a method for manufacturing the semiconductor device according to an embodiment. Figure 5 is a cross-sectional view (3) of a method for manufacturing the semiconductor device according to an embodiment. Figure 6 is a cross-sectional view (4) of a method for manufacturing the semiconductor device according to an embodiment. Figure 7 is a cross-sectional view (5) of a method for manufacturing the semiconductor device according to an embodiment. Figure 8 is a cross-sectional view (6) of a method for manufacturing the semiconductor device according to an embodiment. Figure 9 is a cross-sectional view (7) of a method for manufacturing the semiconductor device according to an embodiment. Figure 10 is a cross-sectional view (8) of a method for manufacturing the semiconductor device according to an embodiment. Figure 11 is a cross-sectional view (9) of a method for manufacturing the semiconductor device according to an embodiment. Figure 12 is a cross-sectional view (10) of a method for manufacturing the semiconductor device according to an embodiment. Figure 13 is a cross-sectional view (11) of a method for manufacturing the semiconductor device according to an embodiment. Figure 14 is a cross-sectional view (12) showing a method for manufacturing a semiconductor device according to an embodiment. 16: Barrier layer 18: Cover layer 26: SiN passivation film 26G: Open 28: Gate electrode 28A: Side view 28B: Side view 30: Insulation layer 52:ZnO membrane 52G: Open 54:Ni film 56: Au membrane 62: Area 1 64: Area 2 66: Area 3

Claims

1. A semiconductor device comprising: a substrate; a semiconductor layer disposed on the substrate; an insulating layer disposed on the semiconductor layer and having a first opening; a gate electrode disposed on the insulating layer and in contact with the semiconductor layer through the first opening; and a source electrode and a drain electrode, etc., in ohmic contact with the semiconductor layer; wherein the gate electrode comprises: a crystallinity control film disposed on the insulating layer and having a second opening, the second opening being formed such that, when viewed from a direction perpendicular to the upper surface of the substrate, its inner wall is connected to the inner wall of the first opening; a first metal film disposed on the crystallinity control film and in Schottky contact with the semiconductor layer through the inner walls of the second opening and the first opening respectively; and a second metal film disposed on the first metal film and having a lower resistance than the first metal film; wherein the crystallinity control film comprises a ZnO film, a GaN film, a TiN film, an Al film, an AlSiCu film, or an AlN film.

2. The semiconductor device of claim 1, wherein the semiconductor layer comprises a nitride semiconductor layer, the first metal film is a Ni film, and the atomic arrangement of the interface between the crystallinity control film and the first metal film is six-fold symmetric.

3. The semiconductor device of claim 1 or 2, wherein the gate electrode, viewed from a direction perpendicular to the upper surface of the substrate, has: a first region that overlaps with the first opening; a second region that is horizontally connected to the first region on the source electrode side; and a third region that is horizontally connected to the first region on the drain electrode side; and the crystallinity control film is disposed at least in a portion of the second region and a portion of the third region.

4. The semiconductor device of claim 3, wherein the half-width of the electron beam diffraction pattern of the second metal film in the second region and the half-width of the electron beam diffraction pattern of the second metal film in the third region are less than 45 times the half-width of the electron beam diffraction pattern of the second metal film in the first region.

5. The semiconductor device of claim 3, wherein the average crystal grain size of the second metal film in the second region and the average crystal grain size of the second metal film in the third region are 60% or more of the average crystal grain size of the second metal film in the first region.

6. The semiconductor device of claim 1 or 2, wherein the thickness of the crystallinity control film is 10 nm or more and 30 nm or less.

7. The semiconductor device of claim 1 or 2, wherein the portion of the gate electrode that is higher than the upper surface of the insulating layer has a tapered shape that becomes wider as it approaches the insulating layer when viewed in cross-section in a direction perpendicular to the direction in which the source electrode and the drain electrode are arranged and parallel to the upper surface of the substrate.

8. The semiconductor device of claim 1 or 2, wherein the insulating layer is an amorphous layer.

9. A semiconductor device comprising: a substrate; a semiconductor layer disposed on the substrate; an insulating layer disposed on the semiconductor layer and having a first opening; a gate electrode disposed on the insulating layer and in contact with the semiconductor layer through the first opening; and a source electrode and a drain electrode, etc., in ohmic contact with the semiconductor layer; wherein the gate electrode comprises: a ZnO film disposed on the insulating layer and having a second opening, the second opening being formed such that its inner wall is connected to the inner wall of the first opening; a Ni film disposed on the ZnO film and in Schottky contact with the semiconductor layer through the inner walls of the second opening and the first opening being connected to each other; and an Au film disposed on the Ni film, having a lower resistance than the Ni film.

10. A method for manufacturing a semiconductor device, comprising the following steps: forming a semiconductor layer on a substrate; forming a source electrode and a drain electrode in ohmic contact with the semiconductor layer; forming an insulating layer on the semiconductor layer; forming a crystallinity control film on the insulating layer; forming a second opening in the crystallinity control film; forming a first opening in the insulating layer such that the inner wall of the second opening is connected to the inner wall of a first opening; forming a resist mask having a third opening having an opening width larger than the opening widths of the second opening and the first opening; forming a first metal film in Schottky contact with the semiconductor layer on the crystallinity control film through the third opening and through the inner walls of the second opening and the first opening, which are respectively connected to each other; forming a second metal film with a lower resistance than the first metal film on the first metal film through the third opening; and removing the resist mask.

11. The method for manufacturing a semiconductor device as claimed in claim 10, wherein in the step of forming the crystallinity control film, the temperature of the substrate is 150°C or higher and 500°C or lower.

12. A method for manufacturing a semiconductor device as claimed in claim 10 or 11, wherein the first metal film and the second metal film are formed by vapor deposition.

13. The method for manufacturing a semiconductor device as claimed in claim 10 or 11, wherein the temperature of the substrate in the steps of forming the first metal film and forming the second metal film is 80°C or below.

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