Process for fabricating a double semiconductor-on-insulator structure

Abstract

This invention relates to a method for fabricating a semiconductor-on-insulator structure, comprising the following steps: providing a first donor substrate and an operating substrate (1); forming a weakening region in the donor substrate to define a first semiconductor layer (2b) to be transferred; bonding the first donor substrate to the operating substrate (1); a first electrical insulating layer (2a) located at the interface and separated in the weakening region; processing the surface of the transferred first semiconductor layer (2b), comprising: (E1) rapid thermal tempering; (E2) thermal oxidation followed by deoxidation treatment; (E3) a smoothing heat treatment at a temperature above 1000°C in a non-oxidizing atmosphere; (E4) chemical mechanical polishing; providing a second donor substrate for a second semiconductor layer (3b) to be transferred; transferring the second semiconductor layer (3b); a second electrical insulating layer (3a) located at the interface.

Description

[Technical Field]

[0001] This invention relates to a method for fabricating a double semiconductor-on-insulator structure. [Previous Technology]

[0002] A semiconductor-on-insulator (SOI) structure is a multilayer structure comprising an operating substrate, typically made of a semiconductor such as silicon; an electrically insulating layer disposed on the operating substrate, typically an oxide layer such as silicon oxide; and a semiconductor layer disposed on the insulating layer, typically a silicon layer. This structure is called a "semiconductor-on-insulator" structure, particularly a "silicon-on-insulator" (SOI) structure when the semiconductor is silicon. The oxide layer is located between the substrate and the semiconductor layer. This oxide layer is then referred to as "buried oxide," or "BOX." For the remainder of this document, the term "SOI" will be used to denote a semiconductor-on-insulator structure.

[0003] In addition to the SOI structure comprising a BOX layer and a semiconductor layer disposed on the BOX layer, a "dual SOI" structure now exists. The "dual SOI" structure includes an operating substrate, a first oxide layer or a lower buried oxide layer disposed on the operating substrate, a first semiconductor layer or a lower semiconductor layer disposed on the first oxide layer, a second oxide layer or an upper buried oxide layer disposed on the first semiconductor layer, and a second semiconductor layer or an upper semiconductor layer disposed on the second oxide layer. In this dual SOI structure, the first oxide layer and the first semiconductor layer constitute a first SOI and are disposed at the lower part of the structure; while the second oxide layer and the second semiconductor layer constitute a second SOI and are disposed at the upper part of the structure.

[0004] A known method for fabricating an SOI structure is called the Smart Cut™ method. The Smart Cut™ method involves implanting atomic species, such as hydrogen (H) and / or helium (He), to create a weakened region within a donor substrate, bonding the donor substrate to a acceptor substrate via an electrically insulating layer, and then separating the donor substrate in the weakened region to transfer a thin layer from the donor substrate to the acceptor substrate. The donor substrate and the acceptor substrate are preferably in the form of a semiconductor wafer with a diameter of 300 mm. The electrically insulating layer may be formed on the donor substrate or on the acceptor substrate.

[0005] One proposed solution for obtaining a dual SOI is to perform two consecutive Smart Cut™ methods. During the second Smart Cut™ method, the SOI obtained after the first Smart Cut™ method serves as the second acceptor substrate, and the second donor substrate is bonded to the second acceptor substrate via a second electrical insulating layer.

[0006] The effectiveness of bonding during the second Smart Cut™ process depends on the surface quality of the first SOI, which serves as the acceptor substrate. This is particularly true after the first donor substrate is separated along the weakened zone during the first Smart Cut™ process, due to its surface roughness and defect density. Specifically, during bonding in the second Smart Cut™ process, defects and other surface irregularities lead to the formation of voids between the acceptor and second donor substrates within the final dual SOI. These voids typically negatively impact the electrical performance of the structure and the mechanical strength of the component.

[0007] After separating the first donor substrate, surface treatment can be performed to reduce the surface roughness and defect density of the first SOI.

[0008] Common surface treatments are heat treatments, such as rapid hot tempering or furnace tempering. Chemical mechanical polishing can also be performed. Finally, chemical treatments that oxidize and then deoxidize the relevant surfaces can be applied.

[0009] However, the surface quality achieved by applying these techniques is insufficient to enable the second donor substrate to bond well to the surface during the new layer transfer step. [Summary of the Invention]

[0010] One object of the present invention is to provide a method for fabricating a semiconductor-on-insulator structure that ensures good bonding of the donor substrate of the second semiconductor layer to the acceptor substrate produced by the first Smart Cut™ method.

[0011] To this end, the present invention provides a method for fabricating a semiconductor-on-insulator structure, comprising the following steps: providing a first donor substrate and an operating substrate; forming a weakening region in the first donor substrate to define a first semiconductor layer to be transferred; bonding the first donor substrate to the operating substrate; a first electrical insulating layer located at the interface between the operating substrate and the first donor substrate; separating the first donor substrate in the weakening region to obtain a semiconductor-on-insulator structure, which includes the operating substrate, the first electrical insulating layer, and the first semiconductor layer to be transferred from the back side to the front side; processing the free surface of the first semiconductor layer to be transferred; providing a second donor substrate having a second semiconductor layer to be transferred; transferring the second semiconductor layer to the front side of the semiconductor-on-insulator structure; a second electrical insulating layer located at the interface between the first semiconductor layer to be transferred and the second donor substrate; wherein processing the surface of the first semiconductor layer to be transferred includes the following consecutive steps: E1: rapid thermal tempering. E2: Includes a sequence of thermal oxidation followed by deoxidation treatment; E3: A smoothing heat treatment performed in a non-oxidizing atmosphere at a temperature above 1000°C; E4: Chemical mechanical polishing.

[0012] The free surface of the first semiconductor layer is generated by separating the first donor substrate along the weakened region. The method for processing this surface is optimized to reduce its roughness and defect density. This method also allows for a reduction in the width of the ring on the outer edge of the second acceptor substrate. Consequently, the reduced defect density, roughness, ring width, and ring irregularity (a phenomenon known as "serrated edge") on the wafer outer edge limit the number of voids formed during the bonding of the donor substrate to the second semiconductor layer.

[0013] According to other selective features of the present invention, when technically feasible, they may be used alone or in combination as follows: The smoothing heat treatment step E3 is a long-term heat tempering performed at a temperature between 1050°C and 1250°C in an atmosphere of pure or mixed hydrogen or argon for several minutes to several hours; The heat treatment step E3 is a rapid heat tempering; The smoothing heat treatment step E3 is performed at a temperature between 1100°C and 1250°C in an atmosphere containing pure or mixed hydrogen or argon for several seconds to about 100 seconds; The rapid heat tempering step E1 is performed at a temperature between 1100°C and 1250°C in an atmosphere containing pure or mixed hydrogen or argon for several seconds to about 100 seconds; The thermal oxidation operation of step E2 is performed at a temperature between 800°C and 1100°C in an atmosphere containing oxygen or water vapor for several minutes to several hours; The deoxidation operation of step E2 is performed by exposing the surface to be treated to a hydrofluoric acid solution; The operating substrate and each donor substrate are in the form of a 300 mm diameter wafer; the weakening region in the first donor substrate is formed by implanting hydrogen atoms; the transfer of the second semiconductor layer includes: forming a weakening region in the second donor substrate to define a second semiconductor layer to be transferred; bonding the second donor substrate to the front side of the semiconductor-on-insulator structure; a second electrical insulating layer located at the interface between the front side of the semiconductor-on-insulator structure and the first donor substrate; separating the second donor substrate in the weakening region to obtain a double semiconductor-on-insulator structure, which includes, from the back side to the front side, the operating substrate, the first electrical insulating layer, the first semiconductor layer to be transferred, the second electrical insulating layer, and the second semiconductor layer to be transferred; the weakening region in the second donor substrate is formed by implanting hydrogen atoms; the second electrical insulating layer is formed by oxidizing the front side of the first semiconductor layer to be transferred, so that when the second semiconductor layer is transferred, the first electrical insulating layer is sandwiched between the first semiconductor layer and the second semiconductor layer, and this additional oxidation step is performed after processing the free surface of the first semiconductor layer; The second electrical insulating layer is formed by oxidizing a portion of the second donor substrate, so that when the second semiconductor layer is transferred, the first electrical insulating layer is also transferred and sandwiched between the first semiconductor layer and the second semiconductor layer; the first electrical insulating layer is formed by oxidizing the front side of the operating substrate before the first donor substrate is bonded to the operating substrate, so that the first electrical insulating layer is sandwiched between the operating substrate and the transferred first semiconductor layer; the first electrical insulating layer is formed by oxidizing a portion of the first donor substrate before the first donor substrate is bonded to the operating substrate via its oxidized surface, so that the first electrical insulating layer is sandwiched between the operating substrate and the transferred first semiconductor layer.

Implementation Method

[0016] A dual SOI substrate structure, which from back to front includes an operating substrate, a first buried oxide layer corresponding to a first electrical insulating layer, a first single crystal semiconductor layer, a second buried oxide layer corresponding to a second electrical insulating layer, and a second single crystal semiconductor layer.

[0017] The first electrically insulating layer and the first single-crystal semiconductor layer together form a first SOI structure called the "lower SOI structure". The second electrically insulating layer and the second single-crystal semiconductor layer together form a second SOI structure called the "upper SOI structure".

[0018] The present invention relates to a method for preparing a dual SOI structure, comprising: firstly transferring a first single-crystal semiconductor layer according to the Smart Cut™ method to prepare a lower SOI structure, an intermediate surface treatment method, and then preparing an upper SOI structure by transferring a single-crystal semiconductor layer.

[0019] More specifically, the present invention relates to an intermediate surface treatment process performed after the Smart Cut™ method for transferring a first single-crystal semiconductor layer, the Smart Cut™ method and other layer transfer methods being known.

[0020] The surface treatment method of the present invention has been optimized to minimize the surface roughness and defect density formed after the implementation of the first Smart Cut™ method, so as to improve the bonding quality during the second layer transfer.

[0021] Roughness as referred to below means the maximum peak-to-valley ranges measured by atomic force microscopy (AFM) on a surface profile between 1×1 µm 2 and 30×30 µm 2.

[0022] Regarding defect density, it is defined as the number of particles deposited on the free surface of a wafer and / or the number of structural defects (such as holes or scratches) present on the wafer surface. These defects have various sizes, such as between 60 nm and several micrometers. These defects may be caused by impurities resulting from irregular edges (serrated edges) of local separation rings, or they may be caused by contamination. Defect density is measured using equipment that employs optical diffusion technology, such as the SP2 device from KLA-Tencor.

[0023] The method of the present invention also aims to widen the effective bonding area of ​​the second transfer layer in order to reduce the width of the peripheral ring of the second SOI substrate.

[0024] The term "ring" refers to the peripheral region of the SOI substrate where the single-crystal semiconductor layer has not been transferred. This ring is based on the fact that the substrate typically has a chamfer several millimeters wide at its perimeter, where the donor substrate cannot bond to the acceptor substrate. Therefore, during the Smart Cut™ method, the single-crystal semiconductor layer of the donor substrate only transfers to the acceptor substrate in the central region where bonding occurs. In some cases, isolated regions of the donor substrate can still transfer to the ring. However, this ring is not perfectly circular but has irregular, serrated edges.

[0025] In the case of a double SOI structure, the problem of irregular rings occurs twice: once when the first SOI substrate is fabricated and again when the second SOI substrate is fabricated, thus significantly affecting the useful width of the upper semiconductor layer. Therefore, if the width of the ring after the first layer transfer is typically between 0.7 mm and 1.5 mm, then the width of the "double ring" resulting from the second layer transfer is between 3 mm and 4 mm.

[0026] The surface treatment method according to the present invention is characterized by comprising four consecutive steps, each of which is a known surface treatment method and can therefore be applied to the parameters defined below.

[0027] However, taking these steps individually alone cannot achieve the expected performance level of effective bonding of good quality, and thus cannot get rid of defects such as bonding interface voids and excessively wide rings in the context of making dual SOI structures.

[0028] The various steps of the intermediate surface treatment method of the present invention and their effects on the surface quality of the treated surface are described in detail below. For informational purposes, embodiments for preparing lower and upper SOI structures are also described below.

[0029] Fabrication of the Lower SOI Structure First, a first lower semiconductor-on-insulator (SOI) structure is fabricated by transferring a single-crystal semiconductor layer. This structure is illustrated in Figure 1. The first transfer is performed using the Smart Cut™ method, which includes the following steps: providing a first donor substrate and an operating substrate 1 for the first single-crystal semiconductor layer 2b; forming a weakening region in the first donor substrate to define the first semiconductor layer 2b to be transferred; bonding the first donor substrate to the operating substrate 1; a first electrical insulating layer 2a located at the interface between the operating substrate 1 and the first donor substrate; and separating the first donor substrate in the weakening region.

[0030] The operating substrate 1 is in the form of a circular semiconductor wafer, preferably a wafer with a diameter of 300 mm. For example, the operating substrate is a silicon wafer. The operating substrate is preferably an ultra-flat silicon wafer, which has a narrower and steeper chamfer than a conventional wafer.

[0031] The width of the wafer edge chamfer can be evaluated using the ZDD148 characteristic, which corresponds to the second derivative of the wafer edge profile at a distance of 2 mm from the wafer edge; in other words, it is the reciprocal of the radius of curvature of the wafer edge. Typically, the ZDD148 for a 300 mm diameter silicon wafer is between -20 and -200 nm / mm². ZDD148 is measured using a KLA-Tencor Wafersight instrument. Silicon wafers known as ultra-flat wafers have a ZDD148 characteristic between 0 and -20 nm / mm².

[0032] Using ultra-flat silicon wafers can reduce the width of the peripheral ring.

[0033] The first donor substrate is a single-crystal semiconductor substrate, such as a single-crystal silicon substrate. The first donor substrate is in wafer form and typically has the same diameter as the operating substrate.

[0034] The weakened region can be generated by co-implanting helium and hydrogen atoms into the first donor substrate of the first semiconductor layer. Helium and hydrogen are implanted at energies between 10 keV and 100 keV, with implantation doses between 10¹⁵ and 10¹⁷ atoms per square centimeter. Alternatively, the weakened region is preferably generated by implanting hydrogen atoms. Co-implanting helium and hydrogen atoms has the advantage of allowing the donor substrate to be more completely peeled along the weakened region, resulting in a lower roughness of the transferred semiconductor layer, on the order of 50 or 60 Å RMS when measured with 30 × 30 µm² AFM, but also exhibiting jagged edges. This phenomenon is more pronounced the thicker the transferred semiconductor layer. Implanting only hydrogen atoms has the advantage of eliminating jagged edges, but on the other hand, it results in a higher roughness of the transferred semiconductor layer. In this case, the roughness measured using 30 × 30 µm² AFM is on the order of 80 Å RMS. However, the process described below will yield a final surface of the transferred first semiconductor layer that is smooth enough to form the second SOI substrate. Therefore, given the advantages presented in limiting jagged edges, implanting only hydrogen atoms is superior to co-implanting helium and hydrogen atoms.

[0035] Separation along the weakened zone can be triggered by mechanical action, thermal contribution, a combination of both as needed, or any other suitable method.

[0036] According to the embodiment illustrated in FIG2, a first electrically insulating layer 2a is formed on the first donor substrate before atoms are implanted through the first electrically insulating layer 2a to form a weakened region within the first donor substrate. The first donor substrate is bonded to the operating substrate 1 via its electrically insulating surface, such that the first electrically insulating layer 2a and the first semiconductor layer 2b are simultaneously transferred and sandwiched between the operating substrate 1 and the transferred first semiconductor layer 2b. The first electrically insulating layer 2a is formed by, for example, oxidizing the front side of the first donor substrate, such that if the first donor substrate is a silicon substrate, then the first electrically insulating layer 2a is a silicon oxide layer.

[0037] According to an alternative embodiment illustrated in FIG3, a first electrically insulating layer 2a is formed on the front side of the operating substrate 1 before the first donor substrate is bonded to the operating substrate, such that the first electrically insulating layer 2a is sandwiched between the operating substrate 1 and the transferred first semiconductor layer 2b. The first electrically insulating layer 2a is formed by, for example, oxidizing the front side of the operating substrate 1, such that if the operating substrate 1 is a silicon substrate, then the first electrically insulating layer 2a is a silicon oxide layer.

[0038] The front surface of the lower SOI structure formed when separating the first donor substrate along the weakened region has roughness and defect density, which are related to the implantation quality of atomic species inside the first donor substrate during the first Smart Cut™ method. As mentioned above, depending on the type of implantation, this roughness can be relatively large, on the order of approximately 50 Å RMS to 80 Å RMS.

[0039] During the second layer transfer in the fabrication of the upper SOI structure, specific defect densities and surface roughness may lead to the formation of pores or defects when bonding the second donor substrate. For example, a roughness greater than 5 Å RMS can produce a pore density on the order of several pores per square centimeter.

[0040] These holes can cause components made with porous SOI substrates to malfunction. Furthermore, the holes are not evenly distributed on the substrate. This unevenness in defect distribution leads to high variability in performance between various components made with the same substrate.

[0041] Therefore, components produced on substrates with high porosity will be inoperable or have high performance variability, which is unacceptable for manufacturers of microelectronic components, especially photonic components.

[0042] Furthermore, the wafers of the operating substrate 1 and the first donor substrate do not have edges perpendicular to the surface, but rather have chamfers or "edge roll-off". Therefore, regarding the surface of the substrate, the first donor substrate can only bond to the operating substrate up to the chamfer at most, and cannot reach the edge of the two substrates. Thus, the transfer portion of the donor substrate does not extend beyond the entire surface of the operating substrate. The outer side of the peripheral ring is defined by the edge of the acceptor substrate, and the inner side is defined by the edge of the transfer layer. For a 300 mm wafer, the peripheral ring CP typically has a width between 0.7 mm and 1.5 mm relative to the wafer edge.

[0043] In fact, as mentioned earlier, the rings typically have irregular shapes (serrated edges) due to the presence of improperly bonded transition regions. These transition regions represent a potential source of defect density: specifically, multiple portions of the transition region can be separated and deposited on the surface of the SOI. During the second layer transfer in fabricating the upper SOI structure, surface finishing also leads to the formation of numerous voids or defects, resulting in double rings that are significantly wider than those produced by the first layer transfer, on the order of 3 to 4 mm. Such widths are unacceptable, especially for photonics applications, which require the fabrication of wafers up to 3 mm from the edge of the silicon wafer.

[0044] The following describes the method of the present invention that can achieve the expected performance level.

[0045] Surface treatment prior to the second layer transfer: Due to the Smart Cut™ method, the front side of the first semiconductor layer is formed when the first donor substrate separates along the weakened region. This invention relates to a method for processing this surface. The processing method according to this invention aims not only to reduce the surface roughness and defect density, but also to reduce the width of the peripheral ring, thereby improving the bonding quality of the second donor substrate.

[0046] According to the present invention, the treatment of the free surface of the first semiconductor layer 2b and / or the second semiconductor layer involves the continuous implementation of the following steps, as shown in FIG4: (E1) rapid thermal tempering, (E2) oxidation / deoxidation treatment sequence, (E3) long-term thermal tempering, referred to by those skilled in the art as batch tempering, (E4) chemical mechanical polishing.

[0047] As an alternative, the long-duration hot tempering step (E3) can be replaced by a rapid hot tempering step (E3').

[0048] "Rapid thermal annealing" refers to annealing under controlled gas conditions for several seconds or tens of seconds. This type of annealing is usually abbreviated as RTA. Rapid thermal annealing (E1) is performed at temperatures between 1100°C and 1250°C for 1 to 90 seconds. Rapid thermal annealing (E1) is performed under a gas mixture containing argon and hydrogen or under a pure argon gas.

[0049] Rapid thermal tempering can strengthen the bonding interface between the operating substrate and the transferred semiconductor layer. It can also smooth the surface of the transferred semiconductor layer by rearranging the atoms present on the surface, and can also restore the lattice that may have been damaged by implantation. However, this is not enough to achieve the roughness level required for bonding the second donor substrate and then transferring the semiconductor layer of the second donor substrate to the first SOI.

[0050] The following oxidation / deoxidation steps (E2) must be understood as including the following sequence of operations: a thermal oxidation operation (E2a), a chemical deoxidation operation (E2b).

[0051] The oxidation operation (E2a) can be carried out by heating the structure at a temperature between 800°C and 1100°C for several minutes to several hours, for example, under an oxidizing gas, such as water vapor (wet oxidation) or only oxygen (dry oxidation). During this oxidation, both sides of the first SOI are oxidized. The deoxidation operation (E2b) can be carried out, for example, by exposing the front side of the structure to a hydrofluoric acid (HF) solution for several seconds to several minutes, to remove the oxide layer formed on the front side without removing the oxide layer on the back side of the structure.

[0052] This oxidation / deoxidation step consumes the silicon surface portion by oxidizing and then removing it. Consuming the surface silicon not only adjusts the thickness of the semiconductor layer, but also eliminates defects that appear on the surface of the transferred layer after Smart Cut™ layer transfer.

[0053] Long-duration heat tempering or batch tempering corresponds to heat tempering on the order of minutes to hours, typically exceeding 15 minutes, which is advantageously carried out in a furnace under controlled gas. Multiple substrate sheets can be processed simultaneously using the furnace.

[0054] Hot tempering (E3) is carried out in an inert gas, such as in a pure or mixed hydrogen or argon gas, at a temperature between 1050°C and 1250°C for several minutes to several hours.

[0055] Temperature (E3) smooths the surface of the transferred semiconductor layer and thus reduces its roughness.

[0056] The surface treatment method according to the present invention finally includes a final chemical mechanical polishing step (E4).

[0057] In the process of chemical mechanical polishing or CMP, the surface to be polished is modified with a chemical agent, such as a suspension of colloidal silica particles in a base liquid, and the modified surface is removed by mechanical abrasion. The rotational speed and pressure used during the CMP step (E4) are optimized to uniformly remove material from the surface of the transferred semiconductor layer or second electrical insulating layer without degrading the surface quality, especially without increasing its roughness.

[0058] Specifically, this chemical mechanical polishing can remove surface particles. Furthermore, as this polishing continues to the substrate edge, the irregularity of the first SOI thickness can be gradually reduced until the wafer edge of the first SOI ring, allowing the second bonding to be closer to the wafer edge. Therefore, the width of the ring caused by the second transfer performed by Smart Cut™ is reduced.

[0059] As an alternative, rapid thermal tempering (E3') is performed for several seconds to about 100 seconds at a temperature between 1100°C and 1250°C, for example in a gas containing only argon or hydrogen, or in a gas containing a mixture of argon or hydrogen.

[0060] The upper SOI structure is prepared with reference to FIG5. Then, the second single crystal semiconductor layer 3b generated by the second donor substrate is transferred to the front side of the first SOI structure to form a second / upper SOI structure on the lower SOI structure. The second electrical insulating layer 3a is located at the interface between the transferred first semiconductor layer and the second donor substrate.

[0061] The second donor substrate is a single-crystal semiconductor substrate, such as a single-crystal silicon substrate. The second donor substrate is in the form of a circular wafer, which typically has the same diameter as the operating substrate.

[0062] According to one embodiment, the second layer transfer is performed according to the second Smart Cut™ method, which includes: forming a weakening region in the second donor substrate to define the second semiconductor layer 3b to be transferred; bonding the second donor substrate to the front side of the SOI structure, the second electrical insulating layer 3a being located at the interface between the front side of the SOI structure and the first donor substrate; and separating the second donor substrate in the weakening region to obtain the dual SOI structure illustrated in FIG5.

[0063] Similar to the first donor substrate, a weakening region within the second donor substrate can be generated by co-implanting helium and hydrogen atoms into the second donor substrate of the second semiconductor layer. Alternatively, the weakening region can be generated by implanting hydrogen atoms.

[0064] As an alternative to the Smart Cut™ method, the second layer transfer can be performed by thinning the second donor substrate relative to the side bonded to the second electrical insulating layer until the desired thickness of the second semiconductor layer 3b is obtained.

[0065] According to the embodiment illustrated in FIG6, the second electrical insulating layer 3a is formed on the second donor substrate, so that when the second semiconductor layer 3b is transferred, the second electrical insulating layer 3a is also transferred and inserted between the first semiconductor layer 2b and the second semiconductor layer 3b. The second electrical insulating layer 3a is prepared, for example, by oxidizing the second donor substrate, so that if the second donor substrate is a silicon substrate, the second electrical insulating layer 3a is a silicon oxide layer.

[0066] In an embodiment of the second layer transfer performed according to the second Smart Cut™ method, the second electrical insulating layer 3a is preferably formed on the second donor substrate before the second electrical insulating layer 3a is implanted with atoms to form a weakening region within the second donor substrate.

[0067] According to the alternative embodiment illustrated in FIG7, a second electrically insulating layer 3a is formed on the first semiconductor layer 2b, such that when the second semiconductor layer 3b is transferred, the second electrically insulating layer 3a is inserted between the first semiconductor layer 2b and the second semiconductor layer 3b. The second electrically insulating layer 3a is, for example, prepared by oxidizing the front side of the transferred first semiconductor layer 2b, such that if the first donor substrate is a silicon substrate, the second electrically insulating layer 3a is a silicon oxide layer. This additional step of forming the second electrically insulating layer 3a is performed after processing the free surface of the first semiconductor layer 2b. Alternatively, steps (E1), (E2), and (E3) of the method are performed on the free surface of the transferred first semiconductor layer 2b before the step of forming the second electrically insulating layer 3a, and step (E4) can be performed on the surface of the transferred first semiconductor layer 2b and the surface of the second electrically insulating layer 3a, respectively, before and after the step of forming the second electrically insulating layer 3a.

[0068] Before the second single-crystal semiconductor layer 3b is then transferred, the free surface of the second electrical insulating layer 3a may be advantageously cleaned once or several times.

[0069] For example, by implementing the surface treatment method according to the present invention, especially by combining thermal smoothing and CMP steps, and using an "ultra-flat" operating substrate, an SOI structure with very few or even no pores and a double ring with a width of less than 3 mm can be obtained.

[0070] As needed, the free surface of the second semiconductor layer 3b may also be treated to reduce defects in the layer and smooth its surface to obtain the properties required for subsequent applications (fabrication of electronic components, epitaxy, etc.). These treatments are well known to those skilled in the art and include, for example, rapid thermal tempering. [Simplified Explanation of the Diagram]

[0014] Other features and advantages of the present invention will become apparent in the following detailed description with reference to the accompanying drawings, in which: FIG1 shows a cross-sectional view of the intermediate SOI structure obtained after the first layer transfer; FIG2 shows a cross-sectional view of the first layer transfer from a first donor substrate to the operating substrate on one side, with a first electrically insulating layer formed on the surface of the first donor substrate; FIG3 shows a cross-sectional view of the first layer transfer from a first donor substrate to the operating substrate on one side, with a first electrically insulating layer formed on the surface of the operating substrate; FIG4 shows the sequence of processing steps according to the method of the present invention; FIG5 shows the final double SOI structure obtained after the second layer transfer; FIG6 shows a cross-sectional view of a second single-crystal semiconductor layer transferred through a second donor substrate, with a second electrically insulating layer formed on the second donor substrate; FIG7 shows a cross-sectional view of a second single-crystal semiconductor layer transferred through a second donor substrate, with a second electrically insulating layer formed on the structure of FIG2.

[0015] For clarity, the diagrams are not necessarily drawn to scale.

Claims

1. A method for fabricating a semiconductor-on-insulator structure, comprising the following steps: providing a first donor substrate and an operating substrate (1); forming a weakening region in the first donor substrate to define a first semiconductor layer (2b) to be transferred; bonding the first donor substrate to the operating substrate (1); a first electrical insulating layer (2a) located at the interface between the operating substrate (1) and the first donor substrate; separating the first donor substrate in the weakening region to obtain a semiconductor-on-insulator structure comprising, from back to front, the operating substrate (1), the first electrical insulating layer (2a), and the first semiconductor layer (2b) to be transferred; processing the free surface of the first semiconductor layer (2b) to be transferred; and providing a second donor substrate having a second semiconductor layer (3b) to be transferred. The second semiconductor layer (3b) is transferred to the front side of the semiconductor-on-insulator structure, and a second electrical insulating layer (3a) is located at the interface between the transferred first semiconductor layer (2b) and the second donor substrate. The processing of the free surface of the transferred first semiconductor layer (2b) includes the following sequential steps: (E1) rapid thermal tempering, (E2) a process including thermal oxidation followed by deoxidation, (E3) a smoothing heat treatment at a temperature above 1000°C in a non-oxidizing atmosphere, and (E4) chemical mechanical polishing.

2. The method of claim 1, wherein the smoothing heat treatment step (E3) is a long-term heat tempering at a temperature between 1050°C and 1250°C in a pure or mixed hydrogen or argon atmosphere for several minutes to several hours.

3. The method of request item 1, wherein the smooth heat treatment step (E3) is a rapid heat tempering.

4. The method of claim 3, wherein the smoothing heat treatment step (E3) is performed for several seconds to about 100 seconds at a temperature between 1100°C and 1250°C in an atmosphere containing pure or mixed hydrogen or argon.

5. The method of any one of claims 1 to 4, wherein the rapid thermal tempering step (E1) is performed for several seconds to about 100 seconds at a temperature between 1100°C and 1250°C in an atmosphere containing pure or mixed hydrogen or argon.

6. The method of claim 1, wherein the thermal oxidation operation of step (E2) is carried out at a temperature between 800°C and 1100°C in an atmosphere containing oxygen or water vapor for several minutes to several hours.

7. The method of claim 1, wherein the deoxidation operation in step (E2) is performed by exposing the surface to be treated to a hydrofluoric acid solution.

8. The method of claim 1, wherein the operating substrate (1) and each donor substrate are in the form of a wafer with a diameter of 300 mm.

9. The method of claim 1, wherein the weakened region in the first donor substrate is formed by implanting hydrogen atoms.

10. The method of claim 1, wherein transferring the second semiconductor layer (3b) comprises: A weakening region is formed in the second donor substrate to define a second semiconductor layer (3b) to be transferred. The second donor substrate is bonded to the front side of the semiconductor-on-insulator structure. A second electrical insulating layer (3a) is located at the interface between the front side of the semiconductor-on-insulator structure and the first donor substrate. The second donor substrate is separated in the weakening region to obtain a double semiconductor-on-insulator structure, which includes the operating substrate (1), the first electrical insulating layer (2a), the first semiconductor layer (2b) to be transferred, the second electrical insulating layer (3a), and the second semiconductor layer (3b) to be transferred from the back side to the front side.

11. The method of claim 10, wherein the weakened regions in the second donor substrate are formed by implanting hydrogen atoms.

12. The method of claim 1, wherein the second semiconductor layer (3b) is formed by oxidation of the front side of the first semiconductor layer (2b) to be transferred, such that when the second semiconductor layer (3b) is transferred, the first electrical insulating layer (3a) is sandwiched between the first semiconductor layer (2b) and the second semiconductor layer (3b), and the additional oxidation step is performed after processing the free surface of the first semiconductor layer (2b).

13. The method of claim 1, wherein the second electrical insulating layer (3a) is formed by oxidizing a portion of the second donor substrate, such that when the second semiconductor layer (3b) is transferred, the first electrical insulating layer (3a) is also transferred and sandwiched between the first semiconductor layer (2b) and the second semiconductor layer (3b).

14. The method of claim 1, wherein the first electrical insulating layer (2a) is formed by oxidizing the front side of the operating substrate (1) before the first donor substrate is bonded to the operating substrate, such that the first electrical insulating layer (2a) is sandwiched between the operating substrate (1) and the transferred first semiconductor layer (2b).

15. The method of claim 1, wherein the first electrical insulating layer (2a) is formed by oxidizing a portion of the first donor substrate before the first donor substrate is bonded to the operating substrate (1) via its oxide surface, such that the first electrical insulating layer (2a) is sandwiched between the operating substrate (1) and the transferred first semiconductor layer (2b).

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