Semiconductor structure and forming method thereof

Abstract

This disclosure provides a semiconductor structure and a method for forming the same. The method includes: forming a structure having a dummy gate stack on a multilayer stack, wherein the multilayer stack is disposed on a semiconductor substrate and includes alternating channel layers and non-channel layers; etching the multilayer stack in a source / drain region; removing the non-channel layers to form a first opening between the channel layers; depositing a dielectric material in the first opening; etching the dielectric material to form an undercut; forming an inner spacer in the undercut; forming epitaxial source / drain components in the source / drain region; removing the dummy gate stack to form a gate trench; removing the dielectric material in the gate trench to form a second opening between the channel layers; and forming a metal gate stack in the gate trench and the second opening.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor technology, and more particularly to semiconductor structures and methods of forming the same. Prior Art

[0002] The electronics industry experiences a continuously growing demand for smaller and faster electronic devices, while simultaneously supporting a greater number of increasingly complex and sophisticated functions. To meet these demands, there is a continuing trend within the integrated circuit (IC) industry toward producing low-cost, high-performance, and low-power ICs. To date, these goals have been largely achieved by reducing IC size (e.g., minimum IC component size), thereby increasing production efficiency and reducing associated costs. However, this scaling increases the complexity of IC manufacturing processes. Therefore, achieving continued advancements in IC devices and their performance requires similar advances in IC manufacturing processes and technologies.

[0003] Recently, multi-gate devices have been introduced to improve gate control. They have been observed to improve gate-channel coupling, reduce off-state current, and / or mitigate short-channel effects (SCE). One such multi-gate device is a gate-all-around (GAA) device, which includes a gate structure that extends partially or completely around the channel region to provide access to the channel region on at least two sides. GAA devices enable aggressive scaling of IC technology, maintain gate control, and mitigate SCE, while seamlessly integrating with traditional IC manufacturing processes. As GAA devices continue to scale, challenges arise. For example, existing structures and manufacturing technologies have various problems, especially as device dimensions shrink. These problems include abnormal doping diffusion, increased built-in stress, unexpected capacitance, device degradation, scaling limits on overlap requirements, and other structural and / or process-related issues. While existing structures and manufacturing technologies have gradually met their intended uses, they do not meet all requirements. Summary of the Invention

[0004] In some embodiments, a method for forming a semiconductor structure is provided. The method includes: forming a structure having a dummy gate stack on a multi-layer stack (ML), wherein the multi-layer stack is disposed on a semiconductor substrate and includes alternating channel layers and non-channel layers; recessing the multi-layer stack in a plurality of source / drain regions; removing the non-channel layers to form a plurality of first openings between the plurality of channel layers; depositing a dielectric material in the plurality of first openings; recessing the dielectric material to form a plurality of undercuts; forming a plurality of inner spacers in the plurality of undercuts; forming a plurality of epitaxial source / drain features in the plurality of source / drain regions; removing the dummy gate stack to form gate trenches; removing the dielectric material in the gate trenches to form a plurality of second openings between the plurality of channel layers; and forming a metal gate stack in the gate trenches and the plurality of second openings.

[0005] In some embodiments, a method for forming a semiconductor structure is provided. The method includes receiving a structure having a dummy gate stack located above a multilayer stack disposed on a semiconductor substrate, the dummy gate stack comprising a plurality of alternating channel layers and a plurality of non-channel layers, and the dummy gate stack comprising a plurality of source / drain regions adjacent to the plurality of channel layers and the plurality of non-channel layers; replacing the plurality of non-channel layers with a dielectric material; recessing the dielectric material to form a plurality of undercuts; forming inner spacers in the plurality of undercuts; forming a plurality of epitaxial source / drain features in the plurality of source / drain regions; and replacing a portion of the dummy gate stack and the dielectric material with a metal gate stack.

[0006] In some embodiments, a semiconductor structure is provided. The semiconductor device includes a semiconductor layer stack, a gate structure, an inner spacer, and the inner spacer. The semiconductor layer stack is disposed above a substrate. The gate structure surrounds each layer in the semiconductor layer stack. The inner spacer is interposed between the gate structure and a source / drain component and extends between two adjacent semiconductor layers in the semiconductor layer stack. A first dielectric layer is disposed on a sidewall of the gate structure. The first dielectric layer contacts the inner spacer and extends to the first semiconductor layer of the two adjacent semiconductor layers. The composition of the inner spacer is different from that of the first dielectric layer. Simple diagram description

[0007] The following describes embodiments of the present invention in detail with reference to the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of the components may be arbitrarily increased or decreased to clearly illustrate the features of the embodiments of the present invention. 1A and 1B are flow charts showing methods for manufacturing a semiconductor structure according to various aspects of the present disclosure. FIG. 2 is a top view of a semiconductor structure according to some embodiments of the present disclosure. 3, 4A to 9A, 10, and 11A to 12A are cross-sectional views of the semiconductor structure along line AA′ in FIG. 2 at various manufacturing stages according to some embodiments of the present disclosure. 4B to 9B, and 11B to 12B are enlarged views of a portion of the semiconductor structure shown in FIG. 4A to 9A, and FIG. 11A to 12A, respectively, according to some embodiments of the present disclosure. FIG. 11C is a cross-sectional view of the semiconductor structure shown in FIG. 11A and along line BB′ in FIG. 2 according to some embodiments of the present disclosure. Implementation Method

[0008] The following disclosure provides various embodiments or examples for implementing various components. Reference numerals and / or letters may be repeated throughout the various examples. This repetition is for the purpose of simplicity and clarity and is not intended to indicate a relationship between the various embodiments and / or configurations discussed. Furthermore, specific examples of various components and their configurations are described below to simplify the description of this disclosure. These are merely examples and are not intended to limit the embodiments of this disclosure. For example, a description of a first component being formed over or on a second component may include embodiments in which the first and second components are in direct contact, as well as embodiments in which an additional component is formed between the first and second components so that they are not in direct contact. Furthermore, in this disclosure, when a component is formed to be located on, connected to, and / or coupled to another component, this may include embodiments in which the components are formed in direct contact, as well as embodiments in which an additional component is formed between the components so that they are not in direct contact.

[0009] Furthermore, this disclosure may repeat reference numerals and / or letters throughout the various examples. This repetition is for the purpose of simplicity and clarity and is not intended to indicate a relationship between the various embodiments and / or configurations discussed. Furthermore, in this disclosure, when a component is formed to be located on, connected to, and / or coupled to another component, this may include embodiments in which the components are formed to be in direct contact, as well as embodiments in which additional components are formed between the components so that they are not in direct contact. Furthermore, spatially relative terms such as "lower," "upper," "horizontal," "vertical," "above," "over," "below," "beneath," "up," "down," "top," "bottom," and similar terms may be used herein to facilitate describing the relationship between one component and another in the drawings. Spatially relative terms are intended to encompass different orientations of components within a device. Furthermore, when using "about," "approximate," or similar terms to describe a number or range of numbers, these terms are intended to encompass a reasonable range inclusive of the number, such as within + / - 10% of the number, or other values ​​understood by those skilled in the art. For example, the term "approximately 5 nm" encompasses a size range of 4.5 nm to 5.5 nm.

[0010] Multi-gate devices, such as gate-all-around (GAA) devices, have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and mitigating short-channel effects (SCE). This allows for significant scaling of GAA devices while maintaining gate control and mitigating SCE. However, conventional approaches for GAA devices can face challenges, including abnormal dopant diffusion, increased built-in stress, unintended intermixing between semiconductor layers, device degradation, and increased capacitance between adjacent conductive regions, such as between SiGe residues in the source / drain regions. These drawbacks worsen with device scaling.

[0011] The present disclosure generally relates to integrated circuits (ICs), semiconductor devices, and methods for forming the same. More specifically, the present disclosure relates to gate-all-around (GAA) devices. A GAA device includes any device in which a gate structure, or a portion thereof, is formed around all sides of a channel region (e.g., surrounding a portion of the channel region). In some cases, a GAA device may also be referred to as a quad-gate device, in which the channel region has four sides and the gate structure is formed on all four sides. The channel region of a GAA device may include one or more semiconductor layers, each of which may have one of many different shapes, such as a wire (or nanowire), a sheet (or nanosheet), a bar (or nanorod), and / or other suitable shapes. In some embodiments, the channel region of a GAA device may have multiple horizontal semiconductor layers (such as nanowires, nanosheets, or nanorods) (hereinafter collectively referred to as a "nanochannel") spaced vertically apart, resulting in a stacked horizontal GAA device. The GAA devices presented herein can be complementary metal-oxide-semiconductor (CMOS) GAA devices, p-type metal-oxide-semiconductor (pMOS) GAA devices, or n-type metal-oxide-semiconductor (nMOS) GAA devices. Furthermore, the GAA devices can have one or more channel regions associated with a single, contiguous gate structure or multiple gate structures. Those skilled in the art will recognize other examples of semiconductor devices that can benefit from various aspects of the present disclosure. For example, other types of metal-oxide semiconductor field-effect transistors (MOSFETs), such as planar MOSFETs, FinFETs, and other multi-gate FETs, can benefit from the present disclosure. The GAA devices and fabrication methods disclosed herein exhibit desirable characteristics, examples of which include reduced dopant diffusion, reduced built-in stress, reduced device degradation, improved silicon performance, higher current drive, reduced short channel effects (SCE), and reduced capacitance between adjacent conductive regions, such as between source / drain regions and adjacent SiGe residues.

[0012] In the illustrated embodiment, an IC device includes a semiconductor structure (e.g., a GAA device) 200. Semiconductor structure 200 may be fabricated during the manufacturing process of an IC or a portion thereof and may include static random access memory (SRAM) and / or logic circuits, passive and active components, other memory cells, and combinations thereof. Passive components include resistors, capacitors, and inductors. Active components include p-type field-effect transistors (pFETs), n-type field-effect transistors (nFETs), FinFETs, MOSFETs, CMOS, bipolar transistors, high-voltage transistors, and high-frequency transistors.

[0013] Figures 1A to 1B are flow charts illustrating an exemplary method 100 for manufacturing an embodiment of a semiconductor structure according to some embodiments of the present disclosure. Figure 2 is a top view illustrating a semiconductor structure according to some embodiments of the present disclosure. Figures 3, 4A to 9A, 10, and 11A to 12A are cross-sectional views of the semiconductor structure at various manufacturing stages along line segment AA' in Figure 2 according to some embodiments of the present disclosure. Figures 4B to 9B, and 11B to 12B are enlarged views of a portion of the semiconductor structure in Figures 4A to 9A and 11A to 12A, respectively, according to some embodiments of the present disclosure. Figure 11C is a cross-sectional view of the semiconductor structure in Figure 11A and along line segment BB' in Figure 2 according to some embodiments of the present disclosure.

[0014] Referring to block 102 of FIG. 1A , and also to FIG. 2 and FIG. 3 , method 100 includes forming a semiconductor structure 200. The semiconductor structure 200 includes one or more fins 203 and one or more dummy gate stacks 210. The fins 203 protrude from a semiconductor substrate 202 and are separated by isolation features 201. The dummy gate stacks 210 are disposed above the fins 203.

[0015] In some embodiments, semiconductor substrate 202 includes a semiconductor material such as bulk silicon (Si). Alternatively or additionally, semiconductor substrate 202 may include another elemental semiconductor, such as a crystalline structure of germanium (Ge). Semiconductor substrate 202 may also include a compound semiconductor, such as silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb), or combinations thereof. The semiconductor substrate 202 may also include a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI), a silicon-germanium-on-insulator (SGOI), or a germanium-on-insulator (GOI) substrate.

[0016] A portion of the semiconductor substrate 202 may be doped, and such portion is referred to as a doped portion. The doped portion may be doped with a p-type dopant, such as boron (B) or boron fluoride (BF3), or with an n-type dopant, such as phosphorus (P) or arsenic (As). The doped portion may also be doped with a combination of p-type and n-type dopants (e.g., to form a p-type well and an adjacent n-type well). The doped portion may be formed directly on the semiconductor substrate 202, in a p-type well structure, in an n-type well structure, in a dual-well structure, or may be formed using a raised structure.

[0017] In some embodiments, semiconductor layers 204 and 206 (collectively referred to as a "multi-layer stack" or "ML") are formed on semiconductor substrate 202 in an interleaving or alternating manner, extending vertically from semiconductor substrate 202 (e.g., along the Z direction). For example, semiconductor layer 204 is disposed on semiconductor substrate 202, semiconductor layer 206 is disposed on semiconductor layer 204, another semiconductor layer 204 is disposed on semiconductor layer 206, and so on. In the depicted embodiment, there are three alternating semiconductor layers 206 and three alternating semiconductor layers 204. However, the multi-layer stack ML may have any suitable number of layers. For example, there may be two to ten alternating semiconductor layers 206 and two to ten alternating semiconductor layers 204 in the multi-layer stack ML. The material compositions of semiconductor layers 206 and semiconductor layers 204 are configured to provide an etch selectivity in a subsequent etching process. For example, in some embodiments, semiconductor layer 204 includes silicon germanium (SiGe), while semiconductor layer 206 includes silicon (Si). In some other embodiments, semiconductor layer 206 includes SiGe, while semiconductor layer 204 includes Si. In the depicted embodiment, each of semiconductor layers 206 has substantially the same thickness (e.g., the difference between the two semiconductor layers 206 is less than 5%), such as thickness T1 shown in FIG. 3 , and each of semiconductor layers 204 has substantially the same thickness (e.g., the difference between the two semiconductor layers 204 is less than 5%), such as thickness T2 shown in FIG. Thicknesses T1 and T2 range from approximately 2 nm to approximately 12 nm.

[0018] Next, the stack of semiconductor layers 204 and 206 is patterned into a plurality of fin structures, such as the plurality of fins 203 shown in FIG. Each of the fins 203 includes a stack of semiconductor layers 204 and 206 arranged in an alternating pattern relative to one another. Each of the plurality of fins 203 extends lengthwise (e.g., longitudinally) in a first direction (e.g., the Y direction) and is spaced apart (e.g., laterally) in a second direction (e.g., the X direction), as shown in FIG. It should be understood that the X and Y directions are horizontal directions perpendicular to each other, and the Z direction is a vertical direction perpendicular (or normal) to the plane defined by the X and Y directions. The top surface of the semiconductor substrate 202 can be aligned parallel to the XY plane.

[0019] Fins 203 can be patterned using any suitable method. For example, the fins can be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography with self-aligned processes, which allows for the creation of patterns with a finer pitch than can be achieved using a single, direct photolithography process, for example. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed adjacent to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers or mandrels can be used to pattern the fins. Patterning can utilize multiple etching processes, which may include dry etching and / or wet etching. The area where the fins are formed will be used to form active devices in subsequent processes and is therefore referred to as the active region. For example, each of the fins 203 is formed in the active region. In FIG. 2 , both fins 203 protrude from the semiconductor substrate 202 (eg, a doped portion).

[0020] Semiconductor structure 200 includes an isolation feature 201, which may be a shallow trench isolation (STI) feature. Isolation feature 201 is formed on semiconductor substrate 202 and surrounds active regions. In some examples, formation of isolation feature 201 includes etching trenches into semiconductor substrate 202 between active regions and filling the trenches with one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or combinations thereof. Isolation feature 201 may be deposited using any suitable method, such as a chemical vapor deposition (CVD) process, an atomic layer deposition (ALD) process, a physical vapor deposition (PVD) process, a plasma-enhanced CVD (PECVD) process, a plasma-enhanced ALD (PEALD) process, and / or combinations thereof. The isolation feature 201 may have a multi-layer structure, such as a thermal oxide liner layer on the semiconductor substrate 202 and a filler layer (e.g., silicon nitride or silicon oxide) on the thermal oxide liner. Alternatively, any other spacer formation technique may be used to form the isolation feature 201. Although not depicted, in some embodiments, the fin 203 is located above the top surface of the isolation feature 201 (e.g., protruding outside the isolation feature 201) and is also located above the top surface of the semiconductor substrate 202.

[0021] Referring to Figures 2 and 3 , a dummy gate stack 210 is formed over a portion of each of the fins 203 and over the isolation feature 201 , with the dummy gate stack 210 positioned between the fins 203 . The dummy gate stacks 210 can be configured to extend lengthwise (e.g., longitudinally) and parallel to each other. For example, each dummy gate stack 210 extends along the X-direction, as shown in Figure 2 . In some embodiments, each dummy gate stack 210 wraps around the top and side surfaces of each of the fins 203 . The dummy gate stacks 210 can include polysilicon. In some embodiments, the dummy gate stacks 210 also include one or more mask layers for patterning the dummy gate electrode layer. Subsequent processes may subject the dummy gate stack 210 to a gate replacement process to form a metal gate, such as a high dielectric constant (high-k) metal gate, as discussed in more detail below. The dummy gate stack 210 may also be subjected to a second gate replacement process to form a dielectric-based gate that electrically isolates the semiconductor structure 200 from adjacent devices. The dummy gate stack 210 may be formed by a process including deposition, lithographic patterning, and etching processes. The deposition process may include CVD, ALD, PVD, other suitable methods, and / or combinations thereof.

[0022] Referring to FIG. 3 , gate spacers 212 are formed on the sidewalls of the dummy gate stack 210. The gate spacers 212 comprise one or more dielectric materials and may include silicon nitride (Si 3 N 4 ), silicon oxide (SiO 2 ), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon oxynitride (SiON), silicon oxycarbon nitride (SiOCN), carbon doped oxide, nitrogen doped oxide, porous oxide, or a combination thereof. The gate spacers 212 may comprise a single layer or a multi-layer structure. In some embodiments, the thickness of each of the gate spacers 212 (e.g., measured in the Y direction) is approximately 3 nm to approximately 10 nm. For device performance, maintaining the thickness within a specified range may be desirable, particularly for advanced technology nodes. In some embodiments, the gate spacer 212 can be formed by depositing a spacer layer (comprising a dielectric material) over the dummy gate stack 210 and subsequently performing an anisotropic etching process to remove a portion of the spacer layer from the top surface of the dummy gate stack 210. After the etching process, a portion of the spacer layer on the sidewall surfaces of the dummy gate stack 210 remains, and this spacer layer becomes the gate spacer 212. In some embodiments, the anisotropic etching process is a dry etching process (e.g., a plasma etching process). Additionally or alternatively, the formation of the gate spacer 212 may involve chemical oxidation, thermal oxidation, ALD, CVD, and / or other suitable methods. In the active region, the gate spacer 212 is formed over the top layers of the semiconductor layer 204 and the semiconductor layer 206. Therefore, the gate spacer 212 may also be interchangeably referred to as a top spacer 212. In some examples, one or more material layers (not shown) may also be formed between the dummy gate stack 210 and the corresponding gate spacer 212. As an example, the one or more material layers may include an interfacial layer and / or a high-k dielectric layer.

[0023] Referring to block 104 in FIG. 1 , and referring to FIG. 4A , at least a portion of the exposed portion of the fin 203 (i.e., the source / drain region 207 of the fin 203 not covered by the dummy gate stack 210 ) is removed to form a source / drain recess (trench) 208 . The term "source / drain region" may be referred to as "source" or "drain" individually, or as "source and drain" collectively, depending on the context. In the depicted embodiment, the etching process completely removes the multilayer stack ML in the source / drain region 207 of the fin 203 , thereby exposing the substrate portion of the fin 203 in the source / drain region 207 . The source / drain recess 208 thus has sidewalls defined by the remaining portion of the multilayer stack ML disposed beneath the dummy gate stack 210 and a bottom defined by the semiconductor substrate 202 . The top surface 202 a of the semiconductor substrate 202 is exposed by the source / drain recess 208 . In some embodiments, the etching process removes a portion, but not all, of the multilayer stack ML, such that the source / drain recess 208 has a bottom defined by the semiconductor layer 204 or the semiconductor layer 206 in the source / drain region 207. In some embodiments, the etching process further removes a portion, but not all, of the substrate portion of the fin 203, such that the source / drain recess 208 extends below the topmost surface of the semiconductor substrate 202. In other words, the top surface 202a is lower than the topmost surface of the semiconductor substrate 202. The etching process may include a dry etching process, a wet etching process, other suitable etching processes, or a combination thereof. In some embodiments, the etching process is a multi-step etching process. For example, the etching process may alternate etchants to separately and alternately remove the semiconductor layer 204 and the semiconductor layer 206. In some embodiments, the etching process parameters are configured to selectively etch the multilayer stack ML while minimally etching (or not etching) the dummy gate stack 210, the gate spacer 212, and / or the isolation feature 201. In some embodiments, a lithography process, such as those described herein, is performed to form a patterned mask layer covering the dummy gate stack 210 and the gate spacers 212 and / or the isolation features 201, and an etching process uses the patterned mask layer as an etch mask.

[0024] FIG4B is an enlarged view of a portion (indicated by the dashed rectangle) of the semiconductor structure 200 in FIG4A . In some embodiments, the semiconductor structure 200 further includes an intermixed layer 205 (also referred to as a "transmission layer") comprising a mixture of materials from the semiconductor layer 204 and the semiconductor layer 206. In some embodiments, the intermixed layer 205 is formed by epitaxial growth of the semiconductor layers 204 and 206. The multilayer stack ML may include the intermixed layer 205, a core layer 206a, and a core layer 204a. The core layer 206a and the core layer 204a each include a relatively high concentration (e.g., greater than 90%) of the material (e.g., Si or SiGe) of the semiconductor layer 204 and the semiconductor layer 206, respectively. Each of the semiconductor layers 206 may include the core layer 206a and at least a portion of the intermixed layer 205. Each of the semiconductor layers 204 may include the core layer 204a and at least a portion of the intermixed layer 205. In some embodiments, the core layer 206a is adjacent to and located above the intermixed layer 205. In the intermixed layer 205, the material concentration of the core layer 206a (e.g., Si) gradually decreases from approximately 90% to approximately 10% from top to bottom in the Z direction. The material concentration of the core layer 204a (e.g., SiGe) gradually increases from approximately 10% to approximately 90% from top to bottom in the Z direction. In these embodiments, the atomic percentage of Ge in the intermixed layer 205 gradually increases from approximately 0.005% to approximately 20% from top to bottom in the Z direction. In some other embodiments, the core layer 204a is adjacent to and located above the intermixed layer 205. In the intermixed layer 205, the material concentration of the core layer 206a (e.g., Si) gradually increases from approximately 10% to approximately 90% from top to bottom in the Z direction. The material concentration (e.g., SiGe) of the core layer 204a decreases gradually from approximately 90% to approximately 10% from top to bottom in the Z direction. In some embodiments, the atomic percentage of Ge in the intermixed layer 205 decreases gradually from approximately 20% to approximately 0.005% from top to bottom in the Z direction. In some embodiments, the material concentration (e.g., Si) of the semiconductor substrate 202 in the bottommost intermixed layer 205 increases gradually from approximately 10% to approximately 90% from top to bottom in the Z direction. The material concentration (e.g., SiGe) of the core layer 204a decreases gradually from approximately 90% to approximately 10% from top to bottom in the Z direction.

[0025] In the depicted embodiment, the core layer 206a interfacing with only one intermixed layer 205 has a thickness T3 of about 2 nm to about 12 nm, the core layer 206a interfacing with two intermixed layers 205 has a thickness T6 of about 2 nm to about 1 nm, and the core layer 204a interfacing with two intermixed layers 205 has a thickness T5 of about 2 nm to about 12 nm. Each of the intermixed layers 205 has a substantially identical thickness T4 (e.g., a difference of less than or equal to 5%), which is about 0.1 nm to about 2 nm. Thickness T5 may be equal to thickness T6. In some embodiments, thickness T5 is different from thickness T6.

[0026] In some embodiments, each of the semiconductor layer 204, the semiconductor layer 206, and the intermixed layer 205 has a uniform profile in each XY plane. For example, the concentration of the material (e.g., SiGe) in the core layer 204a is substantially uniform across the XY plane across one intermixed layer 205. Therefore, the interface between the intermixed layer 205 and the adjacent core layer 204a or core layer 206a extends along the XY plane, and the thickness of each core layer 206a or core layer 204a is substantially the same at different locations on the XY plane. For example, the thickness of the sidewalls of a core layer 206a adjacent to the core layer 206a or the thickness of the sidewalls of a core layer 204a adjacent to the core layer 204a is substantially the same (e.g., differs by less than 5%) as the thickness of the center of the core layer 206a or the center of the core layer 204a (the portion directly below the dummy gate stack 210). Similarly, the thickness of each intermixed layer 205 is substantially the same at different locations on the XY plane. For example, the thickness of the intermixed layer 205 adjacent to the sidewall of the intermixed layer 205 is substantially the same as (eg, differs by less than 5%) the thickness of the center of the intermixed layer 205 (the portion directly below the dummy gate stack 210 ).

[0027] Referring to block 106 in FIG. 1 and FIG. 5A , the semiconductor layer 204 is selectively removed from the multilayer stack ML (exposed by the source / drain recess 208 ), thereby forming a suspended semiconductor layer 206 and an opening 214 between vertically adjacent semiconductor layers 206 (or semiconductor substrate 202 , if applicable) (e.g., in the Z direction). Specifically, the opening 214 is a through-opening that overlaps the core layer 204a and the intermixed layer 205 , and spans between the pair of source / drain regions 207 . The opening 214 is also referred to as a "first opening," as indicated by block 106 in FIG. FIG. 5B is an enlarged view of a portion (dashed rectangle) of the semiconductor structure 200 in FIG. 5A .

[0028] In the depicted embodiment, the etching process selectively etches the core layer 204a and the intermixed layer 205, and minimally (or not) etches the core layer 206a. In some embodiments, the gate spacer 212 is minimally (or not) etched. In some embodiments, the core layer 206a remains unetched. In some embodiments, the semiconductor layer 204 is completely removed. In the depicted embodiment, the core layer 204a and the intermixed layer 205 are completely removed, so that the remaining semiconductor layer 206 includes only the core layer 206a. In some other embodiments, the core layer 204a is completely removed, while the intermixed layer 205 is partially removed, so that the core layer 206a and the remaining portion of the intermixed layer 205 together form the remaining semiconductor layer 206. For ease of description, regardless of whether the intermixed layer 205 is completely removed, the remaining semiconductor layer 206 is referred to as the core layer 206a below. Various etching parameters can be adjusted to achieve selective etching of the core layer 204a and the intermixed layer 205, such as etchant composition, etching temperature, etching solution concentration, etching time, etching pressure, source power, radio frequency (RF) bias voltage, RF bias power, etchant flow rate, other suitable etching parameters, or combinations thereof. For example, the etchant selected for the etching process is one that etches the material of the core layer 204a (in the illustrated embodiment, the material is silicon germanium) at a higher rate than the material of the core layer 206a (in the illustrated embodiment, the material is silicon) (i.e., an etchant with a high etching selectivity relative to the material of the core layer 204a). The intermixed layer 205 includes a certain concentration of the material of the core layer 204a and can therefore be selectively removed along with the core layer 204a. The etching process can be a dry etching process, a wet etching process, other suitable etching processes, or combinations thereof. In some embodiments, a dry etching process (e.g., an RIE process) utilizes a fluorine-containing gas (e.g., SF6) to selectively etch the core layer 204a and the intermixed layer 205. In some embodiments, the ratio of the fluorine-containing gas to the oxygen-containing gas (e.g., O2), the etching temperature, and / or the RF power can be adjusted to selectively etch silicon germanium or silicon. In some embodiments, a wet etching process utilizes an etching solution including ammonium hydroxide (NH4OH) and water (H2O) to selectively etch the core layer 204a and the intermixed layer 205. In some embodiments, a chemical vapor etching process using hydrochloric acid (HCl) is used to selectively etch the core layer 204a and the intermixed layer 205.

[0029] In the depicted embodiment, the multilayer stack ML includes three vertically stacked suspended core layers 206a, which provide three channels. During operation of the semiconductor structure 200, current flows between corresponding epitaxial source / drain features through these channels. Therefore, the core layer 206a is hereinafter referred to as a channel layer 206a. The channel layers 206a are separated from each other by one of the openings 214. The channel layers 206a are also separated from the semiconductor substrate 202 by one of the openings 214. A spacing T7 is defined between the channel layers 206a along the Z direction. Spacing T7 corresponds to the width of the opening 214 along the Z direction. In the depicted embodiment, the core layer 204a and the intermixed layer 205 are completely removed. Therefore, spacing T7 is equal to thickness T5 plus twice thickness T4 (T5+2*T4), which is the sum of the thicknesses of one core layer 204a and two intermixed layers 205. In some other embodiments, the core layer 204a is completely removed, while the intermixed layer 205 is partially removed, so that the spacing T7 is less than the thickness T5 plus twice the thickness T4 (T5+2*T4). The core layer 204a and the removed intermixed layer 205 can be collectively referred to as a non-channel layer. In some embodiments, the spacing between each opening 214 at different locations on the XY plane is substantially the same. For example, the spacing between the edges of the opening 214 (e.g., the portion directly below the gate spacer 212) and the spacing between the centers of the opening 214 (e.g., the portion directly below the dummy gate stack 210) is substantially the same (e.g., differing by less than 5%).

[0030] In some embodiments, pitch T7 is approximately 2 nm to approximately 14 nm. In some embodiments, each channel layer 206a is nanometer-sized and may be referred to as a "nanowire," which generally refers to a channel layer suspended in a manner that allows a metal gate to physically contact at least two sides of the channel layer. In a GAA transistor, this allows physical contact on at least four sides of the channel layer (i.e., surrounding the channel layer). In these embodiments, the vertical stack of suspended channel layers may be referred to as a nanostructure, and the process described in Figures 5A and 5B may be referred to as a channel nanowire release process. In some embodiments, after removing the core layer 204a and the intermixed layer 205, an etching process is performed to modify the profile of the channel layer 206a to obtain a desired size and / or shape (e.g., cylindrical (e.g., nanowire), rectangular (e.g., nanorod), sheet-like (e.g., nanosheet), etc.). The present disclosure further contemplates some embodiments in which the channel layer 206a (nanowire) has sub-nanometer dimensions according to the design requirements of the semiconductor structure 200.

[0031] Referring to block 108 in FIG. 1 and FIG. 6A , dielectric material 216 is deposited into opening 214 and conformally deposited over source / drain regions 207 FIG. 6B is an enlarged view of a portion (dashed rectangle) of semiconductor structure 200 in FIG. Deposition of the dielectric material may include any suitable method, such as atomic layer deposition (ALD), plasma-assisted atomic layer deposition (PEALD), physical vapor deposition (PVD), or a combination thereof. In some embodiments, deposition of the dielectric material includes an atomic layer deposition (ALD) process. Dielectric material 216 may be conformally deposited to form a dielectric material 216 (i.e., a dielectric material layer) having a thickness of approximately 2 nm to approximately 14 nm. In some embodiments, the thickness is approximately 2 nm to approximately 7 nm. In some embodiments, the thickness is approximately 2 nm to approximately 5 nm.

[0032] Dielectric material 216 may comprise any suitable material having a different etch selectivity than channel layer 206a. In some embodiments, dielectric material 216 comprises an oxide material. Dielectric material 216 may comprise at least one of silicon oxide (SiO2, SiO), silicon oxynitride (SiON), aluminum oxide (Al2O3), silicon nitride, SiOC, SiOCN, and combinations thereof. In some embodiments, dielectric material 216 comprises a composition different from that of semiconductor layer 204. In some embodiments, dielectric material 216 comprises less than 0.001 atomic percent germanium (Ge) or no Ge. In some embodiments, dielectric material 216 does not contain SiGe. If the Ge content in dielectric material 216 is too high (e.g., greater than 1 atomic percent), subsequent processes may be affected by Ge residues, as described below.

[0033] In some embodiments, unlike the semiconductor layers 204 and 206, the channel layer 206a and the adjacent dielectric material 216 do not have a clear boundary of intermixed sessions and may include a mixture of the channel layer 206a and the dielectric material 216. The channel layer 206a remains substantially unchanged (e.g., changes by less than 5%) during subsequent processes described below.

[0034] Referring to block 110 in FIG. 1 and FIG. 7A , the dielectric material 216 in the source / drain region 207 is removed, and a portion of the dielectric material 216 between adjacent channel layers 206 a (or semiconductor substrate 202 , if applicable) is recessed through the exposed sidewall surfaces of the source / drain region 207 by a selective etching process to form an undercut 218 and a dielectric layer 216 a (or dielectric interposer 216 a ). FIG. 7B is an enlarged view of a portion of the semiconductor structure 200 (indicated by the rectangular dashed line) in FIG. 7A .

[0035] The selective etching process can be any suitable process, such as a wet or dry etching process. The extent to which the dielectric material 216 is recessed (or the size of the removed portion) is determined by process conditions, such as the duration of exposure of the dielectric material 216 to the etching chemical. In the depicted embodiment, the duration is controlled to completely remove the dielectric material 216 in the source / drain regions 207 and to remove side portions of the dielectric material 216 between adjacent channel layers 206a (or semiconductor substrate 202, as applicable), while leaving the central portion of the dielectric material 216 (e.g., dielectric layer 216a) between adjacent channel layers 206a (or semiconductor substrate 202, as applicable) substantially intact. As shown in FIG. 7B , the selective etching process creates an undercut 218 that extends the source / drain recess 208 into the region beneath the channel layer 206a and the gate spacer 212.

[0036] In some embodiments, the undercut 218 has a convex shape as shown in FIG. 7B . In some embodiments, the dielectric layer 216a includes a tip portion that extends toward the sidewalls of the channel layer 206a (or the semiconductor substrate 202, where applicable). In some embodiments, the tip portion extends to directly contact the entire top or bottom surface of the channel layer 206a (or the semiconductor substrate 202, where applicable). In these embodiments, the dielectric layer 216a has sidewalls that are coplanar with the sidewalls of the channel layer 206a.

[0037] At this point, the channel layer 206a is only slightly affected during the selective etching process. For example, before the selective etching process, the side portions of the channel layer 206a each have a thickness T3 or a thickness T6 (see FIG. 5B ). After the selective etching process, the thickness of the side portions of the channel layer 206a may vary by approximately 1% to 5% from thickness T3 or thickness T6. The different material compositions of these layers enable an etch selectivity between the channel layer 206a and the dielectric material 216. For example, the dielectric material 216 can be etched away at a significantly faster rate (e.g., approximately 5 times or approximately 10 times faster) than the channel layer 206a. As shown in FIG. 5A to FIG. 5B , because the pitch of each opening 214 at different locations on the XY plane is substantially the same, and the channel layer 206 a (or the semiconductor substrate 202 , where applicable) remains substantially constant (e.g., with a variation of less than 5%), the spacing of each undercut 218 in the Z direction is substantially the same as the thickness of each of the dielectric layers 216 a (e.g., with a difference of less than 5%), which is approximately the same as the pitch T7.

[0038] As described above, the selective etching process can be a wet etching process. The etching technique and etchant can be selected to etch the dielectric material 216 without significantly etching surrounding structures, such as the channel layer 206a. In one embodiment, the channel layer 206a comprises Si, and the dielectric material 216 comprises an oxide material (e.g., silicon oxide). In one embodiment, a hydrofluoric acid (HF) solution, such as dilute hydrofluoric acid (DHF), can be used to selectively etch away the dielectric material 216. For example, the dielectric material 216 can be etched away at a significantly faster rate than the channel layer 206a (e.g., with a selectivity greater than 10). In this way, desired portions of the dielectric material 216 (e.g., side portions of the dielectric material 216 between adjacent channel layers 206a (or semiconductor substrate 202, if applicable)) are removed, while the channel layer 206a remains substantially intact. The etching duration is adjusted to control the size of the removed portion of the dielectric material 216. Optimal conditions can be achieved by additional adjustments to etching temperature, doping concentration, and other experimental parameters.

[0039] In some embodiments, the selective etching process may include a dry, plasma-free etching process performed using a suitable etching system, such as the CERTAS® gas chemical etching system from Tokyo Electron Limited, Tokyo, Japan. In some examples, the selective etching process may include etching using a standard clean 1 (SC-1) solution, a solution of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O), hydrofluoric acid (HF), buffered HF, and / or fluorine (F2)-based etching. In some examples, the F2-based etching may include an F2 remote plasma etch.

[0040] Referring to block 112 of FIG. 1A , and also to FIG. 8A , a second dielectric material is deposited in the undercut 218 . The second dielectric material is deposited to form a spacer layer over the dummy gate stack 210 , the gate spacers 212 , and the features defined by the source / drain recesses 208 (e.g., the channel layer 206 a , the dielectric layer 216 a , and the semiconductor substrate 202 ), and may be deposited by methods such as CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, electroplating, or other suitable methods or combinations thereof. The spacer layer partially (and, in some embodiments, completely) fills the source / drain recesses 208 . The deposition process is configured to ensure that the spacer layer fills the undercut 218 . Next, an etching process is performed to selectively etch the spacer layer to form the inner spacer 220 as shown in FIG. 8A and FIG. 8B , while minimally (or not) etching the channel layer 206a, the dummy gate stack 210, and the gate spacer 212. In some embodiments, the spacer layer is removed from the sidewalls of the gate spacer 212, the sidewalls of the channel layer 206a, the dummy gate stack 210, and the semiconductor substrate 202. The spacer layer (and the resulting inner spacer 220) comprises a different material than the channel layer 206a and a different material than the gate spacer 212 to achieve a desired etching selectivity during the etching process. In some embodiments, the spacer layer comprises a different material than the dielectric layer 216a. In some embodiments, the spacer layer comprises a dielectric material including silicon, oxygen, carbon, nitrogen, other suitable materials, or combinations thereof (for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or silicon oxynitride carbon). In some embodiments, the spacer layer comprises a low-k dielectric material, such as those described herein. In some embodiments, a dopant (e.g., a p-type dopant, an n-type dopant, or a combination thereof) is introduced into the dielectric material such that the spacer layer comprises a doped dielectric material.

[0041] FIG8B is an enlarged view of a portion (dashed rectangle) of the semiconductor structure 200 in FIG8A . In some embodiments, the inner spacer 220 fills the undercut 218 and thus has a convex shape as depicted in FIG8B . In these embodiments, the dielectric layer 216a includes a tip portion between the inner spacer 220 and the channel layer 206a (or the semiconductor substrate 202, if applicable). In some embodiments, the tip portion extends toward the sidewalls of the multilayer stack ML but is not exposed to the source / drain recess 208. In these embodiments, the inner spacer 220 separates the dielectric layer 216a from the source / drain recess 208. In some other embodiments, although not depicted, the tip portion extends to directly contact the entire top and / or bottom surface of the channel layer 206a (or the semiconductor substrate 202, if applicable). In these embodiments, the dielectric layer 216a is exposed in the source / drain recess 208 and separates adjacent inner spacers 220 from the adjacent channel layer 206a (or semiconductor substrate 202, where applicable). The dielectric layer 216a may have sidewalls that are coplanar with the sidewalls of the channel layer 206a.

[0042] Referring to block 114 of FIG. 1A , and with reference to FIG. 9A and FIG. 9B , method 100 further includes forming epitaxial source / drain features 223 in source / drain recess 208 . FIG. 9B is an enlarged view of a portion (dashed rectangular line) of semiconductor structure 200 in FIG. 9A . In some embodiments, one source / drain feature 223 is a source electrode, while another source / drain feature 223 is a drain electrode. A channel layer 206a extending from one source / drain feature 223 to another source / drain feature 223 may form a channel of semiconductor structure 200 . The epitaxial source / drain features 223 may be grown using a variety of processes, including etching and growth processes. Each epitaxial source / drain feature 223 may include multiple layers, such as a first source / drain layer 222 and a second source / drain layer 224 . In the depicted embodiment, the epitaxial source / drain features 223 have top surfaces that are substantially aligned with the top surface of the topmost channel layer 206a. However, in other embodiments, the epitaxial source / drain features 223 may alternatively have top surfaces that extend higher (e.g., in the Z direction) than the top surface of the topmost channel layer 206a. In the depicted embodiment, the epitaxial source / drain features 223 occupy the lower portion of the source / drain recess 208 (e.g., the portion defined by the inner spacer 220 and the channel layer 206a), leaving the upper portion of the source / drain recess 208 (e.g., the portion defined by the gate spacer 212) open. In some embodiments, the epitaxial source / drain features 223 may be merged, for example, along the X direction, to provide a greater lateral width than a single epitaxial feature.

[0043] The epitaxial source / drain features 223 may comprise any suitable semiconductor material. For example, the epitaxial source / drain features 223 in an n-type GAA device may comprise Si, SiC, SiP, SiAs, SiPC, or a combination thereof; while the epitaxial source / drain features 223 in a p-type GAA device may comprise Si, SiGe, Ge, SiGeC, or a combination thereof. The epitaxial source / drain features 223 may be doped in situ or ex situ. For example, the epitaxially grown Si source / drain features may be doped with carbon to form silicon:carbon (Si:C) source / drain features, with phosphorus to form silicon:phosphorus (Si:P) source / drain features, or with both carbon and phosphorus to form silicon carbon phosphorus (SiCP) source / drain features. Furthermore, the epitaxially grown SiGe source / drain features may be doped with boron. One or more annealing processes may be performed to activate dopants in the epitaxial source / drain features 223. The annealing processes may include rapid thermal annealing (RTA) and / or laser annealing processes.

[0044] The epitaxial source / drain features 223 can directly interface with the sidewalls of the inner spacer 220 and the sidewalls of the channel layer 206a. During epitaxial growth, semiconductor material grows from the exposed top surface 202a of the semiconductor substrate 202 (e.g., the exposed top surface of the doped region) and from the exposed side surfaces of the channel layer 206a. Notably, during the epitaxial growth process, semiconductor material does not grow from the surfaces of the inner spacer 220 and the gate spacer 212.

[0045] Since the semiconductor layer 204 and the intermixed layer 205 have been removed with reference to block 106 in FIG. 1 , when the epitaxial source / drain features 223 are formed, the SiGe in the multilayer stack ML is negligible (e.g., less than 0.0001% of the total SiGe in the semiconductor layer 204 at block 102 ), thereby reducing dopant diffusion into unintended areas and lowering built-in stress (e.g., tensile stress and compressive stress) during the process.

[0046] Referring to block 116 of FIG. 1A and FIG. 10 , an interlayer dielectric (ILD) layer 225 is formed over the epitaxial source / drain features 223 in the remaining space of the source / drain recesses 208 . The ILD layer 225 is also formed vertically over the isolation features 201 . The ILD layer 225 may also be formed between adjacent dummy gate stacks 210 along the Y direction and between the source / drain features 223 along the X direction. The ILD layer 225 may include a dielectric material such as a high-k material, a low-k material, or an ultra-low-k material. For example, the ILD layer 225 may include SiO 2 , SiOC, SiON, or a combination thereof. The ILD layer 225 may include a single layer or multiple layers and may be formed using a suitable technique, such as CVD, ALD, and / or spin-on coating. In some embodiments, a contact etch-stop layer (CESL) is disposed between the ILD layer 225 and the isolation features 201, and between the epitaxial source / drain features 223 and the gate spacers 212. The CESL comprises a material different from that of the ILD layer 225, such as a dielectric material different from the dielectric material of the ILD layer 225, to achieve an etch selectivity ratio. For example, when the ILD layer 225 comprises a low-k dielectric material, the CESL comprises silicon and nitrogen, such as silicon nitride or silicon oxynitride. After depositing the ILD layer 225 and / or the CESL, a chemical-mechanical planarization (CMP) process and / or other planarization process may be performed to remove excess portions of the ILD layer 225, thereby planarizing the top surface of the ILD layer 225 until the top (or top surface) of the dummy gate stack 210 is reached (exposed). Among other functions, the ILD layer 225 provides electrical isolation between various components of the semiconductor structure 200 .

[0047] The ILD layer 225 may be part of a multilayer interconnect (MLI) component disposed above the semiconductor substrate 202. The MLI component electrically couples various devices (e.g., GAA transistors, transistors, resistors, capacitors, and / or inductors) and / or components (e.g., gate structures and / or epitaxial source / drain components of GAA transistors) of the semiconductor structure 200, enabling the various devices and / or components to operate as specified by the design requirements of the semiconductor structure 200. The MLI component includes a combination of dielectric layers and conductive layers (e.g., metal layers) configured to form various interconnect structures. The conductive layers are configured to form vertical interconnect components, such as device-level contacts and / or vias, and / or horizontal interconnect components, such as conductive lines. Vertical interconnect components typically connect horizontal interconnect components in different layers (or different planes) of the MLI component. During operation, the interconnect component is configured to route signals (e.g., clock signals, voltage signals, and / or ground signals) between components of the device and / or semiconductor structure 200 and / or is configured to distribute signals to the device and / or semiconductor structure 200.

[0048] Referring to block 118 of FIG. 1 and to FIGS. 11A through 11C , the dummy gate stack 210 is selectively removed by any suitable lithography and etching process. In some embodiments, the lithography process includes forming a photoresist layer (photoresist), exposing the photoresist to a pattern, performing a post-exposure bake process, and developing the photoresist to form a masking element that exposes the area including the dummy gate stack 210. The dummy gate stack 210 is then selectively etched through the masking element. In some other embodiments, the gate spacer 212 may serve as the masking element or a portion thereof. For example, the dummy gate stack 210 may comprise polysilicon, the gate spacer 212 and the interspacer 220 may comprise a dielectric material, and the channel layer 206a may comprise a semiconductor material. Thus, by selecting a suitable etch chemistry, an etch selectivity can be achieved, allowing the dummy gate stack 210 to be removed without substantially affecting components of the semiconductor structure 200. The removal of the dummy gate stack 210 creates a gate trench 228. The gate trench 228 exposes the top and side surfaces of the stack of the channel layer 206a and the dielectric layer 216a. In other words, the channel layer 206a and the dielectric layer 216a are exposed on at least two sides of the gate trench 228. Furthermore, the gate trench 228 also exposes the top surface of the isolation structure 201.

[0049] Referring to block 120 of FIG. 1 , and also to FIGS. 11A through 11C , the dielectric layer 216a is selectively removed through the gate trench 228, for example using a wet or dry etching process. The etching chemistry is selected to provide a sufficiently different etching rate for the dielectric layer 216a compared to the channel layer 206a, the inner spacer 220, and the gate spacer 212. This ensures that the channel layer 206a, the inner spacer 220, and the gate spacer 212 remain substantially unchanged. This selective etching process may include one or more etching steps.

[0050] As shown in Figures 11A to 11C , in this embodiment, the removal of dielectric layer 216a forms second openings 226 between the suspended channel layer 206a and vertically adjacent film layers (e.g., in the Z direction), thereby exposing the top and bottom surfaces of the channel layers 206a. Each of the channel layers 206a is now circumferentially exposed in the XZ plane. Furthermore, portions of the doped regions of the semiconductor substrate 202 beneath the channel layers 206a are also exposed in the second openings 226.

[0051] In the example shown in Figures 11A to 11C, the gate trench 228 and the second opening 226 vertically adjacent to the gate trench 228 (e.g., in the Z direction) collectively form an opening having a vertical profile. In other words, the opening formed by the gate trench 228 and its corresponding second opening 226 has vertical sidewalls. In some embodiments, these openings with vertical sidewalls can be formed by multiple etching processes. For example, the etching chemistry used to remove the dummy gate stack 210 and thereby form the gate trench 228 may include a combination of hydrogen bromide (HBr) and chlorine (Cl2), tetrafluoromethane (CF4), oxygen, or a combination thereof. Furthermore, the etching process used to selectively remove the dielectric layer 216a and thereby form the second opening 226 may have an initial etch chemistry including a combination of hydrogen bromide (HBr) and chlorine (Cl2), oxygen, or a combination thereof. Following this initial etch chemistry is a subsequent etch chemistry comprising hydrogen bromide (HBr) and tetrafluoromethane (CF 4 ), oxygen, or a combination thereof, which results in a vertical profile opening formed by the gate trench 228 and its corresponding second opening 226 .

[0052] FIG11B is an enlarged view of a portion (dashed rectangle) of the semiconductor structure 200 in FIG11A . In some embodiments, the removal process removes only some, but not all, of the dielectric layer 216 a. A portion of the dielectric layer 216 a may remain between the inner spacer 220 and the channel layer 206 a (or the semiconductor substrate 202 , if applicable). This remaining portion may be referred to as "remaining dielectric layer 216 b."

[0053] In some embodiments, the remaining dielectric layer 216b does not contain SiGe. In conventional processes, non-channel layers containing SiGe are typically used. After forming the epitaxial source / drain features, most of the non-channel layers are removed, but SiGe residues may remain between adjacent channel layers, resulting in unintended capacitance between the SiGe residues and adjacent conductive features. In the present disclosure, the semiconductor layer 204 and the intermixed layer 205 are removed with reference to block 106 in FIG. 1 . Therefore, the SiGe content in the multilayer stack ML is negligible (e.g., less than 0.0001% of the total SiGe in the semiconductor layer 204 at block 102). Consequently, the capacitance between the SiGe and other conductive features (e.g., the epitaxial source / drain features 223) is reduced or negligible.

[0054] In some embodiments, the etching selectivity of the dielectric layer 216a to the channel layer 206a can be higher than the etching selectivity of the semiconductor layer 204 to the channel layer 206a in conventional processes. In some embodiments, when removing the dielectric layer 216a, the etching selectivity of the dielectric layer 216a to the channel layer 206a is greater than 10. If the etching selectivity of the dielectric layer 216a to the channel layer 206a is too low, the channel layer 206a may be etched, and the thickness and / or width of the channel layer 206a may be reduced, thereby affecting the performance of the semiconductor structure 200 (e.g., more SCE, higher capacitance).

[0055] FIG11C is a cross-sectional view of the semiconductor structure shown in FIG11A and taken along line BB' in FIG2. In some embodiments, during the removal of dielectric layer 216a, channel layer 206a experiences minimal or no width loss. This may be due to the etch selectivity of dielectric layer 216a to channel layer 206a and / or the lack of a clear boundary between the intermixed regions of channel layer 206a and adjacent dielectric material 216, as described above. In some embodiments, the width of channel layer 206a along the X-direction is equal to or less than the width of the bottom portion of fin 203 (e.g., the portion of fin 203 contacting semiconductor substrate 202) along the X-direction, with the difference being less than 2%. In other words, the width loss of channel layer 206a during the fabrication process is negligible, thereby improving device performance and reducing capacitance.

[0056] Referring to block 122 of FIG. 1B and to FIGS. 12A-12B , a metal gate stack is formed. The metal gate stack includes a gate dielectric layer 232 and a gate electrode 230 disposed on the gate dielectric layer 232. For example, the metal gate stack may include a polysilicon gate electrode on a SiON gate dielectric layer. As another example, the metal gate stack may include a metal gate electrode on a high-k dielectric layer. In some cases, a refractory metal layer (such as an aluminum gate electrode) may be interposed between the metal gate electrode and the high-k dielectric layer. As yet another example, the metal gate stack may include silicide. The gate dielectric layer 232 is formed between the gate electrode 230 and the channel formed by the channel layer 206 a.

[0057] In some embodiments, a gate dielectric layer 232 is conformally formed on the semiconductor structure 200 . The gate dielectric layer 232 at least partially fills the gate trench 228 . In some embodiments, a dielectric interfacial layer may be formed on the channel layer 206 a before forming the gate dielectric layer 232 . This dielectric interfacial layer improves adhesion between the channel layer 206 a and the gate dielectric layer 232 . In the examples described herein, this dielectric interfacial layer is omitted. Instead, in the illustrated embodiment, the gate dielectric layer 232 is formed around the exposed surface of each of the channel layers 206 a , such that the gate dielectric layer 232 surrounds the channel layer 206 a 360 degrees. Furthermore, the gate dielectric layer 232 directly contacts the vertical sidewalls of the inner spacer 220 , the sidewalls of the remaining dielectric layer 216 b , and the vertical sidewalls of the gate spacer 212 . The gate dielectric layer 232 may include a dielectric material having a dielectric constant greater than that of SiO 2 , wherein the dielectric constant of SiO 2 is approximately 3.9. For example, the gate dielectric layer 232 may include hafnium oxide (HfO 2 ), which has a dielectric constant of approximately 18 to approximately 40. As various other examples, the gate dielectric layer 232 may include ZrO 2 , Y 2 O 3 , La 2 O 5 , Gd 2 O 5 , TiO 2 , Ta 2 O 5 , HfErO, HfLaO, HfYO, HfGdO, HfAlO, HfZrO, HfTiO, HfTaO, SrTiO, or combinations thereof. The gate dielectric layer 232 may be formed by any suitable process, such as CVD, PVD, ALD, or combinations thereof.

[0058] After forming the gate dielectric layer 232, a gate electrode 230 is formed on the gate dielectric layer 232 to fill the remaining space in the gate trench 228. The gate electrode 230 may include any suitable material, such as titanium nitride (TiN), tantalum nitride (TaN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), tantalum aluminide (TaAl), tantalum aluminum nitride (TaAlN), tantalum aluminum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), copper (Cu), cobalt (Co), nickel (Ni), platinum (Pt), or a combination thereof. In some embodiments, CMP is performed to expose the top surface of the ILD layer 225. The gate dielectric layer 232 and the gate electrode 230 together form a metal gate stack that engages multiple layers (eg, multiple nanochannels) within the channel layer 206a.

[0059] FIG12B is an enlarged view of a portion of the semiconductor structure 200 (indicated by the dashed rectangle) in FIG12A. As previously described in this disclosure, the Z-direction thickness of each channel layer 206a at different locations on the XY plane is substantially the same, and the channel layer 206a remains substantially unchanged throughout the entire process. Therefore, after forming the metal gate stack, the Z-direction thickness of each channel layer 206a at different locations on the XY plane remains substantially the same (e.g., differing by less than 5%). If the Z-direction thickness of each channel layer 206a at different locations on the XY plane is substantially different (e.g., differing by more than 5%), for example, if the thickness at the edge (e.g., closer to the epitaxial source / drain features) is greater than 10% of the thickness at the center (e.g., directly below the metal gate stack above the multilayer stack ML), unintended capacitance may increase. In conventional processes, the non-channel layer, which includes SiGe, is typically removed after forming the epitaxial source / drain features and before forming the metal gate stack. This removal involves multiple etching steps to remove the intermixed layer, which reduces the width of the channel layer (e.g., in the X-direction) and makes the channel layer thicker at the edges (e.g., closer to the epitaxial source / drain features) than at the center (e.g., directly below the metal gate stack above the multilayer stack ML), thereby affecting device performance (e.g., increasing SCE) and increasing unintended capacitance. Furthermore, the SiGe content in the multilayer stack ML of the present disclosure is negligible (e.g., less than 0.0001% of the total SiGe in the semiconductor layer 204 at block 102), resulting in negligible Ge oxide formation during the process, which reduces interface trap effects.

[0060] In some embodiments, as shown in FIG. 12B , at least one remaining dielectric layer 216b (referred to as the "top remaining dielectric layer 216b" or the "bottom remaining dielectric layer 216b") is located within each of the second openings 226 between two adjacent channel layers 206a (or semiconductor substrate 202, as applicable) (referred to as the "top channel layer 206a" and the "bottom channel layer 206a"). The remaining dielectric layer 216b is in direct contact with the top channel layer 206a or the bottom channel layer 206a. The top remaining dielectric layer 216b and / or the bottom remaining dielectric layer 216b may have a triangle-like cross-sectional shape as shown in FIG. In some embodiments, the sidewalls of the top remaining dielectric layer 216b and / or the bottom remaining dielectric layer 216b interface with the top channel layer 206a and / or the bottom channel layer 206a, the adjacent inner spacer 220, and the adjacent gate dielectric layer 232, respectively. In some other embodiments, although not depicted, in addition to intersecting these elements, the top remaining dielectric layer 216b and / or the bottom remaining dielectric layer 216b extend to contact adjacent epitaxial source / drain features 223. In these embodiments, adjacent inner spacers 220 are separated from the top channel layer 206a and / or the bottom channel layer 206a by the top remaining dielectric layer 216b and / or the bottom remaining dielectric layer 216b.

[0061] In some embodiments, the top remaining dielectric layer 216b and / or the bottom remaining dielectric layer 216b extend between one of the inner spacers 220 (the first inner spacer 220) and the gate dielectric layer 232. In some embodiments, the top remaining dielectric layer 216b and the bottom remaining dielectric layer 216b are separated by the first inner spacer 220 and the gate dielectric layer 232 of the metal gate stack. In some other embodiments, the top remaining dielectric layer 216b extends and merges with the bottom remaining dielectric layer 216b. In some embodiments, the top remaining dielectric layer 216b extends to the top channel layer 206a. The top surface of the top remaining dielectric layer 216b and the top surface of the gate dielectric layer 232 can be coplanar and can directly contact the bottom surface of the top channel layer 206a. Similarly, the bottom remaining dielectric layer 216b extends to the bottom channel layer 206a. The bottom surface of the bottom remaining dielectric layer 216b may be coplanar with the bottom surface of the gate dielectric layer 232 and may directly contact the top surface of the bottom channel layer 206a.

[0062] After forming the gate dielectric layer 232 and the gate electrode 230, a planarization process is performed to remove excess gate material from the semiconductor structure 200. For example, a CMP process is performed until the top surface of the ILD layer 225 is reached (exposed), such that after the CMP process, the top surface of the metal gate stack is substantially coplanar with the top surface of the ILD layer 225. Thus, the semiconductor structure 200 may include a GAA transistor having a metal gate stack surrounding a respective channel layer 206a such that the metal gate stack is disposed between respective epitaxial source / drain features 223.

[0063] The manufacturing process can continue to fabricate the semiconductor structure 200. For example, various contacts can be formed to facilitate operation of the GAA transistor. For example, one or more ILD layers and / or CESL layers similar to the ILD layer 225 can be formed on the semiconductor substrate 202 (specifically, on the ILD layer 225 and the metal gate stack). Contacts can then be formed in the ILD layer 225 and / or disposed in the ILD layer above the ILD layer 225. For example, one contact can be electrically and / or physically coupled to the metal gate stack, while another contact can be electrically and / or physically coupled to the source / drain region of the GAA transistor (specifically, the epitaxial source / drain feature 223). The contacts can include a conductive material such as a metal. The metal includes aluminum, an aluminum alloy (such as an aluminum / silicon / copper alloy), copper, a copper alloy, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, polycrystalline silicon, a metal silicide, other suitable metals, or combinations thereof. The metal silicide may include nickel silicide, cobalt silicide, tungsten silicide, tantalum silicide, titanium silicide, platinum silicide, erbium silicide, palladium silicide, or combinations thereof. In some embodiments, the ILD layer and contacts disposed above the ILD layer 225 (eg, extending through the ILD layer 225 and / or other ILD layers) are part of the MLI features described above.

[0064] Other fabrication processes may be applied to semiconductor structure 200 and may be performed before, during, or after the aforementioned processes, such as performing various process steps to form an interconnect structure from the front surface of semiconductor substrate 202 above the transistor in the GAA to electrically connect various circuit elements. The interconnect structure includes metal lines distributed in multiple metal layers (e.g., from bottom to top, a first metal layer, a second metal layer, and a third metal layer) to provide horizontal routing and contact features (between the substrate and the first metal layer, and between multiple via features (between metal layers)) to provide vertical wiring. Semiconductor structure 200 may further include other components, such as other conductive features (e.g., a redistribution layer (RDL)); one or more passivation layers (passivation layers) to provide a sealing effect; and / or bonding structures to provide an interface between semiconductor structure 200 and a circuit board (e.g., a printed circuit board) to be formed on the interconnect structure.

[0065] While not intended to be limiting, embodiments of the present disclosure provide advantageous benefits for semiconductor processes and semiconductor devices. For example, by removing non-channel layers, including a transition layer, prior to forming epitaxial source / drain features, SiGe residue becomes negligible prior to forming the epitaxial source / drain features, thereby reducing abnormal dopant diffusion and built-in stress (e.g., tensile and compressive stress) during subsequent fabrication processes. Early removal of the transition layer also reduces unintended capacitance and device degradation, and avoids loss of channel layer width, thereby improving device performance, reducing short channel effects (SCE), and enabling higher current drive and increased logic density.

[0066] In one exemplary embodiment, the present disclosure provides a method for forming a semiconductor structure. The method includes forming a structure having a dummy gate stack on a multi-layer stack (ML), wherein the multi-layer stack is disposed on a semiconductor substrate and includes alternating channel layers and non-channel layers; recessing the multi-layer stack in source / drain regions; removing the non-channel layers to form a plurality of first openings between the channel layers; depositing a dielectric material in the first openings; recessing the dielectric material to form a plurality of undercuts; forming a plurality of inner spacers in the undercuts; forming a plurality of epitaxial source / drain features in the source / drain regions; removing the dummy gate stack to form gate trenches; removing the dielectric material in the gate trenches to form a plurality of second openings between the channel layers; and forming a metal gate stack in the gate trenches and the second openings.

[0067] In some embodiments, the plurality of source / drain regions include a first source / drain region and a second source / drain region, a dummy gate stack is interposed between the first source / drain region and the second source / drain region, and the step of depositing a dielectric material in the plurality of first openings includes depositing the dielectric material continuously extending from the first source / drain region to the second source / drain region. In some embodiments, before removing the dummy gate stack, the process further includes forming an interlayer dielectric layer over the plurality of epitaxial source / drain features, wherein the step of depositing the dielectric material includes performing an atomic layer deposition process. In some embodiments, the dielectric material is silicon oxide, and the step of recessing the dielectric material includes etching the dielectric material using hydrofluoric acid (HF). In some embodiments, the multilayer stack further includes a plurality of intermix layers, wherein the plurality of intermix layers include a mixture of materials of the plurality of channel layers and the plurality of non-channel layers, and wherein the step of removing the plurality of non-channel layers includes removing the plurality of intermix layers. In some embodiments, the step of forming a metal gate stack includes: forming a high-k dielectric layer in the gate trench and the plurality of second openings; and forming a metal gate electrode on the high-k dielectric layer to fill the gate trench and the plurality of second openings, with the metal gate electrode wrapping around each of the plurality of channel layers. In some embodiments, the composition of the plurality of interspacers is different from the composition of the dielectric material. In some embodiments, the dielectric material includes at least one of silicon oxide, silicon oxynitride (SiON), aluminum oxide (Al2O3), silicon nitride, and combinations thereof. In some embodiments, the plurality of channel layers include elemental silicon, and the plurality of non-channel layers include silicon germanium (SiGe). In some embodiments, the step of removing the dielectric material includes applying an etching process, and the etchant of the etching process has an etching selectivity of the dielectric material to the plurality of channel layers greater than 10. In some embodiments, after removing the dielectric material, a first remaining portion of the dielectric material extends between a first interspacer of the plurality of interspacers and the gate dielectric layer of the metal gate stack, and the gate dielectric layer is located in one of the second openings between two adjacent channel layers. In some embodiments, a top surface of the first remaining portion of the dielectric material is coplanar with a top surface of the gate dielectric layer of the metal gate stack and directly contacts a bottom surface of a top channel layer of the two adjacent channel layers.In some embodiments, the second remaining portion of the dielectric material extends between a first interspacer of the plurality of interspacers and the gate dielectric layer of the metal gate stack, and the first remaining portion of the dielectric material is separated from the second remaining portion by the first spacer and the gate dielectric layer of the metal gate stack. In some embodiments, the first remaining portion of the dielectric material extends to a first channel layer of the two adjacent channel layers, and the second remaining portion of the dielectric material extends to a second channel layer of the two adjacent channel layers.

[0068] In another exemplary aspect, the present disclosure relates to a method for forming a semiconductor structure. The method includes receiving a structure having a dummy gate stack located above a multilayer stack disposed on a semiconductor substrate, the dummy gate stack comprising a plurality of alternating channel layers and a plurality of non-channel layers, and the dummy gate stack comprising a plurality of source / drain regions adjacent to the plurality of channel layers and the plurality of non-channel layers; replacing the plurality of non-channel layers with a dielectric material; recessing the dielectric material to form a plurality of undercuts; forming inner spacers in the plurality of undercuts; forming a plurality of epitaxial source / drain features in the plurality of source / drain regions; and replacing a portion of the dummy gate stack and the dielectric material with a metal gate stack.

[0069] In some embodiments, before replacing the dummy gate stack and a portion of the dielectric material, the step further includes forming an interlayer dielectric layer over the plurality of epitaxial source / drain features. In some embodiments, replacing the dummy gate stack and a portion of the dielectric material includes: removing the dummy gate stack to form a gate trench; removing a portion of the dielectric material to form a plurality of openings between the plurality of channel layers; and forming a metal gate stack in the gate trench and the plurality of openings. In some embodiments, removing the portion of the dielectric material includes applying an etching process, wherein the etchant of the etching process selectively removes the dielectric material without significantly etching the plurality of channel layers.

[0070] In another exemplary embodiment, the present disclosure relates to a semiconductor structure. The semiconductor device includes a semiconductor layer stack, a gate structure, an inner spacer, and an inner spacer. The semiconductor layer stack is disposed above a substrate. The gate structure surrounds each layer in the semiconductor layer stack. The inner spacer is interposed between the gate structure and a source / drain component and extends between two adjacent semiconductor layers in the semiconductor layer stack. A first dielectric layer is disposed on a sidewall of the gate structure. The first dielectric layer contacts the inner spacer and extends to the first semiconductor layer of the two adjacent semiconductor layers. The composition of the inner spacer is different from that of the first dielectric layer.

[0071] In some embodiments, the semiconductor structure further includes a second dielectric layer disposed on the sidewalls of the gate structure. The second dielectric layer contacts the inner spacer and extends to the second semiconductor layer of the two adjacent semiconductor layers, wherein the composition of the first dielectric layer is the same as that of the second dielectric layer.

[0072] The above overview of several embodiments is provided to facilitate understanding of the present invention by those skilled in the art. Those skilled in the art will appreciate that they can design or modify other processes and structures based on the present invention to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also appreciate that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that various modifications, substitutions, and replacements can be made without departing from the spirit and scope of the present invention.

[0073] 100: Method 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122: Box 200:Semiconductor structure 201: Isolation components 202:Semiconductor substrate 202a: Top surface 203: Fins 204, 206: semiconductor layer 204a, 206a: Core layer 205: intermixed layer 207: Source / Drain Region 208: Source / Drain recess 210: dummy gate stack 212: spacer 214: Opening 216: Dielectric materials 216a: dielectric layer 216b: Remaining dielectric layer 220:Internal spacer 222: first source / drain layer 223: Source / drain component 224: Second source / drain layer 225: interlayer dielectric layer 226: Second opening 228: Gate trench 230: Gate electrode 232: Gate dielectric layer A-A', B-B': line segment ML: Multilayer stack T1, T2, T3, T4, T5, T6: thickness T7: Spacing

Claims

1. A method for forming a semiconductor structure, comprising: A structure is formed on a multi-layer stack (ML), wherein the structure has a dummy gate stack, wherein the multi-layer stack is disposed on a semiconductor substrate, and the multi-layer stack includes alternating multiple channel layers and multiple non-channel layers; the multi-layer stack is etched into multiple source / drain regions; the non-channel layers are removed to form multiple first openings between the channel layers; a dielectric material is deposited in the first openings; the dielectric material is etched to form multiple undercuts; multiple internal spacers are formed in the undercuts; and multiple epitaxial source / drain components are formed in the source / drain regions. Remove the dummy gate stack to form a gate trench; remove the dielectric material in the gate trench to form a plurality of second openings between the channel layers; and form a metal gate stack in the gate trench and the second openings.

2. The method of forming a semiconductor structure as claimed in claim 1, wherein the source / drain regions include a first source / drain region and a second source / drain region, the dummy gate stack is interposed between the first source / drain region and the second source / drain region, and the step of depositing the dielectric material in the first openings includes depositing the dielectric material extending continuously from the first source / drain region to the second source / drain region.

3. The method of forming a semiconductor structure as claimed in claim 1, wherein the multilayer stack further includes a plurality of intermix layers having a mixture of materials of the channel layers and the non-channel layers, and wherein the step of removing the non-channel layers includes removing the intermix layers.

4. A method for forming a semiconductor structure as described in any one of claims 1 to 3, wherein the step of removing the dielectric material includes applying an etching process, and the etchant of the etching process has an etch selectivity of the dielectric material to the channel layers greater than 10.

5. A method of forming a semiconductor structure as claimed in claim 1, wherein after the dielectric material is removed, a first remaining portion of the dielectric material extends between a first inner spacer of the inner spacers and a gate dielectric layer of the metal gate stack, and the gate dielectric layer is located in one of the second openings between two adjacent channel layers.

6. The method of forming a semiconductor structure as claimed in claim 5, wherein the top surface of the first remaining portion of the dielectric material and the top surface of the gate dielectric layer of the metal gate stack are coplanar and directly contact the bottom surface of a top channel layer of the two adjacent channel layers.

7. A method of forming a semiconductor structure as claimed in claim 5, wherein a second remaining portion of the dielectric material extends between the first inner spacer of the inner spacers and the gate dielectric layer of the metal gate stack, and wherein the first remaining portion of the dielectric material and the second remaining portion are separated by the first spacer and the gate dielectric layer of the metal gate stack.

8. A method for forming a semiconductor structure, comprising: The method includes receiving a structure having a dummy gate stack located on a multilayer stack disposed on a semiconductor substrate, the dummy gate stack including alternating channel layers and non-channel layers, and the dummy gate stack including multiple source / drain regions adjacent to the channel layers and non-channel layers; replacing the non-channel layers with a dielectric material; etching the dielectric material to form multiple undercuts; forming an inner spacer in the undercuts; forming multiple epitaxial source / drain components in the source / drain regions; and replacing a portion of the dummy gate stack and the dielectric material with a metal gate stack.

9. A semiconductor structure, comprising: A semiconductor layer stack is disposed above a substrate; A gate structure surrounds each layer in the semiconductor layer stack; An inner spacer is inserted between the gate structure and a source / drain component and extends between two adjacent semiconductor layers of the semiconductor layer stack, wherein the inner spacer directly contacts the gate structure; and a first dielectric layer is disposed on a sidewall of the gate structure and directly contacts the gate structure, the first dielectric layer contacts the inner spacer and extends to a first semiconductor layer of the two adjacent semiconductor layers, wherein the composition of the inner spacer is different from the composition of the first dielectric layer.

10. The semiconductor structure as claimed in claim 9 further includes a second dielectric layer disposed on the sidewall of the gate structure, the second dielectric layer contacting the inner spacer and extending to a second semiconductor layer of the two adjacent semiconductor layers, wherein the composition of the first dielectric layer is the same as the composition of the second dielectric layer.

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