Semiconductor device and method of forming package with double-sided integrated passive device

Abstract

This invention discloses a semiconductor device having a semiconductor die, a substrate, and a plurality of first conductor pillars formed above the semiconductor die or the substrate. Alternatively, the first conductor pillars are formed above the semiconductor die and the substrate. An electrical component is disposed above the semiconductor die. The electrical component can be a dual-sided integrated passive device. The semiconductor die and the electrical component are disposed on the substrate. A shielding frame is disposed above the semiconductor die. A plurality of second conductor pillars are formed above a first surface of the electrical component. A plurality of third conductor pillars are formed above a second surface of the electrical component opposite to the first surface of the electrical component. Bump caps can be formed above the distal ends of the conductor pillars. The substrate has a cavity, and the electrical component is disposed within the cavity. An underfill material is deposited between the semiconductor die and the substrate.

Description

Semiconductor device and method for forming a package with integrated passive devices on both sides The present invention relates generally to semiconductor devices, and more particularly to semiconductor devices and methods for forming a package having a dual-sided integrated passive device by means of shielding. Semiconductor devices are commonly found in modern electronic products. They perform a wide range of functions, including signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, optoelectronics, and generating visual images for television displays. Semiconductor devices are used in communications, power conversion, networking, computers, entertainment, and consumer products. They are also found in military applications, aerospace, automotive, industrial controllers, and office equipment for signal transmission. Semiconductor devices typically contain one or more semiconductor chips and integrated passive devices (IPDs) to perform necessary electrical functions. The trend is towards higher efficiency, greater integration, and miniaturization for applications. Semiconductor devices are generally susceptible to electromagnetic interference (EMI), radio frequency interference (RFI), harmonic distortion, or other inter-device interference (such as capacitive, inductive, or conductive coupling that can interfere with semiconductor device operation, commonly known as crosstalk). High-speed switching of digital circuits also generates interference. The combination of digital circuits and IPDs requires shielding to manage interference. Simultaneously achieving all these objectives within a single semiconductor package is a challenging task. According to one aspect of the present invention, a semiconductor device is provided, comprising a semiconductor die, a substrate, a plurality of first conductor pillars, and an electrical component. The first conductor pillars are formed above the semiconductor die or the substrate. The electrical component is disposed above the semiconductor die, wherein the semiconductor die and the electrical component are disposed above the substrate. According to another aspect of the present invention, a semiconductor device is provided, comprising a substrate, a semiconductor die, and an electrical component. The semiconductor die is disposed above the substrate. The electrical component is disposed between the semiconductor die and the substrate, wherein the electrical component is electrically connected to the semiconductor die and the substrate. According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, comprising providing a substrate; disposing a semiconductor die above the substrate; and disposing an electrical component between the semiconductor die and the substrate, wherein the electrical component is electrically connected to the semiconductor die and the substrate. The present invention is described in the following description with reference to the accompanying drawings, in which like element symbols represent like or similar elements. Although the invention is described in the best mode for achieving the objectives of the invention, it will be appreciated by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims and their equivalents supported by the following disclosure and drawings. Semiconductor devices are typically fabricated using two complex processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves the formation of multiple dies on the surface of a semiconductor wafer. Each die on this wafer contains active and passive electrical components that are electrically connected to form functional circuits. For example, active electrical components such as transistors and diodes have the ability to control the flow of current. Passive electrical components such as capacitors, inductors, and resistors create the voltage and current relationships necessary for the circuit to function. Back-end manufacturing refers to the process of dicing or monolithizing a completed wafer into individual semiconductor dies and encapsulating these dies for structural support, electrical interconnection, and environmental isolation. To monolithize the semiconductor dies, the wafer is scribed and cut along non-functional regions (called dicing lines). The wafer is monolithized using a laser cutting tool or saw blade. After monolithization, the individual semiconductor dies are mounted on a package substrate containing pins or contact pads for interconnection with other system components. Contact pads formed above the semiconductor dies are then connected to contact pads within the package. The electrical connections can be made using conductor layers, bumps, short post bumps, conductive paste, or wire bonding. A sealant or other molding material is deposited over the package to provide physical support and electrical isolation. The completed package is then inserted into an electrical system, enabling the semiconductor device to function as a component for use with other system components. Figure 1a illustrates a semiconductor wafer 100 having a substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk materials used for structural support. A plurality of semiconductor chips or electronic components 104 are formed on the wafer 100, the semiconductor chips 104 being separated by non-functional inter-chip wafer regions or dicing channels 106. The dicing channels 106 provide dicing areas to monolithize the semiconductor wafer 100 into individual semiconductor chips 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100 millimeters to 450 millimeters (mm). Figure 1b shows a cross-sectional view of a portion of a semiconductor wafer 100. Each semiconductor die 104 has a back surface or non-active surface 108 and an active surface 110 containing analog or digital circuitry, which is implemented as active elements, passive elements, conductors, and dielectric layers formed within the die and electrically interconnected according to the die's electrical design and function. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuitry, such as digital signal processors (DSPs), application-specific integrated circuits (ASICs), memory, or other signal processing circuitry. The semiconductor die 104 may also include integrated passive devices such as inductors, capacitors, and resistors for radio frequency (RF) signal processing. The conductor layer 112 is formed on the active surface 110 using PVD, CVD, electroplating, electroless plating, or other suitable metal deposition processes. The conductor layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductor layer 112 functions as a contact pad for electrical connections to circuitry on the active surface 110. Figure 2a shows further details of a portion of a semiconductor wafer 100 having a conductor layer 112 and an insulating layer 114. The insulating layer 114 contains one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), photoresist, polyimide, phenylcyclobutene (BCB), and polybenzo[a]pyrene. PBO (polyoxohydrazole) and other materials with similar insulating and structural properties. The insulating layer can be formed using PVD, CVD, printing, lamination, spin coating, spraying, sintering, or thermal oxidation. The insulating layer 114 provides isolation between the conductor layers 112. In Figure 2b, a solder resist or photoresist 120 is formed over the conductor layer 112 and the insulating layer 114. In Figure 2c, the photoresist 120 is exposed, developed, and etched to form vias 122 for the positions of the conductor pillars 130. In Figure 2d, the vias 122 are filled with a conductive material, such as Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials, to form a vertical shaft 126. A Ni layer 127 is formed over the top surface of the vertical shaft 126. A bump material 128 is deposited over the Ni layer 127. The bump material 128 can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, or combinations thereof, and can be a flux solution. In one embodiment, the bump material 128 is a lead-free solder. In Figure 2e, the remaining photoresist 120 is removed by photoresist stripping, wafer plasma, seed layer etching, scrubber cleaning, wafer plasma, scrubber cleaning, etching, scrubber cleaning, and wafer plasma again, leaving the vertical axis 126, Ni layer 127, and bump material 128. In Figure 2f, the bump material 128 is reflowed, followed by flux cleaning, scrubber cleaning ball shear and measurement, to form a bump cap on the distal end of the vertical axis 126, collectively referred to as a conductor post or post 130. In one embodiment, the conductor post 130 has a height H1 of 20 mm to 30 mm, a diameter of 10 mm to 15 mm, and a pitch of 30 mm. Figure 2g illustrates further details of the conductor pillar 130. A conductor layer 112 is formed over the base substrate material 102. An insulating layer 129 is formed over the base substrate material 102 and the conductor layer 112. An insulating layer 131 is formed over the insulating layer 129 and the conductor layer 112. The insulating layers 129 and 131 contain one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, photoresist, polyimide, BCB, PBO, and other materials with similar insulating and structural properties. The insulating layers 129 and 131 can be formed using PVD, CVD, printing, lamination, spin coating, spraying, sintering, or thermal oxidation. Insulating layer 114 is a simplified representation of the more detailed insulating layers 129 to 131. Figure 2h illustrates further details of another embodiment of the conductor post 130. A conductor layer 112 is formed over the base substrate material 102. An insulating layer 129 is formed over the base substrate material 102 and the conductor layer 112. Figure 3a illustrates a semiconductor die 132 manufactured similarly to those of Figures 1a to 1b. The semiconductor die 132 has a first active surface 136 and a second active surface 140, each active surface containing active devices, passive devices, conductor layers, and dielectric layers of analog or digital circuitry implemented within the die and electrically interconnected according to the die's electrical design and function. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active surfaces 136 and 140 to implement analog or digital circuitry, such as DSPs, ASICs, memory, or other signal processing circuitry. The semiconductor die 132 may also contain IPDs for RF signal processing, such as inductors, capacitors, and resistors. In one embodiment, the semiconductor die 132 is a dual-sided IPD. Conductor layer 134 is formed above surface 136 and conductor layer 138 is formed above surface 140 using PVD, CVD, electroplating, electroless plating, or other suitable metal deposition processes. Conductor layer 134 and conductor layer 138 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Conductor layer 134 and conductor layer 138 are electrically connected to the contact pads of circuits or IPDs on active surface 136 and active surface 140, respectively, for operation. In Figure 3b, a plurality of vertical shaft members 144 are formed above the conductor layer 134, similar to the vertical shaft members 126 in Figures 2b to 2f. Similarly, a plurality of vertical shaft members 146 are formed above the conductor layer 138. In Figure 3c, bump caps 148, collectively referred to as conductor pillars or pillars 150, are formed on the distal ends of the vertical shaft members 144, similar to Figures 2b to 2f. Bump caps 152, collectively referred to as conductor pillars or pillars 154, are formed on the distal ends of the vertical shaft members 146, similar to Figures 2b to 2f. Bump caps 148 and bump caps 152 can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, or combinations thereof, and can be selected from flux solutions. In addition, epoxy resin flux can be applied to the conductor pillars 154. The epoxy resin flux has the functions of both flux and epoxy resin. After die attachment, the epoxy resin portion of the epoxy flux protects the bumps on the die. It can be applied to the conductor layer 112 or the conductor pillar 154. In one embodiment, the conductor pillar 150 has a height H2 of 20 μm to 30 μm and a height H3 of 5 μm to 10 μm. The combination of the semiconductor die 132 with the conductor pillars 150 and 154 constitutes the electrical assembly 156. In Figure 2i, the electrical component 156 of Figure 3c is disposed on the surface 110 of the semiconductor wafer 100 and electrically and mechanically connected to the conductor layer 112. The electrical component 156 is positioned above the wafer 100 using a pick-and-place operation. The electrical component 156 can be a semiconductor package, surface mount device, discrete electrical device, or IPD, such as a diode, transistor, resistor, capacitor, or inductor. The conductor posts 154 of the electrical component 156 are brought into contact with and re-soldered to the conductor layer 112 of the wafer 100. Figure 2j illustrates the electrical component 156 electrically and mechanically connected to the conductor layer 112 of the wafer 100 via the conductor posts 154. In one embodiment, as shown in FIG2k, the electrical component 156 is bonded to the wafer 100 using laser-assisted bonding (LAB) with the aid of laser 155. In this case, a metal shield 157 is disposed over the wafer 100 by means of conductor posts 130 covered by a metal shield and the electrical component 156 exposed through openings 159. Laser 155 is fired at the wafer 100 to selectively bond the electrical component 156. Using a saw blade or laser cutting tool, the semiconductor wafer 100 is monolithically divided into individual semiconductor dies 104 via the cutting path 106. Each semiconductor die has additional conductor pillars 130 and electrical components 156 disposed above the surface 110. The individual semiconductor dies 104 with conductor pillars 130 and electrical components 140 can be inspected and electrically tested to identify known good dies or known good units (KGD / KGU) after monolithization. The combination of semiconductor dies 104 and electrical components 156 constitutes a semiconductor package 158. Figure 21 shows a cross-sectional view of a substrate 160 including a conductor layer 162 and an insulating layer 163. The conductor layer 162 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductor materials. The substrate 160 further includes electrical interconnects through the substrate. In one embodiment, the substrate 160 is a PCB. The semiconductor package 158 of Figure 2m is positioned above the surface 164 of the substrate 160, with the conductor pillars 130 positioned facing the substrate. This brings the semiconductor package 158 into contact with the surface 164 of the substrate 160. Figure 2n shows the semiconductor package 158 disposed on the substrate 160, where the conductor pillars 130 and 150 are electrically and mechanically connected to the conductor layer 162 on the surface 164 by reflow soldering. Similar to Figure 2k, a laser beam (LAB) can also be used to bond the semiconductor package 158 to the substrate 160. In this case, a laser is emitted from the bottom side of the substrate 160 to bond the semiconductor package 158 to the substrate. In Figure 2o, an underfill material 166 (such as epoxy resin) is deposited beneath the semiconductor die 104 and around the conductor pillars 130, 150, 154, and the electrical component 156. The underfill material 166 isolates and protects the active surface of the electrical component 156, the active surface 110 of the semiconductor die 104, and the conductor pillars 130, 150, and 154. The electrical components within the semiconductor package 158 may contain IPDs that are susceptible to or generate EMI, RFI, harmonic distortion, and inter-device interference. For example, the IPD or electrical component 156 contained within the semiconductor die 104 provides the electrical characteristics required for high-frequency applications such as resonators, high-pass filters, low-pass filters, band-pass filters, symmetrical Hi-Q resonant transformers, and tuning capacitors. In another embodiment, the semiconductor die 104 or electrical component 156 contains digital circuitry that switches at high frequencies, which can interfere with the operation of other IPDs. To address EMI, RFI, harmonic distortion, and inter-device interference, a shielding frame 170 is positioned above the semiconductor package 158, as shown in Figure 2o. The shielding frame 170 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Alternatively, the shielding frame 170 can be carbonyl iron, stainless steel, nickel silver, low-carbon steel, silicon steel, foil, conductive resin, carbon black, aluminum sheet, and other metals and composites capable of reducing or suppressing EMI, RFI, and other inter-device interference effects. In Figure 2p, the shielding frame 170 is in contact with the semiconductor package 158 and the substrate 160, and grounded via a conductive layer 162 having conductive paste. Alternatively, the frame 170 can be a heat sink or fin with a thermal interface material. The heat sink can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable thermally conductive materials. The heat sink 170 dissipates the heat generated by the semiconductor package 158. The combination of semiconductor package 158, substrate 160 and frame 170 constitutes semiconductor assembly 172. Figure 4a shows a substrate 180, in which conductor layers 182 and 183 are formed on opposite sides of the substrate as contact pads, similar to Figures 21 to 2m. Semiconductor dies 184a, 184b, 184c, and 184d are disposed above the substrate 180. Bonding lines 186 electrically connect conductor layers 187 on semiconductor dies 184a to 184d to conductor layers 183 on the substrate 180. In one embodiment, semiconductor dies 184a to 184d are stacked memory dies. In Figure 4b, an encapsulant or molding compound 188 is deposited on and around semiconductor dies 184a to 184d, bonding wires 186, and substrate 180 using paste printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or other suitable application equipment. The encapsulant 188 can be a polymer composite material, such as a filled epoxy resin, a filled epoxy acrylate, or a polymer with appropriate fillers. The encapsulant 188 is non-conductive, provides structural support, and protects the semiconductor device from external elements and contaminants. In Figure 4c, conductor bump material is deposited on the conductor layer 182 of substrate 180 using vapor deposition, electrolytic plating, electroless plating, ball drop, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, or combinations thereof, and can be a flux solution. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductor layer 182 using a suitable attachment or bonding process. In one embodiment, the bump material is formed by repeatedly soldering the material above its melting point to form balls or bumps 190. In one embodiment, bumps 190 are formed on under bump metallization (UBM) having a wetting layer, a barrier layer, and an adhesive layer. Bumps 190 can also be compression bonded or thermo-pressed to conductor layer 182. In one embodiment, bump 190 is a copper core bump to improve durability and maintain its height. Bump 190 represents one type of interconnect structure that can be formed above conductor layer 182. The interconnect structure can also use bonding wires, conductive paste, short post bumps, microbumps, or other electrical interconnects. The combination of substrate 180, semiconductor dies 184a to 184d, bonding wire 186, encapsulant 188, and bumps 190 constitutes semiconductor package 194. In one embodiment, semiconductor package 194 is a memory device, such as a high-bandwidth memory. Figure 5a shows a cross-sectional view of a substrate 200 including a conductor layer 202 formed on surface 203 and a conductor layer 204 formed on the opposing surface 205 as a contact pad, similar to Figures 21 to 2m. The conductor layers 202 and 204 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductor materials. The substrate 200 further includes electrical interconnects passing through the substrate. In one embodiment, the substrate 200 is a PCB. Semiconductor package 158 of FIG. 2j and semiconductor package 194 of FIG. 4c are disposed above surface 204 of substrate 200, similar to FIG. 2l to 2m. An underfill material 206, such as epoxy resin, is deposited under semiconductor package 158 and semiconductor package 194. The underfill material 206 isolates and protects the active surface of semiconductor package 158 and the active surface, conductor pillars 130, 150, 154 and bumps 190 of semiconductor package 194. In Figure 5b, a shielding frame 208 is positioned above the semiconductor package 158, similar to Figures 21 to 2m. The shielding frame 208 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Alternatively, the shielding frame 208 can be carbonyl iron, stainless steel, nickel silver, low-carbon steel, silicon steel, foil, conductive resin, carbon black, aluminum sheet, and other metals and composites that can reduce or suppress EMI, RFI, and other inter-device interference effects. Alternatively, the frame 208 can be a heat sink or fin with a thermal interface material. The heat sink can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable thermally conductive materials. The heat sink 208 dissipates the heat generated by the semiconductor package 158. In Figure 5c, conductor bump material is deposited on the conductor layer 204 of substrate 200 using processes such as vapor deposition, electrolytic plating, electroless plating, ball drop, or screen printing. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, or combinations thereof, and can be a flux solution. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to conductor layer 204 using a suitable attachment or bonding process. In one embodiment, the bump material is formed by repeatedly soldering the material above its melting point to form balls or bumps 209. In one embodiment, bumps 209 are formed on a UBM having a wetting layer, a barrier layer, and an adhesive layer. Bumps 209 can also be compression bonded or thermocompressed to conductor layer 204. In one embodiment, bumps 209 are copper core bumps to improve durability and maintain their height. Bump 209 represents one type of interconnect structure that can be formed above conductor layer 204. The interconnect structure can also use bonding wires, conductor paste, short post bumps, microbumps, or other electrical interconnects. In Figure 5d, a semiconductor die or package 210 is disposed above surface 205 of substrate 200, similar to Figures 21 to 2m. Bumps 212 electrically and mechanically connect the semiconductor die 210 to the conductor layer 204 of substrate 200 via reflow soldering. An underfill material 214, such as epoxy resin, is deposited beneath the semiconductor die 210. The underfill material 214 isolates and protects the active surface of semiconductor die 210 and bumps 209. The combination of semiconductor package 158, semiconductor package 194, substrate 200, frame 208, bump 209 and semiconductor die 210 constitutes semiconductor assembly 215. In another embodiment shown in FIG. 6a, substrate 216 includes a conductor layer 218 formed on surface 219, similar to FIG. 21 to 2m. The conductor layer 218 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductor materials. Substrate 216 further includes electrical interconnects through the substrate. In one embodiment, substrate 216 is a PCB. A plurality of vertical shaft members 220 are formed above the conductor layer 218, similar to the vertical shaft members 126 in Figures 2b to 2f. Bump caps 222 are formed on the distal ends of the vertical shaft members 220 as conductor pillars or pillars 224. The bump caps 222 can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, or combinations thereof, and can be selected from flux solutions. In one embodiment, depending on the application, the conductor pillars 224 have a height H4 of 70 to 110 mm. Without the conductor pillars 130, the semiconductor package 158 of Figure 21 is positioned above the substrate 216, with the electrical components 156 positioned facing the substrate. Figure 6b illustrates conductor pillars 150 of an electrical component 156 electrically and mechanically connected to conductor layer 218 of substrate 216. Similarly, conductor pillars 224 are electrically and mechanically connected to conductor layer 112 of semiconductor package 158 via reflow soldering. In this embodiment, conductor pillar 224 replaces conductor pillar 130. In Figure 6c, a shielding frame 228 is positioned above the semiconductor package 158, similar to Figures 2o to 2p. The shielding frame 228 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Alternatively, the shielding frame 228 can be carbonyl iron, stainless steel, nickel silver, low-carbon steel, silicon steel, foil, conductive resin, carbon black, aluminum sheet, and other metals and composites that can reduce or suppress EMI, RFI, and other inter-device interference effects. Alternatively, the frame 228 can be a heat sink or fin with a thermal interface material. The heat sink can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable thermally conductive materials. The heat sink 228 dissipates the heat generated by the semiconductor package 158. The semiconductor package 158, the substrate 216 having conductor pillars 224, and the frame 228 together constitute the semiconductor assembly 229. In another embodiment shown in FIG. 7a, the substrate 230 includes a conductor layer 232 formed on surface 233, similar to FIG. 21 to FIG. 2m. The conductor layer 232 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductor materials. The conductor layer 232 further includes electrical interconnects through the substrate. In one embodiment, the substrate 230 is a PCB. A plurality of vertical shaft members 234 are formed above the conductor layer 232, similar to the vertical shaft members 126 in Figures 2b to 2f. Bump caps 236 are formed on the distal ends of the vertical shaft members 234 to form conductor pillars or pillars 238. The bump caps 236 can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder, or combinations thereof, and can be selected from flux solutions. In one embodiment, the conductor pillars 238 have a height H5 of 35-55 mm, or approximately half the height of H1. The semiconductor package 158 of Figure 21 is positioned above the substrate 216, with the conductor pillars 130 and the electrical components 156 positioned towards the substrate. In this configuration, compared to Figure 2f, the conductor pillars 130 have a smaller height due to the nature of the conductor pillars 238. Figure 7b illustrates conductor posts 150 of an electrical assembly 156 electrically and mechanically connected to conductor layer 232 of substrate 230. Similarly, conductor posts 238 are electrically and mechanically connected to conductor posts 130 of semiconductor package 158. In this embodiment, both semiconductor package 158 and substrate 230 have conductor posts that meet between their structures. Figure 7c shows further details of the interconnect region 7c from Figure 7b. The conductor layer 232 extends into the substrate 230. In Figure 7d, an underfill material 240, such as epoxy resin, is deposited beneath the semiconductor package 158. The underfill material 240 isolates and protects the active surfaces of the semiconductor package 158 and the conductor pillars 130, 150, 154, and 238. A shielding frame 242 is disposed above the semiconductor package 158, similar to Figures 2o to 2p. The shielding frame 242 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Alternatively, the shielding frame 242 can be carbonyl iron, stainless steel, nickel silver, low-carbon steel, silicon steel, foil, conductive resin, carbon black, aluminum sheet, and other metals and composites that can reduce or suppress EMI, RFI, and other inter-device interference effects. Alternatively, the frame 242 can be a heat sink or fin with a thermal interface material. The heat sink can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable thermally conductive materials. The heat sink 242 dissipates the heat generated by the semiconductor package 158. The semiconductor package 158, the substrate 216 having conductor pillars 238, and the frame 242 together constitute the semiconductor assembly 248. In another embodiment, substrate 250 includes cavity 252, as shown in FIG. 8a. Conductor layer 254 is formed on surface 256 and in cavity 252. Conductor layer 254 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductor materials. Substrate 250 further includes electrical interconnects through the substrate. In one embodiment, substrate 250 is a PCB. Figure 8b shows conductor pillars 130 and 150 electrically and mechanically connected to conductor layer 254 of substrate 250. Electrical assembly 156 is at least partially disposed in cavity 252. In Figure 8c, an underfill material 258, such as epoxy resin, is deposited under the semiconductor package 158. The underfill material 258 isolates and protects the active surfaces of the semiconductor package 158 and the conductor pillars 130, 150, and 154. A shielding frame 260 is disposed above the semiconductor package 158, similar to Figures 2o to 2p. The shielding frame 260 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Alternatively, the shielding frame 260 can be carbonyl iron, stainless steel, nickel silver, low-carbon steel, silicon steel, foil, conductive resin, carbon black, aluminum sheet, and other metals and composites that can reduce or suppress EMI, RFI, and other inter-device interference effects. Alternatively, the frame 260 can be a heat sink or fin with a thermal interface material. The heat sink can be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable thermally conductive materials. The heat sink 260 dissipates the heat generated by the semiconductor package 158. The combination of semiconductor package 158, substrate 250 and frame 260 constitutes semiconductor assembly 264. Figure 9 illustrates an embodiment of the interconnection structure between semiconductor die 104 and substrate 250 and semiconductor die 132, and further details of the interconnection structure between semiconductor die 132 and substrate 250 within cavity 252. Figure 10 illustrates an electrical device 400 having a wafer carrier substrate or PCB 402, wherein a plurality of semiconductor packages are disposed above the surface of the PCB 402, including a BGA semiconductor assembly 172, a ball grid array (BGA) semiconductor assembly 215, a BGA semiconductor assembly 229, a BGA semiconductor assembly 248, and a BGA semiconductor assembly 264. The electrical device 400 may have one type of semiconductor package or multiple types of semiconductor packages depending on the application. The electrical device 400 can be a standalone system that uses the semiconductor package to perform one or more electrical functions. Alternatively, the electrical device 400 can be a sub-component of a larger system. For example, the electrical device 400 can be part of a tablet computer, mobile phone, digital camera, communication system, or other electronic device. Alternatively, the electrical device 400 can be a graphics card, network interface card, or other signal processing card that can be inserted into a computer. The semiconductor package can contain a microprocessor, memory, ASIC, logic circuit, analog circuit, RF circuit, discrete device, or other semiconductor chips or electrical components. Miniaturization and weight reduction are necessary for product market acceptance. The distance between semiconductor devices can be reduced to achieve higher density. In Figure 10, PCB 402 provides a general-purpose substrate for structural support and electrical interconnection of semiconductor packages disposed on the PCB. Conductor signal traces 404 are formed above the surface of PCB 402 or within layers of PCB 402 using vapor deposition, electroplating, electroless plating, screen printing, or other suitable metal deposition processes. Signal traces 404 provide electrical communication between each of the semiconductor packages, mounted components, and other external system components. Trace 404 also provides power and ground connections to each of the semiconductor packages. In some embodiments, the semiconductor device has two packaging levels. The first-level package is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. The second-level package involves mechanically and electrically attaching the intermediate substrate to the PCB. In other embodiments, the semiconductor device may have only the first-level package, wherein the die is directly mechanically and electrically disposed on the PCB. For illustrative purposes, several types of first-level packages including wire bond package 406 and flip-chip 408 are shown on PCB 402. Additionally, several types of second-level packages, including ball grid array 410, bump chip carrier (BCC) 412, land grid array (LGA) 416, system-in-package (SIP) module 418, quad flat non-leaded package (QFN) 420, quad flat package 422, embedded wafer level ball grid array (eWLB) 424, and wafer level chip scale package (WLCSP) 426, are shown disposed on PCB 402. In one embodiment, eWLB 424 is a fan-out wafer level package (Fo-WLP), and WLCSP 426 is a fan-in wafer level package (Fi-WLP). Depending on system requirements, any combination of semiconductor packages and other electronic components configured using any combination of first and second-level package types can be connected to PCB 402. In some embodiments, electronic device 400 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate pre-fabricated components into electronic devices and systems. Because the semiconductor packages contain complex functionality, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less prone to failure and less expensive to manufacture, resulting in lower costs for consumers. Although one or more embodiments of the present invention have been illustrated in detail, those skilled in the art will understand that modifications and alterations can be made to these embodiments without departing from the scope of the present invention as described in the following claims. 100: Semiconductor wafer; 102: Substrate material; 104: Semiconductor die / electrical component; 106: Cutter track; 108: Non-active surface; 110: Active surface; 112: Conductor layer; 114: Insulating layer; 120: Photoresist; 122: Through-hole; 126: Vertical axis; 127: Ni layer; 128: Bump material; 129: Insulating layer; 130: Conductor post / post; 131: Insulating layer; 132: Semiconductor die; 134: Conductor layer; 136: Active surface / surface; 138: Conductor layer; 140: Second active surface / surface / electrical component; 144: Vertical axis; 146: Vertical axis; 148: Bump cap; 150: Conductor post / post; 152: Bump cap. 154: Conductor Post / Pillar; 155: Laser; 156: Electrical Component; 157: Metal Shield; 158: Semiconductor Package; 159: Opening; 160: Substrate; 162: Conductor Layer; 163: Insulating Layer; 164: Surface; 166: Bottom Filler; 170: Frame / Heater; 172: Semiconductor Assembly; 180: Substrate; 182: Conductor Layer; 183: Conductor Layer; 184a: Semiconductor Die; 184b: Semiconductor Die; 184c: Semiconductor Die; 184d: Semiconductor Die; 186: Bonding Wire; 187: Conductor Layer; 188: Encapsulant / Molding Compound; 190: Bump; 194: Semiconductor Package; 200: Substrate; 202: Conductor Layer 203: Surface 204: Conductor Layer / Surface 205: Surface 206: Underfill Material 208: Frame / Heat Sink 209: Bump 210: Semiconductor Die / Package 212: Bump 214: Underfill Material 215: Semiconductor Assembly 216: Substrate 218: Conductor Layer 219: Surface 220: Vertical Axis 222: Bump Cap 224: Conductor Pillar / Pillar 228: Frame / Heat Sink 229: Semiconductor Assembly 230: Substrate 232: Conductor Layer 233: Surface 234: Vertical Axis 236: Bump Cap 238: Conductor Pillar / Pillar 240: Underfill Material 242: Frame / Heat Sink 248: Semiconductor Assembly 250: Substrate 252: Cavity 254: Conductor Layer 256: Surface 258: Underfill Material 260: Frame / Heat Heatsink 264: Semiconductor Assembly 400: Electrical Device 402: Printed Circuit Board 404: Trace 406: Wire Bond Package 408: Flip Chip 410: Ball Grid Array 412: Bumped Wafer Carrier 416: Platform Grid Array 418: Multi-Wafer Module or System-in-Package Module 420: Square Flat Leadless Package 422: Square Flat Package 424: Embedded Wafer-Level Ball Grid Array 426: Wafer-Level Chip Scale Package H1: Height H2: Height H3: Height H4: Height H5: Height [Figs. 1a] to [Figs. 1b] illustrate a semiconductor wafer having a plurality of semiconductor dies separated by dicing channels; [Figs. 2a] to [Figs. 2p] illustrate the formation of a semiconductor package having semiconductor dies attached between conductor pillars and double-sided IPDs; [Figs. 3a] to [Figs. 3c] illustrate the process of forming double-sided IPDs; [Figs. 4a] to [Figs. 4c] illustrate the process of forming a semiconductor package having stacked semiconductor dies; [Figs. 5a] to [Figs. 5d] illustrate the semiconductor packages of Figs. 2a to 2l and Figs. 4a to 4c on a substrate; [Figs. 6a] to [Figs. 6c] illustrate another embodiment of a semiconductor package on a substrate; [Figs. 7a] to [Figs. 7d] illustrate another embodiment of a semiconductor package on a substrate; [Figs. 8a] to [Figs. 8c] illustrate another embodiment of a semiconductor package on a substrate having cavities; [Fig. 9] illustrates further details of the interconnect structure within the cavity of the substrate; and [Fig. 10] illustrates a printed circuit board. (PCB) refers to a board, on which different types of packages are provided on the surface. 104: Semiconductor chips / electrical components 112: Conductor layer 114: Insulation layer 126: Vertical shaft component 128: Bump Material 130: Conductor post / post 132: Semiconductor die 134: Conductor layer 138: Conductor layer 144: Vertical axis component 146: Vertical axis component 148: Convex Cap 150: Conductor column / pillar 152: Protruding Cap 154: Conductor Post 156: Electrical Components 160:Substrate 162: Conductor layer 163: Insulation layer 166: Bottom filling material 170: Frame / Heater 172: Semiconductor Assembly

Claims

1. A semiconductor device comprising: Semiconductor grains; substrate; A plurality of first conductor pillars formed above the semiconductor die or the substrate; and an electrical component disposed above the semiconductor die, wherein the semiconductor die and the electrical component are disposed above the substrate and the electrical component includes a first electrical connection to the semiconductor die and a second electrical connection to the substrate.

2. The semiconductor device of claim 1, wherein the electrical component includes an integrated passive device.

3. The semiconductor device of claim 1, further comprising a shielding frame disposed above the semiconductor die.

4. The semiconductor device of claim 1, wherein the first electrical connection comprises a plurality of second conductor posts formed above a first surface of the electrical component to the semiconductor die.

5. The semiconductor device of claim 1, wherein the substrate includes a cavity and the electrical component is at least partially disposed within the cavity.

6. A semiconductor device comprising: substrate; Semiconductor chips are disposed above the substrate; An electrical component is disposed between the semiconductor die and the substrate, wherein the electrical component includes a first electrical connection to the semiconductor die and a second electrical connection to the substrate.

7. The semiconductor device of claim 6, further comprising a plurality of conductor pillars formed above the semiconductor die or the substrate.

8. The semiconductor device of claim 6, further comprising a shielding frame disposed above the semiconductor die.

9. The semiconductor device of claim 6, wherein the first electrical connection comprises a plurality of first conductor posts formed above the first surface of the electrical component to the semiconductor die.

10. The semiconductor device of claim 9, wherein the second electrical connection comprises a plurality of second conductor posts formed above the second surface of the electrical component opposite to the first surface of the electrical component to the substrate.

11. A method for manufacturing a semiconductor device, comprising: Provide substrate; Semiconductor chips are placed on top of the substrate; An electrical component is disposed between the semiconductor die and the substrate, wherein the electrical component includes a first electrical connection directly to the semiconductor die and a second electrical connection directly to the substrate.

12. The method of claim 11, further comprising forming a plurality of conductor pillars above the semiconductor die or the substrate.

13. The method of claim 11, further comprising disposing a shielding frame over the semiconductor die.

14. The method of claim 11, wherein the first electrical connection comprises forming a plurality of first conductor pillars directly to the semiconductor die above a first surface of the electrical component.

15. The method of claim 14, wherein the second electrical connection comprises forming a plurality of second conductor posts directly to the substrate above a second surface of the electrical component opposite to the first surface of the electrical component.

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