Semiconductor memory devices

Abstract

An embodiment of the present invention provides a semiconductor memory device that allows for increased design freedom. An embodiment of the semiconductor memory device of the present invention includes a circuit board, electronic components, a plurality of conductive members, and an information display area. The circuit board has a first surface and a second surface located opposite to the first surface. The electronic components are mounted on the first surface of the circuit board. The plurality of conductive members are arranged on the second surface of the circuit board. The plurality of conductive members are electrically connected to the circuit board. The plurality of conductive members are formed of a conductive material. The information display area is disposed on the second surface of the circuit board. The information display area has an information display pattern formed of a coating material or a conductive material identical to the conductive material.

Description

Technical Field

[0001] An embodiment of the present invention relates to a semiconductor memory device. Prior Art

[0002] A semiconductor memory device is known that includes a substrate and electronic components mounted on the substrate. The semiconductor memory device has a marking such as a 2D code. Such a marking may contain management information such as manufacturing history information. Summary of the Invention

[0003] The problem to be solved by the present invention is to provide a semiconductor memory device that can improve the degree of design freedom.

[0004] A semiconductor memory device according to an embodiment includes a circuit substrate, electronic components, a plurality of conductive members, and an information display area. The circuit substrate has a first surface and a second surface opposite the first surface. The electronic components are mounted on the first surface of the circuit substrate. The plurality of conductive members are arranged on the second surface of the circuit substrate. The plurality of conductive members are electrically connected to the circuit substrate. The plurality of conductive members are formed of a conductive material. The information display area is provided on the second surface of the circuit substrate. The information display area has an information display pattern formed of a coating material or a conductive material similar to the conductive material. Simple diagram description

[0005] FIG1 is a perspective view showing a memory device according to a first embodiment. FIG2 is a perspective view showing a partially exploded view of the memory device of the first embodiment. FIG3 is a cross-sectional view showing the structure of the NAND memory according to the first embodiment. FIG4 is a bottom view showing the arrangement of the NAND memory according to the first embodiment. FIG5 is a top view showing the information display pattern of the first embodiment. FIG6A is a diagram illustrating a method for manufacturing a NAND memory according to the first embodiment, and shows a top view of a large circuit substrate. FIG6B is a diagram illustrating the method for manufacturing the NAND memory according to the first embodiment, and is a top view showing a variation of a large circuit substrate. FIG7 is a diagram illustrating a method for manufacturing a NAND memory according to the first embodiment, and is a cross-sectional view showing a portion of a large circuit substrate. FIG8 is a diagram illustrating a method for manufacturing a NAND memory according to the first embodiment, and is a cross-sectional view showing a portion of a large circuit substrate. FIG9 is a diagram illustrating a method for manufacturing a NAND memory according to the first embodiment, and is a cross-sectional view showing a portion of a large circuit substrate. FIG10 is a diagram illustrating a method for manufacturing a NAND memory according to the first embodiment, and is a cross-sectional view showing a portion of a large circuit substrate. FIG11 is a diagram illustrating a method for manufacturing a NAND memory according to the first embodiment, and is a cross-sectional view showing a portion of a large circuit substrate. 12A is a diagram illustrating a method for manufacturing a NAND memory according to the first embodiment, and is a schematic cross-sectional view showing a device used for arranging solder balls on pads. 12B is a diagram illustrating the method for manufacturing the NAND memory according to the first embodiment, and is a schematic cross-sectional view showing a device used for disposing solder balls on pads. FIG13 is a top view showing an information display pattern of the second embodiment. FIG14 is a bottom view showing the structure of a modified example of the NAND memory according to the second embodiment. FIG15 is a bottom view showing the structure of a modified example of the NAND memory according to the second embodiment. FIG16 is a bottom view showing the structure of a modified example of the NAND memory according to the second embodiment. FIG17 is a bottom view showing the structure of a modified example of the NAND memory according to the second embodiment. Implementation Method

[0006] The following describes a semiconductor memory device according to an embodiment with reference to the drawings. In the following description, components having the same or similar functions are denoted by the same reference numerals. In addition, repeated descriptions of these components may be omitted. In this application, ordinal numbers such as "first," "second," and "third" are sometimes used. These ordinal numbers do not indicate the number of components described. In this application, "parallel," "orthogonal," or "identical" may also include "substantially parallel," "substantially orthogonal," or "substantially identical," respectively. In this application, the term "connected" is not limited to mechanical connection but also includes electrical connection. Furthermore, "connected" is not limited to direct connection of two connected elements but also includes connection of two connected elements with other elements interposed therebetween. Furthermore, the term "connected" is not limited to interconnection but also includes mere contact. In this application, "overlapping" may also include situations where two elements overlap with other elements interposed therebetween.

[0007] Here, the +X direction, -X direction, +Y direction, -Y direction, +Z direction, and -Z direction are defined as directions parallel to the first surface 21a of the substrate 21 described later (see FIG2 ).

[0008] The +X direction is the direction from the first end 21e1 of the substrate 21 toward the second end 21e2 (see Figure 2). The -X direction is the direction opposite to the +X direction. When the +X and -X directions are not distinguished, they are simply referred to as the "X direction." The +Y and -Y directions are directions that intersect (e.g., are perpendicular to) the X direction. The X direction is an example of a "first direction."

[0009] The +Y direction is the direction from NAND (Not-AND) memory 25A, described later, toward NAND memory 25B (see Figure 2). The -Y direction is the direction opposite to the +Y direction. When the +Y and -Y directions are not distinguished, they are simply referred to as the "Y direction." The Y direction intersects the X direction and is an example of a "second direction."

[0010] The +Z and -Z directions intersect (e.g., are perpendicular to) the X and Y directions. The +Z and -Z directions are the thickness directions of substrate 21. The +Z direction runs from second surface 21b toward first surface 21a of substrate 21 (see Figure 2). The -Z direction is the direction opposite to the +Z direction. When the +Z and -Z directions are not distinguished, they are simply referred to as the "Z direction."

[0011] <First embodiment> <Overall Structure of Memory Device> 1 to 5, a memory device 1 according to a first embodiment will be described. FIG1 is a perspective view of a memory device 1. Memory device 1 is, for example, a solid state drive (SSD). Memory device 1 is installed in an information processing device (hereinafter referred to as a "host device") such as a server or a personal computer. Memory device 1 serves as a memory area of ​​the host device.

[0012] 2 is a partially exploded perspective view of the memory device 1. The memory device 1 includes, for example, a housing 10 and a substrate unit 20.

[0013] <Housing> The housing 10 is a member that forms the outer shell of the memory device 1 (see FIG. 1 ). The housing 10 is shaped, for example, as a flat rectangular tube. As shown in FIG. 2 , the housing 10 includes, for example, a first member 11, a second member 12, and a plurality of fixing members 13. The first member 11 includes, for example, a wall portion located on the +Z direction side relative to the substrate unit 20, a wall portion located on the +Y direction side relative to the substrate unit 20, and a wall portion located on the -Y direction side relative to the substrate unit 20. The second member 12 includes a wall portion located on the -Z direction side relative to the substrate unit 20. The fixing member 13 connects the first member 11 and the second member 12. The fixing member 13 is, for example, a screw. In this embodiment, the housing 10 is formed by connecting the first member 11 and the second member 12 using a plurality of fixing members 13.

[0014] <Base Unit> The substrate unit 20 is an assembly in which components including circuits are mounted. At least a portion of the substrate unit 20 is housed within the housing 10. The substrate unit 20 includes, for example, a substrate 21, a controller 22, power conversion components 23, power circuit components 24, a plurality of NAND memories 25 (NAND memories 25A-25H), and DRAM (Dynamic Random Access Memory) 26.

[0015] Substrate 21 is a printed wiring board. Substrate 21 is a plate-shaped member extending in the X and Y directions. Substrate 21 has a first surface 21a and a second surface 21b. First surface 21a faces the +Z direction. Second surface 21b is located on the opposite side of first surface 21a. Second surface 21b faces the -Z direction.

[0016] The substrate 21 has a first end 21e1 and a second end 21e2 located opposite the first end 21e1, as both ends of the substrate 21 in its longitudinal direction. The first end 21e1 of the substrate 21 has a connector C. The connector C is an electrical connection portion that can be connected to a host device. The substrate 21 includes an insulating base material 31 and a plurality of bonding pads 32 (see FIG. 3 ) provided on the insulating base material 31. The plurality of bonding pads 32 are portions electrically connected to electrical connection terminals described below.

[0017] <controller> The controller 22 is a control component mounted on the substrate 21. It comprehensively controls the entire memory device 1. For example, the controller 22 includes a host interface circuit for communicating with a host device, a control circuit for controlling the plurality of NAND memories 25, and a control circuit for controlling the DRAM 26, all integrated into a single semiconductor chip. The controller 22 can control the writing, reading, and erasing of data from the plurality of NAND memories 25.

[0018] <Power conversion parts> The power conversion component 23 converts power. For example, the power conversion component 23 is a DC-DC (Direct Current-to-Direct Current) converter. The power conversion component 23 converts power supplied from the host device via connector C into the required power. The power conversion component 23 outputs the converted power to the power supply circuit component 24.

[0019] <Power Circuit Components> The power circuit component 24 is a component that manages power. For example, the power circuit component 24 is a PMIC (Power Management IC). The power circuit component 24 supplies power to the various components included in the substrate unit 20 (such as the controller 22, NAND memory 25, and DRAM 26).

[0020] <dram> The DRAM 26 is a semiconductor package of a semiconductor memory chip that volatilely stores data. The DRAM 26 is an example of a "semiconductor memory device". The DRAM 26 can be used as a data buffer for temporarily storing write data received from a host device, read data read from one or more NAND memories 25, etc.

[0021] <NAND memory> The NAND memory 25 is a semiconductor package of a semiconductor memory chip that non-volatilely stores data. The NAND memory 25 is, for example, a NAND type flash memory. In other words, the NAND memory 25 is an example of a "semiconductor memory", and is also an example of a "semiconductor memory device". As shown in FIG. 2, a plurality of NAND memories 25 are mounted on the first surface 21a and the second surface 21b of the substrate 21. However, the "semiconductor memory" can also be other types of memories such as a NOR (Not-OR) type memory, an MRAM (Magnetoresistive Random Access Memory), a resistive change type memory, etc.

[0022] A plurality of NAND memories 25 are arranged on the +X direction side with respect to the controller 22. The plurality of NAND memories 25 include a plurality (for example, four) of NAND memories 25A to 25D mounted on the first surface 21a of the substrate 21, and a plurality (for example, four) of NAND memories 25E to 25H mounted on the second surface 21b of the substrate 21. The NAND memories 25A and 25B are arranged on the -X direction side with respect to the NAND memories 25C and 25D. The NAND memories 25A and 25B are adjacent in the Y direction. The NAND memories 25C and 25D are adjacent in the Y direction.

[0023] Similarly, the NAND memories 25E and 25F are arranged on the -X direction side with respect to the NAND memories 25G and 25H. The NAND memories 25E and 25F are adjacent in the Y direction. The NAND memories 25G and 25H are adjacent in the Y direction. Hereinafter, when not distinguishing between the NAND memories 25A to 25H from each other, they are simply referred to as "NAND memories 25".

[0024] <Configuration of NAND memory> Next, referring to FIGS. 3 and 4, the configuration of the NAND memory 25 will be described. FIG3 is a cross-sectional view showing the structure of the NAND memory 25. As shown in FIG3, FIG3 is a cross-sectional view showing the structure of the NAND memory 25. Fig. 4 is a bottom view showing the structure of the NAND memory 25. Fig. 4 can also be called a top view of the circuit substrate 41 viewed along the +Z direction. As shown in FIG. 3 , the NAND memory 25 includes a circuit substrate 41 , one or more semiconductor memory chips 42 , a sealing resin portion 43 , a plurality of bonding wires 44 , a plurality of conductive members 45 , a plurality of pads 46 , and an information display area 47 .

[0025] <Circuit Board> The circuit board 41 serves as the base of the NAND memory 25. It is a printed wiring board. It is a plate-shaped member extending in the X and Y directions. The circuit board 41 has a first surface 41a and a second surface 41b located opposite the first surface 41a. When viewed in the Z direction, the circuit board 41 defines the shape of the NAND memory 25. The second surface 41b faces the insulating substrate 31 and is parallel to the X and Y directions.

[0026] As shown in FIG4 , the circuit substrate 41 constituting the NAND memory 25 has a rectangular shape when viewed in the Z direction. The circuit substrate 41 has four side portions S1 to S4, four corner portions C1 to C4, a central region MR, and a corner region CR.

[0027] Side portion S1 is, for example, located at the end of the NAND memory 25 on the -X direction side. Side portion S1 extends along the Y direction. Side portion S2 is, for example, located at the end of the NAND memory 25 on the +Y direction side. Side portion S2 extends along the X direction. Side portion S3 is, for example, located at the end of the NAND memory 25 on the +X direction side. Side portion S3 extends along the Y direction. Side portion S4 is, for example, located at the end of the NAND memory 25 on the -Y direction side. Side portion S4 extends along the X direction.

[0028] Side S1 is located between two adjacent corners C1 and C3. Side S2 is located between two adjacent corners C1 and C2. Side S3 is located between two adjacent corners C2 and C4. Side S4 is located between two adjacent corners C3 and C4.

[0029] Corner C1 is the intersection of side S1 and side S2. Corner C2 is the intersection of side S2 and side S3. Corner C3 is the intersection of side S1 and side S4. Corner C4 is the intersection of side S3 and side S4.

[0030] The central region MR is located in the center in the X direction and the Y direction. The corner region CR is located near one of the plurality of corners C1 to C4, closer to the central region MR. In this embodiment, the corner region CR is located near the corner C4.

[0031] <Semiconductor memory chip> Each of the one or more semiconductor memory chips 42 has a plurality of memory cells. The semiconductor memory chip 42 is a component that can store data. The semiconductor memory chip 42 is an example of an "electronic component." One or more semiconductor memory chips 42 are mounted on the first surface 41a of the circuit board 41. The one or more semiconductor memory chips 42 are stacked on the first surface 41a of the circuit board 41 along the Z direction. Each of the one or more semiconductor memory chips 42 is a plate-shaped member extending in the X and Y directions. A structure formed by stacking one or more semiconductor memory chips 42 can also be referred to as a laminate.

[0032] <Sealing Resin Section> The sealing resin portion 43 is a sealing portion that covers one or more semiconductor memory chips 42 and a plurality of bonding wires 44. The sealing resin portion 43 has insulating properties and can also be called a mold resin portion.

[0033] <Joining Line> The bonding wires 44 electrically connect the semiconductor memory chip 42 and the circuit substrate 41 .

[0034] <Conductive Member> Each of the plurality of conductive members 45 is exposed to the outside of the NAND memory 25. Specifically, the plurality of conductive members 45 is disposed on the second surface 41b of the circuit substrate 41. The plurality of conductive members 45 is arranged on the second surface 41b of the circuit substrate 41. The plurality of conductive members 45 is electrically connected to the circuit substrate 41. The plurality of conductive members 45 is formed of a conductive material. Each of the plurality of conductive members 45 is an electrical connection terminal exposed from the second surface 41 b. The plurality of conductive members 45 are arranged in the X direction and the Y direction. Each of the plurality of conductive members 45 is bonded to the pad 32 of the insulating substrate 31.

[0035] The plurality of conductive members 45 are solder. In this embodiment, the plurality of conductive members 45 have a shape that deforms the solder ball when the NAND memory 25 is mounted on the substrate 21. In this embodiment, the NAND memory 25 is a BGA (Ball Grid Array) type semiconductor package.

[0036] <Pad> A plurality of solder pads 46 are provided on the second surface 41b of the circuit substrate 41. These solder pads 46 are electrically connected one-to-one to the plurality of conductive members 45. These solder pads 46 form part of a wiring layer formed on the circuit substrate 41. This wiring layer is made of copper. Therefore, the solder pads 46 are also made of copper. On the second surface 41b of the circuit substrate 41, solder resist is applied in areas where the plurality of pads 46 are not formed. The solder resist is an insulating layer that covers and protects the electrode layer formed on the circuit substrate 41. The solder resist has a plurality of openings. The positions of the plurality of openings in the solder resist correspond to the positions of the plurality of pads 46. In other words, the electrode layer exposed through the openings in the solder resist serves as the pads 46.

[0037] <Information Display Area> As shown in Figure 4 , information display area 47 is provided on second surface 41b of circuit substrate 41. In this embodiment, information display area 47 is located in corner region CR. In other words, information display area 47 is located near corner C4. In this embodiment, information display area 47 is provided at a different position from the plurality of conductive members 45. The information display area 47 has an information display pattern PT1 formed of a coating material.

[0038] <Example 1 of Changes in Information Display Area> The position of the information display area 47 is not limited to the example shown in FIG. 4 . For example, the corner region CR may be located near one of the four corners C1 to C4, namely, corner C2. In other words, the corner region CR may be located closer to corner C2 than the center region MR. In this case, the information display area 47 is located near corner C2 (the corner region CR indicated by the dashed line in FIG. 4 ).

[0039] <Example 2 of information display area changes> The number of information display areas 47 is not limited to the example shown in FIG. 4 . Alternatively, an information display area 47 may be provided in the corner region CR near the corner C2, and an information display area 47 may be provided in the corner region CR near the corner C4. In this case, the number of information display areas 47 is two. Each of the two information display areas 47 includes the information display pattern PT1. Alternatively, each of the two information display areas 47 may include an information display pattern containing information that is reduced by half the amount of information in the information display pattern PT1.

[0040] <Example 3 of Information Display Area Change> In addition to the configuration of the information display area in Variation 2, a corner area CR may be provided near the corners C1 and C3. Specifically, the corner regions CR are located closer to each of the four corners C1 to C4 than the center region MR. There are four corner regions CR. An information display region 47 is provided in each of the four corner regions CR. Each of the four information display regions 47 has an information display pattern PT1. Alternatively, each of the four information display regions 47 may include an information display pattern containing information that is 1 / 4 less than the information display pattern PT1.

[0041] In the example shown in FIG. 4 and variations 1 to 3 of the information display area, the four corners C1 to C4 can also be referred to as the first corner, the second corner, the third corner, and the fourth corner. The four corner regions CR located closer to the four corners C1 to C4 than the central region MR may also be referred to as the first corner region, the second corner region, the third corner region, and the fourth corner region. The information display areas located in the first corner area, the second corner area, the third corner area, and the fourth corner area may also be referred to as the first information display area, the second information display area, the third information display area, and the fourth information display area, respectively. The information display patterns set in the first information display area, the second information display area, the third information display area, and the fourth information display area may also be referred to as the first information display pattern, the second information display pattern, the third information display pattern, and the fourth information display pattern, respectively.

[0042] <Information Display Pattern> FIG. 5 shows an example of the information display pattern PT1. The information display pattern PT1 is, for example, a well-known 2D code. The information display pattern PT1 is a code having information display modes in the Y direction and the X direction. In this embodiment, a well-known printing method is used to apply a coating material to the corner region CR of the second surface 41b. Thereby, an information display pattern PT1 is formed in the corner region CR. That is, the information display pattern PT1 of the first embodiment is formed of a coating material.

[0043] The information display pattern PT1 includes a plurality of first portions PE where the coating material exists and a plurality of second portions PN where the coating material does not exist. The information display pattern PT1 has a plurality of information display rows PA represented by a combination of a plurality of first portions PE and a plurality of second portions PN. A plurality of information display rows PA are arranged in the X direction and the Y direction intersecting the X direction. The information display pattern PT1 is 18×18 two-dimensional information.

[0044] The information thus displayed by the information display pattern PT1 is management information such as manufacturing history information related to the NAND memory 25 to which the additional information display pattern PT1 is attached. Specifically, the two-dimensional code includes, for example, 18-digit information. As the 18-digit information included in the two-dimensional code, for example, the following information can be cited. · The date when the NAND memory 25 was manufactured · The type of manufacturing apparatus used in the manufacturing process of the NAND memory 25 · The batch number of the manufacturing process of the NAND memory 25 For example, after the NAND memory 25 is shipped, consider the case where the NAND memory 25 has a defect. In this case, the defective NAND memory 25 is recovered and the two-dimensional code attached to the NAND memory 25 is referred to. Thereby, the management information of the defective NAND memory 25 can be obtained. Based on the obtained information, defect analysis such as the cause of the defect can be performed.

[0045] <Manufacturing method of NAND memory Next, the manufacturing method of the NAND memory 25 will be described.

[0046] The manufacturing method of the NAND memory 25 has the following steps of 1 to 9. (Step 1) Pretreatment process of semiconductor wafer (Step 2) Dicing of semiconductor wafer (Step 3) Mounting semiconductor memory chips on a large circuit board (Step 4) Wire bonding of large circuit board and semiconductor memory chips (Step 5) Applying a resin material to the large circuit board (Step 6) Formation of information display pattern on large circuit substrate (Step 7) Solder ball placement on large circuit boards (Step 8) Reflow processing of large circuit boards (Step 9) Cutting of large circuit boards

[0047] Next, the above steps 1 to 9 are explained in sequence. In addition, sometimes, variations are described in each of steps 1 to 9.

[0048] (Step 1: Pre-processing of semiconductor wafers) Pre-processing steps of semiconductor wafers include, for example, thermal oxidation, photoresist coating, exposure (patterning), etching, oxidation diffusion, film formation, ion implantation, planarization, and inspection.

[0049] (Step 2: Cutting of semiconductor wafers) The semiconductor wafer after the pre-processing process is cut into pieces, thereby obtaining a plurality of semiconductor memory chips 42 from the semiconductor wafer.

[0050] (Step 3: Mounting a semiconductor memory chip on a large circuit board) FIG6A is a top view showing a large circuit substrate 50. ... Fig. 7 is a cross-sectional view showing a portion of a large circuit board 50. Fig. 7 is a diagram illustrating a process of mounting a plurality of semiconductor memory chips 42 on the large circuit board 50.

[0051] A plurality of device areas 125 are allocated to a large circuit board 50. In the example shown in FIG6A , the large circuit board 50 has three area groups 50A, 50B, and 50C. Each of the three area groups 50A, 50B, and 50C has a plurality of device areas 125. In each area group, four device areas 125 are arranged in the X direction and five device areas 125 are arranged in the Y direction. In other words, 4×5 device areas 125 are allocated to each area group. In this case, the size of each of the plurality of device areas 125 is, for example, 12 mm in the Y direction and 18 mm in the X direction.

[0052] Each of the plurality of device regions 125 has a mutually independent wiring circuit. As will be described later, the device region 125 corresponds to the NAND memory 25 obtained by cutting the large circuit substrate 50 . 7 , a solid line is shown between two adjacent device regions 125. This portion is cut by a cutter when cutting the large circuit substrate 50.

[0053] As shown in FIG. 7 , the large circuit board 50 has a first main surface 51 and a second main surface 52 . On the first main surface 51 of the large circuit substrate 50 , a semiconductor memory chip 42 is mounted in each of the plurality of device regions 125 . As shown in FIG. 3 , when the NAND memory 25 includes a plurality of semiconductor memory chips 42 , a laminate having the plurality of semiconductor memory chips 42 stacked thereon is prepared in advance, and the laminate is mounted on each of the plurality of device regions 125 . A pad 146 , which will be described later, is formed on the second main surface 52 . On the second main surface 52 of the large circuit board 50, a solder resist is provided in the area where the plurality of pads 146 are not formed. The solder resist has a plurality of openings. In other words, the plurality of openings of the solder resist correspond to the plurality of pads 146.

[0054] (Variation of step 3) The configuration of the large circuit board 50 is not limited to the example shown in FIG. 6A . For example, the large circuit board 50 may also have two area groups 50A and 50B as shown in FIG6B . Each of the two area groups 50A and 50B includes a plurality of device regions 125 . In each area group, six device regions 125 are arranged in the X direction, and five device regions 125 are arranged in the Y direction. In other words, 6×5 device regions 125 are allocated to each area group. As described later, the device regions 125 correspond to the NAND memory cells 25 obtained by cutting the large circuit board 50 .

[0055] (Step 4: Wire bonding between the large circuit substrate and the semiconductor memory chip) Fig. 8 is a cross-sectional view showing a portion of a large circuit substrate 50. Fig. 8 is a diagram illustrating a process of wire bonding the large circuit substrate 50 and the plurality of semiconductor memory chips 42. Wire bonding is performed on the first main surface 51 of the large circuit substrate 50 . In each of the plurality of device regions 125 , each of the plurality of device regions 125 is connected to the semiconductor memory chip 42 by bonding wires 44 through wire bonding.

[0056] (Step 5: Applying resin material to the large circuit board) Fig. 9 is a cross-sectional view showing a portion of the large circuit board 50. Fig. 9 is a view for explaining the process of applying a resin material to the first main surface 51 of the large circuit board 50. The entire first main surface 51 of the large circuit board 50 is covered with resin material 143 so as to cover the plurality of device regions 125, the semiconductor memory chip 42, and the bonding wires 44. The resin material 143 is cured by a well-known method such as a drying process, a heat curing process, or an ultraviolet curing process.

[0057] The distance from the first main surface 51 to the upper surface of the resin material 143 , that is, the height of the resin material 143 in the Z direction on the first main surface 51 , corresponds to the thickness of the sealing resin portion 43 of the NAND memory 25 .

[0058] (Step 6: Formation of information display pattern on large circuit substrate) FIG10 is a cross-sectional view showing a portion of the large circuit board 50. FIG10 is a diagram illustrating the process of applying a coating material to the second main surface 52 of the large circuit board 50. The large circuit board 50 shown in FIG10 is in a posture that is the inversion of the posture of the large circuit board 50 shown in FIG9 in the Z direction.

[0059] On the second main surface 52 of the large circuit substrate 50 , an information display pattern PT1 is formed in the information display region 147 of each of the plurality of device regions 125 using a printing method. The material used to form the information display pattern PT1 is a coating material used to form the information display pattern PT1 by a well-known printing method. The coating material is, for example, ink containing pigments, dyes, solvents, etc.

[0060] In this embodiment, an inkjet method, a type of printing method, is used to form the information display pattern PT1 in the information display area 147. Specifically, as shown in Figure 10 , a droplet ejection device 152 having a discharge head 150 and a head moving mechanism 151 is used. The droplet ejection device 152 ejects ink from the discharge head 150 toward the information display area 147 while moving the head moving mechanism 151 in the X and Y directions. This forms the information display pattern PT1 in the information display area 147. After forming the information display pattern PT1, a drying process may be performed as needed. In addition, the information display area 147 corresponds to the information display area 47 of the NAND memory 25 obtained by cutting the large circuit substrate 50.

[0061] (Variation 1 of Step 6) As long as a two-dimensional code for management information of each of the plurality of device areas 125, that is, each of the plurality of NAND memories 25, can be formed, a printing method other than the inkjet method may be used. For example, a printing method using a master plate can also be used. In other words, a printing method using a master plate with a freely programmable print pattern corresponding to a two-dimensional code used for information management can also be used. This printing method is not limited to inkjet printing; flexographic printing, screen printing, gravure printing, offset printing, and other printing methods can also be used. Silk screen printing can be used.

[0062] (Variation 2 of Step 6) By using the same printing method with the same master plate, it is also possible to form a 2D code with the same pattern on multiple device areas 125. In this case, the 2D code with the same pattern is first formed on the multiple device areas 125. Then, a portion of the 2D code in each of the multiple device areas 125 is fine-tuned so that the 2D code in each of the multiple device areas 125 is different. This fine-tuning allows the 2D codes formed in the multiple device areas 125 to be different from each other. Thus, a 2D code for managing information can be formed on each of the multiple device areas 125, that is, each of the multiple NAND memories 25.

[0063] (Step 7: Solder ball placement on large circuit boards) Fig. 11 is a cross-sectional view showing a portion of the large circuit board 50. Fig. 11 is a diagram illustrating the process of placing solder balls 145 on the second main surface 52 of the large circuit board 50. The large circuit board 50 shown in Fig. 11 has the same posture as the large circuit board 50 shown in Fig. 10 . On the second main surface 52 of the large circuit substrate 50, a plurality of bonding pads 146 are formed in each of the plurality of device regions 125. The bonding pads 146 are exposed from the second main surface 52. The bonding pads 146 correspond to the bonding pads 46 of the NAND memory 25 obtained by cutting the large circuit substrate 50.

[0064] In step 7 , specifically, the plurality of solder balls 145 are disposed on the plurality of pads 146 using the chuck 160 and the solder base 161 .

[0065] 12A and 12B are schematic cross-sectional views showing a device used to arrange solder balls 145 on pads 146. FIG. FIG. 12A shows a collet 160 and a solder base 161 . Chuck 160 includes a vacuum drive unit 160M, a lower surface 160L, and a plurality of suction units 160S. Suction units 160S open on lower surface 160L. Suction units 160S communicate with vacuum drive unit 160M via piping provided within chuck 160. Chuck 160 is a rubber-like member that lifts solder balls 145 by vacuum suction.

[0066] The solder base 161 has a groove portion 162 on which the solder ball 145 is placed. The solder ball 145 is placed in advance in the groove portion 162 of the solder base 161.

[0067] The chuck 160 is lowered in the direction DW, bringing the lower surface 160L of the chuck 160 into contact with the solder balls 145. At this point, the vacuum drive 160M of the chuck 160 is actuated. The plurality of solder balls 145 are attracted one-to-one by the plurality of attracting portions 160S on the lower surface 160L of the chuck 160. Then, while the chuck 160 retains the plurality of solder balls 145, it is raised in the direction UP, separating the chuck 160 from the solder base 161.

[0068] Next, the chuck 160 holding the plurality of solder balls 145 is moved so that the chuck 160 faces the second main surface 52 of the large circuit board 50. The chuck 160 is lowered in the direction DW, so that the plurality of solder balls 145 held by the chuck 160 come into contact with the plurality of pads 146 one-to-one. At this point, the vacuum drive 160M of the chuck 160 is stopped. This releases the suction state (holding state) between the chuck 160 and the plurality of solder balls 145. Consequently, the plurality of solder balls 145 are placed on the plurality of pads 146 in each of the plurality of device areas 125 on the second main surface 52 of the large circuit board 50.

[0069] In this embodiment, step 6 of forming the information display pattern PT1 in the device region 125 is performed before step 7 of placing the solder balls 145 in the device region 125. This prevents ink from adhering to the solder balls 145. Consequently, poor electrical contact between the solder balls 145 and the pads 146 caused by ink adhering to the solder balls 145 can be prevented.

[0070] (Step 8: Reflow processing of large circuit boards) A well-known reflow oven is used to reflow (heat treatment) the large circuit board 50. The reflow temperature is, for example, approximately 240°C. This partially melts the solder balls 145 located on the pads 146 in each of the plurality of device regions 125. The solder balls 145 then become conductive members 45, which are bonded to the pads 146. In other words, the conductive members 45 have a shape that is deformed by the reflow process.

[0071] (Step 9: Cutting of large circuit boards) Using a well-known cutting device, the large circuit substrate 50 is cut into a plurality of NAND memory cells 25. Each of the plurality of NAND memory cells 25 has the structure shown in Figures 3 and 4. Subsequently, the plurality of NAND memory cells 25 undergoes testing, scanning, visual inspection, baking, and other processes before being mounted on the insulating base material 31 of the substrate 21 described above.

[0072] According to this embodiment, the information display area 47 can be formed on the second surface 41b of the circuit substrate 41 constituting the NAND memory 25. In addition, the information display pattern PT1 formed of a coating material can be formed in the information display area 47. Here, the effects of the present embodiment will be described by comparing the comparative example with the present embodiment.

[0073] The semiconductor package of the comparative example has a structure in which a semiconductor chip is covered by a sealing resin portion. Management information, namely a mark (information), is affixed to the semiconductor package of the comparative example. The mark is affixed to the semiconductor package of the comparative example by irradiating the surface of the sealing resin portion with laser light. In the semiconductor package of the comparative example, irradiating the surface of the sealing resin portion with laser light may damage the semiconductor chip covered by the sealing resin portion.

[0074] In the semiconductor package of the comparative example, in order to avoid damage to the semiconductor chip, it is considered to irradiate the laser light only to a specific area on the surface of the sealing resin portion so that the laser light irradiation position does not overlap with the semiconductor chip. However, when the area of ​​the semiconductor wafer is large, the area of ​​the region where the laser irradiation position and the semiconductor wafer do not overlap becomes smaller. Therefore, it is considered that the surface of the sealing resin portion cannot sufficiently ensure an area for adding a mark.

[0075] Furthermore, as another comparative example of a semiconductor package, in order to protect the semiconductor chip from the influence of laser light, it is also considered to increase the thickness of the sealing resin portion and to protect the semiconductor chip. However, in this case, the semiconductor package cannot be made thinner due to the increase in the thickness of the sealing resin portion.

[0076] In contrast, according to this embodiment, there is no need to irradiate the surface of the sealing resin portion 43 with laser light. Therefore, there is no damage to the semiconductor memory chip 42. This allows the thickness of the sealing resin portion 43 to be reduced, thereby reducing the thickness of the NAND memory 25. Since the position of the information display pattern PT1 is not limited to the surface of the sealing resin portion 43, the degree of freedom in designing the NAND memory 25 can be improved.

[0077] <Second embodiment> 13, the second embodiment will be described. In the second embodiment, the same reference numerals are used for the same components as those in the first embodiment, and their descriptions are omitted or simplified. FIG13 shows an example of an information display pattern PT2 of the second embodiment.

[0078] In the second embodiment, an information display pattern PT2 is provided instead of the information display pattern PT1 provided in the information display area 47 shown in FIG4. That is, the information display area 47 of the second embodiment has the information display pattern PT2 formed of the same conductive material as the conductive material constituting the conductive member 45. The second embodiment is different from the first embodiment in that a plurality of pads 46 are provided in the information display area 47. An information display pattern PT2 is formed depending on whether a conductive material is disposed on each of the plurality of pads 46.

[0079] <Information Display Pattern> The information display pattern PT2 is, for example, a well-known 2D code. The information display pattern PT2 is a code having information display modes in the Y direction and the X direction. The information display pattern PT2 is formed using a conductive material. The conductive material is solder. Specifically, in this embodiment, the conductive material is placed in the corner region CR of the second surface 41b through the solder ball placement and reflow process described in the first embodiment. This forms the information display pattern PT2 in the corner region CR. That is, the information display pattern PT2 of the second embodiment is formed of a conductive material. Like the information display pattern PT1, the information display pattern PT2 has management information related to each of the plurality of NAND memories 25 manufactured.

[0080] In FIG. 13, a white circular portion and a black circular portion are shown. The white circular portion shows that the conductive material is mounted on the pad 46. The black circular portion shows that the conductive material is not mounted on the pad 46. That is, in the black circular portion, the pad 46 is exposed. The pitch between two adjacent pads 46 can be appropriately adjusted. The pitch can be set to, for example, 60 μm. The diameter of the conductive material and the diameter of the pad 46 can be set to, for example, 30 μm.

[0081] The material of the pad 46 is copper. Therefore, the pad 46 has a red metallic luster. The material of the solder ball contains lead. Therefore, the color of the solder ball is gray. The colors of the pad 46 and the solder ball are different. Therefore, it can be used as a two-dimensional code. The pad 46 and the conductive material constituting the two-dimensional code are in an electrically floating state. The pad 46 is not connected to the wiring pattern inside the circuit board 41.

[0082] The information display pattern PT2 includes a plurality of first portions PE where the conductive material exists and a plurality of second portions PN where the conductive material does not exist. The information display pattern PT2 has a plurality of information display lines PA represented by the combination of the plurality of first portions PE and the plurality of second portions PN. A plurality of information display lines PA are arranged in the X direction and the Y direction intersecting the X direction. That is, in the present embodiment, a two-dimensional code is formed by the presence or absence of each of the plurality of conductive materials.

[0083] The position where the information display pattern PT2 is arranged is not limited to the information display area 47 shown in FIG. 4. The information display pattern PT2 can also be applied to replace the information display pattern PT1 of the variation examples 1-3 of the information display area described in the first embodiment.

[0084] <Manufacturing method of NAND memory> Next, a manufacturing method of the NAND memory 25 having the information display pattern PT2 will be described. The difference between the manufacturing method of the NAND memory 25 of the present embodiment and the manufacturing method of the first embodiment is that step 6 is not performed, and step 7A is performed instead of step 7. In the following description, the description of the steps common to steps 1 to 9 in the above first embodiment will be omitted.

[0085] First, steps 1 to 5 described above are sequentially performed. Thereby, the large circuit board 50 shown in FIG. 9 is obtained. Next, the following step 7A is performed.

[0086] (Step 7A: Solder Ball Arrangement on Large Circuit Board) In step 7A, the chuck 160 and solder base 161 shown in Figures 12A and 12B are used. As shown in Figure 11 , solder balls 145 are placed on pads 146 and in information display regions 147 of each of the plurality of device regions 125. Subsequently, solder balls 145 are partially removed in a manner corresponding to information display pattern PT2. Thereafter, steps 8 and 9 described above are performed.

[0087] <Variation 1 of Step 7A> The method of arranging the solder balls 145 in the information display area 147 is not limited to the above method. As a first variation of step 7A, the arrangement pattern of the solder balls 145 can also be formed by inkjet method. In this case, first, a large circuit board 50 is prepared in which the information display area 147 is covered with solder resist. Then, an inkjet device is prepared that can eject an etching solution from a nozzle head to remove the solder resist.

[0088] The inkjet head ejects an etching solution onto information display area 147 based on the pattern for placing solder balls 145, namely, information display pattern PT2. The etching solution partially removes information display area 147 based on information display pattern PT2. A cleaning step may also be performed as needed. This exposes solder pads 146 corresponding to information display pattern PT2 in information display area 147.

[0089] Then, similar to step 7A above, the solder balls 145 are placed on the pads 146 using the chuck 160. In this method, the solder balls 145 can also be placed on the pads 146 and in the information display regions 147 of each of the plurality of device regions 125.

[0090] <Variation 2 of Step 7A> The method for placing solder balls 145 in information display area 147 is not limited to the method described above. As a second variation of step 7A, a mask layer may be placed on pads 146 where solder balls 145 are not placed. A mask layer is used to prevent solder balls from being placed on specific pads. A mask layer may also be called a barrier layer.

[0091] In this method of forming a mask layer, for example, an inkjet device capable of dispensing a mask material for forming the mask layer is used. The inkjet device applies the mask material to the pads 146 according to a pattern where solder balls 145 are not arranged, thereby forming the mask layer. In other words, the inkjet device applies the mask material to the pads 146 according to a reverse pattern where the white and black circular portions of the information display pattern PT2 are inverted, thereby forming the mask layer. In this way, a mask layer is formed on the pads 146 where solder balls 145 are not arranged.

[0092] After forming the mask layer, the same process as step 7A is performed. Specifically, solder balls 145 are placed on pads 146 using chuck 160. In this method, solder balls 145 can also be placed on pads 146 and in the information display regions 147 of each of the plurality of device regions 125.

[0093] According to this embodiment, an information display area 47 can be formed on the second surface 41b of the circuit substrate 41 constituting the NAND memory 25. Furthermore, an information display pattern PT2 made of a conductive material can be formed in the information display area 47. Since the surface of the sealing resin portion 43 does not need to be irradiated with laser light, damage to the semiconductor wafer is avoided. This reduces the thickness of the sealing resin portion 43, thereby reducing the thickness of the NAND memory 25.

[0094] Furthermore, the conductive material that constitutes the information display pattern PT2 is solder, namely lead. Therefore, when X-rays are irradiated onto the NAND memory 25, the X-rays do not penetrate the areas where solder balls are placed, but penetrate areas where the conductive material is not placed. Therefore, the presence of conductive material, that is, the conductive material arrangement pattern, can be determined using X-rays. In other words, even after assembly is complete, the information display pattern PT2 can be read using X-rays.

[0095] Generally speaking, a semiconductor package has a plurality of conductive portions that are bonded to a substrate, which is a mounting object of the semiconductor package. When viewing the semiconductor package from above, the conductive portions at the four corners of the plurality of conductive portions serve as dummy bumps. According to this embodiment, at least a portion of the dummy bump can be used as the information display pattern PT2.

[0096] The plurality of conductive members 45 of the NAND memory 25 are used for signal input and output within the NAND memory 25. The information display pattern PT2 is a two-dimensional code used to manage information for each of the plurality of NAND memories 25. Therefore, the signal input and output terminals and the two-dimensional code can be formed in the same process.

[0097] According to this embodiment, the same or similar effects as those of the first embodiment can be obtained. In particular, since the position of the information display pattern PT2 is not limited to the surface of the sealing resin portion 43, the design freedom of the NAND memory 25 can be improved.

[0098] <Variations of the Second Embodiment> 14 to 17 , a variation of the second embodiment will be described. In the variation of the second embodiment, the same reference numerals are given to the same components as those in the first embodiment and the description thereof is omitted or simplified.

[0099] <Variation 1> Fig. 14 shows a first variation of the second embodiment. Fig. 14 is a bottom view showing the structure of the NAND memory 25. Fig. 14 can also be called a top view of the circuit board 41 viewed from the +Z direction. The second surface 41b of the circuit board 41 has a central region MR located in the center in the X and Y directions. The information display region 47 is located in the central region MR. The information display region 47 is provided with an information display pattern PT2. In the X and Y directions, the distance between the plurality of first portions PE and the plurality of second portions PN constituting the information display pattern PT2 is 1 / 2 of the distance between the plurality of conductive members 45. According to the first variation, the same or similar effects as those of the second embodiment can be obtained.

[0100] <Variation 2> Fig. 15 shows a second variation of the second embodiment. Fig. 15 is a bottom view showing the structure of the NAND memory 25. Fig. 15 can also be called a top view of the circuit board 41 viewed from the +Z direction. The second surface 41b includes a central region MR, a first side region SR1, and a second side region SR2. The central region MR is located at the center in the X and Y directions. The first side region SR1 is located closer to the side S4 than the central region MR. The second side region SR2 is located closer to the side S2 than the central region MR. The information display area 47 is located in each of the first side region SR1 and the second side region SR2. Each of the first side region SR1 and the second side region SR2 is an example of a "side region."

[0101] The first information display pattern PT2A is formed in the information display area 47 of the first side region SR1. The second information display pattern PT2B is formed in the information display area 47 of the second side region SR2. The two information display patterns, the first information display pattern PT2A and the second information display pattern PT2B, form the information display pattern PT2. In other words, the first side region SR1 and the second side region SR2 are arranged in symmetrical positions. In the X direction and the Y direction, the distance between the plurality of first portions PE and the plurality of second portions PN constituting each of the first information display pattern PT2A and the second information display pattern PT2B is 1 / 2 of the distance between the plurality of conductive members 45 . According to variation 2, the same or similar effects as those of the above-mentioned second embodiment can be obtained.

[0102] <Variation 3> Fig. 16 shows a third variation of the second embodiment. Fig. 16 is a bottom view showing the structure of the NAND memory 25. Fig. 16 can also be called a top view of the circuit board 41 viewed from the +Z direction. The second surface 41b of the circuit board 41 has a central extension region MRL located in the center in the X and Y directions. The central extension region MRL is an example of a central region. The central extension region MRL extends from the side portion S1 to the side portion S3. In other words, the central extension region MRL has a rectangular shape. The information display region 47 is located in the central extension region MRL. The information display pattern PT2 is provided in the information display region 47. In the X direction and the Y direction, the distance between the plurality of first portions PE and the plurality of second portions PN constituting the information display pattern PT2 is 1 / 2 of the distance between the plurality of conductive members 45 . According to variation 3, the same or similar effects as those of the above-mentioned second embodiment can be obtained.

[0103] <Variation 4> Fig. 17 shows a fourth variation of the second embodiment. Fig. 17 is a bottom view showing the structure of the NAND memory 25. Fig. 17 can also be called a top view of the circuit board 41 viewed from the +Z direction. The information display area 47 includes a first area 47F and a second area 47S. In FIG17 , the second area 47S is shown with hatching. The NAND memory 25 has a terminal region 48. The terminal region 48 is provided on the second surface 41b of the circuit substrate 41. A plurality of conductive members 45 are arranged in the terminal region 48.

[0104] The first region 47F is located at a different position from the plurality of conductive members 45. That is, the first region 47F is located at a different position from the terminal region 48. In other words, the first region 47F is located near the terminal region 48. The second region 47S is provided at a position overlapping with the plurality of conductive members 45. That is, the second region 47S is a region overlapping with the terminal region 48. A portion of the plurality of conductive members 45 is a portion of the plurality of first portions PE in the second region 47S. In the example shown in FIG17 , two conductive members 45 correspond to the first portions PE.

[0105] In other words, in the second region 47S, the conductive member 45 is the same as the first portion PE constituting the information display pattern PT2. Furthermore, the conductive member 45 forming part of the plurality of first portions PE is a heat dissipation portion for dissipating heat generated in the NAND memory 25. In other words, the conductive member 45 forming part of the plurality of first portions PE is a heat ball.

[0106] According to variation 4, the same or similar effects as those of the above-mentioned second embodiment can be obtained. Furthermore, a portion of the plurality of conductive members 45 is a portion of the plurality of first portions PE in the second region 47S. Therefore, the conductive member 45 and the information display pattern PT2 in the second region 47S can be made common. The conductive member 45 forming part of the plurality of first portions PE is a heat dissipation portion. Therefore, the heat generated in the NAND memory 25 can be dissipated.

[0107] In Variation 4, the two conductive members 45 correspond to the first portion PE. The number of common portions between the conductive member 45 and the first portion PE is not limited to two. The number of common portions may be one or three or more. In Variation 4, the common portion is located in the corner region forming the terminal region 48. However, the common portion may also be located in the linear region forming the terminal region 48. The linear region is, for example, a portion of a region extending in the X-direction or the Y-direction.

[0108] <Variations of the First and Second Embodiments> In the above embodiment, the structure of the NAND memory 25 having the information display area has been described. The structure applied to the NAND memory 25 can also be applied to the DRAM 26 or the controller 22.

[0109] Furthermore, in the above embodiment, the information display pattern is described as a 2D code. However, the above embodiment is not limited to a 2D code. The information display pattern may also be a 1D code, i.e., a barcode.

[0110] In the variations 1 to 3 of the second embodiment, the information display pattern PT2 is formed in the information display area 47. However, the information display pattern PT1 may be formed in the information display area 47 of the variations 1 to 3.

[0111] According to at least one embodiment described above, a semiconductor memory device comprises a circuit substrate, electronic components, a plurality of conductive members, and an information display area. The circuit substrate has a first surface and a second surface opposite the first surface. The electronic components are mounted on the first surface of the circuit substrate. The plurality of conductive members are arranged on the second surface of the circuit substrate. The plurality of conductive members are electrically connected to the circuit substrate. The plurality of conductive members are formed from a conductive material. The information display area is provided on the second surface of the circuit substrate. At least a portion of the information display area is provided at a position different from that of the plurality of conductive members. The information display area has an information display pattern formed from a coating material or a conductive material identical to the conductive material. This provides a semiconductor memory device that offers increased design freedom.

[0112] While several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments may be implemented in various other forms and may be omitted, replaced, or modified without departing from the spirit of the invention. These embodiments and their modifications, as long as they fall within the scope and spirit of the invention, are encompassed by the invention described in the claims and their equivalents. [References to related applications]

[0113] This application claims the benefit of priority from Japanese Patent Application No. 2023-043821 (filing date: March 20, 2023), the entire contents of which are hereby incorporated by reference into this application.

[0114] 1: Memory device 10: Shell 11: Component 1 12: Component 2 13:Fixed components 14: Circuit board 20: Baseboard unit 21:Substrate 21a: Page 1 21b: Side 2 21e1: End 1 21e2: Second end 22: Controller 23: Power conversion parts 24: Power circuit parts 25,25A~25H: NAND memory (semiconductor memory device) 26:DRAM (semiconductor memory device) 31: Insulation substrate 32: Solder pad 41: Circuit board 41a: Page 1 41b: Page 2 42: Semiconductor memory chip (electronic components) 43: Sealing resin part 44:Joint line 45: conductive component 46: pad 47: Information display area 47F: Area 1 47S: Area 2 48: Terminal area 50: Large circuit board 50A, 50B, 50C: Regional Group 51: 1st main side 52: 2nd main side 125: device area 143: Resin material 145:Solder ball 146: pad 147: Information display area 150: Spray head 151: Head moving mechanism 152: Droplet ejection device 160:Chuck 160L: bottom surface 160M: Vacuum drive unit 160S: Adsorption unit 161:Solder base 162: Groove C: Connector C1~C4: Corner CR: Corner Region MR: Central Region MRL: Central Extended Region (Central Region) PA: Information display line PE: Part 1 PN: Part 2 PT: Information display pattern PT1, PT2: Information display pattern PT2A: 1st information display pattern (information display pattern) PT2B: Second information display pattern (information display pattern) S1~S4: side SR1: 1st side region (side region) SR2: Second side area (side area) UP: Direction DW: direction< / dram>

Claims

1. A semiconductor memory device comprising: a circuit board having a first surface and a second surface located opposite to the first surface; an electronic component mounted on the first surface of the circuit board; a plurality of conductive members equally arranged on the second surface of the circuit board and electrically connected to the circuit board, formed of a conductive material; and an information display area disposed on the second surface of the circuit board; wherein the information display area has: an information display pattern formed of a coating material or a conductive material similar to the conductive material; and has: a first region disposed at a position different from the plurality of conductive members; and a second region disposed at a position overlapping with the plurality of conductive members; the information display pattern comprising: The device comprises a plurality of first portions having the aforementioned conductive material; and a plurality of second portions not having the aforementioned conductive material; and has a plurality of information display lines, which are represented by a combination of the plurality of first portions and the plurality of second portions; and the plurality of information display lines are arranged in a first direction and a second direction intersecting the first direction; a portion of the plurality of conductive members is a portion of the plurality of first portions in the second region.

2. The semiconductor memory device of claim 1, wherein the second surface is parallel to a first direction intersecting the thickness direction of the circuit substrate and a second direction intersecting both the thickness direction and the first direction; the circuit substrate has a plurality of corners; the second surface has: a central region located at the center of the first direction and the second direction; and a corner region located near one of the plurality of corners, closer to the central region; the information display area is located in the corner region.

3. The semiconductor memory device of claim 1, wherein the second surface is parallel to a first direction intersecting the thickness direction of the circuit substrate and a second direction intersecting both the thickness direction and the first direction; the second surface has a central region located at the center of the first direction and the second direction; and the information display area is located in the central region.

4. The semiconductor memory device of claim 1, wherein the second surface is parallel to a first direction intersecting the thickness direction of the circuit substrate and a second direction intersecting both the thickness direction and the first direction; the circuit substrate has a plurality of corners and a side portion located between two adjacent corners among the plurality of corners; the second surface has: a central region located at the center of the first direction and the second direction; and a side region located closer to the side portion than the central region; the information display area is located in the side region.

5. The semiconductor memory device of claim 1, wherein the conductive member forming a portion of one of the plurality of first portions is a heat sink.

6. The semiconductor memory device of claim 1, wherein the plurality of conductive members are electrical connection terminals exposed from the second surface of the circuit board.

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