System for analog neural memory in a deep learning artificial neural network

Abstract

Numerous specific examples are disclosed for splitting a physical array into multiple arrays for individual vector matrix multiplication (VMM) operations. In one embodiment, a system includes: a nonvolatile memory cell array configured in columns and rows; and a plurality of sets of output lines, wherein each row contains one set of output lines; wherein each column is coupled to only one output line in the set of output lines of each row.

Description

Technical Field

[0001] [Priority Statement]

[0002] This patent application claims priority to U.S. patent application No. 18 / 125,703, filed on March 23, 2023, and entitled “Split Array Architecture for Analog Neural Memory in a Deep Learning Artificial Neural Network,” which is a continuation-in-part of U.S. patent application No. 17 / 461,901, filed on August 30, 2021, and entitled “Split Array Architecture for Analog Neural Memory in a Deep Learning Artificial Neural Network,” which claims priority to U.S. Provisional Patent Application No. 63 / 190,228, filed on May 18, 2021, and entitled “Split Array Architecture for Analog Neural Memory in a Deep Learning Artificial Neural Network.”

[0003] Numerous embodiments are disclosed for splitting a physical array into multiple arrays for performing separate vector-matrix multiplication (VMM) operations by providing more than one output line per row in the physical array, which allows multiple sets of columns in the same row to be accessed simultaneously, with different sets of columns being assigned to different arrays for VMM operations. Prior Art

[0004] Artificial neural networks (ANNs) mimic biological neural networks (the central nervous system of animals, specifically the brain) and are used to estimate or approximate functions that may depend on a large number of inputs and are usually unknown. ANNs generally consist of layers of interconnected "neurons" that exchange messages with each other.

[0005] Figure 1 illustrates an artificial neural network, where circles represent inputs or layers of neurons. Connections (called synapses) are represented by arrows and have numerical weights that can be tuned based on experience. This allows the neural network to adapt to the input and learn. Typically, a neural network consists of a layer with multiple inputs. There are usually one or more layers of intermediate neurons and a layer of output neurons that provide the neural network's output. Neurons at each layer make decisions individually or collectively based on the data received from synapses.

[0006] One of the major challenges in developing artificial neural networks for high-performance information processing is the lack of appropriate hardware technology. Practical neural networks rely on a large number of synapses to achieve a high degree of connectivity between neurons, which in turn requires extremely high computational parallelism. In principle, this complexity could be achieved using digital supercomputers or clusters of specialized graphics processing units. However, in addition to high cost, these approaches also suffer from moderate energy efficiency compared to biological networks, primarily because biological networks perform low-precision analog computations and therefore consume much less energy. CMOS analog circuits have been used in artificial neural networks, but given the large number of neurons and synapses, the synapses in most CMOS implementations are too large.

[0007] Applicant previously disclosed in U.S. patent application Ser. No. 15 / 594,439, incorporated by reference, an artificial (analog) neural network utilizing one or more non-volatile memory arrays as synapses. The non-volatile memory array serves as an analog neuromorphic memory. The neural network component includes: a first plurality of synapses configured to receive a first plurality of inputs and generate a first plurality of outputs from the first plurality of inputs; and a first plurality of neurons configured to receive the first plurality of outputs. The first plurality of synapses includes a plurality of memory cells, wherein each of the memory cells includes: a source region and a drain region formed in a semiconductor substrate, spaced apart, with a channel region extending between the source region and the drain region; a floating gate disposed over and insulated from a first portion of the channel region; and a non-floating gate disposed over and insulated from a second portion of the channel region. Each of the plurality of memory cells is configured to store a weight value corresponding to the number of electrons on the floating gate. The plurality of memory cells are configured to multiply a first plurality of inputs by the stored weight value to generate a first plurality of outputs. Non-volatile memory cells

[0008] Non-volatile memory is well known. For example, U.S. Patent No. 5,029,130 ​​(the "'130 patent"), incorporated herein by reference, discloses an array of split-gate non-volatile memory cells, a type of flash memory cell. Such a memory cell 210 is shown in FIG. Each memory cell 210 includes a source region 14 and a drain region 16 formed in a semiconductor substrate 12, with a channel region 18 located between the source and drain regions. A floating gate 20 is formed over and insulated from (and controls the conductivity of) a first portion of the channel region 18, and is also formed over a portion of the source region 14. A wordline terminal 22 (typically coupled to a wordline) has a first portion disposed over and insulated from (and controls the conductivity of) a second portion of the channel region 18, and a second portion extending upward and past the floating gate 20. The floating gate 20 and the word line terminal 22 are insulated from the substrate 12 by a gate oxide. The bit line 24 is coupled to the drain region 16.

[0009] The memory cell 210 is erased (where electrons are removed from the floating gate) by placing a high positive voltage on the wordline terminal 22 , which causes the electrons on the floating gate 20 to tunnel from the floating gate 20 to the wordline terminal 22 through the intermediate insulating member via FN tunneling.

[0010] Memory cell 210 is programmed using source-side injection (SSI) of hot electrons (where electrons are placed on the floating gate) by applying a positive voltage to wordline terminal 22 and a positive voltage to source region 14. Electrons flow from drain region 16 toward source region 14. When the electrons reach the gap between wordline terminal 22 and floating gate 20, they accelerate and heat up. Some of the heated electrons are injected through the gate oxide onto floating gate 20 due to the attractive electrostatic force from floating gate 20.

[0011] Memory cell 210 is read by applying a positive read voltage to drain region 16 and wordline terminal 22 (this turns on the portion of channel region 18 below the wordline terminal). If floating gate 20 is positively charged (i.e., electrons are erased), the portion of channel region 18 below floating gate 20 is also turned on, and current will flow through channel region 18, which is sensed as an erased or "1" state. If floating gate 20 is negatively charged (i.e., programmed with electrons), the portion of the channel region below floating gate 20 is mostly or completely off, and no current (or very little current) will flow through channel region 18, which is sensed as a programmed or "0" state.

[0012] Table 1 describes typical voltage and current ranges that may be applied to the terminals of the memory cell 110 for performing read, erase, and program operations: Table 1: Operations of the flash memory cell 210 in FIG. 3 WL BL SL Read 2 to 3 V 0.6 to 2 V 0 V Erase About 11 to 13 V 0 V 0 V Programming 1 to 2 V 10.5 to 3 μA 9 to 10 V

[0013] Other split-gate memory cell configurations for other types of flash memory cells are known. For example, FIG3 depicts a quad-gate memory cell 310 comprising a source region 14, a drain region 16, a floating gate 20 above a first portion of a channel region 18, a select gate 22 (typically coupled to a word line WL) above a second portion of the channel region 18, a control gate 28 above the floating gate 20, and an erase gate 30 above the source region 14. This configuration is described in U.S. Patent 6,747,310, which is incorporated herein by reference for all purposes. Here, except for floating gate 20, all gates are non-floating, meaning they are electrically connected or connectable to a voltage source. Programming is performed by heated electrons from the channel region 18 injecting themselves onto the floating gate 20. Erasing is performed by electron tunneling from the floating gate 20 to the erase gate 30 .

[0014] Table 2 describes typical voltage and current ranges that may be applied to the terminals of the memory cell 310 for performing read, erase, and program operations: Table 2: Operations of the flash memory cell 310 in FIG. 3 WL / SG BL CG EG SL Read 1.0 to 2 V 0.6 to 2 V 0 to 2.6 V 0 to 2.6 V 0 V Erase -0.5 V / 0 V 0 V 0 V / -8 V 8 to 12 V 0 V Programming 1 V 0.1 to 1 μA 8 to 11 V 4.5 to 9 V 4.5 to 5 V

[0015] Figure 4 depicts a tri-gate memory cell 410, another type of flash memory cell. Memory cell 410 is identical to memory cell 310 of Figure 3, except that memory cell 410 does not have a separate control gate. Erase operations (in which erase is performed using the erase gate) and read operations are similar to those of Figure 3, except that no control gate bias is applied. Programming operations are also performed without a control gate bias, and therefore, a higher voltage is applied to the source line during programming operations to compensate for the lack of a control gate bias.

[0016] Table 3 describes typical voltage and current ranges that may be applied to the terminals of the memory cell 410 for performing read, erase, and program operations: Table 3: Operations of the flash memory cell 410 of FIG. 4 WL / SG BL EG SL Read 0.7 to 2.2 V 0.6 to 2 V 0 to 2.6 V 0 V Erase -0.5 V / 0 V 0 V 11.5 V 0 V Programming 1 V 0.2 to 3 μA 4.5 V 7 to 9 V

[0017] FIG5 depicts a stacked-gate memory cell 510, another type of flash memory cell. Memory cell 510 is similar to memory cell 210 of FIG2 , except that floating gate 20 extends entirely over channel region 18, and control gate 22 (which will be coupled to the word line here) extends over floating gate 20, separated from the control gate by an insulating layer (not shown). Erasing is performed by FN tunneling of electrons from the FG to the substrate, while programming is performed by channel hot electron (CHE) injection in the region between channel region 18 and drain region 16, with electrons flowing from source region 14 toward drain region 16. Reading is similar to the read operation for memory cell 210 with a higher control gate voltage.

[0018] Table 4 describes typical voltage ranges that may be applied to the terminals of the memory cell 510 and the substrate 12 for performing read, erase, and program operations: Table 4: Operations of the flash memory cell 510 in FIG. 5 CG BL SL substrate Read 2 to 5 V 0.6 to 2 V 0 V 0 V Erase -8 to -10 V / 0 V FLT FLT 8 to 10 V / 15 to 20 V Programming 8 to 12 V 3 to 5 V 0 V 0 V

[0019] The methods and approaches described herein can be applied to other non-volatile memory technologies, such as, but not limited to, FINFET split-gate flash or stacked-gate flash, NAND flash, silicon-oxide-nitride-oxide-silicon (SONOS, charge trap in nitride), metal-oxide-nitride-oxide-silicon (MONOS, metal charge trap in nitride), resistive RAM (ReRAM), phase-change memory (PCM), magnetic RAM (MRAM), ferroelectric RAM (FeRAM), charge trap (CT) memory, carbon tube (CN) memory, dual-level or multi-level one-time programmable (OTP) and correlated electron RAM (CeRAM).

[0020] To utilize a memory array containing one of the non-volatile memory cell types described above in artificial neural networks, two modifications are made. First, the lines are configured so that each memory cell can be individually programmed, erased, and read without adversely affecting the memory state of other memory cells in the array, as explained further below. Second, serial (analog) programming of the memory cells is provided.

[0021] Specifically, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be independently and continuously changed from a fully erased state to a fully programmed state with minimal disruption to other memory cells. In another embodiment, the memory state (i.e., the charge on the floating gate) of each memory cell in the array can be independently and continuously changed from a fully programmed state to a fully erased state, and vice versa, with minimal disruption to other memory cells. This means that the cell memory is analog, or at least can store one of many discrete values ​​(e.g., 16 or 64 different values), which allows for extremely precise and individual tuning of all cells in the memory array, making the memory array ideal for storing and fine-tuning the synaptic weights of neural networks. Neural network using non-volatile memory cell array

[0022] FIG6 conceptually illustrates a non-limiting embodiment of a neural network utilizing a non-volatile memory array according to an embodiment of the present invention. This embodiment uses a non-volatile memory array neural network for a facial recognition application, but any other suitable application may be implemented using a non-volatile memory array-based neural network.

[0023] S0 is the input layer, which for this embodiment is a 32×32 pixel RGB image with 5-bit precision (i.e., three 32×32 pixel arrays, one for each color R, G, and B, with 5-bit precision per pixel). Synapse CB1 entering layer C1 from input layer S0 applies different sets of weights in some cases and shares weights in others, and scans the input image with a 3×3 pixel overlapping filter (kernel), shifting the filter by 1 pixel (or more than 1 pixel, as dictated by the model). Specifically, the values ​​of 9 pixels in the 3×3 portion of the image (i.e., called the filter or kernel) are provided to synapse CB1, where these 9 input values ​​are multiplied by the appropriate weights. After summing the outputs of these multiplications, a single output value is determined by the first synapse CB1 and provided for use in generating a pixel in one of the feature maps of layer C1. The 3×3 filter is then shifted right by one pixel within input layer S0 (i.e., a row of three pixels is added to the right and a row of three pixels is dropped to the left). The nine pixel values ​​in this newly positioned filter are then provided to synapse CB1, where they are multiplied by the same weights and a second single output value is determined by connecting the synapses. This process continues for all three colors and for all bits (precision values) until the 3×3 filter has swept through the entire 32×32 pixel image of input layer S0. The process is then repeated using different sets of weights to generate different feature maps for layer C1 until all feature maps for layer C1 have been calculated.

[0024] In this embodiment, layer C1 contains 16 feature maps, each with 30×30 pixels. Each pixel is a new feature pixel extracted by multiplying the input by the kernel, and each feature map is therefore a two-dimensional array. Therefore, in this embodiment, layer C1 comprises 16 layers of a two-dimensional array (it should be noted that the terms layer and array are logically related, not necessarily physically related; that is, the arrays are not necessarily oriented in a physical two-dimensional array). Each of the 16 feature maps in layer C1 is generated by one of sixteen different sets of synaptic weights applied to the filter scans. The C1 feature maps can each address different aspects of the same image feature, such as edge recognition. For example, a first map (generated using a first set of weights, common to all scans used to generate this first map) can identify circular edges, while a second map (generated using a second set of weights, different from the first) can identify rectangular edges, or the aspect ratios of certain features.

[0025] Before entering layer S1 from layer C1, activation function P1 (pooling) is applied. This pooling function pools values ​​from consecutive, non-overlapping 2×2 regions within each feature map. The purpose of pooling function P1 is to average nearby locations (or alternatively, a maximum function can be used), for example, to reduce dependencies at edge locations and reduce data size before entering the next stage. At layer S1, there are 16 15×15 feature maps (i.e., each with a different array of sixteen 15×15 pixels). Synapse CB2, entering layer C2 from layer S1, scans the map in S1 using a 4×4 filter with a filter shift of 1 pixel. At layer C2, there are 22 12×12 feature maps. Before entering layer S2 from layer C2, activation function P2 (pooling) is applied. This pooling function pools values ​​from consecutive, non-overlapping 2×2 regions within each feature map. At layer S2, there are 22 6×6 feature maps. An activation function (pooling) is applied at synapse CB3 from layer S2 into layer C3, where each neuron in layer C3 is connected to each graph in layer S2 via a respective synapse CB3. Layer C3 has 64 neurons. Synapse CB4 from layer C3 into output layer S3 fully connects C3 to S3, meaning that every neuron in layer C3 is connected to every neuron in layer S3. The output from layer S3 consists of 10 neurons, with the highest output neuron determining the class. This output can, for example, indicate the recognition or classification of the content of the original image.

[0026] Each synaptic layer is implemented using an array or portion of an array of non-volatile memory cells.

[0027] Figure 7 is a block diagram of an array that can be used for this purpose. The vector-matrix multiplication (VMM) array 32 includes non-volatile memory cells and serves as the synapse between one layer and the next (such as CB1, CB2, CB3, and CB4 in Figure 6). Specifically, the VMM array 32 includes a non-volatile memory cell array 33, an erase gate and wordline gate decoder 34, a control gate decoder 35, a bitline decoder 36, and a source line decoder 37. These decoders decode the respective inputs of the non-volatile memory cell array 33. The inputs to the VMM array 32 can come from either the erase gate and wordline gate decoder 34 or the control gate decoder 35. In this embodiment, the source line decoder 37 also decodes the output of the non-volatile memory cell array 33. Alternatively, the bitline decoder 36 can decode the output of the non-volatile memory cell array 33.

[0028] Non-volatile memory cell array 33 serves two purposes. First, it stores weights to be used by VMM array 32. Second, non-volatile memory cell array 33 efficiently multiplies inputs by the weights stored in non-volatile memory cell array 33 and adds the results along an output line (source line or bit line) to produce an output, which will be the input to the next layer or the final layer. By performing multiplication and addition functions, non-volatile memory cell array 33 eliminates the need for separate multiplication and addition logic circuits and is also power-efficient due to its in-memory computation.

[0029] The output of the non-volatile memory cell array 33 is supplied to a differential summer (such as a summing operational amplifier or a summing current mirror) 38, which sums the output of the non-volatile memory cell array 33 to produce a single value for the convolution. The differential summer 38 is configured to perform the summation of positive and negative weights.

[0030] The total output value of the differential summer 38 is then supplied to the activation function block 39, which modifies the output. The activation function block 39 can provide a sigmoid, hyperbolic tangent (tanh), or Reluctant Unified Unit (ReLU) function. The modified output value of the activation function block 39 becomes an element of the feature map of the next layer (e.g., C1 in FIG6 ) and is then applied to the next synapse to generate the next feature map layer or the final layer. Therefore, in this embodiment, the non-volatile memory cell array 33 constitutes a plurality of synapses (which receive their inputs from the previous neuron layer or from an input layer such as an image database), and the summing operational amplifier 38 and activation function block 39 constitute a plurality of neurons.

[0031] The inputs (WLx, EGx, CGx, and optionally BLx and SLx) to the VMM array 32 in FIG. 7 can be analog levels, binary levels, or digital bits (in which case the DACs are configured to convert the digital bits to the appropriate input analog levels), and the outputs can be analog levels, binary levels, or digital bits (in which case the output ADCs are configured to convert the output analog levels to digital bits).

[0032] FIG8 is a block diagram illustrating the use of various layers of VMM array 32, here labeled VMM arrays 32a, 32b, 32c, 32d, and 32e. As shown in FIG8 , the input, designated Inputx, is converted from digital to analog by digital-to-analog converter 31 and provided to input VMM array 32a. The converted analog input can be either voltage or current. The first layer of input D / A conversion can be performed using a function or lookup table (LUT) that maps the input Inputx to the appropriate analog levels for the matrix multipliers of input VMM array 32a. Input conversion can also be performed using an analog-to-analog (A / A) converter to convert external analog inputs to mapped analog inputs for input VMM array 32a.

[0033] The output generated by input VMM array 32a is set as the input to the next VMM array (hidden layer 1) 32b, which in turn generates an output, which is set as the input to the next VMM array (hidden layer 2) 32c, and so on. The various layers of VMM array 32 serve as different synaptic and neuron layers of a convolutional neural network (CNN). Each VMM array 32a, 32b, 32c, 32d, and 32e can be a separate physical non-volatile memory array, or multiple VMM arrays can utilize different portions of the same physical non-volatile memory array, or multiple VMM arrays can utilize overlapping portions of the same physical non-volatile memory array. The embodiment shown in FIG8 contains five layers (32a, 32b, 32c, 32d, 32e): an input layer (32a), two hidden layers (32b, 32c), and two fully connected layers (32d, 32e). One of ordinary skill in the art will appreciate that this is merely illustrative and that the system may alternatively include more than two hidden layers and more than two fully connected layers. Vector-Matrix Multiplication (VMM) Array

[0034] FIG9 depicts a neuron VMM array 900, which is particularly suitable for memory cells 310 shown in FIG3 and serves as the synapse-to-neuron portion between the input layer and the next layer. VMM array 900 includes a memory array 901 of non-volatile memory cells and a reference array 902 of non-volatile reference memory cells (at the top of the array). Alternatively, another reference array can be placed at the bottom.

[0035] In VMM array 900, control gate lines, such as control gate line 903, run vertically (thus, reference array 902 in the column direction is orthogonal to control gate line 903), and erase gate lines, such as erase gate line 904, run horizontally. Inputs to VMM array 900 are provided on control gate lines (CG0, CG1, CG2, CG3), and outputs from VMM array 900 appear on source lines (SL0, SL1). In one embodiment, only even-numbered columns are used, and in another embodiment, only odd-numbered columns are used. The current placed on each source line (SL0, SL1, respectively) performs a summation function on all currents from the memory cells connected to that particular source line.

[0036] As described herein for the neural network, the non-volatile memory cells of the VMM array 900, ie, the memory cells 310 of the VMM array 900, may preferably be configured to operate in the sub-threshold region.

[0037] The non-volatile reference memory cell and the non-volatile memory cells described herein are biased in a weak inversion region (sub-threshold region): Ids = Io * e (Vg- Vth) / nVt= w * Io * e (Vg) / nVt, where w = e (- Vth) / nVt Where Ids is the drain-to-source current; Vg is the gate voltage on the memory cell; Vth is the threshold voltage of the memory cell; Vt is the thermal voltage = k*T / q, where k is the Boltzmann constant, T is the temperature in kelvins, and q is the electron charge; n is the slope factor = 1 + (Cdep / Cox), where Cdep = the capacitance of the depletion layer and Cox is the capacitance of the gate oxide layer; Io is the memory cell current at a gate voltage equal to the threshold voltage, and Io is proportional to (Wt / L)*u*Cox* (n-1) * Vt², where u is the carrier mobility of the memory cell, and Wt and L are the width and length of the memory cell, respectively.

[0038] For I to V logarithmic converters that use memory cells (such as reference memory cells or peripheral memory cells) or transistors to convert input current to input voltage: Vg= n*Vt*log [Ids / wp*Io] Here, wp is the reference or peripheral memory cell w.

[0039] For a memory array used as a vector matrix multiplier VMM array with current input, the output current is: Iout = wa * Io * e (Vg) / nVt, that is Iout = (wa / wp) * Iin = W * Iin W = e (Vthp - Vtha) / nVt Here, wa = w of each memory cell in the memory array. Vthp is the effective threshold voltage of the peripheral memory cell, and Vtha is the effective threshold voltage of the main (data) memory cell. It should be noted that the transistor's threshold voltage is a function of the substrate bulk bias voltage, and the substrate bulk bias voltage, represented as Vsb, can be adjusted to compensate for various conditions at this temperature. The threshold voltage Vth can be expressed as: Vth = Vth0 + γ (SQRT |Vsb - 2*φF) - SQRT |2* φF |) where Vth0 is the threshold voltage with zero substrate bias, φF is the surface potential, and γ is the body effect parameter.

[0040] The word line or control gate may serve as the input of the memory cell for the input voltage.

[0041] Alternatively, the flash memory cells of the VMM array described herein may be configured to operate in the linear region: Ids = β* (Vgs-Vth)*Vds;β = u*Cox*Wt / L W = α (Vgs-Vth) This means that the weight W in the linear region is proportional to (Vgs-Vth).

[0042] The word line or control gate or bit line or source line can be used as the input of the memory cell operating in the linear region. The bit line or source line can be used as the output of the memory cell.

[0043] For an I-to-V linear converter, a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor operating in a linear region may be used to linearly convert an input / output current to an input / output voltage.

[0044] Alternatively, the memory cells of the VMM array described herein may be configured to operate in the saturation region: Ids = ½ * β* (Vgs-Vth) 2;β = u*Cox*Wt / L Wα (Vgs-Vth) 2, which means that the weight W is proportional to (Vgs-Vth) 2.

[0045] The word line, control gate, or erase gate can be used as the input of a memory cell operating in the saturation region. The bit line or source line can be used as the output of an output neuron.

[0046] Alternatively, the memory cells of the VMM array described herein may be used in all regions or combinations thereof (subthreshold, linear, or saturation regions) of each or multiple layers of a neural network.

[0047] Other embodiments of the VMM array 32 of Figure 7 are described in U.S. Patent Application No. 15 / 826,345, which is incorporated herein by reference. As described in that application, source lines or bit lines can be used as neuron outputs (current summing outputs).

[0048] FIG10 illustrates a neuron VMM array 1000, which is particularly well-suited for memory cells 210 shown in FIG2 and serves as a synapse between the input layer and the next layer. VMM array 1000 includes a memory array 1003 of non-volatile memory cells, a reference array 1001 of first non-volatile reference memory cells, and a reference array 1002 of second non-volatile reference memory cells. Reference arrays 1001 and 1002, arranged in the row direction of the array, are used to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs WL0, WL1, WL2, and WL3. In practice, the first and second non-volatile reference memory cells are diode-connected through multiplexers 1014 (only partially illustrated), into which the current inputs flow. The reference cells are calibrated (e.g., programmed) to a target reference level. The target reference level is provided by a reference mini-array matrix (not shown).

[0049] Memory array 1003 serves two purposes. First, it stores weights to be used by VMM array 1000 on its individual memory cells. Second, memory array 1003 effectively multiplies inputs (i.e., current inputs provided at terminals BLR0, BLR1, BLR2, and BLR3, which are converted by reference arrays 1001 and 1002 into input voltages supplied to word lines WL0, WL1, WL2, and WL3) by the weights stored in memory array 1003, and then sums all the results (memory cell currents) to produce outputs on individual bit lines (BL0 to BLN), which will be inputs to the next layer or to the final layer. By performing multiplication and addition functions, memory array 1003 eliminates the need for separate multiplication and addition logic circuits and is also power-efficient. Here, voltage inputs are provided on word lines WL0, WL1, WL2, and WL3, and outputs appear on respective bit lines BL0 through BLN during a read (inference) operation. The current placed on each of the bit lines BL0 through BLN performs a summing function of the currents from all non-volatile memory cells connected to that particular bit line.

[0050] Table 5 describes the operating voltages and currents for VMM array 1000. The rows in the table indicate the voltages applied to the word line for a selected cell, the word line for unselected cells, the bit line for a selected cell, the bit line for unselected cells, the source line for a selected cell, and the source line for unselected cells. The columns indicate read, erase, and program operations. Table 5: Operations of the VMM array 1000 of FIG. 10: WL WL-Not Selected BL BL-Not selected SL SL-Not Selected Read 1 to 3.5 V -0.5 V / 0 V 0.6 to 2 V (Ineuron) 0.6 V to 2 V / 0 V 0 V 0 V Erase About 5 to 13 V 0 V 0 V 0 V 0 V 0 V Programming 1 to 2 V -0.5 V / 0 V 0.1 to 3 μA Vinh about 2.5 V 4 to 10 V 0 to 1 V / FLT

[0051] FIG11 depicts a neuron VMM array 1100, which is particularly well-suited for memory cells 210 shown in FIG2 and serves as the synaptic link between the input layer and the next layer. VMM array 1100 includes a memory array 1103 of nonvolatile memory cells, a reference array 1101 of first nonvolatile reference memory cells, and a reference array 1102 of second nonvolatile reference memory cells. Reference arrays 1101 and 1102 run in the column direction of VMM array 1100. VMM array 1100 is similar to VMM 1000, except that in VMM array 1100, word lines run vertically. Here, inputs are provided on word lines (WLA0, WLB0, WLA1, WLB1, WLA2, WLB2, WLA3, WLB3), and outputs appear on source lines (SL0, SL1) during a read operation. The current placed on each source line performs a summing function on all currents from the memory cells connected to that particular source line.

[0052] Table 6 describes the operating voltages and currents for VMM array 1100. The rows in the table indicate the voltages applied to the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The columns indicate read, erase, and program operations. Table 6: Operations of the VMM array 1100 of FIG. 11 WL WL-Not Selected BL BL-Not selected SL SL-Not Selected Read 1 to 3.5 V -0.5 V / 0 V 0.6 to 2 V 0.6 V to 2 V / 0 V About 0.3 to 1 V (Ineuron) 0 V Erase About 5 to 13 V 0 V 0 V 0 V 0 V SL-Suppression (approximately 4 to 8 V) Programming 1 to 2 V -0.5 V / 0 V 0.1 to 3 μA Vinh about 2.5 V 4 to 10 V 0 to 1V / FLT

[0053] FIG12 illustrates a neuron VMM array 1200, which is particularly suitable for memory cell 310 shown in FIG3 and serves as the synaptic interface between the input layer and the next layer. VMM array 1200 includes a memory array 1203 of nonvolatile memory cells, a reference array 1201 of first nonvolatile reference memory cells, and a reference array 1202 of second nonvolatile reference memory cells. Reference arrays 1201 and 1202 are used to convert current inputs flowing into terminals BLR0, BLR1, BLR2, and BLR3 into voltage inputs CG0, CG1, CG2, and CG3. In practice, the first and second nonvolatile reference memory cells are diode-connected through multiplexers 1212 (only partially shown), with current inputs flowing into these multiplexers via BLR0, BLR1, BLR2, and BLR3. Multiplexers 1212 each include a respective multiplexer 1205 and a cascaded transistor 1204 to ensure a constant voltage on the bit line (such as BLR0) of each of the first and second non-volatile reference memory cells during a read operation. The reference cells are tuned to a target reference level.

[0054] Memory array 1203 serves two purposes. First, it stores weights to be used by VMM array 1200. Second, memory array 1203 effectively multiplies inputs (current inputs provided to terminals BLR0, BLR1, BLR2, and BLR3, which reference arrays 1201 and 1202 convert into input voltages for supply to control gates (CG0, CG1, CG2, and CG3)) by the weights stored in the memory array. All results (cell currents) are then summed to produce an output, which appears on BL0 through BLN and will be the input to the next layer or the final layer. By performing multiplication and addition functions, the memory array eliminates the need for separate multiplication and addition logic circuits and is also power-efficient. Here, the inputs are provided on the control gate lines (CG0, CG1, CG2, and CG3), and the outputs appear on the bit lines (BL0 through BLN) during a read operation. The current placed on each bit line performs a summing function on all currents from the memory cells connected to that particular bit line.

[0055] VMM array 1200 performs unidirectional tuning for the non-volatile memory cells in memory array 1203. That is, each non-volatile memory cell is erased and then partially programmed until the desired charge on the floating gate is reached. If excessive charge is placed on the floating gate (causing an incorrect value to be stored in the cell), the sequence of cell erase and partial programming operations begins again. As shown, two rows sharing the same erase gate (e.g., EG0 or EG1) are erased together (this is called a page erase), and then each cell is partially programmed until the desired charge on the floating gate is reached.

[0056] Table 7 describes the operating voltages and currents for VMM array 1200. The rows in the table indicate the voltages applied to the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the control gate for a selected cell, the control gate for an unselected cell in the same sector as the selected cell, the control gate for an unselected cell in a different sector from the selected cell, the erase gate for a selected cell, the erase gate for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The columns indicate read, erase, and program operations. Table 7: Operations of the VMM array 1200 of FIG. 12 WL WL-Not Selected BL BL-Not selected CG CG-Same sector not selected CG-not Selected EG EG-Not Selected SL SL-Not yet Selected Read 1.0 to 2 V -0.5 V / 0 V 0.6 to 2 V (Ineuron) 0 V 0 to 2.6 V 0 to 2.6 V 0 to 2.6 V 0 to 2.6 V 0 to 2.6 V 0 V 0 V Erase 0 V 0 V 0 V 0 V 0 V 0 to 2.6 V 0 to 2.6 V 5 to 12 V 0 to 2.6 V 0 V 0 V Programming 0.7 to 1 V -0.5 V / 0 V 0.1 to 1 μA Vinh (1 to 2 V) 4 to 11 V 0 to 2.6 V 0 to 2.6 V 4.5 to 5 V 0 to 2.6 V 4.5 to 5 V 0 to 1 V

[0057] FIG13 depicts a neuron VMM array 1300, which is particularly well-suited for memory cell 310 shown in FIG3 and serves as the synaptic link between the input layer and the next layer. VMM array 1300 includes a memory array 1303 of nonvolatile memory cells, a reference array 1301 of first nonvolatile reference memory cells, and a reference array 1302 of second nonvolatile reference memory cells. EG lines EGR0, EG0, EG1, and EGR1 run vertically, while CG lines CG0, CG1, CG2, and CG3 and SL lines WL0, WL1, WL2, and WL3 run horizontally. VMM array 1300 is similar to VMM array 1400, except that VMM array 1300 implements bidirectional tuning. Because separate EG lines are used, individual cells can be fully erased, partially programmed, and partially erased as needed to achieve the desired charge on the floating gate. As shown, reference arrays 1301 and 1302 convert input currents at terminals BLR0, BLR1, BLR2, and BLR3 into control gate voltages CG0, CG1, CG2, and CG3 to be applied to the memory cells in the column direction (via the diode-connected reference cells through the multiplexer 1314). The current outputs (neurons) are on bit lines BL0 through BLN, where each bit line sums all currents from the non-volatile memory cells connected to that bit line.

[0058] Table 8 describes the operating voltages and currents for VMM array 1300. The rows in the table indicate the voltages applied to the word line for a selected cell, the word line for an unselected cell, the bit line for a selected cell, the bit line for an unselected cell, the control gate for a selected cell, the control gate for an unselected cell in the same sector as the selected cell, the control gate for an unselected cell in a different sector from the selected cell, the erase gate for a selected cell, the erase gate for an unselected cell, the source line for a selected cell, and the source line for an unselected cell. The columns indicate read, erase, and program operations. Table 8: Operations of the VMM array 1300 of FIG. 13 WL WL-not Selected BL BL-not Selected CG CG-not Select the same One sector CG-not Selected EG EG-Not Selected SL SL-Not yet Selected Read 1.0 to 2 V -0.5 V / 0 V 0.6 to 2 V (Ineuron) 0 V 0 to 2.6 V 0 to 2.6 V 0 to 2.6 V 0 to 2.6 V 0 to 2.6 V 0 V 0 V Erase 0 V 0 V 0 V 0 V 0 V 4 to 9 V 0 to 2.6 V 5 to 12 V 0 to 2.6 V 0 V 0 V Programming 0.7 to 1 V -0.5 V / 0 V 0.1 to 1 μA Vinh (1 to 2 V) 4 to 11 V 0 to 2.6 V 0 to 2.6 V 4.5 to 5 V 0 to 2.6 V 4.5 to 5 V 0 to 1 V

[0059] FIG22 illustrates a neuron VMM array 2200, which is particularly suitable for the memory cell 210 shown in FIG2 and serves as the synapse-to-neuron portion between the input layer and the next layer. In VMM array 2200, inputs INPUT 0, ..., INPUT N are received on bit lines BL 0, ..., BL N, respectively, and outputs OUTPUT 1, OUTPUT 2, OUTPUT 3, and OUTPUT 4 are generated on source lines SL 0, SL 1, SL 2, and SL 3, respectively.

[0060] FIG23 illustrates a neuron VMM array 2300, which is particularly suitable for the memory cell 210 shown in FIG2 and serves as the synapse-to-neuron portion between the input layer and the next layer. In this embodiment, inputs INPUT 0, INPUT 1, INPUT 2, and INPUT 3 are received on source lines SL0, SL1, SL2, and SL3, respectively, and outputs OUTPUT 0, ..., OUTPUT N are generated on bit lines BL0, ..., BLN.

[0061] FIG24 illustrates a neuron VMM array 2400, which is particularly suitable for the memory cell 210 shown in FIG2 and serves as the synapse-to-neuron portion between the input layer and the next layer. In this embodiment, inputs INPUT 0, ..., INPUT M are received on word lines WL0, ..., WL M, respectively, and outputs OUTPUT 0, ..., OUTPUT N are generated on bit lines BL0, ..., BL N, respectively.

[0062] FIG25 illustrates a neuron VMM array 2500, which is particularly suitable for memory cell 310 shown in FIG3 and serves as the synapse-to-neuron portion between the input layer and the next layer. In this embodiment, inputs INPUT 0, ..., INPUT M are received on word lines WL0, ..., WL4, respectively, and outputs OUTPUT 0, ..., OUTPUT N are generated on bit lines BL0, ..., BL4. Alternatively, the inputs can be received on control gates CG0, ..., CG4.

[0063] FIG26A depicts a neuron VMM array 2600, which is particularly suitable for the memory cell 410 shown in FIG4 and serves as the synapse-to-neuron portion between the input layer and the next layer. In this embodiment, inputs INPUT 0, ..., INPUT n are received on vertical control gate lines CG 0, ..., CG N, respectively, and outputs OUTPUT 1 and OUTPUT 2 are generated on source lines SL 0 and SL 1.

[0064] 26B depicts a neuron VMM array 2620, an alternative design to the VMM array 2600, with vertical rather than horizontal word lines. In this case, inputs can be received on vertical word lines WL0, WL1, and outputs OUTPUT1 and OUTPUT2 are generated on horizontal source lines SL0 and SL1.

[0065] 26C depicts a neuron VMM array 2640, an alternative design to the VMM array 2600, having vertical rather than horizontal erase gate lines. In this case, inputs are received on vertical erase gate lines EG0, EG1, and outputs OUTPUT 1 and OUTPUT 2 are generated on horizontal source lines SL0 and SL1.

[0066] FIG27 illustrates a neuron VMM array 2700, which is particularly well-suited for memory cell 410 shown in FIG4 and serves as the synapse-to-neuron portion between the input layer and the next layer. In this embodiment, inputs INPUT 0, ..., INPUT N are received at bitline control gates 2701-1, 2701-2, ..., 2701-(N-1), and 2701-N, respectively, which are coupled to bitlines BL0, ..., BLN, respectively. Exemplary outputs OUTPUT 1 and OUTPUT 2 are generated on source lines SL0 and SL1.

[0067] FIG28 depicts a neuron VMM array 2800, which is particularly suitable for memory cell 310 shown in FIG3 , memory cell 510 shown in FIG5 , and memory cell 710 shown in FIG7 , and serves as the synapse-to-neuron portion between the input layer and the next layer. In this embodiment, inputs INPUT 0, ..., INPUT M are received on word lines WL0, ..., WL4, and outputs OUTPUT 0, ..., OUTPUT N are generated on bit lines BL0, ..., BL4, respectively. Alternatively, the inputs can be received on control gate lines CG0, ..., CG4.

[0068] FIG29 depicts a neuron VMM array 2900, which is particularly suitable for memory cell 310 shown in FIG3 , memory cell 510 shown in FIG5 , and memory cell 710 shown in FIG7 , and serves as the synapse-to-neuron portion between the input layer and the next layer. In this embodiment, inputs INPUT 0, ..., INPUT M are received on control gate lines CG 0, ..., CG M. Outputs OUTPUT 0, ..., OUTPUT N are generated on vertical source lines SL 0, ..., SL N, respectively, where each source line SL i is coupled to the source lines of all memory cells in row i. Alternatively, inputs can be received on word lines WL 0, ..., WL M.

[0069] FIG30 illustrates a neuron VMM array 3000, which is particularly suitable for memory cell 310 shown in FIG3 , memory cell 510 shown in FIG5 , and memory cell 710 shown in FIG7 , and serves as the synapse-to-neuron portion between the input layer and the next layer. In this embodiment, inputs INPUT 0, ..., INPUT M are received on control gate lines CG 0, ..., CG M. Outputs OUTPUT 0, ..., OUTPUT N are generated on vertical bit lines BL 0, ..., BL N, respectively, where each bit line BL i is coupled to the bit lines of all memory cells in row i. Long Short-Term Memory

[0070] Prior art includes a concept called long short-term memory (LSTM). LSTM cells are often used in neural networks. LSTM allows neural networks to remember information for a predetermined, arbitrary time interval and use that information in subsequent operations. Conventional LSTM cells consist of a cell, an input gate, an output gate, and a forget gate. These three gates regulate the flow of information into and out of the cell and the time interval over which information is remembered within the LSTM. VMMs are particularly well-suited for LSTM cells.

[0071] FIG14 illustrates an exemplary LSTM 1400. In this embodiment, LSTM 1400 includes cells 1401, 1402, 1403, and 1404. Cell 1401 receives an input vector x0 and generates an output vector h0 and a cell state vector c0. Cell 1402 receives an input vector x1, the output vector (hidden state) h0 from cell 1401, and the cell state c0 from cell 1401, and generates an output vector h1 and a cell state vector c1. Cell 1403 receives an input vector x2, the output vector (hidden state) h1 from cell 1402, and the cell state c1 from cell 1402, and generates an output vector h2 and a cell state vector c2. Cell 1404 receives input vector x3, output vector (hidden state) h2 from cell 1403, and cell state c2 from cell 1403, and produces output vector h3. Additional cells may be used, and an LSTM with four cells is merely an example.

[0072] FIG15 illustrates an exemplary implementation of an LSTM cell 1500, which may be used for cells 1401, 1402, 1403, and 1404 in FIG14. LSTM cell 1500 receives an input vector x(t), a cell state vector c(t-1) from the previous cell, and an output vector h(t-1) from the previous cell, and generates a cell state vector c(t) and an output vector h(t).

[0073] LSTM cell 1500 includes sigmoid function components 1501, 1502, and 1503, each of which uses a number between 0 and 1 to control the amount of each component in the input vector that is allowed to pass through the output vector. LSTM cell 1500 also includes hyperbolic tangent components 1504 and 1505 for applying the hyperbolic tangent function to the input vector, multiplier components 1506, 1507, and 1508 for multiplying two vectors together, and addition component 1509 for adding two vectors together. The output vector h(t) can be provided to the next LSTM cell in the system or accessed for other purposes.

[0074] FIG16 depicts LSTM cell 1600, which is an example of an implementation of LSTM cell 1500. For the convenience of the reader, the same numbering as in LSTM cell 1500 is used in LSTM cell 1600. Sigmoid function components 1501, 1502, and 1503, as well as hyperbolic tangent component 1504, each include multiple VMM arrays 1601 and an activation function block 1602. Therefore, it can be seen that VMM arrays are particularly suitable for LSTM cells used in certain neural network systems. Multiplier components 1506, 1507, and 1508, as well as adder component 1509, are implemented digitally or analogically. Activation function block 1602 can be implemented digitally or analogically.

[0075] An alternative to LSTM cell 1600 (and another example implementation of LSTM cell 1500) is shown in Figure 17. In Figure 17, sigmoid function components 1501, 1502, and 1503 and hyperbolic tangent component 1504 share the same physical hardware (VMM array 1701 and activation function block 1702) in a time-multiplexed manner. LSTM cell 1700 also includes a multiplier component 1703 for multiplying two vectors together, an addition component 1708 for adding two vectors together, a hyperbolic tangent component 1505 (which includes an activation function block 1702), a register 1707 for storing the value i(t) when it is output from the sigmoid function block 1702, a register 1704 for storing the value f(t)*c(t-1) when it is output from the multiplier component 1703 through a multiplexer 1710, a register 1705 for storing the value i(t)*u(t) when it is output from the multiplier component 1703 through the multiplexer 1710, and a register 1706 for storing the value o(t)*c~(t) when it is output from the multiplier component 1703 through the multiplexer 1710 and the multiplexer 1709.

[0076] LSTM cell 1600 contains multiple sets of VMM arrays 1601 and respective activation function blocks 1602, while LSTM cell 1700 contains only one set of VMM arrays 1701 and activation function blocks 1702, which are used to represent multiple layers in the specific example of LSTM cell 1700. LSTM cell 1700 requires less space than LSTM 1600 because LSTM cell 1700 requires ¼ of the space for VMM and activation function blocks compared to LSTM cell 1600.

[0077] It will be further appreciated that an LSTM cell will typically include multiple VMM arrays, each of which requires functionality provided by certain circuit blocks external to the VMM array, such as summers, excitation function blocks, and high-voltage generation blocks. Providing a separate circuit block for each VMM array would require a significant amount of space within the semiconductor device and would be somewhat inefficient. Therefore, the embodiment described below attempts to minimize the circuitry required external to the VMM array itself. Gated recursive unit

[0078] An analogy to the VMM implementation can be applied to a Gated Recurrent Unit (GRU) system. The GRU is a gating mechanism in recurrent neural networks. The GRU is similar to the LSTM, except that a GRU cell typically contains fewer components than an LSTM cell.

[0079] FIG18 depicts an exemplary GRU 1800. In this embodiment, GRU 1800 includes cells 1801, 1802, 1803, and 1804. Cell 1801 receives an input vector x0 and produces an output vector h0. Cell 1802 receives an input vector x1, the output vector h0 from cell 1801, and produces an output vector h1. Cell 1803 receives an input vector x2 and the output vector (hidden state) h1 from cell 1802, and produces an output vector h2. Cell 1804 receives an input vector x3 and the output vector (hidden state) h2 from cell 1803, and produces an output vector h3. Additional cells may be used, and a GRU with four cells is merely an example.

[0080] FIG19 illustrates an exemplary implementation of a GRU cell 1900, which may be used in cells 1801, 1802, 1803, and 1804 of FIG18. GRU cell 1900 receives an input vector x(t) and an output vector h(t-1) from the previous GRU cell and generates an output vector h(t). GRU cell 1900 includes sigmoid function components 1901 and 1902, each of which applies a number between 0 and 1 to the components of the output vector h(t-1) and the input vector x(t). GRU cell 1900 also includes a hyperbolic tangent component 1903 for applying a hyperbolic tangent function to the input vector, a plurality of multiplier components 1904, 1905, and 1906 for multiplying two vectors together, an addition component 1907 for adding two vectors together, and a complement component 1908 for subtracting the input from 1 to generate the output.

[0081] FIG20 depicts GRU cell 2000, which is an example of an implementation of GRU cell 1900. For the convenience of the reader, the same numbering as in GRU cell 1900 is used in GRU cell 2000. As shown in FIG20, sigmoid function components 1901 and 1902, as well as hyperbolic tangent component 1903, each include multiple VMM arrays 2001 and an activation function block 2002. Thus, it can be seen that VMM arrays are particularly useful for GRU cells used in certain neural network systems. Multiplier components 1904, 1905, and 1906, addition component 1907, and complement component 1908 are implemented digitally or analogically. Activation function block 2002 can be implemented digitally or analogically.

[0082] FIG21 shows an alternative embodiment of GRU cell 2000 (and another example implementation of GRU cell 1900). In FIG21, GRU cell 2100 utilizes a VMM array 2101 and an activation function block 2102. The activation function block, when configured as a sigmoid function, applies a number between 0 and 1 to control the amount of each component in the input vector that is allowed to pass through to the output vector. In FIG21, sigmoid function components 1901 and 1902 and hyperbolic tangent component 1903 share the same physical hardware (VMM array 2101 and activation function block 2102) in a time-multiplexed manner. The GRU cell 2100 also includes a multiplier component 2103 for multiplying two vectors together, an addition component 2105 for adding two vectors together, a complement component 2109 for subtracting an input from 1 to produce an output, a multiplexer 2104, a register 2106 for storing the value h(t-1)*r(t) when it is output from the multiplier component 2103 through the multiplexer 2104, a register 2107 for storing the value h(t-1)*z(t) when it is output from the multiplier component 2103 through the multiplexer 2104, and a register 2108 for storing the value h^(t)*(1-z(t)) when it is output from the multiplier component 2103 through the multiplexer 2104.

[0083] GRU cell 2000 contains multiple sets of VMM arrays 2001 and excitation function blocks 2002, while GRU cell 2100 contains only one set of VMM arrays 2101 and excitation function blocks 2102, which are used to represent multiple layers in the specific example of GRU cell 2100. GRU cell 2100 requires less space than GRU cell 2000 because GRU cell 2100 requires 1 / 3 of the space for VMM and excitation function blocks compared to GRU cell 2000.

[0084] It will be further understood that a GRU system will typically include multiple VMM arrays, each of which requires functionality provided by certain circuit blocks external to the VMM array (such as summers, excitation function blocks, and high-voltage generation blocks). Providing a separate circuit block for each VMM array would require a significant amount of space within the semiconductor components and would be somewhat inefficient. Therefore, the embodiment described below attempts to minimize the circuitry required external to the VMM array itself.

[0085] The inputs to the VMM array can be analog levels, binary levels, pulses, time-modulated pulses, or digital bits (in which case a DAC is required to convert the digital bits to the appropriate input analog level), and the outputs can be analog levels, binary levels, timed pulses, pulses, or digital bits (in which case an output ADC is required to convert the output analog level to digital bits).

[0086] Generally speaking, for each memory cell in the VMM array, each weight W can be implemented by a single memory cell, a differential cell, or two mixed memory cells (the average of the two cells). In the case of a differential cell, two memory cells are required to implement the weight W as a differential weight (W = W+ - W-). In the case of two mixed memory cells, two memory cells are required to implement the weight W as the average of the two cells.

[0087] Each non-volatile memory cell used in an analog neuromorphic memory system must be erased and programmed to maintain a very specific and precise charge level (i.e., number of electrons) in its floating gate. For example, each floating gate must maintain one of N different values, where N is the number of different weights that can be represented by each cell. Examples of N include 16, 32, 64, 128, and 256.

[0088] One challenge with prior art is that the physical memory array can be much larger than the memory array required for a particular VMM operation. For example, the physical array may contain 1000 rows and 512 columns, but a VMM operation may require only 256 rows and 256 columns. A method is needed to support multiple arrays so that separate VMM operations can use the same physical array, with simultaneous access to each of the multiple arrays. Summary of the Invention

[0089] A number of embodiments are disclosed for splitting a physical array into multiple arrays for separate VMM operations by providing more than one output line per row in the physical array, which allows simultaneous access to multiple sets of columns in the same row, where different sets of columns are assigned to different arrays for VMM operations. Simple diagram description

[0090] FIG1 is a diagram illustrating an example of an artificial neural network.

[0091] FIG. 2 depicts a prior art split-gate flash memory cell.

[0092] FIG. 3 illustrates another prior art split-gate flash memory cell.

[0093] FIG. 4 illustrates another prior art split-gate flash memory cell.

[0094] FIG. 5 illustrates another prior art split-gate flash memory cell.

[0095] 6 is a diagram illustrating different levels of an exemplary artificial neural network utilizing one or more non-volatile memory arrays.

[0096] FIG7 is a block diagram of an exemplary vector-matrix multiplication system.

[0097] 8 is a block diagram illustrating an exemplary artificial neural network utilizing one or more vector-matrix multiplication systems.

[0098] FIG9 illustrates another embodiment of a vector-matrix multiplication system.

[0099] FIG10 illustrates another embodiment of a vector-matrix multiplication system.

[0100] FIG11 illustrates another embodiment of a vector-matrix multiplication system.

[0101] FIG12 illustrates another embodiment of a vector-matrix multiplication system.

[0102] FIG13 illustrates another embodiment of a vector-matrix multiplication system.

[0103] FIG. 14 depicts a prior art LSTM system.

[0104] FIG. 15 depicts an exemplary cell for use in a long short-term memory system.

[0105] FIG. 16 depicts a specific example of the exemplary cell of FIG. 15 .

[0106] FIG17 depicts another embodiment of the exemplary cell of FIG15.

[0107] FIG. 18 depicts a prior art gated recursive cell system.

[0108] FIG. 19 depicts an exemplary cell for use in a gated recursive cell system.

[0109] FIG. 20 depicts a specific example of the exemplary cell of FIG. 19 .

[0110] FIG. 21 depicts another embodiment of the exemplary cell of FIG. 19 .

[0111] FIG22 illustrates another specific example of a vector-matrix multiplication system.

[0112] FIG23 illustrates another specific example of a vector-matrix multiplication system.

[0113] FIG24 illustrates another specific example of a vector-matrix multiplication system.

[0114] FIG25 illustrates another specific example of a vector-matrix multiplication system.

[0115] FIG26A depicts another embodiment of a vector-matrix multiplication system.

[0116] FIG26B illustrates another embodiment of a vector-matrix multiplication system.

[0117] FIG26C depicts another specific example of a vector-matrix multiplication system.

[0118] FIG27 illustrates another specific example of a vector-matrix multiplication system.

[0119] FIG28 describes another specific example of a vector-matrix multiplication system.

[0120] FIG29 describes another specific example of a vector-matrix multiplication system.

[0121] FIG30 illustrates another specific example of a vector-matrix multiplication system.

[0122] Figure 31 describes the vector-matrix multiplication system.

[0123] Figure 32 describes a specific example of a separate vector-matrix multiplication system.

[0124] Figure 33 describes a specific example of a separate array-vector-matrix multiplication system.

[0125] FIG34 illustrates another embodiment of a split array-vector-matrix multiplication system.

[0126] FIG35 describes another specific example of a split array vector matrix multiplication system.

[0127] FIG36 describes another embodiment of a split array vector matrix multiplication system.

[0128] Figure 37 describes a specific example of a split array in a vector-matrix multiplication system.

[0129] FIG38 illustrates another embodiment of a split array in a vector-matrix multiplication system.

[0130] FIG39 depicts exemplary layouts of single and separate arrays in a vector-matrix multiplication system.

[0131] Figure 40 describes an embodiment of a split array vector-matrix multiplication system with multiple output lines per row.

[0132] Figure 41 describes an embodiment of a split array vector-matrix multiplication system with multiple output lines per row.

[0133] Figure 42 depicts an embodiment of an array having multiple output lines per row.

[0134] Figure 43 describes an embodiment of a split array vector-matrix multiplication system with multiple output lines per row.

[0135] FIG. 44 depicts an embodiment of an array comprising a plurality of arrays depicted in FIG. 42 . Implementation Method

[0136] The artificial neural network of the present invention utilizes a combination of CMOS technology and a non-volatile memory array. VMM System Overview

[0137] FIG31 depicts a block diagram of a VMM system 3100. VMM system 3100 includes a VMM array 3101, a row decoder 3102, a high-voltage decoder 3103, a column decoder 3104, a bitline driver 3105, input circuitry 3106, output circuitry 3107, control logic 3108, and a bias generator 3109. VMM system 3100 further includes a high-voltage generation block 3110, which includes a charge pump 3111, a charge pump regulator 3112, and a high-voltage level generator 3113. VMM system 3100 further includes a (program / erase, or also known as weight tuning) algorithm controller 3114, analog circuitry 3115, a control engine 3116 (which may include specialized functions such as arithmetic functions, activation functions, embedded microcontroller logic, etc.), and test control logic 3117. The systems and methods described below may be implemented in VMM system 3100.

[0138] Input circuit 3106 may include circuits such as a DAC (digital-to-analog converter), a DPC (digital-to-pulse converter, digital-to-time-modulated-pulse converter), an AAC (analog-to-analog converter, such as a current-to-voltage converter or a logarithmic converter), a PAC (pulse-to-analog level converter), or any other type of converter. Input circuit 3106 may implement normalization, a linear or nonlinear upscaling / downscaling function, or an arithmetic function. Input circuit 3106 may implement a temperature compensation function for the input level. Input circuit 3106 may implement an activation function such as a ReLU or a sigmoid. Output circuit 3107 may include circuits such as an ADC (analog-to-digital converter, which converts neuron analog outputs into digital bits), an AAC (analog-to-analog converter, such as a current-to-voltage converter or a logarithmic converter), an APC (analog-to-pulse converter, analog-to-time-modulated-pulse converter), or any other type of converter. Output circuit 3107 may implement an activation function such as a ReLU or a sigmoid. Output circuit 3107 can implement statistical normalization, regularization, scaling up / down / gain functions, statistical truncation, or arithmetic functions (e.g., addition, subtraction, division, multiplication, shift, logarithm) for neuron outputs. Output circuit 3107 can implement a temperature compensation function on neuron outputs or array outputs (e.g., bit line outputs) to keep the power consumption of the array approximately constant or improve the accuracy of the array (neuron) outputs, such as by keeping the IV slope approximately the same.

[0139] 32 to 36 illustrate a specific example of a VMM system that has certain similarities with VMM system 3100 but also includes some modifications.

[0140] FIG32 illustrates a VMM system 3200. VMM system 3200 includes an array 3201, a shared column decoder 3202, a shared high-voltage decoder 3203, row decoders 3204 and 3205, (column) input circuits 3220, output circuits 3206 and 3207, and a shared bitline driver 3208. Shared column decoder 3202 is coupled to all columns in array 3201 and applies voltage to selected columns. Shared high-voltage decoder 3203 can selectively couple to all columns in array 3201. Shared high-voltage decoder 3203 optionally includes a control gate high-voltage decoder 3231 that can selectively couple to all columns in the array, and a shared erase gate high-voltage decoder 3232 that can selectively couple to all columns in the array. Input circuit 3220 is, for example, similar to input circuit 3106 in FIG31. The circuitry and functionality of output circuits 3206 and 3207 are, for example, similar to those of output circuit 3107 in FIG. Unlike VMM system 3100, certain operations are split between different sets of circuitry in VMM system 3200. Specifically, half of the rows in array 3201 (e.g., all odd-numbered rows) are operated by row decoder 3204 and output circuit 3206, while the other half of the rows in array 3201 (e.g., all even-numbered rows) are operated by row decoder 3205 and output circuit 3207. Thus, output circuit 3206 is coupled to row decoder 3204 to generate a first output for one or more rows in the first half during a read operation, and output circuit 3207 is coupled to row decoder 3207 to generate a second output for one or more rows in the second half during a read operation. In this embodiment, all rows are coupled to a common bit line driver 3208 during programming or erasing operations. This allows for simultaneous reading of multiple bit lines, meaning that the bit lines coupled to row decoder 3204 and output circuit 3206 and the bit lines coupled to row decoder 3205 and output circuit 3207 are simultaneously enabled for read operations via a common bit line driver 3208. This increases the throughput of reading array 3201. Alternatively, the read operations need not be simultaneous.

[0141] Optionally, referring further to FIG. 39 , continuous diffusion may be implemented between the top and bottom halves of the array.

[0142] FIG33 illustrates a VMM system 3300. VMM system 3300 includes arrays 3301a and 3301b, a row decoder 3302, a shared high-voltage decoder 3303, column decoders 3304 and 3305, input circuitry 3320, current-to-voltage converter circuits 3306 and 3307, a shared analog-to-digital converter (ADC) 3308, and a shared bitline driver 3309. Current-to-voltage converter circuits 3306 and 3307 and shared ADC circuitry 3308 are part of output circuitry 3207 in FIG32.

[0143] Unlike VMM system 3100, certain operations are split between different sets of circuitry in VMM system 3300. Specifically, array 3301a is operated by row decoder 3304 and current-to-voltage converter 3306, and array 3301b is operated by row decoder 3305 and current-to-voltage converter 3307. This allows multiple read and / or program operations to be performed simultaneously, where a read or program operation can be performed simultaneously on one or more cells in array 3301a and one or more cells in array 3301b.

[0144] Both current-to-voltage converter circuits 3306 and 3307 are coupled to a common analog-to-digital converter 3308, which is used in a time-multiplexed manner during read operations, and to a common bit-line driver 3309, which is used during program and erase operations. For example, during a read operation, array 3301a is enabled and coupled to row decoder 3304 and current-to-voltage converter circuit 3306, while array 3301b is enabled and simultaneously coupled to row decoder 3305 and current-to-voltage converter circuit 3307. The output voltages from current-to-voltage converter circuits 3306 and 3307 are sampled and held (S / H) by, for example, S / H capacitors within a shared ADC 3308. These array output voltages are then digitized (converted) by the time-multiplexed shared ADC 3308 (since the ADC is shared between current-to-voltage converter circuits 3306 and 3307). For example, two sets of S / H capacitors are used for one ADC shared between two current-to-voltage converter circuits. In another embodiment, one ADC can be used for N current-to-voltage converter circuits, in which case N sets of S / H capacitors are used.

[0145] Using a common ADC between two current-to-voltage converter circuits is also applicable to Figure 34 / Figure 35 / Figure 36.

[0146] FIG34 illustrates a VMM system 3400. VMM system 3400 includes arrays 3401a and 3401b, a shared row decoder 3402, a shared high-voltage decoder 3403, row decoders 3404 and 3405, input circuitry 3420, output circuitry 3406 and 3407, and a shared bitline driver 3408. Unlike VMM system 3100, certain operations are split between different sets of circuitry in VMM system 3400. Specifically, array 3401a is operated by row decoder 3404 and output circuitry 3406, while array 3401b is operated by row decoder 3405 and output circuitry 3407. This allows multiple read and / or program operations to be performed simultaneously, where a read or program operation can be performed on one or more cells in array 3401a and one or more cells in array 3401b simultaneously. Both arrays 3401a and 3401b are coupled to common bit line drivers 3408, which are used during program and erase operations.

[0147] FIG35 illustrates a VMM system 3500. VMM system 3500 includes arrays 3501a, 3501b, 3501c, and 3501d; row decoders 3502 and 3503; a shared high-voltage decoder 3504; row decoders 3505, 3506, 3507, and 3508; input circuit 3520; output circuits 3509, 3510, 3511, and 3512; and shared bitline drivers 3513 and 3514. Shared high-voltage decoder 3504 can be selectively coupled to all rows in arrays 3501a, 3501b, 3501c, and 3501d. Row decoder 3502 is shared by arrays 3501a and 3501b and is coupled to all columns in those arrays and applies voltage to selected columns, and row decoder 3503 is shared by arrays 3501c and 3501d and is coupled to all columns in those arrays and applies voltage to selected columns.

[0148] In VMM system 3500, certain operations are split between different sets of circuitry. Specifically, array 3501a is operated by row decoder 3505 and output circuit 3509; array 3501b is operated by row decoder 3507 and output circuit 3511; array 3501c is operated by row decoder 3506 and output circuit 3510; and array 3501d is operated by row decoder 3508 and output circuit 3512. This allows multiple read and / or program operations to be performed simultaneously across all four arrays. Read or program operations can be performed simultaneously on one or more cells in array 3501a, one or more cells in array 3501b, one or more cells in array 3501c, and one or more cells in array 3501d. Both arrays 3501a and 3501b are selectively coupled to a shared bitline driver 3513 during program and erase operations. Both arrays 3501c and 3501d are selectively coupled to a common bit line driver 3514 during program and erase operations.

[0149] For example, a first read operation may be performed, wherein row decoder 3505 and output circuit 3509 generate a first output from one or more columns in array 3501a; a second read operation may be performed, wherein row decoder 3506 and output circuit 3510 generate a second output from one or more columns in array 3501c; a third read operation may be performed, wherein row decoder 3507 and output circuit 3511 generate a third output from one or more columns in array 3501b; and a fourth read operation may be performed, wherein row decoder 3508 and output circuit 3512 generate a fourth output from one or more columns in array 3501d. Optionally, the first and third read operations may occur simultaneously. Optionally, the second and fourth read operations may occur simultaneously.

[0150] FIG36 illustrates a VMM system 3600. VMM system 3600 includes arrays 3601a, 3601b, 3601c, and 3601d; column decoder 3621; control gate decoders 3602 and 3603; a shared high voltage decoder 3604; row decoders 3605, 3606, 3607, and 3608; output circuits 3609, 3610, 3611, and 3612; and shared bit line drivers 3613 and 3614. In VMM system 3600, certain operations are split between different sets of circuitry. Specifically, array 3601a is operated by row decoder 3605 and output circuit 3609; array 3601b is operated by row decoder 3607 and output circuit 3611; array 3601c is operated by row decoder 3606 and output circuit 3610; and array 3601d is operated by row decoder 3608 and output circuit 3612. This allows multiple read and / or program operations to be performed simultaneously across all four arrays at once, with read or program operations being performed simultaneously on one or more cells in array 3601a, one or more cells in array 3601b, one or more cells in array 3601c, and one or more cells in array 3601d. Both arrays 3601a and 3601b are selectively coupled to a common bitline driver 3613 during program and erase operations. Both arrays 3601c and 3601d are selectively coupled to a common bit line driver 3614 during program and erase operations.

[0151] Figures 32 through 36 show that reading is accomplished via the row input on the control gate. Alternatively, reading can be accomplished on the word line or erase gate. Input circuit 3220 in Figure 32, input circuit 3320 in Figure 33, input circuit 3420 in Figure 34, input circuit 3520 in Figure 35, and input circuit 3620 in Figure 36 are similar to input circuit 3106 in Figure 31. Output circuits 3206 / 3207 in Figure 32, output circuits 3406 / 4307 in Figure 34, output circuits 3507 / 3508 / 3509 / 3510 in Figure 35, and output circuits 3607 / 3608 / 3609 / 3610 in Figure 36 are similar to output circuit 3107 in Figure 31.

[0152] FIG37 illustrates a portion of a VMM array 3700. VMM array 3700 includes columns 3701, 3702, 3703, 3704, 3705, 3706, 3707, and 3708. Columns 3701, 3702, 3705, and 3706 share an erase gate line (EG0) and a source line (SL0); columns 3703, 3704, 3707, and 3708 share an erase gate line (EG1) and a source line (SL1). Furthermore, columns 3701 and 3703 share control gate lines (CG0 / CG2); columns 3702 and 3704 share control gate lines (CG1 / CG3); columns 3705 and 3707 share control gate lines (CG4 / CG6); and columns 3706 and 3708 share control gate lines (CG5 / CG7). This coupling allows different columns to share decoder circuitry. The array terminals are shared so that program or erase disturb is reduced by having a reduced amount of erase or program voltage stress on unselected cells.

[0153] In the arrays of Figures 37 and 38 (described below), the row inputs of VMM arrays 3700 and 3800 for neural read operations are turned on the word lines (multiple rows and multiple bit lines are turned on simultaneously). If the inputs for neural read are turned on the control gates, the control gates cannot be shared across multiple rows in the same sub-array or array group.

[0154] 38 depicts a portion of an array 3800. Array 3800 includes sectors 3809 and 3819. Sector 3809 includes columns 3801, 3802, 3803, 3804, 3805, 3806, 3807, and 3808. Sector 3819 includes columns 3811, 3812, 3813, 3814, 3815, 3816, 3817, and 3818.

[0155] Rows 3801 (the first row) and 3811 (the second row) share a control gate line (CG0) (meaning that the control gate terminals of the cells in those rows are coupled to the same control gate line); rows 3802 and 3812 share a control gate line (CG1) (meaning that the control gate terminals of the cells in those rows are coupled to the same control gate line); rows 3803 and 3813 share a control gate line (CG2) (meaning that the control gate terminals of the cells in those rows are coupled to the same control gate line); rows 3804 and 3814 share a control gate line (CG3) (meaning that the control gate terminals of the cells in those rows are coupled to the same control gate line); rows 3805 and 3815 share a control gate line (CG4) (meaning that the control gate terminals of the cells in those rows are coupled to the same control gate line); rows 3806 and 3816 share a control gate line (CG5). Columns 3807 and 3817 share a control gate line (CG6), meaning that the control gate terminals of the cells in those columns are coupled to the same control gate line. Columns 3808 and 3818 share a control gate line (CG7), meaning that the control gate terminals of the cells in those columns are coupled to the same control gate line. This means that the control gates are shared across sectors. This coupling allows different columns to share decoder circuitry. Sharing array terminals reduces program or erase disturb by placing a reduced amount of erase or program voltage stress on unselected cells.

[0156] Rows 3801 (first row), 3802 (third row), 3805, and 3806 share an erase gate line (EG0) (meaning the erase gate terminals of the cells in those rows are coupled to the same erase gate line) and a source line (SL0) (meaning the source line terminals of the cells in those rows are coupled to the same source line); rows 3803, 3804, 3807, and 3808 share an erase gate line (EG1) (meaning the erase gate terminals of the cells in those rows are coupled to the same erase gate line) and a source line (SL1) (meaning the source line terminals of the cells in those rows are coupled to the same source line); rows 3811, 3812, 3815, and 3816 share an erase gate line (EG0). (meaning that the erase gate terminals of each cell in those rows are coupled to the same erase gate line) and source line (SL0) (meaning that the source line terminals of each cell in those rows are coupled to the same source line); and rows 3813, 3114, 3817 and 3818 share the erase gate line (EG1) (meaning that the erase gate terminals of each cell in those rows are coupled to the same erase gate line) and source line (SL1) (meaning that the source line terminals of each cell in those rows are coupled to the same source line).

[0157] FIG39 depicts an exemplary layout of a portion of a single array 3901 (such as array 3101 in FIG31 and array 3201 in FIG32 ) and a split array 3902 (such as arrays 3301a and 3301b in FIG33 , arrays 3401a and 3401b in FIG34 , arrays 3501a, 3501b, 3501c, and 3501d in FIG35 , and arrays 3601a, 3601b, 3601c, and 3601d in FIG36 ). Split array 3902 follows the same design as array 3901, except that certain contacts and metal connections 3904 are removed (or not formed), resulting in sub-arrays 3903a and 3903b. A few dummy columns at the interface are disabled, such as by grounding the word lines and control gates. This is because the front-end layers (i.e., continuous row diffusions within a row and continuous column diffusions within a source line) and polysilicon are continuous and uniform between the two arrays of non-volatile memory cells (between electrically separated arrays), thus maintaining process uniformity. This also results in a reduced area penalty compared to physically separating different arrays. Array with multiple output lines per row

[0158] FIG40 depicts VMM system 4000. VMM system 4000 includes arrays 4001a and 4001b, a shared column decoder 4002, a shared high-voltage decoder 4003, a row decoder 4005, input circuitry 4020, output circuits 4006 and 4007, and a shared bitline driver 4008 (which controls programming, such as providing programming current or inhibiting a bitline during programming). Unlike VMM system 3100, certain operations in VMM system 4000 are separated between different sets of circuitry. Specifically, while arrays 4001a and 4001b can be formed from the same physical array, by design, there are multiple output lines per memory row (a row of memory cells). In this embodiment, the output lines are bitlines, meaning there are multiple bitlines per row, with one set of bitlines coupled to output circuitry 4006 and another set of bitlines coupled to output circuitry 4007. This allows read and / or program operations to be performed simultaneously on arrays 4001a and 4001b, where a read or program operation can be performed simultaneously on one or more cells in array 4001a and one or more cells in array 4001b. Both arrays 4001a and 4001b are coupled to a common bit line driver 4008, which is used during program and erase operations. Alternatively, the read or program operations can be performed independently at different time periods.

[0159] FIG41 depicts VMM system 4100. VMM system 4100 includes arrays 4101a and 4101b, a shared column decoder 4102, a shared high-voltage decoder 4103, a row decoder 4105, input circuitry 4120, a shared output circuitry 4106, and a shared bitline driver 4107. VMM system 4100 is similar to VMM system 4100, except that VMM system 4100 includes a single output circuitry 4106 instead of two output circuits 4006 and 4007. As in VMM system 4000, certain operations are separated between different sets of circuitry in VMM system 4100. Specifically, although arrays 4101a and 4101b may be formed from the same physical array, by design, multiple output lines exist for each row. In this embodiment, the output lines are bitlines, meaning that there are multiple bitlines per row, all of which are coupled to output circuitry 4106. This allows read and / or program operations to be performed simultaneously on array 4101a and array 4101b, where a read or program operation can be performed simultaneously on one or more cells in array 4101a and one or more cells in array 4101b. Both arrays 4101a and 4101b are coupled to a common bit line driver 4108, which is used during program and erase operations. Alternatively, the read or program operations can be performed independently at different time periods.

[0160] FIG42 depicts a portion of an array 4200. Array 4200 includes a plurality of non-volatile memory cells arranged in rows and columns 4201, 4202, 4203, and 4204. It should be understood that array 4200 may include many additional rows and columns not shown, but the same principles shown will apply to these additional rows and columns. In this embodiment, each non-volatile memory cell is included in a column and row and has a bit line terminal, a word line terminal, an erase gate terminal, and a control gate terminal, as in memory cell 310 of FIG3 .

[0161] Unlike the prior art, where each row contains two output lines (two bit lines), it may instead contain more than two output lines. For example, row 4201 includes bit lines BLB0 and BLTO, row 4202 includes bit lines BLB1 and BLT1, row 4203 includes bit lines BLB2 and BLT2, and row 4204 includes bit lines BLB3 and BLT3. Rows are grouped into block arrays 4210 and 4220. The cells in array 4210 are coupled to bit lines BLT0, BLT1, BLT2, and BLT3 but not to bit lines BLB0, BLB1, BLB2, and BLB3. The cells in array 4220 are coupled to bit lines BLB0, BLB1, BLB2, and BLB3 but not to bit lines BLT0, BLT1, BLT2, and BLT3.

[0162] Due to this configuration, rows in array 4210 can be read or programmed simultaneously with rows in array 4220 without any contention. This provides significant efficiency when, for example, array 4210 is used in a first VMM operation and array 4220 is used in a second, separate VMM operation. This allows the same physical array to operate two separate VMM arrays and operations simultaneously, which improves the speed of the VMM system compared to prior art.

[0163] FIG43 illustrates VMM system 4300. VMM system 4300 includes arrays 4301a, 4301b, 4301c, and 4301d, a shared column decoder 4302, a shared high-voltage decoder 4303, row decoders 4305 and 4310, shared input circuitry 4320, output circuitry 4306, 4307, 4311, and 4312, and bitline drivers 4308 and 4313. Unlike VMM system 3100, certain operations are separated between different sets of circuitry in VMM system 4300. Specifically, although arrays 4301a, 4301b, 4301c, and 4301d may be formed from the same physical array, by design, multiple output lines exist for each row. In this embodiment, the output lines are bit lines, and there are four output lines (bit lines) per memory row, where a first set of bit lines is coupled to output circuit 4306, a second set of bit lines is coupled to output circuit 4307, a third set of bit lines is coupled to output circuit 4311, and a fourth set of bit lines is coupled to output circuit 4312. This allows read and / or program operations to be performed on arrays 4301a, 4301b, 4301c, and 4301d simultaneously, where a read or program operation can be performed on one or more cells in array 4301a, one or more cells in array 4301b, one or more cells in array 4301c, and one or more cells in array 4301d simultaneously. Arrays 4301a and 4301b are both coupled to bit line drivers 4313, which are used during programming and erasing operations involving those arrays, and arrays 4301c and 4301d are coupled to bit line drivers 4308, which are used during programming and erasing operations involving those arrays. Alternatively, read and program operations can be performed independently at different time periods.

[0164] 44 depicts a VMM system 4400 comprising a plurality of sets of arrays, where each set comprises an array 4401a and an array 4401b, where each array 4401a is an instance of array 4210 in FIG. 42 and each array 4401b is an instance of array 4220 in FIG. 42.

[0165] It should be noted that as used herein, the terms "over" and "on" include both "directly on" (without intervening materials, elements, or spaces) and "indirectly on" (with intervening materials, elements, or spaces). Similarly, the term "adjacent" includes both "directly adjacent" (without intervening materials, elements, or spaces) and "indirectly adjacent" (with intervening materials, elements, or spaces), "mounted to" includes both "directly mounted to" (without intervening materials, elements, or spaces) and "indirectly mounted to" (with intervening materials, elements, or spaces), and "electrically coupled to" includes both "directly electrically coupled to" (without intervening materials or elements electrically connecting the elements together) and "indirectly electrically coupled to" (with intervening materials or elements electrically connecting the elements together). For example, forming a component "over a substrate" can include forming the component directly on the substrate without intervening materials / elements, as well as forming the component indirectly on the substrate with one or more intervening materials / elements.

[0166] 12:Substrate 14: Source region 16: Drain area 18: Channel Area 20: Floating Gate 22: Word line terminal / select gate 24: Bit line 28: Control gate 30: Erase Gate 31: Digital to Analog Converter 32,1601,1701,2001,2101,3101,3700,3800: Vector-Matrix Multiplication (VMM) array 32a: Input VMM array / input layer 32b: Next VMM array (hidden level 1) / hidden layer 32c: Next VMM array (hidden level 2) / hidden layer 32d: VMM array / fully connected layer 32e: VMM array / fully connected layer 33: Non-volatile memory cell array 34: Erase gate and word line gate decoder 35: Control gate decoder 36: Bit Line Decoder 37: Source Line Decoder 38: Differential Summer 39: Activation function block 210: Memory cell / Flash memory cell 310: Quad-gate memory cell / Flash memory cell 410: Tri-gate memory cell / flash memory cell 510: Stacked Gate Memory Cell / Flash Memory Cell 710: Memory Cell 900, 1000, 1100, 1200, 1300, 2200, 2300, 2400, 2500, 2600, 2620, 2640, 2700, 2800, 2900, 3000: Neuron VMM Array 901, 1003, 1103, 1203, 1303: memory array 902,1001,1002,1101,1102,1201,1202,1301,1302: Reference array 903: Control gate line 904: Erase gate line 1014,1212: Diode-connected through-multiplexer 1204: Stacked transistor 1205, 1709, 1710, 2104: Multiplexer 1314: Diode-connected reference cell through multiplexer 1400:LSTM / VMM array 1401, 1402, 1403, 1404, 1801, 1802, 1803, 1804: Cell 1500, 1600, 1700: LSTM cells 1501, 1502, 1503, 1901, 1902: S-type function components 1504,1505,1903: Hyperbolic tangent component 1506, 1507, 1508, 1703, 1904, 1905, 1906, 2103: Multiplier components 1509, 1708, 1907, 2105: Additive components 1602, 1702, 2002, 2102: incentive function blocks 1704, 1705, 1706, 1707, 2106, 2107, 2108: registers 1800, 1900, 2000, 2100: GRU cells 1908,2109: complementary components 3100, 3200, 3300, 3400, 3500, 3600, 4000, 4100, 4300, 4400: VMM systems 3102,3202,3302,3402,3502,3503,3621,4002,4102,4302: Column decoder 3103,3203,3303,3403,3504,3604,4003,4103,4303: High Voltage Decoder 3104,3204,3205,3304,3305,3404,3405,3505,3506,3520,3605,3606,4005,4105,4305,4310: Row Decoder 3105,3208,3309,3408,3513,3514,3613,3614,4008,4107,4308,4313: Bit Line Drivers 3106,3220,3320,3420,3620,4020,4120,4320: Input circuit 3107,3206,3207,3406,3407,3509,3510,3511,3512,3609,3610,3611,3612,4006,4007,4106,4306,4307,4311,4312: Output circuit 3108: Control Logic 3109: Bias generator 3110: High voltage generation block 3111: Charge Pump 3112: Charge Pump Regulator 3113: High Voltage Level Generator 3114:Algorithm Controller 3115:Analog Circuit System 3116: Control Engine 3117: Test control logic 3201,3301a,3301b,3401a,3401b,3501a,3501b,3501c,3501d,3601a,3601b,3601c,3601d,4001a,4001b,4101a,4101b,4200,4301a,4301b,4301c,4301d,4401a,4401b: Array 3231: Control Gate High Voltage Decoder 3232: Erase Gate High Voltage Decoder 3306,3307: Current to voltage converter circuit 3308:Analog-to-Digital Converter (ADC) 3507,3508,3607,3608: Row decoder / output circuit 3602,3603: Control gate decoder 3701,3702,3703,3704,3705,3706,3707,3708,3801,3802,3803,3804,3805,3806,3807,3808,3811,3812,3813,3814,3815,3816,3817,3818: Column 3809,3819: sectors 3901: Single array 3902: Separation Array 3903a, 3903b: Subarray 3904:Metal connection 4201,4202,4203,4204: OK 4210,4220:Block array C1, C2, C3: layers CB1, CB2, CB3, CB4: synapses P1: Activation function / pooling function P2: Activation function S0: Input layer S1, S2: layers S3: Output layer

Claims

1. A system for analog neural memory in deep learning artificial neural networks, comprising: a physical array of nonvolatile memory cells configured in columns and rows, the physical array being divided into two or more logical arrays, each including two or more columns of nonvolatile memory cells; and a plurality of sets of two or more output lines, wherein... Each row contains one set of two or more output lines; wherein, within each logic array, each cell in each row is coupled to only one of the set of two or more output lines of the other row.

2. As in the system of request item 1, wherein, These output lines are bit lines.

3. As in request item 1, where, Each set of two or more output lines contains two output lines.

4. As in request item 1, where, Each set of two or more output lines contains four output lines.

5. As in request item 1, where, The non-volatile memory cells in this physical array are discrete gate flash memory cells.

6. As in request item 1, where, The non-volatile memory cells in this physical array are stacked gate flash memory cells.

7. The system of claim 1 includes: an output driver coupled to the plurality of sets of two or more output lines.

8. The system of claim 1, comprising: a first output driver coupled to a first line in each set of two or more output lines in the plurality of sets of two or more output lines; and a second output driver coupled to a second line in each set of two or more output lines in the plurality of sets of two or more output lines.

9. The system of claim 8, comprising: a third output driver coupled to a third line in each set of two or more output lines in the plurality of sets of two or more output lines; and a fourth output driver coupled to a fourth line in each set of two or more output lines in the plurality of sets of two or more output lines.

10. The system of claim 8, comprising: a high-voltage decoder for providing a high voltage to the array during programming and erasure operations.

11. The system of claim 8, comprising: a bit line driver coupled to the plurality of sets of two or more output lines.

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