Memory device with sinx material and manufacturing thereof

Abstract

This invention relates to a memory cell with silicon nitride and its manufacturing method, which is applied to a memory device comprising a silicon substrate and a plurality of memory cells. The memory cells are disposed on the silicon substrate and are respectively coupled to an access control circuit via a word line and at least one bit line. Each memory cell comprises a first electrode layer, a ferroelectric layer, an interface capping layer (ICL), and a second electrode layer. The ICL is made of silicon nitride. The ICL can reduce the coefficient of thermal expansion of the ferroelectric layer and increase the tensile stress of the ferroelectric layer, and the polarization degree of the ferroelectric layer will be increased. Furthermore, oxygen ions will be transferred between the second electrode layer and the ICL to prevent oxygen ions from entering the ferroelectric layer, thereby improving the durability of the ferroelectric layer.

Description

[Technical Field]

[0001] This invention relates to a semiconductor structure and manufacturing method, particularly a memory cell containing silicon nitride and its manufacturing method. [Previous Technology]

[0002] Memory devices are widely used in various electronic devices, from the most basic electronic devices, such as handheld computers, to more complex electronic devices, such as smartphones. Memory devices contain multiple memory units. A memory unit can be a basic electronic circuit used to store one bit of information. For example, a memory unit can have logic "1" representing a higher potential and logic "0" representing a lower potential to represent binary bit information. It is maintained (stored) until the storage state of the memory unit is changed.

[0003] The demand for non-volatile memory with low operating voltage, low power consumption, and high speed for various electronic devices such as portable terminals and integrated circuit (IC) cards has increased, leading to extensive development of ferroelectric random access memory (F-RAM) by the memory industry. F-RAM typically contains a grid or array of many storage elements or cells, each including at least one ferroelectric capacitor and at least one transistor for selecting cells and controlling read or write operations thereon. The ferroelectric material layer of the ferroelectric capacitor has a non-linear relationship between the applied electric field and the stored apparent charge, and therefore can switch polarity under an electric field. The advantages of ferroelectric memory elements include low power consumption, fast write performance, and high maximum read / write endurance.

[0004] Ferroelectric memory has received widespread attention in memory device development in recent years due to its relatively simple structure, scalability, and high compatibility with CMOS processes. At room temperature and pressure, the most stable crystalline phase of HfO₂ is the monoclinic phase (P₂ 1 / c, m-phase). Upon heating, it transforms into the tetragonal phase (P₄ 2 / nmc, t-phase) or the cubic phase (Fm₃m, c-phase). Under increased pressure, it forms a paraelectric / non-polar orthorhombic phase (Pbca, Pmna), but none of these phases possess ferroelectricity. Experiments and theoretical calculations show that ferroelectric HfO₂ crystallizes into a non-centrosymmetric / polar orthorhombic phase (Pca₂ 1, o-phase). However, achieving high remanent polarization in ferroelectric memories with HfO2 thin films is very challenging due to the instability of the o-phase of ferroelectric memory and its coexistence with the more stable m-phase (P21 / c) and t-phase.

[0005] Although TIN / HZO has been developed in recent years to provide a stable o-phase and enhance the capping effect, HZO, as a ferroelectric layer, leads to reduced polarization of the ferroelectric layer when vacancy defects are generated. This results in increased leakage current. To address the leakage current problem, Ru has been developed as the top electrode material to reduce leakage current at the interface between the top electrode and HZO. However, the high power function of Ru leads to an increase in the potential barrier for electron injection.

[0006] Therefore, providing a stable o-phase remains an urgent problem that memory devices need to solve. [Summary of the Invention]

[0007] One object of the present invention is to provide a memory cell with silicon nitride and a method for manufacturing the same, wherein an interface covering layer is formed in the memory device with silicon nitride to provide a ferroelectric layer with a stable o phase, thereby reducing the coefficient of thermal expansion of the ferroelectric layer, increasing the tensile stress of the ferroelectric layer, increasing the polarization of the ferroelectric layer, and preventing oxygen ions from entering the ferroelectric layer.

[0008] To achieve the above objectives, the present invention provides a memory cell with silicon nitride, which is applied to a memory device, comprising a silicon substrate and a plurality of memory cells. Each memory cell is disposed on the silicon substrate and coupled to an access control circuit via a word line and at least one bit line. Each memory cell comprises a first electrode layer, a ferroelectric layer, an interface capping layer and a second electrode layer. The first electrode layer is disposed on the silicon substrate, the ferroelectric layer is disposed on the first electrode layer, the interface capping layer is disposed on the ferroelectric layer, and the area of ​​the interface capping layer is less than or equal to the area of ​​the ferroelectric layer. The second electrode layer is disposed on the interface capping layer, and the area of ​​the second electrode layer is equal to the area of ​​the interface capping layer. The material of the interface capping layer is selected from silicon nitride (SiNx). This interface capping layer helps control oxygen migration and drive the generation of oxygen vacancies in the ferroelectric layer, thereby providing a ferroelectric layer with a stable o-phase. This reduces the coefficient of thermal expansion of the ferroelectric layer, increases its tensile stress, enhances its polarization, and prevents oxygen ions from entering the ferroelectric layer. Furthermore, the interface capping layer in this invention has a higher rhombohedral phase and a lower monoclinic phase, increasing the residual polarization (2Pr value), which helps memory cells store corresponding unit data.

[0009] The present invention provides an embodiment in which, when the thickness of the interface capping layer is 1 nanometer or less, the coefficient of thermal expansion of the ferroelectric layer will decrease, the tensile stress of the ferroelectric layer will increase, and the polarization degree of the ferroelectric layer will increase, while oxygen ions will transfer between the second electrode layer and the ICL. When the thickness of the interface capping layer is 2 nanometers to 3 nanometers, the durability of the ferroelectric layer can be improved, and oxygen ions can be prevented from entering the ferroelectric layer.

[0010] The present invention provides an embodiment in which the nitride is selected from silicon nitride, silicon oxynitride, metal nitride or metal carbonitride.

[0011] The present invention provides an embodiment in which the metal nitride is titanium silicon nitride (TiSiN) or manganese silicon nitride (MoSiN).

[0012] The present invention provides an embodiment in which the material of the ferroelectric layer is selected from the group consisting of zirconium hafnium oxide (HfZrOx), silicon hafnium oxide (HfSiOx), hafnium oxide (HfOx), yttrium hafnium oxide (HfYOx), thorium hafnium oxide (HfGdOx), strontium hafnium oxide (HfSrOx), titanium strontium oxide (SrTiOx), calcium strontium titanate (SrCaTiO3), Ag(Nb1-xTax)O3, barium strontium titanate (BaSrTiO3), barium titanate (BaTiO3), zirconium oxide (ZrOx), or aluminum hafnium oxide (HfAlOx).

[0013] The present invention provides an embodiment in which the materials of the first electrode layer and the second electrode layer are selected from the group consisting of zirconium (Zr), hafnium (Hf), titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), silicon tantalumide (TaSi), tantalum carbonitride (TaCN), titanium aluminum nitride (TiAlN), zinc (Zn), nickel (Ni), nickel siliconide (NiSi), ruthenium (Ru), carbon (C), silicon (Si), silicon nitride (SiNx), germanium (Ge), platinum (Pt), aluminum (Al), aluminum nitride (AlN), yttrium (Y), thorium (Gd), strontium (Sr), tungsten (W), tungsten siliconide (WSi), tungsten nitride (WN), gallium (Ga), and gallium nitride (GaN).

[0014] The present invention further provides a method for manufacturing a memory cell, comprising the steps of first providing a silicon substrate, subsequently forming a first electrode layer on the silicon substrate, then forming a ferroelectric layer on the first electrode layer, further forming an interface capping layer on the ferroelectric layer using a silicon nitride, the area of ​​the interface capping layer being less than or equal to the area of ​​the ferroelectric layer, then forming a second electrode layer on the interface capping layer, the area of ​​the second electrode layer being equal to the area of ​​the interface capping layer, and finally performing an annealing process to form at least one memory cell. Thereby, the present invention provides a ferroelectric layer having a stable o-phase in the memory cell, thereby reducing the coefficient of thermal expansion of the ferroelectric layer, increasing the tensile stress of the ferroelectric layer, increasing the polarization of the ferroelectric layer, and preventing oxygen ions from entering the ferroelectric layer. Furthermore, the interface capping layer in this case has a higher rhombohedral phase and a reduced monoclinic phase, which increases the residual polarization (Pr value) and helps the memory cell store the corresponding unit data.

[0015] The present invention provides another embodiment in which, in the step of forming a first electrode layer on the silicon substrate, in the step of forming an interface capping layer on the ferroelectric layer, and in the step of forming a second electrode layer on the interface capping layer, an radio frequency sputtering process is used to perform the steps of forming a first electrode layer on the silicon substrate, forming an interface capping layer on the ferroelectric layer, and forming a second electrode layer on the interface capping layer.

[0016] The present invention provides another embodiment in which an atomic layer deposition (ALD) process is used in the step of forming a ferroelectric layer on the first electrode layer.

[0017] The memory device with nitride as described in claim 7, wherein in the step of performing an annealing process to form the memory device, annealing is performed in a nitrogen (N2) atmosphere at 350°C to 450°C for 0.5 to 1.5 hours.

Implementation Method

[0019] To enable your review committee to have a better understanding of the features and effects achieved by the present invention, preferred embodiments and detailed descriptions are provided below:

[0020] Certain terms are used in the specification and claims to refer to specific elements. However, those skilled in the art will understand that the same element may be referred to by different names. Moreover, the specification and claims do not distinguish elements by differences in name, but by differences in the overall technology of the elements. The term "comprising" as used throughout the specification and claims is an open-ended term and should be interpreted as "comprising but not limited to". Furthermore, the term "coupled" here includes any direct and indirect means of connection. Therefore, if a first device is described as coupled to a second device, it means that the first device can be directly connected to the second device, or can be indirectly connected to the second device through other devices or other means of connection.

[0021] In view of the fact that conventional memory devices provide a stable o-phase but generate other electrical problems, the present invention proposes a memory cell with silicon nitride and a method for manufacturing the same, which is formed between a second electrode layer and a ferroelectric layer through an interface capping layer, thereby enabling the ferroelectric layer of the present invention to provide a stable o-phase and avoid generating other electrical problems, such as avoiding leakage current.

[0022] In the following, the invention will be described in detail by way of the drawings illustrating various embodiments thereof. However, the concept of the invention may be embodied in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein.

[0023] First, please refer to Figures 1A and 2A, which are schematic diagrams of the structure of the memory cell of the present invention and circuit diagrams of the memory device with silicon nitride of the present invention. As shown in Figure 1A, the memory cell 12 of the present invention includes a ferroelectric capacitor element 16. The ferroelectric capacitor element 16 includes a first electrode layer 162, a ferroelectric layer 164, an interface capping layer (ICL) 166, and a second electrode layer 168. The first electrode layer 162 is disposed on the silicon substrate Si. The ferroelectric layer 164 is disposed on the first electrode layer 162. The interface capping layer 166 is disposed on the ferroelectric layer 164. The second electrode layer 168 is disposed on the interface capping layer 166. The area of ​​the interface capping layer 166 is equal to the area of ​​the ferroelectric layer 164, and the area of ​​the second electrode layer 168 is equal to the area of ​​the interface capping layer 166. The area of ​​the capping layer 166, the first electrode layer 162 is coupled to ground, the second electrode layer 168 is coupled to the switching element 14, the material of the interface capping layer 166 is selected from silicon nitride (SiNx), thereby providing a ferroelectric layer 164 with a stable o phase, reducing the coefficient of thermal expansion of the ferroelectric layer 164, increasing the tensile stress of the ferroelectric layer 164, increasing the polarization of the ferroelectric layer 164, and preventing oxygen ions from entering the ferroelectric layer 164.

[0024] Furthermore, as shown in Figure 1B, since the area of ​​the second electrode layer 168 is equal to the area of ​​the interface cover layer 166, the interface cover layer 166 can be combined with the second electrode layer 168 to form a plurality of cylindrical bodies on the ferroelectric layer 164. That is, the area of ​​the interface cover layer 166 can be smaller than the area of ​​the ferroelectric layer 164. In this case, the material of the interface cover layer 16 can be selected from silicon oxynitride (SiON), which is also a silicon nitride (SiNx).

[0025] As shown in Figure 2, the memory device 10 of the present invention includes a plurality of memory cells 12 and a silicon substrate Si. This embodiment is illustrated by each memory cell 12 including a switching element 14 and a ferroelectric capacitor element 16. Each memory cell 12 is coupled to a word line and a bit line through a corresponding switching element 14, and is coupled to an access control circuit 30. The word line controls the switching element 14 to be turned on or off, so as to access the corresponding bit data in the ferroelectric capacitor element 16 through the bit line. Therefore, by design, these memory cells 12 are coupled to a plurality of word lines WL1-WLn and a plurality of bit lines BL1-BLn, and are coupled to the access control circuit 30.

[0026] The access control circuit 30 described above is coupled to the ferroelectric capacitor element 16 via a switching element 14. This is only one embodiment of the present invention. Alternatively, as shown in Figure 3, the access control circuit 30 can have a built-in row decoder 32 and a column decoder 34, and the ferroelectric capacitor elements 16 of the memory cells 12 can be coupled via the character lines WL1-WLn and the bit lines BL1-BLn, respectively. That is, the memory cells 12 only contain the ferroelectric capacitor elements 16. Ferroelectric capacitor elements 16 are coupled to the word lines via the first electrode layer 162 and to the bit lines via the second electrode layer 168. This is equivalent to the ferroelectric capacitor elements 16 being coupled to the word lines via the first electrode layer 162 and to the bit lines via the second electrode layer 168. Thus, the memory cells 12 are coupled to the word lines WL1-WLn and the bit lines BL1-BLn, thereby simplifying the structure of the memory cells 12 and increasing the density of the memory cells 12.

[0027] Please refer to Figure 4, which is a flowchart of one embodiment of the present invention. As shown in the figure, the method for manufacturing a memory cell of the present invention is applied to manufacturing at least one memory cell 12 of the memory device 10. The steps of the manufacturing method include:

[0028] Step S10: Provide a silicon substrate;

[0029] Step S20: Form a first electrode layer on a silicon substrate;

[0030] Step S30: Form a ferroelectric layer on the first electrode layer;

[0031] Step S40: Form an interface capping layer on the ferroelectric layer using nitride;

[0032] Step S50: Form a second electrode layer on the interface capping layer; and

[0033] Step S60: Perform an annealing process to form the memory cell of the memory device.

[0034] In step S10, as shown in Figure 5A, the fabrication of a silicon nitride-containing memory device 10 in this embodiment is performed on a 4-inch silicon substrate. Specifically, an n-type doped silicon substrate is provided as the silicon substrate Si and disposed on a stage 40 in a chamber C for subsequent steps. In step S20, as shown in Figure 5B, an radio frequency (RF) sputtering process is used on the silicon substrate Si. A titanium nitride (TiN) target 42 is driven by a sputtering source SP to release titanium nitride (TiN) atoms 422, and a titanium nitride (TiN) layer with a thickness of 50 nm is deposited on the silicon substrate Si to form a first electrode layer 162 on the silicon substrate Si. Subsequently, in step S30, as shown in Figure 5C, an atomic layer deposition (ALD) process is used to deposit a 10 nm thick Hf 0.5Zr 0.5O 2 (HZO) thin film through Hf 0.5Zr 0.5O 2 (HZO) atoms 44 on the first electrode layer 162, thereby forming the ferroelectric layer 164 on the first electrode layer 162.

[0035] Continuing from the above, after the HZO thin film as the ferroelectric layer 164 is deposited, in step S40, as shown in Figure 5D, using the RF sputtering process, silicon nitride (Si 3N 4) (99.9%) target 46 is deposited at 100W power, 15 standard cubic centimeters per minute (sccm) of argon (Ar) gas and 15 sccm of nitrogen (N 2) gas under deposition conditions to release silicon nitride (Si 3N 4) atoms 462 corresponding to the silicon nitride (Si 3N 4) (99.9%) target 46, and silicon nitride (Si 3N 4) is deposited on the ferroelectric layer 164 to form the interface capping layer 166. Then, in step S50, as shown in Figure 5E, using the RF sputtering process, ruthenium (Ru) target 48 is deposited at 25 sccm... Under argon deposition conditions, ruthenium (Ru) atoms 482 corresponding to the ruthenium (Ru) target 48 are released, and ruthenium (Ru) with a thickness of 50 nm is deposited on the interface capping layer 166 to form the second electrode layer 168. Subsequently, in step S60, as shown in Figure 5F, the stacked ruthenium (Ru) / silicon nitride (Si3N4) / HZO thin film / titanium nitride (TiN) layer is annealed in a nitrogen atmosphere at a temperature of 400°C for 1 hour (for example, using a microwave transmitter 50 as a heating source, microwaves 502 are emitted to the stacked ruthenium (Ru) / silicon nitride (Si3N4) / HZO thin film / titanium nitride (TiN) layer for annealing for 1 hour) to form at least one memory cell 12 of the memory device 10, particularly the ferroelectric capacitor element 16.

[0036] The materials of the first electrode layer 162 and the second electrode layer 168 in the above embodiments are selected from titanium nitride (TiN) and ruthenium (Ru), respectively, and may also be selected from zirconium (Zr), hafnium (Hf), titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), silicon tantalumide (TaSi), tantalum carbonitride (TaCN), titanium aluminum nitride (TiAlN), zinc (Zn), nickel (Ni), nickel silicon (NiSi), ruthenium (Ru), carbon (C), silicon (Si), silicon nitride (SiNx), germanium (Ge), platinum (Pt), aluminum (Al), aluminum nitride (AlN), yttrium (Y), thorium (Gd), strontium (Sr), tungsten (W), tungsten silicon (WSi), tungsten nitride (WN), gallium (Ga) and gallium nitride (GaN), or combinations thereof. The material of the ferroelectric layer 164 in the above embodiments is selected from zirconium hafnium oxide (HfZrOx), and may also be selected from silicon hafnium oxide (HfSiOx), hafnium oxide (HfOx), yttrium hafnium oxide (HfYOx), thorium hafnium oxide (HfGdOx), strontium hafnium oxide (HfSrOx), titanium strontium oxide (SrTiOx), calcium strontium titanate (SrCaTiO3), Ag(Nb1-xTax)O3, barium strontium titanate (BaSrTiO3), barium titanate (BaTiO3), zirconium oxide (ZrOx), or aluminum hafnium oxide (HfAlOx), or a combination of the above materials.

[0037] The material of the interface cover layer 166 in the above embodiments is selected from silicon nitride, and may also be selected from metal nitride or metal carbonitride, or a combination of the above materials, especially the metal nitride is titanium silicon nitride (TiSiN) or manganese silicon nitride (MoSiN).

[0038] Through the above manufacturing steps, the present invention manufactures four embodiments, each of which has an interface cover layer 166 with a different thickness, namely, embodiment S1 (thickness about 1 nm), embodiment S2 (thickness about 1.5 nm), embodiment S3 (thickness about 2 nm) and embodiment S4 (thickness about 3 nm).

[0039] As shown in Figures 6A and 6B, these are cross-sectional images of the ferroelectric capacitor element 16 of the memory device 10 in Examples S1 and S3, respectively, obtained using a high-resolution transmission electron microscope (HRTEM). In the memory device of Example S3, the thickness of the silicon nitride (Si3N4) deposited interface capping layer 166 is 1.9 nm, while the memory device of Example S1 has a thinner interface capping layer 166 (Si3N4) with a thickness of 1.1 nm. After being woken up (working cycle count exceeding 1E+3 times), the ferroelectric layer 164 of Example S1 is shown in Figure 6C, and the ferroelectric layer 164 of Example S3 is shown in Figure 6D. In the 10 nm thick ferroelectric layer (HZO), the analysis results using geometric phase analysis (GPA) are shown in Figure 6E. This shows that the o-phase distribution ratio (Phase Fraction (%)) remains relatively stable (47.1% to 46.9%), while the r-phase distribution ratio remains relatively stable (47.1% in Example S1 and 46.9% in Example S3). At this time, the r-phase distribution ratio in Example S3 is 23.6%, and the r-phase ratio in the ferroelectric layer 164 of the memory device 10 in Example S1 decreases to 10.3%.

[0040] Furthermore, as shown in Figure 6E, compared with Example S1, the proportion of m-phase distribution in the ferroelectric layer of the memory device in Example S3 is increased (compared to 10.4% in Example S1, Example S3 increases to 23.1%).

[0041] Figure 7A shows the polarization-to-voltage characteristic curve of the Ru / Si 3N 4 / Hf 0.5Zr 0.5O 2 / TIN ferroelectric capacitor element 16 measured under power supply conditions of ±4V and 1kHz.

[0042] The interface cover layer 166 of the memory device in Example S1 has the thinnest thickness (1 nm) and its highest residual polarization (2Pr) value is 53.4 μC / cm2.

[0043] However, as the thickness of the interface capping layer 166 formed by the nitride system increases, the polarization value decreases in Examples S2 (thickness 1.5 nm), S3 (thickness 2 nm), and S4 (thickness 3 nm). According to Figures 6C, 6D, and 6E, the increased thickness of the interface capping layer 166 formed by silicon nitride Si3N4 leads to a decrease in polarization value due to the increased distribution ratio of the parasitic m-phase.

[0044] The relative voltage (1.5 to 4V) correction in the memory device of Example S1 is shown in Figure 7B as the Pr value. Under the conditions of power supply ±3V and frequency 100Hz, as shown in Figure 7C, the ferroelectric capacitor element 16 of Example S1 can be observed to have a wake-up effect with increased window and coercive electric field (±ΔEC) shift. As shown in Figure 7D, it shows the +Pr value and coercive electric field (±ΔEC) shift of the ferroelectric capacitor element 16 of Examples S1, S2, S3 and S4. Due to the reduction in the formation of monoclinic crystal phase and the increase in the r crystal phase of ferroelectric layer 164, the reduction in the thickness of interface capping layer 166 leads to an increase in polarization value. The thicker interface capping layer 166 formed by silicon nitride (Si3N4) prevents oxidation of the second electrode (Ru in this embodiment) 168, while a thinner interface capping layer 166 leads to the formation of ruthenium oxide (RuO2) (5.1 eV) at the interface with the second electrode layer 168 after wake-up. Due to the formation of ruthenium oxide (RuO2), the effective work function of the second electrode layer 168 is changed, making it higher than that of the first electrode layer 162 (4.65 eV), thereby causing a significant change in the coercive electric field (±ΔEC) of the memory device 10 in embodiment S1.

[0045] As shown in Figure 7E, the memory device 10 of embodiment S1, with a thinner interface capping layer 166, has the highest positive coercive electric field (+Ec), which is due to the change in the effective metal work function at the second electrode layer 168 caused by the formation of RuO2 by Ru. The thinner SiNxOy layer formed at the ferroelectric layer 164 and the interface capping layer 166 further increases the positive coercive electric field (+Ec) due to the built-in potential caused by the trap charge and shielding effect. Conversely, the thicker interface capping layer 166 behaves more like a bulk material, resulting in a decrease in the positive coercive electric field (+Ec).

[0046] However, since the interface between the first electrode layer 162 and the ferroelectric layer 164 is the same in all embodiments of the ferroelectric capacitor element 16, the negative coercive electric field (-Ec) remains unchanged. Due to the increased thickness of the interface capping layer 166, the m-phase of the ferroelectric layer 164 increases. Compared with the leakage current density of 49.1 μA / cm2 in Embodiment S2 and the leakage current density of 16.3 μA / cm2 in Embodiment S1, the ferroelectric capacitor element 16 of Embodiment S3 exhibits a higher leakage current density of 231 μA / cm2, corresponding to an increased proportion of the m-phase distribution in the ferroelectric layer 164. Conversely, when the interface capping layer 166 becomes thicker and acts as a bulk barrier layer, the leakage current density of the ferroelectric capacitor element 16 of Embodiment S4 is 53.6 μA / cm2, which is relatively lower than that of Embodiment S3.

[0047] Regarding the collapse electric field, the memory device 10 of Embodiment S1, which has a thinner interface cover layer 166, exhibits the highest value, with a collapse electric field of 4 MV / cm, exceeding the collapse electric field of Embodiment S2 (3.65 MV / cm) and Embodiment S3 (3.5 MV / cm), which have thicker interface cover layers 166. On the other hand, compared with Embodiments S2 and S3, the memory device 10 of Embodiment S4 has the thickest interface cover layer 166, yet exhibits an even better collapse electric field (3.81 MV / cm).

[0048] In the memory device of Example S1, the highest barrier height is 2.15 eV, which is the barrier height extracted based on the Fowler-Nordheim tunneling slope fitted to the high-field region (≥2.6 MV / cm) under negative polarity. In contrast, the memory devices 10 of Examples S2, S3, and S4 have a thicker interface capping layer 166, resulting in lower energy levels of 1.92 eV, 1.59 eV, and 0.83 eV, respectively. The thinner interface capping layer 166 is used to adjust the effective work function (Pm) of the second electrode layer 168 through oxidation (RuO2), while the thicker interface capping layer 166 acts as a barrier to oxygen movement, thereby reducing the degree of oxidation of the second electrode layer 168.

[0049] As shown in Figures 8A and 8B, the device of Example S2 underwent a long-term durability cycle test (3 × 10¹¹ cycles at ±4V and 0.1 μs), and after 106 cycles at ±4V and 0.1 μs, the fatigue rate was approximately 39.9%, indicating that the ferroelectric layer of Example S1 collapsed. However, as shown in Figure 8A, the device of Example S1 exhibited a long durability of 5 x 10¹⁰ at a lower operating voltage of ±3.5V and 0.1 μs (Figure 3(a)). Compared to the 1 nm thick interface capping layer 166 of Example S1, the 1.5 nm thick interface capping layer 166 in the ferroelectric capacitor element 16 of Example S2 has a positive effect on durability cycling due to the higher proportion of the m-phase distribution in the ferroelectric layer 164. As shown in Figure 8B, the good polarization of 36 μC / cm² and long durability of 3 × 10¹¹ cycles were compared with results from other reports, and the results showed relatively superior performance.

[0050] Figures 9B to 9D show the fatigue state of the ferroelectric capacitor element 16 of Embodiment S1, including the initial state, the awakened state, and after 10 cycles. Initially, in the initial state, the ferroelectric capacitor element 16 of Embodiment S1 has a high t-phase distribution ratio. After awakening, some of the t-phase of the ferroelectric capacitor element 16 transforms into the m-phase. During this process, the interface between the ferroelectric layer 164 and the interface capping layer 166 is oxidized by collecting oxygen from Hf 0.5Zr 0.5O 2, forming a thin SiNxOy interface layer. At the same time, as shown in Figure 9A, a thin TiNxOy interface layer is also formed at the interface between the first electrode layer 162 and the ferroelectric layer 164 due to oxidation, increasing the durability cycle life. As the interface between the first electrode layer 162 and the ferroelectric layer 164 becomes more oxidized, the interface transforms into titanium oxide (TiO2), while the thin SiNxOy interface layer acts as an oxygen ion reservoir. The TiO2 interface layer at the first electrode layer 162 and the ferroelectric layer 164 forms more oxygen vacancies, causing the coercive electric field (Ec) to decrease with increasing durability cycling.

[0051] As shown in Figures 9E to 9G, the electron energy loss spectrum (EELS) of the ferroelectric capacitor element 16 of Example S1 in its original and awakened states shows the area between the first electrode 162 and the ferroelectric layer 164, the ferroelectric layer 164, and the interface capping layer 166. Oxygen migrates from the ferroelectric layer 164 to the area between the first electrode 162 and the ferroelectric layer 164 and the interface capping layer 166, resulting in the formation of oxygen vacancies in the ferroelectric layer 164. Reducing the thickness of the interface capping layer 166 leads to significantly higher polarization (2P, 53.4 μC / cm²). Furthermore, optimizing the thickness of the interface capping layer 166 (approximately 1.5 nm) achieves excellent long durability (>3 × 10¹¹) because the proportion of rhombohedral phase in the ferroelectric layer 164 is relatively high, while the formation of monoclinic phase is reduced.

[0052] In summary, the present invention is a memory device with silicon nitride, comprising a plurality of memory cells and a silicon substrate. The memory cells are disposed on the silicon substrate and are each coupled to an access control circuit via a word line and at least one bit line. Each memory cell comprises a first electrode layer, a ferroelectric layer, an interface capping layer, and a second electrode layer. The first electrode layer is disposed on the silicon substrate, the ferroelectric layer is disposed on the first electrode layer, and the interface capping layer is disposed on the ferroelectric layer. The material of the interface capping layer is selected from silicon nitride (SiNx); and the second electrode layer is disposed on the interface capping layer. Through the interface capping layer formed by silicon nitride, the ferroelectric layer is provided with various electrical advantages and improved durability for application in various ferroelectric memory devices.

[0053] Therefore, this invention is indeed novel, inventive and industrially applicable, and should undoubtedly meet the requirements for patent application under the Patent Law of our country. Therefore, we hereby file an invention patent application in accordance with the law, and earnestly pray that the Bureau will grant the patent as soon as possible.

[0054] However, the above description is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. All equivalent changes and modifications made to the shape, structure, features and spirit described in the claims of the present invention should be included in the scope of the claims of the present invention. [Simplified Explanation of the Diagram]

[0018] Figure 1A: A schematic diagram of the structure of a memory unit according to one embodiment of the present invention; Figure 1B: A schematic diagram of another structure of a memory unit according to one embodiment of the present invention; Figure 2: A circuit diagram of a memory device according to one embodiment of the present invention; Figure 3: A circuit diagram of another memory device according to one embodiment of the present invention; Figure 4: A flowchart of a method for manufacturing a memory unit according to one embodiment of the present invention; Figure 5A: A schematic diagram of the steps of a method for manufacturing a memory unit according to one embodiment of the present invention; Figure 5B: A schematic diagram of the steps of a method for manufacturing a memory unit according to one embodiment of the present invention; Figure 5C: A schematic diagram of the steps of a method for manufacturing a memory unit according to one embodiment of the present invention; Figure 5D: A schematic diagram of the steps of a method for manufacturing a memory unit according to one embodiment of the present invention; Figure 5E: A schematic diagram of the steps of a method for manufacturing a memory unit according to one embodiment of the present invention; Figure 5F: A schematic diagram of the steps of a method for manufacturing a memory unit according to one embodiment of the present invention; Figure 6A: A schematic diagram of a transmission electron microscope image of embodiment S1 of the present invention; Figure 6B: A schematic diagram of a transmission electron microscope image of Embodiment S3 of the present invention; Figure 6C: A partial schematic diagram of a transmission electron microscope image after wake-up of Embodiment S1 of the present invention; Figure 6D: A partial schematic diagram of a transmission electron microscope image after wake-up of Embodiment S3 of the present invention; Figure 6E: A schematic diagram of the crystal phase distribution ratio of Embodiments S1 and S3 of the present invention; Figure 7A: A schematic diagram of voltage versus polarization in one embodiment of the present invention; Figure 7B: A schematic diagram of voltage versus Pr value in one embodiment of the present invention; Figure 7C: A schematic diagram of voltage versus polarization and Pr value in Embodiment S1 of the present invention; Figure 7D: A schematic diagram of the silicon nitride thickness of the interface capping layer in Embodiments S1-S4 of the present invention and its effect on coercive electric field shift (±ΔEC); Figure 7E: This is a schematic diagram of voltage versus coercive electric field (EC) in embodiments S1-S4 of the present invention; Figure 7F: This is a schematic diagram of electric field (E) versus current density in embodiments S1-S4 of the present invention; Figure 8A: This is a schematic diagram of cycle number versus polarization in the present invention; Figure 8B: This is a schematic diagram of electric field versus endurance cycle in the present invention; Figure 9A: This is a schematic diagram of signal transmission in the silicon nitride-based memory devices of embodiments S1 and S2 of the present invention;Figure 9B: A schematic diagram of the crystal phase distribution of the ferroelectric capacitor element in its original state according to Embodiment S1 of the present invention; Figure 9C: A schematic diagram of the crystal phase distribution of the ferroelectric capacitor element in its awakened state according to Embodiment S1 of the present invention; Figure 9D: A schematic diagram of the crystal phase distribution of the ferroelectric capacitor element in its fatigued state according to Embodiment S1 of the present invention; Figure 9E: An electron energy loss spectrum diagram between the first electrode and the ferroelectric layer of the ferroelectric capacitor element in Embodiment S1 of the present invention; Figure 9F: An electron energy loss spectrum diagram of the ferroelectric layer of the ferroelectric capacitor element in Embodiment S1 of the present invention; and Figure 9G: An electron energy loss spectrum diagram of the interface capping layer of the ferroelectric capacitor element in Embodiment S1 of the present invention.

Claims

1. A memory cell with a silicon nitride, used in a memory device, the memory device comprising a plurality of memory cells and a silicon substrate, each memory cell disposed on the silicon substrate and coupled to an access control circuit via a word line and at least one bit line, each memory cell comprising: a first electrode layer formed on the silicon substrate; a ferroelectric layer disposed on the first electrode layer; an interface capping layer formed on the ferroelectric layer, the material of the interface capping layer being selected from metal silicon nitride or metal carbonitride, the area of ​​the interface capping layer being less than or equal to the area of ​​the ferroelectric layer; and a second electrode layer formed on the interface capping layer, the area of ​​the second electrode layer being equal to the area of ​​the interface capping layer; wherein the thickness of the interface capping layer is 1 nanometer to 3 nanometers.

2. The memory device with silicon nitride as described in claim 1, wherein the metal silicon nitride is titanium silicon nitride (TiSiN) or manganese silicon nitride (MoSiN).

3. The memory device with nitride as described in claim 1, wherein the material of the ferroelectric layer is selected from the group consisting of zirconium hafnium oxide (HfZrOx), silicon hafnium oxide (HfSiOx), hafnium oxide (HfOx), yttrium hafnium oxide (HfYOx), thorium hafnium oxide (HfGdOx), strontium hafnium oxide (HfSrOx), titanium strontium oxide (SrTiOx), calcium strontium titanate (SrCaTiO3), Ag(Nb1-xTax)O3, barium strontium titanate (BaSrTiO3), barium titanate (BaTiO3), zirconium oxide (ZrOx), or aluminum hafnium oxide (HfAlOx).

4. The memory device with silicon nitride as described in claim 1, wherein the materials of the first electrode layer and the second electrode layer are selected from the group consisting of zirconium (Zr), hafnium (Hf), titanium nitride (TiN), titanium (Ti), tantalum (Ta), tantalum nitride (TaN), silicon tantalum nitride (TaSi), tantalum carbonitride (TaCN), titanium aluminum nitride (TiAlN), zinc (Zn), nickel (Ni), nickel silicon nitride (NiSi), ruthenium (Ru), carbon (C), silicon (Si), silicon nitride (SiNx), germanium (Ge), platinum (Pt), aluminum (Al), aluminum nitride (AlN), yttrium (Y), thorium (Gd), strontium (Sr), tungsten (W), tungsten silicon nitride (WSi), tungsten nitride (WN), gallium (Ga), and gallium nitride (GaN).

5. A method for manufacturing a memory cell with silicon nitride, comprising the steps of: providing a silicon substrate; forming a first electrode layer on the silicon substrate using an radio frequency sputtering process; forming a ferroelectric layer on the first electrode layer; forming an interface capping layer on the ferroelectric layer using a silicon nitride and the radio frequency sputtering process, wherein the area of ​​the interface capping layer is less than or equal to the area of ​​the ferroelectric layer; forming a second electrode layer on the interface capping layer using the radio frequency sputtering process, wherein the area of ​​the second electrode layer is equal to the area of ​​the interface capping layer; and performing an annealing process to form at least one memory cell; wherein the thickness of the interface capping layer is 1 nanometer to 3 nanometers.

6. The method for manufacturing a memory cell containing silicon nitride as described in claim 6, wherein in the step of forming a ferroelectric layer on the first electrode layer, an atomic layer deposition (ALD) process is used to perform the step of forming a ferroelectric layer on the first electrode layer.

7. A method for manufacturing a memory cell containing silicon nitride as described in claim 6, wherein in the step of performing an annealing process to form the memory device, the annealing is carried out in a nitrogen (N2) atmosphere at 350°C to 450°C for 0.5 to 1.5 hours.

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