Chip packaging structure, semiconductor structure and fabricating method thereof

Abstract

Embodiments of a wafer packaging structure, a semiconductor structure, and a method for fabricating the same are disclosed. The wafer packaging structure includes a substrate, comprising a signal transmission wiring structure embedded in the substrate and a heat transfer wiring structure embedded in the substrate. The wafer packaging structure also includes a first wafer located on the substrate and electrically connected to the signal transmission wiring structure. The wafer packaging structure further includes at least one thermally conductive structure located on the substrate, in thermal contact with the heat transfer wiring structure, and laterally surrounding the first wafer.

Description

Wafer Packaging Structure, Semiconductor Structure and Method of Fabricating the Same The present disclosure generally relates to the field of semiconductor technology, and more particularly, to a wafer packaging structure, a related semiconductor structure, and a method of fabricating the same. As the power consumption of semiconductor wafers continues to increase, the requirements for heat dissipation of the packaging become higher. However, on the one hand, the packaging materials have poor thermal conductivity, and on the other hand, the existing heat dissipation methods are mainly processed at the system level. There is a need for a special heat conduction channel inside the wafer package. Embodiments of a wafer packaging structure, a semiconductor structure, and a method of fabricating the same are described in the present disclosure. One aspect of the present disclosure provides a wafer packaging structure, including: a substrate including a signal transmission wiring structure embedded in the substrate and a heat transmission wiring structure embedded in the substrate; a first wafer located on the substrate and electrically connected to the signal transmission wiring structure; and at least one heat conduction structure located on the substrate, in thermal contact with the heat transmission wiring structure, and laterally surrounding the first wafer. In some embodiments, the wafer packaging structure further includes: a molding compound layer located on the substrate and covering the first wafer, wherein at least one heat conduction structure is embedded in the molding compound layer; and a heat conduction cover located on the molding compound layer and in thermal contact with at least one heat conduction structure. In some embodiments, the wafer packaging structure further includes: a ball grid array located on a side of the substrate opposite to the first wafer and the at least one heat conduction structure, the ball grid array including: a plurality of signal solder balls in contact with the signal transmission wiring structure; and at least one heat solder ball in contact with the heat transmission wiring structure. In some embodiments, at least one heat conduction structure includes: a plurality of heat conduction blocks, each heat conduction block vertically penetrating the molding compound layer and including a top surface in contact with the heat conduction cover and a bottom surface in contact with a heat pad located on the substrate, the heat pad being connected to the heat transmission wiring structure. In some embodiments, the ratio between the first lateral area of each heat conduction block and the second lateral area of the first wafer is in the range of approximately 1 / 20 to approximately 1 / 10. In some embodiments, the wafer packaging structure further includes: a second wafer located on the substrate and outside the at least one heat conduction structure. In some embodiments, the wafer packaging structure further includes: a first operating power of the first wafer being greater than a second operating power of the second wafer. In some embodiments, the first wafer includes at least one of a microprocessing wafer, a logic control wafer, a power management wafer, a driver wafer, and an analog wafer; and the second wafer includes at least one of a memory wafer and a sensing wafer. In some embodiments, the wafer packaging structure further includes: a third wafer, which is located on the substrate and beside the first wafer, and is laterally surrounded by at least one heat conducting structure. In some embodiments, a part of at least one heat conducting structure is located between the third wafer and the first wafer. In some embodiments, the material of at least one heat conducting structure has a thermal conductivity greater than 1. In some embodiments, the material is one of a metal, a ceramic material, or a silicon material. In some embodiments, the ratio between the first wiring width of the heat transfer wiring structure and the second wiring width of the signal transmission wiring structure in the wafer packaging structure is in the range of approximately 1.5 to approximately 2. Another aspect of the present disclosure provides a method of forming a wafer packaging structure, including: providing a substrate, which includes: a signal transmission wiring structure embedded in the substrate and a heat transfer wiring structure embedded in the substrate; forming at least one heat conducting structure located on a first side of the substrate and in thermal contact with the heat transfer wiring structure; forming a first wafer located on the first side of the substrate and laterally surrounded by at least one heat conducting structure; and electrically connecting the first wafer to the signal transmission wiring structure. In some embodiments, the method further includes: forming a molding compound layer on the first side of the substrate to cover the first wafer and at least one heat conducting structure; and forming a heat conducting cover on the molding compound layer, the heat conducting cover being located on the molding compound layer and in thermal contact with at least one heat conducting structure. In some embodiments, the method further includes: forming a ball grid array on a second side of the substrate opposite to the first side, including: forming a plurality of signal solder balls in contact with the signal transmission wiring structure, and forming at least one heat solder ball in contact with the heat transfer wiring structure. In some embodiments, forming at least one heat conducting structure includes: forming a plurality of heat conducting blocks, each heat conducting block being located on a heat pad, the heat pad being located on the first side of the substrate and connected to the heat transfer wiring structure. In some embodiments, at least one heat conducting structure and the first wafer are formed on the substrate by using a surface mount technology (SMT) process. In some embodiments, the method further includes: forming a second wafer located on the first side of the substrate and outside at least one heat conducting structure, wherein a first operating power of the first wafer is greater than a second operating power of the second wafer. Another aspect of the present disclosure provides a semiconductor structure, comprising: a printed circuit board; a chip packaging structure, the chip packaging structure comprising: a substrate, the substrate comprising: a signal transmission wiring structure embedded in the substrate and a heat transmission wiring structure embedded in the substrate; a first chip located on the substrate and electrically connected to the signal transmission wiring structure; and at least one heat conduction structure located on the substrate, in thermal contact with the heat transmission wiring structure, and laterally surrounding the first chip; and a ball grid array located on a side of the substrate opposite to the first chip and the at least one heat conduction structure, and connected between the printed circuit board and the substrate, the ball grid array comprising: a plurality of signal solder balls in contact with the signal transmission wiring structure; and at least one heat solder ball in contact with the heat transmission wiring structure. Based on the description, claims and drawings of the present disclosure, those skilled in the art can understand other aspects of the present disclosure. Although specific structures and arrangements have been discussed, it should be understood that this is only for illustrative purposes. Those skilled in the relevant art will recognize that other structures and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure can also be used in various other applications. Note that references in the specification to "one embodiment", "an embodiment", "exemplary embodiments", "some embodiments", etc. indicate that the described embodiments may include specific features, structures or characteristics, but each embodiment may not necessarily include the specific feature, structure or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such feature, structure or characteristic in connection with other embodiments is within the knowledge of those skilled in the relevant art. Generally, terms can be understood at least in part from their usage in context. For example, depending at least in part on the context, as used herein, the term "one or more" can be used to describe any feature, structure or characteristic in a singular sense, or can be used to describe a combination of features, structures or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as "a" or "the" can also be understood to convey a singular usage or a plural usage. Additionally, again depending at least in part on the context, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but can allow for additional factors that may not be explicitly described. It should be readily understood that the meanings of "on", "above", and "over" in this disclosure should be construed in the broadest manner such that "on" not only means "directly on something", but also includes the meaning of "on something" with intermediate features or layers therebetween. Further, "above" or "over" not only means "above something" or "over something", but can also include the meaning of "above something" or "over something" with no intermediate features or layers therebetween (i.e., directly on something). In addition, for ease of description, spatial relative terms such as "under", "below", "lower", "over", "upper", etc. may be used herein to describe the relationship of one element or feature shown in the figures to another (or other) element or feature. Except for the orientation depicted in the figures, the spatial relative terms are intended to encompass different orientations of the device during use or process steps. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and similarly the spatial relative descriptors used herein may be interpreted accordingly. As used herein, the term "substrate" refers to a material on which subsequent material layers are added. The substrate includes a "top" surface and a "bottom" surface. The front surface of the substrate is typically where the semiconductor device is formed, and thus, unless otherwise specified, the semiconductor device is formed on the top side of the substrate. The bottom surface is opposite the front surface, and thus, the bottom side of the substrate is opposite the top side of the substrate. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Further, the substrate may include various semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer. As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer has a top side and a bottom side, where the bottom side of the layer is adjacent to the substrate and the top side is relatively farther from the substrate. The layer may extend over the entire underlying or overlying structure, or may have a range less than the underlying or overlying structure. Further, the layer may be a region of a uniform or non-uniform continuous structure having a thickness less than that of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any set of horizontal planes at the top and bottom surfaces. The layer may extend horizontally, vertically, and / or along a tapered surface. The substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. The layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (wherein contact points, interconnect lines, and / or vertical interconnect channels (VIAs) are formed) and one or more dielectric layers. As used herein, the term "nominal / nominally" refers to the expected value or target value of a characteristic or parameter set for a component or process step during the design phase of a product or process, as well as a range of values above and / or below the expected value. The range of values may be due to minor variations in the manufacturing process or tolerances. As used herein, the term "about" indicates a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" may indicate a value of a given quantity that varies within, for example, 10 - 30% of that value (e.g., ±10%, ±20%, or ±30% of that value). In the present disclosure, the term "horizontal / horizontally" means nominally parallel to the lateral surface of the substrate, and the term "vertical / vertically" means nominally perpendicular to the lateral surface of the substrate. The present disclosure provides a wafer package structure with high thermal conductivity. The manufacturing process can be modularized. In the disclosed wafer package space, a certain number of heat conducting structures of the same or different sizes can be packaged around the wafer stack, and connected between the metal layer located in the front of the package and the solder balls located in the back to achieve a strong heat dissipation effect. Through the surface mount technology (SMT) packaging process, the connection between the high thermal conductivity material and the copper layer of the substrate and the connection of the surface metal coating can be achieved. Thus, high thermal conductivity within the package structure can be obtained, thereby significantly improving product heat dissipation and product performance. The disclosed manufacturing process for forming the disclosed wafer package structure can be modularized, making it relatively simple. Conventional equipment can be used for the disclosed manufacturing process without a large amount of cost investment. A modular packaging solution can be adopted to reduce the difficulty of packaging and handling, which is conducive to mass production. The disclosed design can achieve a better internal heat conduction effect of the wafer package structure without changing the external dimensions of the existing package and the existing packaging materials. The heat conducting structure can be selected from materials with high thermal conductivity and high mechanical strength, such that the entire wafer package structure can have a better heat dissipation effect and better mechanical properties. In addition, the disclosed manufacturing process can allow for flexible design of different sizes and / or different quantities of the heat conducting structure according to space requirements. Therefore, the heat dissipation conditions of high-power wafers within the disclosed wafer package structure can be significantly improved, and the operating temperature of the disclosed wafer package structure can be significantly reduced. Referring to FIG. 1, a schematic diagram of an exemplary semiconductor device structure according to some embodiments of the present disclosure is shown in a perspective side view. As shown in FIG. 1, the semiconductor device structure may include a wafer package structure 100, which includes a substrate 120, a package body 110 located on a first side of the substrate 120, and a ball grid array (BGA) 130 located on a second side of the substrate 120 opposite to the first side. It should be noted that the semiconductor device structure may further include any other suitable components not shown in FIG. 1. For example, the semiconductor device may further include a printed circuit board (PCB), and the wafer package structure 100 is mounted on the printed circuit board (PCB) via the BGA 130. The substrate 120 may be any suitable semiconductor substrate having any suitable structure, such as a single crystal silicon monolayer substrate, a polysilicon monolayer substrate, a multilayer substrate of polysilicon and metal, etc. The substrate 120 may include a signal transmission wiring structure 146 and a heat transmission wiring structure 148 embedded in the substrate. The signal transmission wiring structure 146 may include any suitable conductive interconnect structure, such as a conductive via and a patterned conductive layer, etc., and is configured to transmit electrical signals. The heat transmission wiring structure 148 may include any suitable heat conductive interconnect structure, such as a heat conduction channel, and is configured to transmit heat. The signal transmission wiring structure 146 and the heat transmission wiring structure 148 may be isolated from each other. In some embodiments, the signal transmission wiring structure 146 may include any suitable conductive material, such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), platinum (Pt), cobalt (Co), titanium (Ti), chromium (Cr), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tungsten (W), rhenium (Re), graphite, carbon black, combinations thereof, and / or other materials known to those skilled in the art. The heat transmission wiring structure 148 may include any suitable heat conductive material, such as Ag, Cu, aluminum (Al), aluminum nitride, silicon carbide, W, graphite, zinc (Zn), combinations thereof, and / or other materials known to those skilled in the art. In some embodiments, the ratio between the first wiring width of the heat transmission wiring structure 148 and the second wiring width of the signal transmission wiring structure 146 may be in the range of approximately 1.5 to approximately 2. The package 110 may include a first die / die stack 162 and a second die / die stack 164, which are attached to the first side of the substrate 120 through an adhesive film (not shown). In some embodiments, the first die / die stack 162 and the second die / die stack 164 may be any suitable semiconductor die / die stack including one or more semiconductor wafers. The first die / die stack 162 may include a low-power wafer having a maximum operating power lower than a threshold power value. The second die / die stack 164 may include a high-power wafer having a maximum operating power higher than the threshold power value. For example, the second die / die stack 164 includes at least one of a microprocessing wafer, a logic control wafer, a power management wafer, a driver wafer, and an analog wafer; and, the first die / die stack 162 includes at least one of a memory wafer and a sensing wafer. In some embodiments, the adhesive film may be any suitable die attach film (DAF). In some embodiments, a plurality of bonding pads 157 (also referred to as contact pads, redistribution pads, or similar structures known to those skilled in the art) may be located at the periphery of the first die / die stack 162 and the second die / die stack 164 and are electrically connected to the signal transmission wiring structure 146. In some embodiments, a plurality of signal lines 153 may be electrically connected between the plurality of bonding pads 157 and the first die / die stack 162 or the second die / die stack 164. Thus, electrical signals can be transmitted from the first die / die stack 162 and the second die / die stack 164 to the signal transmission wiring structure 146. The wafer package structure 100 may further include a molding compound layer 116, which is located on the substrate 120 to completely cover the first die / die stack 162, the second die / die stack 164, and the plurality of signal lines 153. In some embodiments, the molding compound layer 116 may be a thermally curable epoxy molding compound or a thermally curable epoxy molding resin. For example, the molding compound layer 116 includes inorganic fillers (e.g., silica), epoxy resin, curing agent, flame retardant, curing accelerator, release agent, and any other suitable components known to those skilled in the art. In some embodiments, the heat-conducting cover 190 may cover the encapsulation compound layer 116. At least one heat-conducting structure 180 may be arranged to laterally surround the second die / die stack 164 and vertically penetrate the encapsulation compound layer 116, and be connected between the heat-conducting cover 190 and the heat transfer wiring structure 148. In some embodiments, the height of at least one heat-conducting structure 180 may be greater than the height of the first die / die stack 162 or the second die / die stack 164. At least one heat-conducting structure 180 may include a plurality of heat-conducting blocks, each heat-conducting block vertically penetrating the encapsulation compound layer 116 and including a top surface in contact with the heat-conducting cover 190 and a bottom surface in contact with a heat pad, the heat pad being connected to the heat transfer wiring structure 148. In some embodiments, the material of the heat-conducting cover 190 and / or at least one heat-conducting structure 180 has a thermal conductivity greater than 1, for example, between 1 and 3. In some embodiments, the material of the heat-conducting cover 190 and / or at least one heat-conducting structure 180 is one of a metal, a ceramic material, or a silicon material. In some embodiments, the ball grid array (BGA) 130 may include a plurality of solder balls 132 / 135 attached to the second side of the substrate 120 opposite to the first side. The BGA 130 may include a plurality of signal solder balls 132 in contact with the signal transmission wiring structure 146, and at least one heat solder ball 135 in contact with the heat transfer wiring structure 148. That is, the signal solder balls 132 are electrically coupled to the first die / die stack 162 and the second die / die stack 164 to provide transmission of electrical signals between the first die / die stack 162 and the second die / die stack 164 and the PCB. The heat solder ball 135 may be coupled to the heat-conducting structure 180 via the heat transfer wiring structure 148 and is configured for heat dissipation of the second die / die stack 164. In some embodiments, the signal solder balls 132 and the heat solder balls 135 may include the same material and may be formed in the same process. For example, the signal solder balls 132 and the heat solder balls 135 may include any suitable metal material, such as aluminum (Al), antimony (Sb), arsenic (As), bismuth (Bi), cadmium (Cd), Co, Cu, Ni, Au, Ag, indium (In), iron (Fe), lead (Pb), phosphorus (P), tin (Sn), sulfur (S), zinc (Zn), germanium (Ge), etc., and any suitable alloys thereof. In some other embodiments, the signal solder balls 132 and the heat solder balls 135 may include different materials. For example, the signal solder balls 132 may include a first material with a high electrical conductivity coefficient, while the heat solder balls 135 may include a second material with a high thermal conductivity coefficient. Figures 2A-2D schematically illustrate various designs of exemplary semiconductor structures 200A, 200B, 200C, and 200D according to various embodiments of the present disclosure. It should be noted that the disclosed flexible design can allow different sizes, different shapes, and / or different numbers of heat conducting structures 180 according to spatial requirements. In the examples shown in 200A, 200B, 200C, and 200D, the heat conducting structure 180 can include a plurality of heat conducting blocks 185, each heat conducting block 185 having a generally square shape in a planar cross-section. In some other embodiments not shown, the planar cross-section of each heat conducting structure 180 can have a generally rectangular shape, a generally circular shape, a generally elliptical shape, a generally trapezoidal shape, etc. As shown in FIG. 2A, a plurality of heat conducting blocks 185 can be arranged to laterally surround a first wafer 264. The first wafer 264 can be a high-power wafer having a first operating power higher than a threshold power value. A second wafer 262 located outside the plurality of heat conducting blocks 185 can be a low-power wafer having a second operating power higher than the threshold power value. In some embodiments, the first wafer 264 can be a microprocessor wafer, a logic control wafer, a power management wafer, a driver wafer, or an analog wafer. The second wafer 262 can be a memory wafer or a sensing wafer. In some other embodiments as shown in FIG. 2B, a plurality of second wafers 262 (e.g., M low-power wafers) can be stacked in a vertical direction to form a die stack. Due to thermal management, the first wafers 264 are not stacked together to form a die stack. Instead, as shown in FIG. 2C, the first wafers 264 can be arranged side by side and laterally surrounded by a plurality of heat conducting blocks 185. In some other embodiments as shown in FIG. 2D, some of the plurality of heat conducting blocks 185 can be located between adjacent first wafers 264 (e.g., one of the first wafers can also be referred to as a third wafer). In some embodiments, the first lateral area of the planar cross-section of each heat conducting block 185 can be about 1 mm2. In some embodiments, the ratio between the first lateral area of each heat conducting block 185 and the second lateral area of the first wafer 264 can be in the range of about 1 / 20 to about 1 / 10. It should be noted that although as shown in FIGS. 2A-2D, the plurality of heat conducting blocks 185 surround the first wafer 264 in one circle, in some other embodiments not shown, the plurality of heat conducting blocks 185 can surround the first wafer 264 more than one circle. Referring to FIG. 3, a flowchart of an exemplary method for forming a semiconductor structure according to some embodiments of the present disclosure is shown. It should be understood that the operations and / or steps shown in FIG. 3 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. FIGS. 4-9 show schematic diagrams of exemplary semiconductor structures at certain fabrication steps of the method shown in FIG. 3 in perspective side views according to some embodiments of the present disclosure. As shown in FIG. 3, method 300 begins at operation 310, in which a substrate including a signal transmission wiring structure and a heat transmission wiring structure may be provided. FIG. 4 shows a schematic diagram of an exemplary semiconductor structure 400 after operation 310 of method 300 shown in FIG. 3 in a perspective side view according to some embodiments of the present disclosure. As shown in FIG. 4, in some embodiments, substrate 120 may include a signal transmission wiring structure 146 and a heat transmission wiring structure 148 embedded therein. Substrate 120 may be any suitable semiconductor substrate having any suitable structure, such as a single crystal silicon monolayer substrate, a polysilicon monolayer substrate, a multilayer substrate of polysilicon and metal, etc. The signal transmission wiring structure 146 may include any suitable conductive interconnect structure, such as conductive vias and patterned conductive layers, etc., and is configured to transmit electrical signals. The heat transmission wiring structure 148 may include any suitable heat conductive interconnect structure, such as heat conductive channels, and is configured to transmit heat. The signal transmission wiring structure 146 and the heat transmission wiring structure 148 may be isolated from each other. In some embodiments, the signal transmission wiring structure 146 may include any suitable conductive material, such as copper (Cu), nickel (Ni), gold (Au), silver (Ag), platinum (Pt), cobalt (Co), titanium (Ti), chromium (Cr), zirconium (Zr), molybdenum (Mo), ruthenium (Ru), hafnium (Hf), tungsten (W), rhenium (Re), graphite, carbon black, combinations thereof, and / or other materials known to those skilled in the art. The heat transmission wiring structure 148 may include any suitable heat conductive material, such as Ag, Cu, aluminum (Al), aluminum nitride, silicon carbide, W, graphite, zinc (Zn), combinations thereof, and / or other materials known to those skilled in the art. In some embodiments, the ratio between the first wiring width of the heat transmission wiring structure 148 and the second wiring width of the signal transmission wiring structure 146 may be in the range of approximately 1.5 to approximately 2. In some embodiments, a plurality of bonding pads 157 (also referred to as contact pads, redistribution pads, or similar structures known to those skilled in the art) may be formed on a first surface of a substrate 120 and may be electrically connected to a signal transmission wiring structure 146. In some embodiments, an array of ball pads (not shown) may be formed on a second surface of the substrate 120 opposite the first surface. The array of ball pads may be used to form an array of BGAs in a subsequent process. Returning to FIG. 3, method 300 may proceed to operation 320, in which at least one heat conducting structure may be formed on a first side of the substrate. FIG. 5 shows a schematic diagram of an exemplary semiconductor structure 500 after operation 320 of method 300 shown in FIG. 3 according to some embodiments of the present disclosure in a perspective side view. In some embodiments, at least one heat conducting structure 180 may be formed on a first surface of the substrate 120 and may be in thermal contact with a heat transfer wiring structure 148. In some embodiments, at least one heat conducting structure 180 may laterally surround at least one region for attaching at least one first wafer having a first operating power higher than a threshold power value in a subsequent process. In some embodiments, forming at least one heat conducting structure 180 may include: forming a plurality of heat conducting blocks (e.g., the heat conducting blocks shown in FIGS. 2A-2D), each heat conducting block being located on a heat pad 582, the heat pad 582 being located on a first side of the substrate 120 and connected to the heat transfer wiring structure 148. In some embodiments, the material of at least one heat conducting structure 180 has a thermal conductivity greater than 1, for example, between 1 and 3. In some embodiments, the material of at least one heat conducting structure 180 is one of a metal, a ceramic material, or a silicon material. In some embodiments, a first lateral area of a planar cross-section of each heat conducting block may be 1 mm 2 or so. Returning to FIG. 3, method 300 may proceed to operation 330, in which a first wafer may be formed on a first side of the substrate and laterally surrounded by at least one heat conducting structure. In some embodiments, operation 330 further includes: forming a second wafer, which is located on a first side of the substrate and outside of at least one heat conducting structure. FIG. 6 shows a schematic diagram of an exemplary semiconductor structure 600 after operation 330 of method 300 shown in FIG. 3 according to some embodiments of the present disclosure in a perspective side view. In some embodiments, the first wafer 664 and / or the second wafer 662 can be attached to the first surface of the substrate 120 by using any suitable adhesion or fastening means known in the art. In some embodiments, an adhesive film (not shown), such as a die attach film (DAF), can be attached to the bottom surface of the first wafer 664 and / or the second wafer 662. And then, the first wafer 664 and / or the second wafer 662 can be permanently attached or fixed to the first surface of the substrate 120. In some embodiments, the first wafer 664 can be a high-power wafer having a first operating power higher than a threshold power value, and can be attached in an area surrounded by at least one heat conducting structure 180. The second wafer 664 can be a low-power wafer having a second operating power higher than the threshold power value, and can be attached in an area located outside at least one heat conducting structure 180. In some embodiments, the first wafer 664 can be a microprocessor wafer, a logic control wafer, a power management wafer, a driver wafer, or an analog wafer. The second wafer 662 can be a memory wafer or a sensing wafer. In some embodiments, multiple second wafers 662 can be stacked in the vertical direction to form a die stack. Due to thermal management, the first wafers 264 are not stacked together to form a die stack. Instead, the first wafers 664 can be arranged side by side and laterally surrounded by at least one heat conducting structure 180. In some embodiments, the ratio between the first lateral area of each heat conducting block and the second lateral area of the first wafer 664 can be in the range of approximately 1 / 20 to approximately 1 / 10. In some embodiments, operation 330 further includes: wiring the first wafer 664 and / or the second wafer 662 to a plurality of bonding pads 157. For example, a plurality of signal lines 153 can be formed to electrically connect the plurality of bonding pads 157 to the first wafer 664 and / or the second wafer 662, such that the first wafer 664 and / or the second wafer 662 are electrically coupled to the signal transmission wiring structure 146. Referring back to FIG. 3, method 300 can proceed to operation 340, in which a molding compound layer can be formed on the first side of the substrate to cover the wafers and at least one heat conducting structure. FIG. 7 shows a schematic diagram of an exemplary semiconductor structure 700 after operation 340 of method 300 shown in FIG. 3 according to some embodiments of the present disclosure in a perspective side view. In some embodiments, a molding compound layer 116 may be formed on a first side of the substrate 120 to cover the first wafer 664 and / or the second wafer 662, at least one heat conducting structure 180, and the plurality of signal lines 153. In some embodiments, the molding compound layer 116 may be formed of any suitable material, such as a thermally curable epoxy molding compound material or a thermally curable epoxy molding resin. For example, the molding compound layer 116 may be formed by using an inorganic filler (e.g., silica), an epoxy resin, a curing agent, a flame retardant, a curing accelerator, a mold release agent, and any other suitable components known to those skilled in the art. Referring back to FIG. 3, method 300 may proceed to operation 350, in which a heat conducting cover located on the molding compound layer and in contact with at least one heat conducting structure may be formed. FIG. 8 shows a schematic diagram of an exemplary semiconductor structure 800 after operation 350 of method 300 shown in FIG. 3 in a perspective side view according to some embodiments of the present disclosure. In some embodiments, an upper portion of the molding compound layer 116 may be removed by any suitable process, such as chemical mechanical polishing (CMP) or grinding, such that at least one heat conducting structure 180 may be exposed. Then a heat conducting cover 190 may be formed on the remaining portion of the molding compound layer 116, and the heat conducting cover 190 is in direct contact with at least one heat conducting structure 180. Thus, the heat generated by the first wafer 664 may be dissipated to two surfaces of the formed semiconductor through at least one heat conducting structure 180, i.e., the heat conducting cover 190 and the heat transfer wiring structure 148. In some embodiments, the heat conducting cover 190 may be formed of a heat conducting material having a thermal conductivity greater than 1 (e.g., between 1 and 3). In some embodiments, the material of the heat conducting cover 190 is one of a metal, a ceramic material, or a silicon material. Referring back to FIG. 3, method 300 may proceed to operation 360, in which a ball grid array (BGA) may be formed on a second side of the semiconductor structure. FIG. 9 shows a schematic diagram of an exemplary wafer package structure 900 after operation 360 of method 300 shown in FIG. 3 in a perspective side view according to some embodiments of the present disclosure. As shown in FIG. 9, a ball grid array (BGA) 130 may be formed on a second surface of the base substrate 120 opposite to the package 110. The BGA 130 may include a plurality of solder balls 132 / 135 attached to an array of ball pads (not shown) located on the second surface of the base substrate 120. A plurality of signal solder balls 132 may be formed to contact the signal transmission wiring structure 146, and at least one thermal solder ball 135 may be formed to contact the heat transmission wiring structure 148. Thus, the thermal solder ball 135 may be coupled to the heat conduction structure 180 via the heat transmission wiring structure 148 and is configured to dissipate the operating heat generated by the first chip 664. The signal solder balls 132 may be electrically coupled to the first chip 664 and the second chip 662 to provide signal transmission. In some embodiments, the signal solder balls 132 and the thermal solder balls 135 may be formed simultaneously in the same process using the same material. For example, the signal solder balls 132 and the thermal solder balls 135 may be formed by using any suitable metal material (e.g., aluminum (Al), antimony (Sb), arsenic (As), bismuth (Bi), cadmium (Cd), Co, Cu, Ni, Au, Ag, indium (In), iron (Fe), lead (Pb), phosphorus (P), tin (Sn), sulfur (S), zinc (Zn), germanium (Ge), etc., and any suitable alloys thereof). In some other embodiments, the signal solder balls 132 and the thermal solder balls 135 may be formed by different processes and using different materials. For example, the signal solder balls 132 may be formed by using a first material with a high conductivity coefficient, while the thermal solder balls 135 may be formed by using a second material with a high heat conductivity coefficient. It should be noted that although not shown, the method 300 may further include any other suitable operations to further form the semiconductor structure. For example, the formed chip package structure 900 may be attached to a printed circuit board (PCB). Also, the plurality of signal solder balls 132 and thermal solder balls 135 may be used to provide a mechanical connection between the chip package structure 900 and the PCB. Accordingly, the present disclosure provides a chip package structure with high thermal conductivity. The manufacturing process can be modularized. In the disclosed chip package space, a certain number of the same or different sized heat conduction structures may be encapsulated around the chip stack and connected between the metal layer in the front of the package and the solder balls in the back to achieve a strong heat dissipation effect. Through the surface mount technology (SMT) packaging process, the connection between the high thermal conductivity material and the copper layer of the substrate and the connection of the surface metal coating can be achieved. Thus, high thermal conductivity can be obtained within the package structure, thereby significantly improving the product heat dissipation and improving the product performance. The disclosed manufacturing process for forming the disclosed chip package structure can be modularized, making it relatively simple. Conventional equipment can be used for the disclosed manufacturing process without substantial cost investment. A modular packaging solution can be adopted to reduce the difficulty of packaging and handling, which is conducive to mass production. The disclosed design can achieve better internal heat conduction in the chip package structure without changing the external dimensions of the existing package and existing packaging materials. The heat conduction structure can select materials with high thermal conductivity and high mechanical strength, enabling the entire chip package structure to have better heat dissipation and better mechanical properties. In addition, the disclosed manufacturing process can allow for flexible design of different sizes and / or different quantities of the heat conduction structure according to space requirements. Therefore, the heat dissipation conditions of high-power chips within the disclosed chip package structure can be significantly improved, and the operating temperature of the disclosed chip package structure can be significantly reduced. The foregoing description of specific embodiments will so fully disclose the general nature of the disclosure that others can, by applying knowledge within the scope of the art, readily modify and / or adapt various applications of such specific embodiments without undue experimentation and without departing from the general concept of the disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and scope of the equivalent of the disclosed embodiments based on the disclosure and guidance given herein. It will be understood that the terminology or phraseology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of this specification will be interpreted by those skilled in the art in light of the disclosure and guidance. The embodiments of the disclosure have been described above by means of functional building blocks, which illustrate the embodiments of specific functions and their relationships. For the sake of description, the boundaries of these functional building blocks have been arbitrarily defined herein. Alternative boundaries can be defined as long as the specified functions and their relationships are appropriately performed. The Summary and Abstract sections may set forth one or more exemplary embodiments conceived by the (multiple) inventors of the disclosure, but not all of the exemplary embodiments, and thus are not intended to limit the disclosure and the appended claims in any way. The breadth and scope of the disclosure should not be limited by any of the embodiments in the above exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents. 100, 900: Chip packaging structure; 110: Package body; 116: Molding compound layer; 120: Substrate; 130: Ball grid array (BGA); 132: Signal solder ball; 135: Thermal solder ball; 146: Signal transmission wiring structure; 148: Heat transmission wiring structure; 153: Signal line; 157: Bonding pad; 162: First die / die stack; 164: Second die / die stack; 180: Thermal conduction structure; 185: Thermal conduction block; 190: Thermal conduction cover; 200A, 200B, 200C, 200D, 400, 500, 600, 700, 800: Semiconductor structure; 262, 662: Second chip; 264, 664: First chip; 300: Method; 310, 320, 330, 340, 350, 360: Operations; 582: Thermal pad The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and, together with the description, further serve to explain the principles of the disclosure and enable a person skilled in the relevant art to make and use the disclosure. FIG. 1 shows a schematic diagram of an exemplary semiconductor structure according to some embodiments of the disclosure in a perspective side view. FIG. 2A shows a schematic diagram of an exemplary semiconductor structure according to some embodiments of the disclosure in a plan view. FIG. 2B shows a schematic diagram of another exemplary semiconductor structure according to some other embodiments of the disclosure in a plan view. FIG. 2C shows a schematic diagram of another exemplary semiconductor structure according to some other embodiments of the disclosure in a plan view. FIG. 2D shows a schematic diagram of another exemplary semiconductor structure according to some other embodiments of the disclosure in a plan view. FIG. 3 shows a flowchart of an exemplary method for forming a semiconductor structure according to some embodiments of the disclosure. FIGS. 4 to 9 show schematic diagrams of exemplary semiconductor structures at certain manufacturing steps of the method shown in FIG. 3 according to some embodiments of the disclosure in a perspective side view. The features and advantages of the disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings. In all the drawings, like reference numerals always denote corresponding elements. In the drawings, like reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. The drawing in which an element first appears is indicated by the leftmost (multiple) digit(s) in the corresponding reference numeral. Embodiments of the disclosure will be described with reference to the accompanying drawings. 100: Chip packaging structure 110: Package body 116: Molding compound layer 120: Substrate 130: Ball Grid Array (BGA) 132: Signal solder ball 135: Thermal solder ball 146: Signal transmission wiring structure 148: Thermal transmission wiring structure 153: Signal line 157: Bonding pad 162: First die / die stack 164: Second die / die stack 180: Thermal conduction structure 185: Thermal conduction block 190: Thermal conduction cover

Claims

1. A chip packaging structure, comprising: A substrate includes: a signal transmission wiring structure embedded in the substrate, and a heat transfer wiring structure embedded in the substrate; a first wafer located on the substrate and electrically connected to the signal transmission wiring structure, wherein the heat transfer wiring structure is closer to the first wafer than the signal transmission wiring structure, and the signal transmission wiring structure and the heat transfer wiring structure are isolated from each other; at least one thermally conductive structure located on the substrate, in thermal contact with the heat transfer wiring structure, and laterally surrounding the first wafer; and a ball grid array located on a side of the substrate opposite to the first wafer and the at least one thermally conductive structure, the ball grid array including: a plurality of signal solder balls in contact with the signal transmission wiring structure, and at least one thermal solder ball in contact with the heat transfer wiring structure, wherein each of the thermal solder balls is coupled to the plurality of the thermally conductive structures via the heat transfer wiring structure.

2. The wafer packaging structure according to claim 1 further includes: A molding compound layer located on the substrate and covering the first wafer, wherein the at least one thermally conductive structure is embedded in the molding compound layer; and a thermally conductive cap located on the molding compound layer and in thermal contact with the at least one thermally conductive structure.

3. The wafer packaging structure according to claim 2, wherein, The at least one thermally conductive structure includes: a plurality of thermally conductive blocks, each of the thermally conductive blocks vertically penetrating the molding compound layer and including a top surface in contact with the thermally conductive cover and a bottom surface in contact with a thermal pad located on the substrate, the thermal pad being connected to the heat transfer wiring structure.

4. The wafer packaging structure according to claim 3, wherein, The ratio between the first lateral area of ​​each of the heat-conducting blocks and the second lateral area of ​​the first wafer is in the range of approximately 1 / 20 to approximately 1 / 10.

5. The wafer packaging structure according to claim 1 further includes: The second wafer is located on the substrate and outside the at least one thermally conductive structure.

6. The wafer packaging structure according to claim 5, wherein, The first operating power of the first chip is greater than the second operating power of the second chip.

7. The wafer packaging structure according to claim 5, wherein, The first chip includes at least one of a microprocessor chip, a logic control chip, a power management chip, a driver chip, and an analog chip; and the second chip includes at least one of a memory chip and a sensing chip.

8. The wafer packaging structure according to claim 1 further includes: A third wafer is located on the substrate and next to the first wafer, and is laterally surrounded by the at least one thermally conductive structure.

9. The wafer packaging structure according to claim 8, wherein, A portion of the at least one thermally conductive structure is located between the third wafer and the first wafer.

10. The wafer packaging structure according to claim 1, wherein, The material of the at least one thermally conductive structure has a thermal conductivity greater than 1.

11. The wafer packaging structure according to claim 10, wherein, The material is one of metal, ceramic, or silicon.

12. The wafer packaging structure according to claim 1, wherein, The ratio between the first wiring width of the heat transfer wiring structure and the second wiring width of the signal transmission wiring structure is in the range of approximately 1.5 to approximately 2.

13. A method for forming a wafer package structure, comprising: A substrate is provided, the substrate comprising: a signal transmission wiring structure embedded in the substrate, and a heat transfer wiring structure embedded in the substrate; forming at least one thermally conductive structure located on a first side of the substrate and in thermal contact with the heat transfer wiring structure; forming a first wafer located on the first side of the substrate and laterally surrounded by the at least one thermally conductive structure, wherein the heat transfer wiring structure is closer to the first wafer than the signal transmission wiring structure, and the signal transmission wiring structure and the heat transfer wiring structure are isolated from each other; and electrically connecting the first wafer to the signal transmission wiring structure; the method further comprising: forming a ball grid array on a second side of the substrate opposite to the first side, comprising: forming a plurality of signal solder balls in contact with the signal transmission wiring structure, and forming at least one thermal solder ball in contact with the heat transfer wiring structure, wherein each of the thermal solder balls is coupled to the plurality of thermally conductive structures via the heat transfer wiring structure.

14. The method according to claim 13 further includes: A molding compound layer is formed on the first side of the substrate to cover the first wafer and the at least one thermally conductive structure; A thermally conductive cap is formed on the molding compound layer, the thermally conductive cap being located on the molding compound layer and in thermal contact with the at least one thermally conductive structure.

15. The method according to claim 13, wherein, Forming the at least one thermally conductive structure includes: forming a plurality of thermally conductive blocks, each of the thermally conductive blocks being located on a thermal pad, the thermal pad being located on the first side of the substrate and being connected to the thermal transfer wiring structure.

16. The method according to claim 13, wherein, The at least one thermally conductive structure and the first wafer are formed on the substrate using a surface mount technology (SMT) process.

17. The method according to claim 14, further comprising: A second wafer is formed, the second wafer being located on the first side of the substrate and outside the at least one thermally conductive structure, wherein the first operating power of the first wafer is greater than the second operating power of the second wafer.

18. A semiconductor structure comprising: Printed circuit boards; The chip package structure includes: a substrate, including: a signal transmission wiring structure embedded in the substrate, and a heat transfer wiring structure embedded in the substrate; a first chip located on the substrate and electrically connected to the signal transmission wiring structure, wherein the heat transfer wiring structure is closer to the first chip than the signal transmission wiring structure, and the signal transmission wiring structure and the heat transfer wiring structure are isolated from each other; and at least one thermally conductive structure located on the substrate, in thermal contact with the heat transfer wiring structure, and laterally surrounding the first chip; and a ball grid array located on a side of the substrate opposite to the first chip and the at least one thermally conductive structure, and connected between the printed circuit board and the substrate, the ball grid array including: a plurality of signal solder balls in contact with the signal transmission wiring structure, and at least one thermal solder ball in contact with the heat transfer wiring structure, wherein each of the thermal solder balls is coupled to the plurality of the thermally conductive structures via the heat transfer wiring structure.

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