2d tdc arrangement

Abstract

A sensor configuration for high-resolution imaging using a shared single-photon avalanche diode (SPAD) to time-to-digital converter (TDC) interconnect includes: a) a two-dimensional SPAD array arranged in columns and rows, wherein each SPAD is associated with a quenching circuit (QU) that generates a digital pulse for each SPAD event; b) a column interconnect and a row interconnect, wherein each QU of the SPAD array is connected to the column interconnect and the row interconnect; c) a plurality of TDC channels, each TDC channel associated with a specific column or a specific row of the SPAD array, wherein the TDC channels are driven by a shared clock generator and have N levels, and wherein the TDC channels are configured to measure the time interval between the occurrence of a SPAD event and the clock signal; d) a synchronization means to ensure synchronized operation of the TDC channels associated with the columns and rows of the SPAD array. e) a measurement means for acquiring measurement results from the TDC channels associated with the columns and rows of the SPAD array; f) a comparison means for comparing the measurement results from the column and row TDC channels to identify the source SPAD associated with a specific SPAD event; and g) a classification means for assigning the identified SPAD event to the corresponding histogram of the source SPAD.

Description

Technical Field

[0001] The present invention relates to a sensor arrangement for high-resolution imaging using a shared single-photon avalanche diode (SPAD) and a time-to-digital converter (TDC) interconnection, a method for detecting events in a high-resolution imaging system using a shared single-photon avalanche diode (SPAD) to a time-to-digital converter (TDC) interconnection, and a use of a system for event detection in a high-resolution imaging device, the system comprising such a sensor arrangement. Prior Art

[0002] Time-of-Flight (ToF) systems are commonly used in the art. Typically, conventional ToF systems use a dedicated TDC channel for each SPAD or group of SPADs (macropixels). Therefore, large SPAD arrays require multiple TDCs or multi-channel TDCs, which significantly increases the area requirements of the system. Alternatively, the TDC channel is shared between multiple macropixels, which requires time multiplexing within a frame and thus results in a decrease in the frame rate.

[0003] It is common to use a dedicated TDC channel for each pixel or SPAD in a ToF system to achieve maximum resolution. However, due to the large size of the TDC, in practice multiple SPADs are often assigned to a single TDC channel. Typically, each SPAD is equipped with a quench circuitry (QU) that generates a digital pulse for each SPAD event.

[0004] However, when multiple SPADs are combined into one pixel, for example using a compression tree or an OR tree, the information about which SPAD in the array actually fired is lost. However, identifying the active SPAD is crucial to achieve higher resolution or measurement accuracy.

[0005] Conventional methods of improving resolution use time multiplexing, where the SPADs are activated sequentially. However, this results in problems such as rolling shutter effects and a fixed integration time for each SPAD, which limits the temporal resolution and achievable light intensity. Summary of the invention

[0006] The present invention aims to overcome the information loss of conventional systems and recover the identification of active SPADs without using time multiplexing. This enables event capture in ToF systems with higher resolution and flexibility.

[0007] The paper “An all-in-one 64-zone SPAD-based Direct-Time-of-Flight Ranging Sensor with Embedded Illumination” by FMartin et al. (2021 IEEE Sensors | DOI: 10.1109 / SENSORS47087.2021.9639840) describes a SPAD-based direct time-of-flight multi-zone parallel ranging device using STMicroelectronics 40nm CMOS SPAD technology.

[0008] The paper “A 32 × 128 SPAD-257 TDC Receiver IC for Pulsed TOF Solid-State 3-D Imaging” of Jahromi et al. (1960 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 55, NO. 7, JULY 2020) discloses a single-chip receiver for pulsed laser direct time-of-flight 3D imaging applications implemented in 0.35-μm HV CMOS technology.

[0009] However, the prior art still lacks high-resolution imaging capabilities, flexibility in array configuration, enhanced synchronization and timing accuracy, improved source SPAD identification, and adaptability to various aspect ratios.

[0010] It is therefore an object of the present invention to provide a ToF sensor arrangement with more accurate and efficient imaging performance, which is particularly suitable for advanced imaging applications and systems. It is another object of the present invention to provide an area-efficient implementation of a high-resolution SPAD array with a global shutter similar to data processing and in particular without the need for time multiplexing. It is another object of the present invention to provide a method and arrangement to overcome the information loss problem when using a shared single photon avalanche diode (SPAD) to time-to-digital converter (TDC) interconnect and increase the resolution of the system without the need for time multiplexing.

[0011] With respect to the sensor configuration according to the present invention, these objects are met by a sensor configuration according to the present invention for high resolution imaging using a shared single photon avalanche diode (SPAD) to time-to-digital converter (TDC) interconnect.

[0012] Such sensor configurations include: a) a two-dimensional array of SPADs arranged in columns and rows, wherein each SPAD is associated with a quenching circuit (QU) that generates a digital pulse for each SPAD event; b) a column interconnect line and a row interconnect line, wherein each QU of the SPAD array is connected to the column interconnect line and the row interconnect line; c) a plurality of TDC channels, each TDC channel being associated with a specific column or a specific row of the SPAD array, wherein the TDC channels are driven by a common clock generator and have N stages, and wherein the TDC channels are configured to measure a time interval between the occurrence of a SPAD event and the clock signal; d) a synchronization means to ensure synchronous operation of the TDC channels associated with the columns and the rows of the SPAD array; e) a measurement means for acquiring measurement results from the TDC channels associated with the columns and the rows of the SPAD array; f) a comparison means to compare the measurements from the column and row TDC channels to identify the source SPAD associated with a particular SPAD event; and g) a classification means to assign the identified SPAD events to the corresponding histogram of the source SPAD.

[0013] Thus, the present invention provides a shared interconnect of multiple SPADs to TDC channels in the form of a two-dimensional implementation of a multi-event TDC channel, i.e., one TDC channel per column and per row. Such a two-dimensional implementation advantageously allows identification and localization of the individual SPAD that is generating the event. Thus, each pulse can be assigned to a dedicated SPAD. In other words, implementing a TDC channel per column and per row according to the present invention allows identification of the source of the SPAD event. Thus, in a shared interconnect and TDC environment, single SPAD resolution operations can be performed in parallel for all SPADs within a frame.

[0014] Thus, the inventors have surprisingly discovered that such a sensor configuration of the present invention advantageously provides a structured setup for capturing high resolution images using a SPAD and a TDC, and thereby is not only able to identify the source of a SPAD event, but also allows data to be collected at a single SPAD resolution by sharing the SPAD to TDC interconnect and TDC channel without the need for time multiplexing.

[0015] In an advantageous embodiment of the sensor arrangement according to the invention, the SPAD array comprises a plurality of SPADs arranged in an MxN arrangement, wherein M and N are positive integers greater than one.

[0016] This advantageously allows flexible configuration of the SPAD array with different sizes (M columns and N rows), allowing scalability and adaptability to various imaging requirements.

[0017] In a further advantageous embodiment of the sensor arrangement according to the invention, the quenching circuit (QU) comprises a pulse generating circuit which generates a digital pulse of a predetermined duration in response to a SPAD event.

[0018] This advantageously allows the quenching circuit to generate a digital pulse of a predetermined duration in response to a SPAD event, thereby enabling accurate detection and measurement of photon events.

[0019] In another advantageous embodiment of the sensor arrangement according to the invention, an NMOS transistor connected between the QU and the column and row interconnects is used as a switch to selectively connect the QU to the interconnects.

[0020] This advantageously allows the transistors to act as switches, thereby allowing the quenching circuit to be selectively connected to the interconnect lines, which enables efficient routing of signals within the sensor configuration.

[0021] In another advantageous embodiment of the sensor arrangement according to the invention, pull-up resistors connected to the column and row interconnects contribute to the restoration of the voltage levels of the interconnects.

[0022] This advantageously allows the pull-up resistors to ensure proper voltage levels in the interconnect lines, thereby enhancing signal integrity and minimizing signal degradation during transmission.

[0023] In another advantageous embodiment of the sensor arrangement according to the invention, the TDC channels are implemented in N stages using a delay line or a ring oscillator, wherein N is a positive integer greater than one.

[0024] This advantageously allows the TDC channels to accurately measure the time interval between a SPAD event and a clock signal using a delay line or a ring oscillator. This allows precise time measurement, which is critical for high-resolution imaging applications.

[0025] In another advantageous embodiment of the sensor arrangement according to the invention, it further comprises an offset adjustment means for compensating any timing offset between the TDC channels associated with the columns and the rows of the SPAD array.

[0026] This advantageously allows the offset adjustment means to compensate for any timing offsets between the TDC channels associated with the columns and the rows of the SPAD array, thereby ensuring accurate synchronization and reducing timing errors.

[0027] In a further advantageous embodiment of the sensor arrangement according to the invention, the synchronization means comprises a global synchronization signal which ensures synchronous operation of the TDC channels associated with the columns and the rows of the SPAD array.

[0028] This advantageously allows the global synchronization signal to achieve synchronized operation of the TDC channels associated with the columns and rows of the SPAD array. Such synchronized operation ensures coordinated measurements of the entire array, thereby avoiding timing differences.

[0029] In a further advantageous embodiment of the sensor arrangement according to the invention, the measuring means comprises an analog-to-digital converter (ADC) which converts the measurement results from the TDC channels into digital values.

[0030] This advantageously allows the ADCs to convert the measurements from the TDC channels into digital values, thereby allowing easy processing, analysis and storage of the captured data.

[0031] In a further advantageous embodiment of the sensor arrangement according to the invention, the comparison means comprises a comparator circuit which compares the measurement results from the column and row TDC channels to determine the relative timing of the SPAD events.

[0032] This advantageously allows the comparator circuit to compare the measurements from the column and row TDC channels to accurately determine the relative timing of the SPAD events. This comparison helps identify the source SPAD associated with a particular event.

[0033] In a further advantageous embodiment of the sensor arrangement according to the invention, the classification means comprises a histogram memory storing an occurrence count of SPAD events associated with each SPAD in the SPAD array.

[0034] This advantageously allows the classification means to include a histogram memory. An advantage of this approach is that the histogram memory stores the occurrence counts of SPAD events associated with each SPAD in the array. This facilitates statistical analysis, visualization and efficient storage of event data, which is valuable for various imaging applications.

[0035] In another advantageous embodiment of the sensor arrangement according to the invention, the transistor connecting each QU of the SPAD array to the column and row interconnection lines is a respective NMOS transistor and / or wherein the resistor connecting each interconnection line is a pull-up resistor.

[0036] This advantageously allows specific selection of the NMOS transistor and pull-up resistor to provide optimal circuit characteristics and performance for the sensor configuration.

[0037] In another advantageous embodiment of the sensor arrangement according to the invention, the SPAD array comprises a plurality of SPADs arranged in an MxN configuration, wherein the MxN configuration is selected from the group consisting of 3x4, 4x3, 16x9 or 9x16.

[0038] This advantageously allows the sensor configuration to be designed with dimensions that conform to common aspect ratios, such as those found in standard display formats. This facilitates compatibility and integration with existing imaging systems.

[0039] The above mentioned problems are also advantageously solved by a method according to the present invention for detecting events in a high resolution imaging system using a shared single photon avalanche diode (SPAD) and a time to digital converter (TDC) interconnect.

[0040] The method comprises at least the following steps: Step a) providing a two-dimensional array of SPADs arranged in rows and columns, each SPAD being associated with a quenching circuit (QU) which generates a digital pulse for each SPAD event, preferably providing a sensor configuration as claimed in any one of claims 1 to 13; Step b) connecting each QU of the SPAD array to a row and column interconnection line through a transistor, and connecting the interconnection line to a resistor; Step c) associating each column and row of the SPAD array with a dedicated TDC channel, which are driven by a common clock generator in the N-level case; Step d) synchronizing the operation of the TDC channels associated with the columns and rows of the SPAD array; Step e) receiving incident photons by the SPADs, generating SPAD events, and generating digital pulses for each SPAD event through the associated QU 3; Step f) transmitting the digital pulses via the row and column interconnects to the individual TDC channels associated with the column and row of the SPAD that generated the event; Step g) measuring the time interval between the occurrence of a SPAD event and the clock signal in each TDC channel; Step h) capturing measurement results from the TDC channels associated with the columns and rows of the SPAD array; Step i) comparing the measurements obtained from the column and row TDC channels to identify the source SPAD associated with the particular SPAD event; Step j) classifies the identified SPAD events into the corresponding histogram of the source SPAD.

[0041] It should be noted that the steps given above do not necessarily have to be performed in the order given. The steps provided can be performed in any other suitable order. However, the order given above can be applicable to specific variations of the method.

[0042] The advantages of this method are, in particular, that the method provides a systematic approach for event detection in a high resolution imaging system. Thus, the method ensures accurate detection of events in a high resolution imaging system. By utilizing a shared SPAD and TDC interconnect, it is possible to capture precise timing information for each SPAD event, thereby allowing accurate event detection. This level of accuracy is critical in high resolution imaging applications where accurate event identification is required. Furthermore, because the method according to the invention captures measurements from the TDC channels associated with the columns and rows of the SPAD array, efficient data capture and processing is facilitated. These measurements can be efficiently processed and analyzed for further use. By converting the measurements into digital values ​​using an analog-to-digital converter (ADC), the method enables easy manipulation, storage and transmission of the captured data. Furthermore, real-time event classification is advantageously achieved. The method of the invention includes a classification means that assigns the identified SPAD event to a corresponding histogram of the source SPAD. This allows real-time event classification and organization, thereby facilitating further analysis and visualization of the captured data. Real-time event classification can enable real-time feedback and response in applications that require real-time processing or monitoring. Furthermore, compensation for timing offsets can be advantageously achieved using the method of the present invention, which includes an offset adjustment means to compensate for any timing offsets between the TDC channels associated with the columns and rows of the SPAD array. This compensation ensures precise synchronization and alignment of timing measurements, thereby reducing timing errors and improving the overall accuracy of the imaging system.

[0043] Furthermore, the method of the present invention utilizes a synchronization means (e.g., a global synchronization signal) to ensure synchronous operation of the TDC channels associated with the columns and rows of the SPAD array. Synchronous operation eliminates timing differences and enables coordinated measurements across the entire array, resulting in more accurate and reliable imaging results.

[0044] Furthermore, the method of the present invention achieves high-speed imaging capability by utilizing a common clock generator and a TDC channel with multiple stages. This design can quickly and efficiently measure the time interval between the SPAD event and the clock signal. High-speed performance is particularly advantageous in applications that require real-time imaging or fast data acquisition.

[0045] In summary, the method according to the present invention provides advantages such as accurate event detection, efficient data acquisition and processing, real-time event classification, timing offset compensation, synchronous operation and high-speed performance. These advantages contribute to the effectiveness, accuracy and reliability of the high-resolution imaging system using the method.

[0046] The above-mentioned problems are also advantageously solved by using a system for event detection in a high-resolution imaging device according to the invention. Thus, the system comprises a sensor arrangement according to the invention.

[0047] Those skilled in the art will immediately recognize the various uses of the described sensor configurations and / or methods according to the present invention. The sensor configurations and methods according to the present invention can be applied to a variety of uses in high-resolution imaging and related applications. Without being limited thereto, some possible uses include: using the present invention in medical imaging applications, such as high-resolution microscopy, fluorescence imaging, or tissue imaging, which can enable precise and accurate imaging of biological samples, thereby facilitating diagnostic procedures, research, and medical interventions; using the present invention in industrial inspection scenarios, such as quality control, defect detection, and dimensional measurement, which can advantageously allow high-resolution imaging of manufactured products, thereby enabling detailed analysis, defect identification, and ensuring product quality; using the present invention in security and monitoring systems for high-resolution imaging and event detection, which can advantageously enable accurate monitoring, tracking, and identification of objects or individuals, thereby enabling them to be used in video surveillance, facial recognition, or perimeter security (perimeter security); using the present invention in robots and autonomous systems that require precise perception and object recognition capabilities, which can advantageously enable high-resolution imaging for object detection, positioning and mapping, thereby facilitating autonomous navigation, object manipulation or intelligent robotic systems; using the present invention in virtual and augmented reality applications by providing high-resolution imaging for realistic visualization and immersive experience, which can advantageously enable the capture of detailed 3D scenes, object reconstruction and tracking, thereby improving the quality and accuracy of virtual and augmented reality environments; using the present invention in various scientific research fields, such as astronomy, physics or biology, which can advantageously enable detailed imaging and analysis of celestial bodies, particle detection or cell imaging, thereby providing valuable data for scientific discovery and progress; using the present invention in remote sensing and earth observation applications, which can enable high-resolution imaging of the earth's surface, vegetation monitoring, environmental assessment or disaster management, thereby providing key information for agriculture, forestry, urban planning and natural resource management; using the present invention in autonomous vehicles for advanced perception capabilities, which can advantageously allow high-resolution imaging for object detection, obstacle avoidance and environmental mapping, thereby improving the safety and performance of autonomous driving systems.

[0048] Those skilled in the art will immediately recognize that features, embodiments, effects or advantages described herein in connection with the sensor configuration of the present invention may also be features, embodiments, effects or advantages of the method of the present invention or the use of the present invention, and vice versa.

[0049] In the context of the present invention, the term "SPAD" as used herein preferably means a single photon avalanche diode. A single photon avalanche diode is a solid-state photodetector that operates in a high sensitivity mode, enabling it to detect and measure single photons of light. It is designed to detect very low intensity light and convert it into an electrical signal for further processing. Therefore, a SPAD preferably consists of a pn junction, similar to a standard diode, but it may include additional features that enable it to operate in the avalanche breakdown region. When a photon of sufficient energy strikes a SPAD, it creates electron-hole pairs, initiating the avalanche multiplication process. This process results in a rapid and significant increase in the number of charge carriers, resulting in a measurable current pulse.

[0050] In the context of this patent application, the term "SPAD" more preferably refers to a specific type of photodetector employed in the sensor configuration and method according to the present invention. It means that single photon avalanche diodes are used in the system to achieve photon detection, timing measurement and event identification.

[0051] As used herein, the term "time-to-digital converter or TDC" preferably refers to a device that converts a time interval into a digital representation. Those skilled in the art know that such TDCs are typically used to measure time differences or to convert continuous time signals into discrete digital values.

[0052] As used herein, the term "SPAD array" preferably refers to an array or matrix of single photon avalanche diodes (SPADs), which are light detectors capable of detecting and measuring single photons of light and arranged in a two-dimensional configuration.

[0053] As used herein, the term "quenching circuit (QU)" preferably refers to the circuit associated with each single photon avalanche diode (SPAD) in a sensor configuration that generates a digital pulse for each SPAD event and assists in resetting the SPAD for subsequent photon detection.

[0054] As used herein, the terms "column interconnect" and "row interconnect" preferably refer to wiring or conductive paths that connect components associated with columns and rows, respectively, of a SPAD array to facilitate the transfer of signals and data between the SPADs and other circuits in a sensor configuration.

[0055] These and other features, embodiments, objects and advantages of the present invention will become apparent from the following description. Simple diagram description

[0056] Exemplary embodiments of the present invention are discussed below with reference to the accompanying drawings. FIG. 1 schematically illustrates a sensor configuration according to the prior art, wherein a conventional SPAD / quench readout architecture is used in an example with 16 SPADs per TDC channel; FIG2 schematically illustrates a sensor configuration according to a first embodiment of the present invention, wherein a TDC row-column configuration for a 2x2 SPAD array is depicted; FIG. 3 schematically illustrates a sensor configuration according to a first embodiment of the present invention in the event of Example Scenario 1; and FIG. 4 schematically illustrates a sensor configuration according to a second embodiment of the present invention in the event of a single collision occurring on separate rows and / or columns, respectively. Implementation

[0057] In FIG. 1 , a sensor configuration 1 according to the prior art is shown. Each SPAD is associated with a quenching circuit (QU) 3. A 4×4 SPAD configuration is shown here. Because layout area limitations usually do not allow the use of a dedicated TDC for each SPAD, multiple SPADs (here 16) are usually combined by using a compression tree (logical OR) 5 and connected to a single TDC channel 2. Therefore, a single TDC channel 2 is shared between multiple pixels. In order to operate the system in high-resolution mode (single SPAD resolution), time multiplexing similar to rolling shutter operation is used. In time multiplexing operation, the 16 SPADs are enabled one by one, while all other 15 SPADs are disabled, and integration is done for a certain period of time. In order to capture a full frame, each of the 16 SPADs must be selected in sequence and repeatedly integrated. Therefore, the frame decreases by 1 / N (here 1 / 16) with the number of SPADs connected to the single TDC 2. This leads to a significant reduction in performance and efficiency. In this example of the prior art, only 1 / 16 (1 / N) of the SPADs are enabled, while 16-1 (N-1) SPADs receive the emitted light but do not detect it.

[0058] In particular for illustrative reasons, in FIG2 a sensor arrangement 1 according to the invention is shown in simplified form. In the illustrated embodiment, a two-dimensional TDC arrangement 1 (columns 71 and 72 and rows 81 and 82) is used to allow identification of the source of a SPAD event in a shared SPAD-to-TDC interconnect. The principle is explained based on a 2x2 SPAD array, but the benefits can only be seen in larger SPAD arrays.

[0059] A sensor arrangement 1 for high resolution imaging using a shared single photon avalanche diode (SPAD) to time-to-digital converter (TDC) interconnect comprises a two-dimensional array of 2x2 SPADs 3 arranged in two columns 71 and 72 and two rows 81 and 82, wherein each SPAD is associated with a quenching circuit (QU), represented by a single element symbol of SPAD-QU 3, which generates a digital pulse for each SPAD event. Thus, there is a column interconnect line and a row interconnect line, wherein each QU of the SPAD array is connected to the column interconnect line and the row interconnect line. A plurality of TDC channels 21, 22, 25 and 26 are provided, each channel being associated with a specific column (21 to 71; 22 to 72) or a specific row (25 to 81; 26 to 82) of the SPAD array 1, wherein the TDC channels 21, 22, 25 and 26 are driven by a common clock generator 4 and have N stages, and wherein the TDC channels 21, 22, 25 and 26 are configured to measure the time interval between the occurrence of a SPAD event and a clock signal 6. Synchronization means (not depicted in detail in the figure) are further provided to ensure synchronized operation of the TDC channels 21, 22, 25 and 26 associated with the columns 71 and 72 and rows 81 and 82 of the SPAD array 1. Therefore, measurement means (not depicted in detail in the figure) are provided to capture measurement results from the TDC channels 21, 22, 25 and 26 associated with the columns 71 and 72 and rows 81 and 82 of the SPAD array 1. Comparison means (not depicted in detail in the figure) are provided to compare the measurement results from the column TDC channels 21 and 22 and the row TDC channels 25 and 26, respectively, to identify the source SPAD associated with a particular SPAD event. Furthermore, sorting means (not depicted in detail in the figure) are provided to assign the identified SPAD event to a corresponding histogram of the source SPAD.

[0060] In Figure 1, each SPAD is represented by a quenching circuit (QU) 3, which generates a digital pulse for each event of the SPAD. The output of each quenching unit is connected to the column and row interconnects using NMOS transistors. The interconnects are connected to pull up resistors. The location of the SPAD can be identified by the row and column addresses, for example, A1 = column 71, row 81; B1 = column 71, row 82; A2 = column 72, row 81; and B2 = column 72, row 82.

[0061] For each column 71 and 72, respectively, and for each row 81 and 82, respectively, a dedicated TDC channel is used (column 71 - TDC channel 21, column 72 - TDC channel 22, row 81 - TDC channel 25, row 82 - TDC channel 26), which in the N-stage case is driven by a common clock generator 4 (i.e., a delay line or ring oscillator). For this approach, a multi-event / multi-channel TDC is required. The TDC channels can advantageously be named according to their implementation (e.g., TDC channels A, B or 1, 2). The SPAD generates events randomly depending on the incident photon rate. Each SPAD event generates a pulse on the corresponding row and column interconnect lines. As usual, in the SPAD to TDC interconnect, the best possible balance of the SPAD to TDC interconnect is implemented.

[0062] In the example shown, the SPAD array 1 includes a plurality of SPADs 3 arranged in an MxN configuration, where M and N are positive integers greater than 1, here M is 2 and N is 2. Thus, each quenching circuit (QU) 3 includes a pulse generating circuit for generating a digital pulse of a predetermined duration in response to a SPAD event. NMOS transistors connected between QU 3 and column and row interconnects are used as switches to selectively connect QU 3 to these interconnects (not shown in detail in the schematic diagram). Thus, pull-up resistors connected to the column and row interconnects facilitate voltage level restoration of the interconnects. TDC channels 21, 22, 25 and 26 are implemented using a delay line or a ring oscillator in the N-stage case, respectively, where N is a positive integer greater than 1. Here, the sensor arrangement 1 further comprises offset adjustment means for compensating any timing offset between TDC channels 21, 22, 25 and 26 associated with columns 71 and 72 and rows 81 and 82 of the SPAD array 1. The synchronization means comprises a global synchronization signal which ensures synchronous operation of the TDC channels 21, 22, 25 and 26 associated with the columns 71 and 72 and rows 81 and 82 of the SPAD array, respectively. The measurement means comprises an analog-to-digital converter (ADC) which converts the measurement results from the TDC channels 21, 22, 25 and 26 into digital values. The comparison means comprises a comparator circuit which compares the measurement results from the column (21, 22) and row (25, 26) TDC channels to determine the relative timing of the SPAD events. The classification means comprises a histogram memory which stores the occurrence counts of the SPAD events associated with each SPAD 3 in the SPAD array 1. The transistors connecting each QU 3 of the SPAD array 1 to the column and row interconnects are individual NMOS transistors and / or the resistors connecting each interconnect are pull-up resistors. The number of rows and columns can be implemented in other ways than 2x2, i.e., in an MxN ratio of 3x4, 4x3, 16x9 or 9x16.

[0063] Using the configuration shown in FIG. 1 , a method for detecting events in a high-resolution imaging system using a shared single-photon avalanche diode (SPAD) to time-to-digital converter (TDC) interconnect according to the present invention can be advantageously performed. Such a method comprises at least the following steps: Step a) providing a two-dimensional array 1 of SPADs 3 arranged in columns 71, 72 and rows 81, 82, each SPAD being associated with a quenching circuit (QU) 3 which generates a digital pulse for each SPAD event; Step b) connecting each QU 3 of the SPAD array 1 to the column 71, 72 and row 81, 82 interconnection lines through transistors, and connecting the interconnection lines to resistors; Step c) Associating each column 71, 72 and row 81, 82 of the SPAD array 1 with a dedicated TDC channel 21, 22, 25, 26, which are driven by a common clock generator 4 in the N-level case; Step d) synchronizing the operation of the TDC channels 21, 22, 25, 26 associated with the columns 71, 72 and rows 81, 82 of the SPAD array 1; Step e) receiving incident photons by SPAD 3, generating SPAD events, and generating digital pulses for each SPAD event through the associated QU 3; Step f) transmitting the digital pulses to the individual TDC channels 21, 22, 25, 26 associated with the columns 71, 72 and rows 81, 82 of the SPADs generating the event via the column and row interconnects; Step g) measuring the time interval between the occurrence of a SPAD event and the clock signal in each TDC channel 21, 22, 25, 26; Step h) capturing measurement results from the TDC channels 21, 22, 25, 26 associated with the columns 71, 72 and rows 81, 82 of the SPAD array 1; Step i) comparing the measurements obtained from the column (21, 22) and row (25, 26) TDC channels to identify the source SPAD 3 associated with a particular SPAD event; Step j) Classify the identified SPAD events into the corresponding histogram of the source SPAD 3.

[0064] In FIG. 3 , a specific example is shown where SPAD A1 (i.e., in position column 71, row 81) is triggered (in this and other figures, the triggering event is depicted in the form of a lightning symbol). If a photon triggers SPAD A1, a pulse will be propagated from SPAD / quench 3 to TDC channels 21 and 25 on the column and row interconnects. Thus, TDC channel 25 and TDC channel 21 will capture this event. For simplicity, it is assumed that all channels (row channels 25 and 26 and column channels 21 and 22) operate perfectly synchronously, although in reality, perfect synchronous operation is not even required. Even in the case of offsets between different TDC channels, the time sequence of events in the column and row channels represents a certain SPAD event. Therefore, the lowest TDC count for the column and row represents the first event. In the case of perfect "in-phase" operation of all TDC channels, the resulting SPAD event will result in a measurement result of "X" (e.g., "5") at TDC channels 21 and 25. After reading all TDC channels 21, 22 and 25, 26 and comparing the measurements of the column channels (21, 22) and the row channels (25, 26), the source of the event can be identified, in this case SPAD A1. Therefore, this event can be classified into the histogram of SPAD A1.

[0065] In Example 2, it is assumed that SPADs A1 (row 81, column 71), B1 (row 82, column 71), and A2 (row 81, column 72) are triggered in sequence in the exemplary first embodiment shown in FIGS. 2 and 3.

[0066] The event signal from SPAD A1 will be passed to TDC channels 25 and 21, and TDC results "X" (e.g., 5) will be captured in both channels. Subsequently, SPAD B1 triggers and produces TDC results "X" (e.g., 7) at TDC channels 26 and 21. Finally, TDC channels 25 and 22 are triggered by SPAD A2 to have "X" (e.g., 9). After the period ends, the following TDC contents exist. TDC CH1 (21) 5 7 TDC CH2 (22) 9 TDC CHA (25) 5 9 TDC CHB (26) 7 During readout, the common result among multiple TDCs allows identification of the source: Event 1 from SPAD A1 at timestamp 5 Event 2 from SPAD B1 at timestamp 7 Event 3 from SPAD A2 at timestamp 9

[0067] Of course, the principle can be extended to higher resolutions and MxN ratios. Although the number of pixels increases with the square of the resolution (N^2), the number of TDC channels required only increases by 2*N.

[0068] All embodiments of the present invention as described above in the claims and specification and in relation to the drawings herein provide advantages in that single SPAD pixel resolution is achievable without time multiplexing and is achievable in a scalable arrangement where the number of SPADs / pixel increases by N^2 while the number of TDC channels increases by only ~2*N. Thus, reducing the number of TDC channels reduces layout area and power consumption.

[0069] Therefore, trigger conflicts on a shared SPAD-to-TDC interconnect, such as multiple events (A1 and A2) occurring simultaneously, can also be advantageously resolved using the sensor configuration of the present invention. In FIG4, such conflicts are schematically demonstrated using the sensor configuration according to the first embodiment shown in FIGS. 2 and 3 above.

[0070] In Figure 4, another embodiment of an MxN, 4x4 SPAD array according to the present invention is schematically shown. In this embodiment of Figure 4, a conflict situation on multiple columns / rows is shown. During readout, the common result in multiple TDCs allows identification of the source.

[0071] In this case, it is impossible to identify the source from the outset, as the following scenarios lead to the same result: Events at A1 (81, 71) and D4 (84, 74) Events at A4 (81, 74) and D1 (84, 71) Events in all combinations of A1 (81, 71), A4 (81, 74), D1 (84, 71) and D4 (84, 74).

[0072] Therefore, two possible solutions are as follows: 1) Skip all frames where multiple (2+) row and column TDC channels do have the same count. This will only slightly reduce bandwidth, especially in the case of cross talk and correlated pulses generated by the target. 2) Add additional observations for the read interconnects by adding current comparator circuits on the diagonally arranged SPADs. The currents on the rows and columns will scale with the number of events on the same channel. 1 event -> 1xI, 2 events -> 2xI, .... Since in this case 2x current is observed on the top left to bottom right observers and no current on the top right to bottom left current observation comparators, the source of the event can be identified. Since in this case 2x current is observed on the top left to bottom right observers and no current on the top right to bottom left current observation comparators, the source of the event can be identified. An alternative solution based on digital logic is a series of full adders for the diagonally arranged quenching circuits, which digitally indicate multiple events on a certain diagonal.

[0073] With such a simple correction method, the sensor configuration according to the invention can be advantageously used even in the case of conflicting SPAD triggering.

[0074] The embodiments in the drawings may relate to preferred embodiments, and all elements and features described with respect to the embodiments may be used in combination with any other embodiments and features discussed herein, where appropriate, and in particular in relation to any other embodiments discussed further above.

[0075] 1: Sensor Configuration 2: TDC channel 21:TDC channel 1 22: TDC channel 2 23:TDC channel 3 24: TDC channel 4 25:TDC channel A 26:TDC channel B 27:TDC channel C 28:TDC channel D 3: SPAD+QU 4: TDC core clock generator 5:16 to 1 "or tree" 6: Channel clock (N phases) 71: Column 1 72: Column 2 73: Column 3 74: Column 4 81: Row A 82: Row B 83: Row C 84: Row D

Claims

1. A sensor configuration for high-resolution imaging using a shared single-photon avalanche diode (SPAD) to time-to-digital converter (TDC) interconnect, comprising: a) A two-dimensional SPAD array arranged in columns and rows, wherein each SPAD is associated with a quench circuitry (QU) that generates a digital pulse for each SPAD event; b) A column interconnect and a row interconnect, wherein each QU of the SPAD array is connected to the column interconnect and the row interconnect; c) A plurality of TDC channels, each TDC channel associated with a specific column or a specific row of the SPAD array, wherein the TDC channels are driven by a common clock generator and have N levels, and wherein the TDC channels are configured to measure the time interval between the occurrence of a SPAD event and a clock signal; d) A synchronization means to ensure synchronized operation of the TDC channels associated with the columns and rows of the SPAD array; e) A measurement means to acquire measurement results from the TDC channels associated with the columns and rows of the SPAD array; f) a comparison means for comparing the measurement results from the column and row TDC channels to identify the source SPAD associated with a specific SPAD event; and g) a classification means for assigning the identified SPAD event to the corresponding histogram of the source SPAD.

2. The sensor configuration as described in claim 1, wherein the SPAD array comprises a plurality of SPADs arranged in an M x N configuration, wherein M and N are positive integers greater than 1.

3. The sensor configuration as requested in item 1 or 2, wherein the quenching circuit (QU) includes a pulse generation circuit that generates a digital pulse of a predetermined duration in response to a SPAD event.

4. The sensor configuration of any one of claims 1 to 2, wherein the NMOS transistor connected between the QU and the column and row interconnects is used as a switch to selectively connect the QU to the interconnects.

5. As in any of the requests 1 to 2, the sensor configuration wherein pull-up resistors connected to the column and row interconnects facilitate voltage level restoration of the interconnects.

6. The sensor configuration of any of the requests 1 to 2, wherein the TDC channels are implemented using a delay line or a ring oscillator in the N-level case, wherein N is a positive integer greater than 1.

7. The sensor configuration of any of claims 1 to 2 further includes an offset adjustment means for compensating for any timing offset between the TDC channels associated with the columns and rows of the SPAD array.

8. The sensor configuration as requested in any of claims 1 to 2, wherein the synchronization means includes a global synchronization signal that ensures synchronized operation of the TDC channels associated with the columns and rows of the SPAD array.

9. The sensor configuration of any one of claims 1 to 2, wherein the measurement means includes an analog-to-digital converter (ADC) that converts the measurement results from the TDC channels into digital values.

10. The sensor configuration of any one of claims 1 to 2, wherein the comparison means includes a comparator circuit that compares the measurement results from the column and row TDC channels to determine the relative timing of the SPAD event.

11. The sensor configuration of any one of requests 1 to 2, wherein the classification means includes a logarithmic memory that stores a count of occurrences of SPAD events associated with each SPAD in the SPAD array.

12. The sensor configuration of any one of claims 1 to 2, wherein each QU of the SPAD array is connected to a separate NMOS transistor of the column and row interconnects and / or wherein the resistor connecting each interconnect is a pull-up resistor.

13. The sensor configuration of any one of claims 1 to 2, wherein the SPAD array comprises a plurality of SPADs arranged in an MxN configuration, wherein the MxN configuration is selected from the group including 3x4, 4x3, 16x9 or 9x16.

14. A method for detecting events in a high-resolution imaging system using a shared single-photon avalanche diode (SPAD) to time-to-digital converter (TDC) interconnect, the method comprising at least the following steps: Step a) providing a two-dimensional array of SPADs arranged in columns and rows, each SPAD associated with a quenching circuit (QU) that generates a digital pulse for each SPAD event, preferably providing a sensor configuration as described in any of claims 1 to 13; Step b) connecting each QU of the SPAD array to a column and row interconnect via a transistor, and connecting the interconnect to a resistor; Step c) associating each column and row of the SPAD array with a dedicated TDC channel, the TDC channels being driven by a shared clock generator in the N-level case; Step d) synchronizing the operation of the TDC channels associated with the columns and rows of the SPAD array; Step e) The SPADs receive incident photons, generating SPAD events, and generate digital pulses for each SPAD event via the associated QU; Step f) The digital pulses are transmitted via the column and row interconnects to the individual TDC channels associated with the column and row of the SPAD that generated the event; Step g) The time interval between the occurrence of a SPAD event and the clock signal is measured in each TDC channel; Step h) Measurement results are captured from the TDC channels associated with the columns and rows of the SPAD array; Step i) The measurement results obtained from the column and row TDC channels are compared to identify the source SPAD associated with the specific SPAD event; Step j) The identified SPAD event is classified into the corresponding histogram of the source SPAD.

15. Use of a system for event detection in a high-resolution imaging apparatus, the system comprising a sensor configuration as described in any of claims 1 to 13.

Images