Method for making semiconductor device and semiconductor die

Abstract

Semiconductor dies and methods for forming semiconductor dies are provided. One method includes forming a semiconductor die with under-bump metal (UBM) pads in a dense region and in an isolated region; forming an external electrical connector in contact with the under-bump metal pads; and limiting the external electrical connector to a preselected vertical height.

Description

Technical Field

[0001] none Prior Art

[0002] Semiconductor devices are used in a variety of electronic applications, for example, personal computers, cell phones, digital cameras, and other electronic devices are examples. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form multiple circuit components and multiple components thereon. Dozens or hundreds of integrated circuits are typically manufactured on a single semiconductor wafer. Multiple individual dies are singulated by sawing the multiple integrated circuits along scribe lines. The individual dies are then packaged separately, such as individually or in multi-chip modules, or in other types of packages.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, which allows more components to be integrated into a given area. In some applications, these smaller electronic components such as integrated circuit dies may also require smaller packages (utilizing less area than previous packages). Summary of the invention

[0004] none Simple diagram description

[0005] Various aspects of the present disclosure can be best understood by the following detailed description and reading in conjunction with the accompanying drawings. Note that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion. 1-8 are cross-sectional views of various intermediate steps during a process for forming a package structure according to some embodiments. 9 through 16 are multiple cross-sectional views focusing on the formation of under bump metal (UBM) structures and solder bumps during multiple steps of a process for forming a package structure according to some embodiments. FIG. 17 is a layout diagram of under bump metallization (UBM) structures and solder bump locations in multiple regions of a die according to some embodiments. 18 and 19 are cross-sectional views of under bump metallization (UBM) structures and solder bumps at various locations in different regions in FIG. 17 . FIG. 20 is a layout diagram of under bump metallization (UBM) structures and solder bump locations in multiple regions of a die according to some embodiments. 21 to 23 are cross-sectional views of under bump metallization (UBM) structures and solder bumps at various locations in different regions in FIG. 20 . FIG. 24 is a layout diagram of under bump metallization (UBM) structures and solder bump locations in multiple regions of a die in accordance with some embodiments. FIG. 25 is a layout diagram of the shape of an under bump metallurgy (UBM) structure according to some embodiments. FIG. 26 is a flow chart of a method according to some embodiments. Implementation

[0006] The disclosure that follows provides many different implementations or embodiments for implementing different features of the subject matter provided. Specific embodiments of components and arrangements are described below to simplify the disclosure. Of course, these are merely embodiments and are not intended to be limiting. For example, in the description that follows, forming a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature, such that the first feature and the second feature may not be in direct contact. As used herein, "directly above" refers to the vertical alignment of multiple features such that when the overlying feature is directly above the underlying feature, the vertical axis passes through the two features. In addition, the disclosure may repeat reference numerals and / or letters in various embodiments. Such repetition is for the purpose of simplicity and clarity, and the repetition itself is not intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0007] Additionally, to facilitate describing the relationship of one element or feature to another element or feature as depicted in the drawings, spatially relative terms such as "directly above," "above," "overlying," "above," "over," "top," "below," "below," "below," "lower," "bottom," "side," "positive slope," and "negative slope," and the like may be used herein. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the drawings. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted similarly accordingly.

[0008] All numbers in this description indicating quantities, ratios of materials, physical properties of materials, and / or uses are to be understood as modified by the word "about" unless otherwise expressly stated. When modifying a numerical value in the specification or claims, "about" indicates an interval of accuracy that is familiar and acceptable to those skilled in the art. Generally, such an interval of accuracy is ± 10 percent. Thus, "about 10" means nine to eleven.

[0009] In certain embodiments herein, a "material structure" includes at least 50% by weight of an identified material, such as at least 60% by weight of an identified material, at least 75% by weight of an identified material, at least 90% by weight of an identified material, at least 95% by weight of an identified material, or at least 99% by weight of an identified material; and a structure formed from a "material" includes at least 50% by weight of an identified material, such as at least 60% by weight of an identified material, at least 75% by weight of an identified material, at least 90% by weight of an identified material, at least 95% by weight of an identified material, or at least 99% by weight of an identified material. For example, in certain embodiments, each of a tungsten structure and a structure formed from tungsten is at least 50%, at least 60%, at least 75%, at least 90%, at least 95%, or at least 99% by weight of tungsten.

[0010] For the sake of brevity, known techniques related to the manufacture of semiconductor devices may not be described in detail herein. In addition, the various tasks and processes described herein may be combined into more comprehensive programs or processes with additional functions that are not described in detail herein. In particular, various processes in the manufacture of semiconductor devices are known, and therefore, for the sake of brevity, many processes will only be briefly mentioned or omitted entirely herein without providing known process details. It will be apparent to those skilled in the art, after reading this disclosure in its entirety, that the multiple structures disclosed herein can be used with various techniques and can be incorporated into various semiconductor devices and products. Further, it is noted that the semiconductor device structure includes different numbers of components, and a single component shown in the drawings can represent multiple components.

[0011] The various embodiments discussed herein may be discussed in a specific context, namely, a package structure having a fan-out or fan-in wafer-level package. Other embodiments contemplate other applications, such as different package types or different configurations, which will be apparent to a person of ordinary skill in the art reading this disclosure. It should be noted that the various embodiments discussed herein do not necessarily depict every component or feature that may be present in the structure. For example, multiple components may be omitted from the drawings, such as when a discussion of one of the components is sufficient to convey multiple aspects of the embodiment. In addition, the various method embodiments discussed herein may be discussed as being performed in a particular order; however, other method embodiments may be performed in any logical order.

[0012] In various embodiments herein, external electrical connectors (i.e., bumps) are formed at uniform heights in dense areas and in isolated areas, although such multiple bumps tend to be formed with different heights, i.e., higher heights in isolated areas and lower heights in dense areas. This can be achieved in two ways. First, multiple under bump metal pads in isolated areas can be formed to have larger critical dimensions than multiple under bump metal pads in dense areas. Therefore, multiple bumps formed over multiple under bump metal pads in isolated areas have lower heights, similar or the same as those in dense areas. Second, multiple dummy under bump metal pads can be formed in isolated areas to effectively increase pad and bump density in such areas. As a result, multiple bumps are formed with uniform heights in both dense and isolated areas.

[0013] Thus, various embodiments herein provide for forming a plurality of external electrical connectors over under bump metallization or under ball metallization (UBMs) with improved height uniformity in dense and isolated regions of a semiconductor die. These external electrical connectors may include a low temperature reflowable material, such as a solder, such as a lead-free solder. In some embodiments, the external electrical connectors are ball grid array (BGA) solder balls, controlled collapse chip connection (C4) bumps, microbumps, or the like, or metal pillars. For example, various embodiments herein counteract the tendency for a plurality of external electrical connectors formed in a dense external electrical connector region to have a lower height than a plurality of external electrical connectors formed in an isolated external electrical connector region during a process for forming a plurality of external electrical connectors spanning two regions. In some embodiments, the under bump metal in the dense region and the external electrical connector formed thereon are formed to have a first critical dimension; and the under bump metal in the isolated region and the external electrical connector formed thereon are formed to have a second critical dimension greater than the first critical dimension. In some embodiments, a dummy UBM is formed adjacent to an isolated active UBM to reduce the relative isolation of such isolated multiple active UBMs. As a result, the formation of external electrical connectors over the active and dummy UBMs is performed in the same or more similar manner, resulting in multiple external electrical connectors having the same, more similar, or consistent heights.

[0014] FIG. 1 to FIG. 8 illustrate multiple cross-sectional views of multiple intermediate steps during a process for forming a package structure 100 according to some embodiments. FIG. 1 illustrates a carrier substrate 20 and a release layer 22 formed on the carrier substrate 20. The carrier substrate 20 may be a glass carrier substrate, a ceramic carrier substrate, or the like. The carrier substrate 20 may be a wafer. The release layer 22 may be formed of a polymer-based material that may be removed together with the carrier substrate 20 from a cover structure to be formed in a subsequent step. In some embodiments, the release layer 22 is an epoxy-based thermal release material that loses its adhesive properties when heated, such as a light-to-heat-conversion (LTHC) release coating. In other embodiments, the release layer 22 may be an ultraviolet (UV) glue that loses its adhesive properties when exposed to ultraviolet light. The release layer 22 may be dispensed and cured in liquid form, may be a laminated film laminated to the carrier substrate 20, or may be the like. The adhesive 24 may be formed or dispensed on the release layer 22. The adhesive 24 may be a die attach film (DAF), glue, a polymer material, or the like.

[0015] The integrated circuit die 26 is attached to the carrier substrate 20 via an adhesive 24 (e.g., through a release layer 22). As shown, one integrated circuit die 26 is attached, and in other embodiments, more integrated circuit die may be attached. Prior to being attached to the carrier substrate 20, the integrated circuit die 26 may be processed according to an applicable manufacturing process to form an integrated circuit in the integrated circuit die 26. For example, the integrated circuit die 26 includes a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, a multilayer or gradient substrate, or the like. The semiconductor of the substrate may include any semiconductor material, such as an elemental semiconductor, such as silicon, germanium, or the like; a compound or alloy semiconductor, including SiC, GaAs, GaP, InP, InAs, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GalnAs, GaInP, and / or GaInAsP; the like; or a combination thereof. Devices such as transistors, diodes, capacitors, resistors, etc. may be formed in and / or on a semiconductor substrate and may be interconnected via an interconnect structure formed by, for example, a plurality of metallization patterns in one or more dielectric layers on the semiconductor substrate to form an integrated circuit.

[0016] The integrated circuit die 26 also includes pads 28, such as aluminum pads, that are connected to external connections. The pads 28 may be on the so-called active side of the integrated circuit die 26. A passivation film 30 is on the integrated circuit die 26 and on portions of the plurality of pads 28. A plurality of openings are provided through the passivation film 30 to reach the plurality of pads 28. Die connectors 32, such as conductive posts (e.g., comprising a metal such as copper) are in the openings through the passivation film 30 and are mechanically and electrically coupled to the respective pads 28. The die connectors 32 may be formed, for example, by plating or the like. The die connectors 32 electrically couple the integrated circuits of the integrated circuit die 26. For clarity and simplicity, one pad 28 and one die connector 32 are depicted on the integrated circuit die 26, and one skilled in the art will readily appreciate that there may be more than one pad 28 and more than one die connector 32.

[0017] Dielectric material 34 is on the active side of IC die 26, such as on passivation film 30 and die connector 32. Dielectric material 34 laterally encapsulates die connector 32, and dielectric material 34 laterally co-terminates with IC die 26. Dielectric material 34 may be a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, dielectric material 34 is formed of a nitride, such as silicon nitride; an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or a similar material. Dielectric material 34 may be formed via any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), lamination, the like, or a combination thereof. The plurality of IC dies 26 may be singulated, for example, by sawing or dicing, and attached to the carrier substrate 20 via the adhesive 24 using, for example, a pick and place tool.

[0018] In FIG. 2 , encapsulant 36 is formed on adhesive 24 around integrated circuit die 26 and / or on various components on integrated circuit die 26. Encapsulant 36 may be a molding compound, epoxy, or the like, and may be applied via compression molding, transfer molding, or the like. After curing, encapsulant 36 may undergo a grinding process to expose die connector 32. After the grinding process, the top surfaces of die connector 32, dielectric material 34, and encapsulant 36 are coplanar. In some embodiments, for example, if die connector 32 is already exposed, grinding may be omitted.

[0019] In FIG3, a dielectric layer 38 and a metallization pattern 40 of a redistribution structure are formed. FIG3 and subsequent figures illustrate an example configuration of a redistribution structure, and in other embodiments, the redistribution structure may include any number of dielectric layers, metallization patterns, and vias.

[0020] A dielectric layer 38 is formed over the encapsulant 36, the dielectric material 34, and the die connector 32. In some embodiments, the dielectric layer 38 is formed of a polymer, which may be a photosensitive material, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like, which can be easily patterned using a lithographic mask. In other embodiments, the dielectric layer 38 is formed of a nitride, such as silicon nitride; formed of an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like. The dielectric layer 38 may be formed by spin coating, lamination, chemical vapor deposition, the like, or a combination thereof. The dielectric layer 38 is then patterned to form openings to expose portions of the die connector 32. Patterning may be performed by an acceptable process, such as by exposing dielectric layer 38 to light when the dielectric layer is a photosensitive material, or by etching using, for example, anisotropic etching.

[0021] A metallization pattern 40 having a guide hole 42 is formed on the dielectric layer 38. As an embodiment of forming the metallization pattern 40 and the guide hole 42, a seed layer (not shown) is formed above the dielectric layer 38. In some embodiments, the seed layer is a metal layer, which can be a single layer or a composite layer including a plurality of sublayers formed of different materials. In some embodiments, the seed layer includes a titanium layer and a copper layer above the titanium layer. The seed layer can be formed using, for example, physical vapor deposition (PVD), or the like. A photoresist is then formed on the seed layer and patterned. The photoresist can be formed by spin coating or the like, and can be exposed to patterning. The pattern of the photoresist corresponds to the metallization pattern 40. The patterning forms a plurality of openings through the photoresist to expose the seed layer. A conductive material is formed in the plurality of openings of the photoresist and on the exposed portions of the seed layer. The conductive material can be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may include a metal such as copper, titanium, tungsten, aluminum, or the like. The photoresist is then removed, as well as portions of the seed layer (on which no conductive material is formed). The photoresist may be removed via an acceptable ashing or stripping process, such as using an oxygen plasma or the like. Once the photoresist is removed, the exposed portions of the seed layer are removed, such as by using an acceptable etching process, such as by wet or dry etching. The remaining portions of the seed layer and the conductive material form the metallization pattern 40 and the vias 42. The vias 42 are formed in openings through the underlying layers (e.g., the dielectric layer 38).

[0022] By repeating the process for forming dielectric layer 38 and metallization pattern 40, one or more additional metallization patterns and vias and dielectric layers may be formed in the redistribution structure. As discussed, vias may be formed during the formation of the metallization pattern. Thus, the vias may interconnect and electrically couple the various metallization patterns. The depiction of one dielectric layer (e.g., dielectric layer 38) and one metallization pattern (e.g., metallization pattern 40) is for ease and simplicity of illustration.

[0023] In FIG. 4 , a dielectric layer 44 is formed on the metallization pattern 40 and the dielectric layer 38. In some embodiments, the dielectric layer 44 is formed of a polymer, which may be a photosensitive material, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like, which can be easily patterned using a photolithography mask. In other embodiments, the dielectric layer 44 is formed of a nitride such as silicon nitride; formed of an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (PSG), or the like. The dielectric layer 44 may be formed by spin coating, lamination, chemical vapor deposition, the like, or a combination thereof. Then, the dielectric layer 44 is patterned to form a plurality of openings 46 to expose portions of the metallization pattern 40. Patterning can be done by an acceptable process, such as by exposing the dielectric layer 44 to light when the dielectric layer is a photosensitive material, or by etching using, for example, anisotropic etching. In FIG. 4 , a single opening 46 is formed; however, a suitable number of openings 46 may be formed. For example, in FIGS. 6 to 8 , two openings 46 are shown.

[0024] 5 to 8 illustrate the formation of under ball metallizations (UBMs) 56 for connection to external electrical connectors, as described in subsequent figures.

[0025] In FIG. 5 , a seed layer 48 is formed over the dielectric layer 44 and in the opening 46, for example, on the sidewalls of the dielectric layer 44 and on the metallization pattern 40. In some embodiments, the seed layer 48 is a metal layer, which can be a single layer or a composite layer including a plurality of sub-layers formed of different materials. In some embodiments, the seed layer 48 includes a titanium layer and a copper layer over the titanium layer. Forming the seed layer 48 can use, for example, physical vapor deposition, or the like.

[0026] Note that in Figures 4 and 5, a single opening 46 is shown; however, any number of suitable openings 46 may be formed. For example, in Figures 6 to 8, two openings 46 are shown.

[0027] In FIG. 6 , a photoresist 50 is formed on the seed layer 48. In this embodiment, the photoresist 50 is a negative photoresist material. The photoresist 50 may be formed on the seed layer by spin coating, or the like.

[0028] In FIG. 7 , a photoresist 50 is patterned on the seed layer 48. The photoresist 50 can be exposed and subsequently developed for patterning. Using a negative photoresist, exposed portions of the photoresist 50 remain after patterning. After exposure, the photoresist 50 is developed to remove soluble portions of the photoresist 50, so that insoluble portions of the photoresist 50 remain on the seed layer 48 with a plurality of openings 52 through the photoresist 50. The pattern of the photoresist 50 corresponds to the under bump metal 60 or other metallization pattern to be formed.

[0029] In FIG. 8 , under bump metal 60 is formed in corresponding openings 52 of photoresist 50 and on seed layer 48. Conductive material is formed in openings 52 of photoresist 50 and on exposed portions of seed layer 48, for example, by plating, such as electroplating or chemical plating, or the like. The conductive material may include a metal, such as copper, titanium, tungsten, aluminum, or the like.

[0030] FIG. 1 to FIG. 8 illustrate the formation of three UBMs 60 above the semiconductor die 26: an active UBM 61, a dummy UBM 62, and a dummy UBM 63. After further processing, the seed layer 48 below the UBM 60 will be etched into different sections insulated from each other. Specifically, portions of the seed layer 48 not covered by the UBM 60 will be removed. As shown, the UBM 61 is electrically connected to the active side of the integrated circuit die 26 through the pad 28, the die connector 32, the via 42, the metallization pattern 40, and the seed layer 48. The dummy UBM 62 is formed on a portion of the seed layer 48 above the dielectric layer 44 and, after etching, is disconnected from any electrical path. The dummy UBM 63 is formed on a portion of the seed layer 48 located above a portion of the metallization pattern 40 and, after etching, is disconnected from any electrical path.

[0031] Although FIGS. 1 to 8 illustrate the formation of multiple UBMs 60 at a level above the seed layer 48, in other embodiments, multiple UBMs 60 may be formed at a higher or lower level. For example, FIGS. 1 to 8 illustrate the formation of two dielectric layers 34 and 44 and the metallization pattern 40 and the via 42. However, additional dielectric layers and upper metallization patterns and vias may be formed, wherein the UBMs 60 are formed above the upper metallization patterns. Alternatively, the UBMs 60 may be formed on the pads 28 at a lower level.

[0032] Referring now to FIGS. 9-16 , multiple focused views of an under bump metal 160 are provided during the fabrication of the semiconductor die 26. In FIGS. 9-16 , the under bump metal 160 is formed on the conductive contact 140. The under bump metal 160 may be formed according to the process described with respect to FIGS. 1-8 , such that the conductive contact 140 is formed by the metallization pattern 40. Alternatively, the conductive contact 140 may be a pad 28 as described in FIGS. 1-8 , or the conductive contact 140 may be formed by a higher metallization level (not shown in FIGS. 1-8 ).

[0033] In FIGS. 9-16 , the underlying structures of FIGS. 1-8 beneath the conductive contacts 140 are collectively and generally designated by reference numeral 70 and may include conductive interconnect structures extending through various dielectric layers or structures.

[0034] 9, a passivation layer 144 is formed on the integrated circuit die 26 and on portions of the conductive contacts 140. A plurality of openings 142 are formed through the passivation layer 144 to the plurality of conductive contacts 140.

[0035] In FIG. 10 , insulating material 145 is formed on the active side of IC die 26, such as on passivation layer 144. Insulating material 145 may be a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like. In other embodiments, insulating material 145 is formed of a nitride, such as silicon nitride; formed of an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or a similar material. Insulating material 145 may be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), lamination, the like, or a combination thereof.

[0036] In FIG. 11 , a conductive material 148 is then formed, for example, via sputtering, over the conductive contacts 140 and the insulating material 145. The conductive material 148 may include a metal such as copper, titanium, tungsten, aluminum, or the like. The conductive material 148 may be a seed layer.

[0037] As shown in FIG. 12 , a photoresist 150 is then formed on the conductive material 148 and patterned. The photoresist 150 may be formed by spin coating, or the like, and may be exposed for patterning. The pattern of the photoresist corresponds to the metallization pattern conductive contact 140. Patterning forms an opening 151 through the photoresist 150 to expose the conductive material 148. As shown, the opening 151 is formed to have a lateral width W1 or critical dimension.

[0038] In FIG. 13 , a conductive material 158 is formed in the openings of the photoresist 150 and on the exposed portions of the conductive material 148. The conductive material 158 may be formed by plating, such as electroplating or chemical plating, or the like. The conductive material 158 may include a metal, such as nickel, tin, silver, copper, titanium, tungsten, aluminum, or the like. In some embodiments, the conductive material 158 is nickel or a tin and silver alloy. The conductive material 158 may form and define an under bump metallization structure 160 or pad, or the under bump metallization structure 160 may include the conductive material 158 and the conductive material 148.

[0039] Further, in FIG. 13 , an external electrical connector 170 is formed on the under bump metallurgy structure 160 through an opening in the photoresist 150. In some embodiments, the external electrical connector 170 may include a low temperature reflowable material, such as solder, such as lead-free solder, formed on the under bump metallurgy 160 using an acceptable ball drop process. In some embodiments, the external electrical connector 170 is a ball grid array (BGA) ball, a controlled collapse chip connection (C4) bump, a micro bump, or the like. In additional embodiments, the external electrical connector 170 may include a metal post.

[0040] As shown in FIG. 13 , the external electrical connector 170 is formed to have an uppermost surface at a height H1 above the uppermost surface of the photoresist 150 .

[0041] In FIG. 14 , the photoresist 150 is removed. The photoresist may be removed via an acceptable ashing or stripping process, such as using an oxygen plasma, or the like.

[0042] After removing the photoresist 150, the exposed portions of the conductive material 148 are removed, as shown in FIG. 15. The exposed portions of the conductive material 148 may be removed using an acceptable etching process, such as wet or dry etching. The remaining portions of the conductive material 148 and the conductive material 158 may form an under bump metallurgy structure 160. Cross-referencing FIGS. 12 and 15, the under bump metallurgy structure 160 is formed to have a lateral width or critical dimension W1.

[0043] In FIG. 16 , a reflow process is performed and the material of the external electrical connector 170 is reformed. The reflow process can be used to form a metal interconnect phase between the material of the under bump metal structure 160 and the external electrical connector 170. In some embodiments, the reflow process forms the external electrical connector 170 into a homogenous solder ball. As shown, after the reflow process, each external electrical connector 170 has a height H2, and the height H2 is from the uppermost surface of the external electrical connector 170 to the uppermost surface of the insulating material 145.

[0044] Further processing may then be performed to complete the package. For example, referring to the structure of package 100 in FIGS. 1 to 8 , carrier substrate de-bonding may be performed to separate (peel off) carrier substrate 20 from the package structure. According to some embodiments, de-bonding includes projecting light, such as laser light or ultraviolet light, onto release layer 22, so that release layer 22 decomposes under the heating of the light, and carrier substrate 20 may be removed.

[0045] Then, this structure can be turned over and placed on tape and separated. It will be understood by those skilled in the art that many such package structures can be formed on the carrier substrate 20 at the same time, so that individual packages can be separated from other packages, such as by sawing or cutting.

[0046] Various embodiments herein provide for forming a plurality of external electrical connectors 170 having the same height H1 and / or having the same height H2 despite being located in a plurality of regions of an IC die 26 having different UBM densities, ie, different external electrical connector densities.

[0047] FIG. 17 provides a schematic top view of an integrated circuit die 26 including a first region 201 and a second region 202. FIG. 18 is a cross-sectional view of an under bump metallurgy structure 160 in the first region 201, and FIG. 19 is a cross-sectional view of an under bump metallurgy structure 160 in the second region 202. As shown in FIG. 17, the under bump metallurgy structure 160 is more densely arranged in the first region 201 than in the second region 202. For example, the first region 201 may be a dense region 201, and the second region 202 may be an isolated region. The first region 201 has a first ratio of under bump metallurgy structures per unit area, and the second region 202 has a second ratio of under bump metallurgy structures per unit area. As shown, the first ratio is greater than the second ratio.

[0048] It has been found that the formation of multiple external electrical connectors 170 above the under bump metal structure 160 in the dense area 201 generally results in multiple external electrical connectors 170 having a relatively short height (H1 in FIG. 13 and / or H2 in FIG. 16), and the formation of multiple external electrical connectors 170 above the under bump metal structure 160 in the isolated area 202 results in multiple external electrical connectors 170 having a relatively high height (H1 in FIG. 13 and / or H2 in FIG. 16).

[0049] The embodiments herein counteract the tendency of forming a plurality of external electrical connectors 170 having different heights in the dense region 201 and in the isolated region 202. Specifically, the embodiments herein compensate for such a tendency by changing the structure and / or layout of the under bump metallurgy structure 160 in at least one of the regions 201 and / or 202. As a result, the plurality of external electrical connectors 170 are formed to have the same height in the dense region 201 and in the isolated region 202.

[0050] For example, in FIGS. 17 and 18, the plurality of UBM structures 160 in the dense region 201 are formed to have a lateral width or critical dimension W1 equal to the distance D1, while in FIGS. 17 and 19, the plurality of UBM structures 160 in the isolated region 202 are formed to have a lateral width or critical dimension W1 equal to the distance D2. As shown, the distance D2 is greater than the distance D1. In some embodiments, distance D1 or D2 is about 1 to 20 microns, for example, at least 1, at least 2, at least 3, at least 4, at least 5, at least 6, at least 7, at least 8, at least 9, at least 10, at least 11, at least 12, at least 13, at least 14, at least 15, at least 16, at least 17, at least 18, or at least 19 microns; and at most 2, at most 3, at most 4, at most 5, at most 6, at most 7, at most 8, at most 9, at most 10, at most 11, at most 12, at most 13, at most 14, at most 15, at most 16, at most 17, at most 18, at most 19, or at most 20 microns.

[0051] In some embodiments, distance D1 is from 10% to 90% of distance D2. For example, distance D1 can be at least 10%, at least 20%, at least 30%, at least 40%, at least 50%, at least 60%, at least 70%, at least 80%, or at least 90% of distance D2. In some embodiments, distance D1 can be at most 15%, at most 20%, at most 30%, at most 40%, at most 50%, at most 60%, at most 70%, at most 80%, at most 90%, or at most 95% of distance D2.

[0052] As shown in FIGS. 18 and 19 , a plurality of external electrical connectors 170 are formed to have the same height H1 in the dense region 201 and the isolated region 202 .

[0053] In FIGS. 17 to 19 , all the UBM structures 160 may be active UBM structures 161, such as the UBM structure 61 in FIG. 8 . Specifically, the active UBM structure 161 is electrically interconnected with other conductive structures in the die 26 .

[0054] An alternative or additional embodiment is shown in FIGS. 20 to 23. FIG. 20 provides a schematic top view of an integrated circuit die 26 including a first dense region 201, a second isolated region 202, and a third intermediate region 203. As shown in FIG. 20, the integrated circuit die 26 is formed with an active UBM structure 161, a dummy UBM structure 162, such as the dummy UBM structure 62 in FIG. 8, and a dummy UBM structure 163, such as the dummy UBM structure 63 in FIG. 8.

[0055] FIG. 21 is a cross-sectional view of an active UBM structure 161 in regions 201, 202, and 203. FIG. 22 is a cross-sectional view of an inactive or dummy UBM structure 162, which may be located in regions 202 and 203. FIG. 23 is a cross-sectional view of an inactive or dummy UBM structure 163, which may be located in regions 202 and 203.

[0056] As shown in FIG. 20, the active under bump metal structures 161 are arranged more densely in the first region 201 than in the third region 203. Further, the active under bump metal structures 161 are arranged more densely in the third region 203 than in the second region 202. The first region 201 has a first ratio of active under bump metal structures per unit area, the second region 202 has a second ratio of active under bump metal structures per unit area, and the third region 203 has a third ratio of active under bump metal structures per unit area. As shown in the figure, the first ratio is greater than the third ratio, and the third ratio is greater than the second ratio.

[0057] As further shown, a plurality of inactive or dummy UBM structures 162 and / or 163 are provided in the second region 202 and the third region 203 to increase the density of the total plurality of UBM structures 160 therein. As a result, the difference between the plurality of ratios of the total plurality of UBM structures 160 (including active and dummy structures) across the regions 201, 202, and 203 is less than the difference between the plurality of ratios of the plurality of active UBM structures 161. For example, the first region 201 may have a first ratio of the total plurality of UBM structures 160 per unit area, the second region 202 may have a second ratio of the total plurality of UBM structures 160 per unit area, and the third region 203 may have a third ratio of the total plurality of UBM structures 160 per unit area. The first ratio of the total number of UBM structures 160 per unit area, the second ratio of the total number of UBM structures 160 per unit area, and the third ratio of the total number of UBM structures 160 per unit area may be equal, or may be within 1%, within 2%, within 3%, within 4%, within 5%, within 10%, within 15%, or within 20%. In some embodiments, the plurality of local sub-regions within the region 201, the region 202, and the region 203 have an equal ratio of the total number of UBM structures 160 per unit area, or such ratios are within 1%, within 2%, within 3%, within 4%, within 5%, within 10%, within 15%, or within 20%.

[0058] Another way to evaluate the relative density or isolation of the UBM structures 161 involves the inter-structure distance from each UBM structure 161 to the corresponding nearest neighbor UBM structure 161. As shown in FIG. 20, the selected UBM structure 161' in the region 202 is located at an inter-structure distance D9 from the nearest neighbor UBM structure 161.

[0059] In the dense region 201, the active UBM structure 161 may be located at a maximum first inter-active structure distance from the corresponding nearest neighboring active UBM structure 161. In the isolated region 202, the active UBM structure 161 may be located at a second maximum first inter-active structure distance from the corresponding nearest neighboring active UBM structure 161. In the intermediate region 203, the active UBM structure 161 may be located at a third maximum first inter-active structure distance from the corresponding nearest neighboring active UBM structure 161. In some embodiments, the first maximum first inter-active structure distance is less than the third maximum first inter-active structure distance, and less than the second maximum first inter-active structure distance. In some embodiments, the third maximum first inter-active structure distance is less than the second maximum first inter-active structure distance.

[0060] In the dense region 201, the active under bump metal structure 161 may be located at a minimum first inter-active structure distance from the corresponding most adjacent active under bump metal structure 161. In the isolated region 202, the active under bump metal structure 161 may be located at a second minimum first inter-active structure distance from the corresponding most adjacent active under bump metal structure 161. In the intermediate region 203, the active under bump metal structure 161 may be located at a third minimum first inter-active structure distance from the corresponding most adjacent active under bump metal structure 161. In some embodiments, the first minimum first inter-active structure distance is less than the third minimum first inter-active structure distance, and less than the second minimum first inter-active structure distance. In some embodiments, the third minimum first inter-active structure distance is less than the second minimum first inter-active structure distance.

[0061] As shown in FIG. 20, non-active or dummy UBM structures 162 and / or 163 are provided in the second region 202 and the third region 203 to reduce the distance between each active UBM structure 161 and the nearest UBM structure 160 (including the non-active or dummy UBM structures 162 and / or 163). As a result, the isolation of each active UBM structure 161 is reduced. For example, the dummy UBM structures 162 and / or 163 are located at an inter-structure distance D8 from the selected active UBM structure 161'. As shown, the inter-structure distance D8 is less than the active inter-structure distance D9. In addition, the inter-structure distance D8 may be equal to or less than a selected threshold for the inter-structure distance. For example, the thresholds selected for the inter-structure distances in region 202 and region 203 may be based on the active inter-structure distances in region 201, such as based on the average or median active inter-structure distance in region 201, the maximum active inter-structure distance in region 201, or the minimum active inter-structure distance in region 201.

[0062] In some embodiments, each inter-structure distance D8 in region 202 and region 203 is equal to or less than the maximum active inter-structure distance in region 201. In some embodiments, each inter-structure distance D8 in region 202 and region 203 is within 1%, within 2%, within 3%, within 4%, within 5%, within 10%, within 15%, or within 20% of the maximum active inter-structure distance in region 201.

[0063] In some embodiments, each inter-structure distance D8 in region 202 and region 203 is equal to the average or median active inter-structure distance in region 201. In some embodiments, each inter-structure distance D8 in region 202 and region 203 is within 1%, within 2%, within 3%, within 4%, within 5%, within 10%, within 15%, or within 20% of the average or median active inter-structure distance in region 201.

[0064] In some embodiments, each active UBM structure 161 within region 202 and region 203 that is located at an inter-active structure distance D9 from the nearest active UBM structure 161 (greater than a selected threshold) is provided with a closer non-active or dummy UBM structure (or structures) 162 and / or 163 to reduce the relative isolation of the active UBM structures 161. By providing the non-active or dummy UBM structures 162 and / or 163 in the second region 202 and the third region 203, the relative isolation of each active UBM structure 161 in the second region 202 and in the third region 203 is reduced.

[0065] By reducing the relative isolation of each UBM structure 160, i.e., no UBM structure 160 is spaced apart from a corresponding nearest UBM structure by a distance greater than a selected threshold, variations in height between the plurality of external electrical connectors 170 formed above the UBM structure 160 are reduced or eliminated.

[0066] As shown in FIGS. 21 to 23 , a plurality of external electrical connectors 170 formed above the active under-bump metal structure 161, above the dummy under-bump metal structure 162, and above the dummy under-bump metal structure 163 are each formed to have an uppermost surface at the same height H1 above the uppermost surface of the photoresist 150.

[0067] Note that the embodiments of FIGS. 17 to 19 limit the vertical height of the plurality of external electrical connectors 170 by forming a plurality of UBM pads 160 having different critical dimensions, and the embodiments of FIGS. 20 to 23 limit the vertical height of the plurality of external electrical connectors 170 by forming a plurality of dummy UBM pads 162 to 163 adjacent to the relatively isolated active UBM pads 161. In addition, note that the die 26 may be provided with a combination of the embodiments of FIGS. 17 to 19 and 20 to 23, such that in some embodiments, the plurality of UBM pads 160 are formed to have different critical dimensions, and a plurality of dummy UBM pads are formed to reduce the isolation of the relatively isolated active UBM pads.

[0068] Referring now to FIG. 24 , a process for forming an active UBM structure 161 and a process for forming dummy UBM structures 162 and / or 163 are further described. During the formation of the active UBM structure 161, the process may use a first pitch P1. However, the formation of multiple dummy UBM structures 162 and / or 163 may be performed with a second pitch P2 different from the first pitch P1. As a result, the formation process may be smoother and cavity defects may be prevented.

[0069] FIG. 25 provides a top view of the UBM structure 160. As shown, the UBM structure 160 may be provided to have a circular, oval, or hexagonal shape. The UBM structure 160 is not limited to a circular, oval, or hexagonal shape. Specifically, the UBM structure 160 may be formed into any suitable shape, including a triangle, a square, a rectangle, a pentagon, an octagon, an irregular shape, etc. Further, it is noted that each active UBM structure 161, each dummy UBM structure 162, and each dummy UBM structure 163 may be formed into any selected shape, regardless of the shapes of other active UBM structures 161, dummy UBM structures 162, and dummy UBM structures 163 on the die 26.

[0070] FIG26 provides a flow chart of method 900. As shown in the figure, method 900 includes determining an integrated circuit (IC) layout design at operation S902.

[0071] The method 900 also includes determining the relative isolation of the UBM structure at operation S904. For example, the integrated circuit layout design may include a dense area and an isolated area, the dense area including a plurality of external electrical connectors densely arranged on the UBM structure, and the isolated area including a plurality of external electrical connectors isolated on the UBM structure. Determining the relative isolation of the UBM structure may include determining an active structure distance between each active UBM structure.

[0072] At operation S906, the method 900 determines the effect on bump height resulting from the relative isolation of the UBM structures. For example, the method 900 may determine that a plurality of external electrical connectors formed over isolated UBM structures will be formed to have an increased height relative to a plurality of external electrical connectors formed over densely packed UBM structures. Determining the effect on bump height resulting from the relative isolation of the UBM structures may include a repository of known height effects based on active structure to active structure distance or device density or isolation reference.

[0073] In operation S908, method 900 changes the integrated circuit layout design to improve bump height uniformity. For example, the integrated circuit layout design may be changed to provide a plurality of densely arranged external electrical connectors having a first height on an under bump metal (UBM) pad, and to provide a plurality of isolated external electrical connectors having a second height equal to the first height on the under bump metal (UBM) pad. In other words, operation S908 may limit the plurality of external electrical connectors to a preselected vertical height, i.e., the first height.

[0074] For example, at operation S908, the method 900 may increase the critical dimension of the openings under the UBM structure and / or above the UBM structure in the isolated region. Additionally or alternatively, at operation S908, the method 900 may reduce the critical dimension of the openings under the UBM structure and / or above the UBM structure in the dense region. Additionally or alternatively, at operation S908, the method 900 may add a dummy UBM structure to the integrated circuit layout design to reduce the inter-structure distance of multiple UBM structures in the isolated region.

[0075] In operation S910, method 900 manufactures an integrated circuit (IC) according to the changed integrated circuit layout design. Manufacturing the integrated circuit includes forming a plurality of under bump metal (UBM) pads in the dense area and in the isolated area; and forming a plurality of external electrical connectors over the plurality of under bump metal (UBM) pads in the dense area and in the isolated area.

[0076] As a result of operation S908, an integrated circuit having improved bump height uniformity is manufactured. For example, external electrical connectors in the integrated circuit can be formed to have the same height, or to have heights that are within 1%, within 2%, within 3%, within 4%, within 5%, within 10%, or within 20% of each other, whether in dense areas or in isolated areas.

[0077] In one embodiment, a method includes forming a semiconductor die having a plurality of under bump metallization (UBM) pads in dense areas and in isolated areas; forming a plurality of external electrical connectors in contact with the UBM pads; and limiting the external electrical connectors to a preselected vertical height.

[0078] In some embodiments, the method further includes forming an opening above the under bump metal pad; wherein forming an external electrical connector in contact with the under bump metal pad includes forming the external electrical connector in the opening.

[0079] In some embodiments of the method, forming the external electrical connector includes dropping a solder ball into the opening.

[0080] In some embodiments of the method, limiting the plurality of external electrical connectors to a preselected vertical height includes forming a plurality of openings having a first critical dimension over the plurality of under bump metal pads in a dense region; forming a plurality of openings having a second critical dimension greater than the first critical dimension over the plurality of under bump metal pads in an isolated region, and forming a plurality of external electrical connectors in contact with the plurality of under bump metal pads includes forming the plurality of external electrical connectors in the plurality of openings.

[0081] In some embodiments of the method, limiting the external electrical connector to a preselected vertical height includes forming a plurality of under bump metal pads having a first critical dimension in a dense area; and forming a plurality of under bump metal pads having a second critical dimension greater than the first critical dimension in an isolated area.

[0082] In some embodiments of the method, each UBM pad in the dense region is separated from the nearest UBM pad by a first distance; at least one UBM pad in the isolated region is separated from the relatively nearest UBM pad by a second distance greater than the first distance; and limiting the external electrical connector to a preselected vertical height includes forming a dummy pad in the isolated region at a third distance from at least one UBM pad, wherein the third distance is less than the second distance; and forming an external electrical connector in contact with the dummy pad while forming an external electrical connector in contact with the UBM pad. In some embodiments, the third distance is within 20% of the first distance. In some embodiments, the third distance is equal to the first distance.

[0083] In some embodiments of the method, each under bump metal pad in the dense area is separated from the nearest under bump metal pad by a first distance; at least one under bump metal pad in the isolated area is separated from the relatively nearest under bump metal pad by a second distance greater than the first distance; and limiting the external electrical connector to a preselected vertical height includes forming a plurality of under bump metal pads having a first critical dimension in the dense area; forming a plurality of under bump metal pads having a second critical dimension greater than the first critical dimension in the isolated area; forming a dummy pad in the isolated area at a third distance from at least one under bump metal pad, wherein the third distance is less than the second distance; and forming an external electrical connector in contact with the dummy pad while forming an external electrical connector in contact with the under bump metal pad.

[0084] In another embodiment, a method includes determining an integrated circuit layout design, wherein the integrated circuit layout design includes a dense area and an isolated area, the dense area including external electrical connectors densely arranged on an under bump metal (UBM) pad, and the isolated area including multiple external electrical connectors isolated on multiple under bump metal (UBM) pads, wherein determining the integrated circuit layout design includes providing multiple densely arranged external electrical connectors having a first height on the under bump metal (UBM) pads, and wherein determining the integrated circuit layout design includes providing multiple isolated external electrical connectors having a second height equal to the first height on the multiple under bump metal (UBM) pads; forming multiple under bump metal (UBM) pads in the dense area and in the isolated area; and forming multiple external electrical connectors over the multiple under bump metal (UBM) pads in the dense area and in the isolated area.

[0085] In some embodiments of the method, determining the integrated circuit layout design includes providing an under bump metal (UBM) pad having a first lateral critical dimension in the dense area and providing an under bump metal (UBM) pad having a second lateral critical dimension different from the first lateral critical dimension in the isolated area. In some embodiments, the second lateral critical dimension is greater than the first lateral critical dimension.

[0086] In some embodiments of the method, determining an integrated circuit layout design includes providing a dummy under bump metallization (UBM) pad in the isolation region.

[0087] In some embodiments of the method, the UBM pads in the dense area, the UBM pads in the isolated area, and the dummy UBM pads have the same lateral critical dimension.

[0088] In some embodiments of the method, the dense region has a first ratio of UBM pads per unit area; the isolated region has a combined ratio of UBM pads and dummy UBM pads per unit area; and the first ratio is equal to the combined ratio.

[0089] In another embodiment, a semiconductor die includes a dense region, the dense region includes a plurality of first under bump metal (UBM) pads, wherein the dense region has a first ratio of the plurality of first under bump metal pads per unit area; a first plurality of external electrical connectors in contact with the first under bump metal pads, wherein each first external electrical connector has a first vertical height; an isolation region including a plurality of second under bump metal (UBM) pads, wherein the isolation region has a second ratio of the plurality of second under bump metal (UBM) pads per unit area, wherein the first ratio is greater than the second ratio; and a plurality of second external electrical connectors in contact with the plurality of second under bump metal (UBM) pads, wherein each second external electrical connector has a second vertical height; wherein the semiconductor die is configured such that the first vertical height is equal to the second vertical height.

[0090] In some embodiments of the semiconductor die, a plurality of first external electrical connectors have a first lateral critical dimension, and by providing a plurality of second external electrical connectors with a second lateral critical dimension different from the first lateral critical dimension, the semiconductor die is configured such that a first vertical height is equal to a second vertical height.

[0091] In some embodiments of the semiconductor die, the second lateral critical dimension is greater than the first lateral critical dimension.

[0092] In some embodiments, the semiconductor die includes a dielectric layer covering the dense area and the isolated area, and a plurality of openings are formed in the dielectric layer covering the first under-bump metal pad and the second under-bump metal pad, wherein the openings limit the first external electrical connector to a first lateral critical dimension and limit the second external electrical connector to a second lateral critical dimension.

[0093] In some embodiments of the semiconductor die, the semiconductor die is configured such that a first vertical height is equal to a second vertical height by including a dummy under bump metal (UBM) pad in an isolation region, wherein a third ratio of a total plurality of under bump metal pads including a plurality of second under bump metal pads and a plurality of dummy under bump metal pads per unit area is present in the isolation region, wherein the third ratio is greater than the second ratio.

[0094] The above summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art should understand that they may easily use the present disclosure as a basis for the design or modification of other processes and structures to achieve the same purpose and / or achieve the same advantages as the embodiments introduced herein. Those skilled in the art should also understand that such equal constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications without departing from the spirit and scope of the present disclosure.

[0095] 20: Carrier substrate 22: Release layer 24: Adhesive 26: Grain 28: Solder pad 30: Passivation film 32: Die connector 34: Dielectric material (dielectric layer) 36: Sealant 38: Dielectric layer 40:Metalized pattern 42: Guide hole 44: Dielectric layer 46: Opening 48: Seed layer 50: Photoresist 52: Opening 60: Under Bump Metal 61: Active under-bump metal (under-bump metal, under-bump metal structure) 62: dummy under-bump metal (dummy under-bump metal structure) 63: dummy under-bump metal (dummy under-bump metal structure) 70: Lower structure 100: Packaging (packaging structure) 140: Conductive contact 142: Opening 144: Passivation layer 145: Insulation material 148: Conductive material 150: Photoresist 151: Opening 158: Conductive materials 160: Under-bump metal structure (under-bump metal, under-bump metal pad) 161: Active under-bump metal structure (under-bump metal pad) 161': Active metal structure under the bump 162: Virtual under-bump metal structure (virtual under-bump metal pad) 163: Virtual under-bump metal structure (virtual under-bump metal pad) 170: External electrical connector 201: Dense area (first area, area) 202: Isolation area (second area, area) 203: Middle area (third area, area) 900: Method D1: Distance D2: Distance D8: Distance between structures D9: Distance between active structures H1: Height H2: Height P1: First spacing P2: Second spacing S902: Operation S904: Operation S906: Operation S908: Operation S910: Operation W1: Key dimension (lateral width)

[0096] Domestic storage information (please note the order of storage institution, date and number) none Overseas deposit information (please note the order of deposit country, institution, date and number) none

Claims

1. A method of manufacturing a semiconductor device, comprising: forming a semiconductor die having a plurality of under-bump metal (UBM) pads in a dense region and an isolated region; forming a plurality of external electrical connectors in contact with the UBM pads; and limiting the external electrical connectors to a preselected vertical height; wherein, In the dense region, each of the under-bump pads is spaced a first distance from a nearest neighboring under-bump pad; in the isolated region, at least one under-bump pad is spaced a second distance from a relatively nearest neighboring under-bump pad greater than the first distance; and limiting the external electrical connectors to the preselected vertical height includes: forming a dummy pad in the isolated region at a third distance from the at least one under-bump pad, wherein the third distance is less than the second distance and is within 20% of the first distance, the dummy pad being disconnected from any electrical path of the semiconductor die; and forming an external electrical connector in contact with the dummy pad, while simultaneously forming the external electrical connectors in contact with the under-bump pads.

2. The method of manufacturing a semiconductor device as claimed in claim 1, further comprising: forming a plurality of openings above the under-bump metal pads, wherein the external electrical connectors that contact the under-bump metal pads are formed in the openings.

3. The method of manufacturing a semiconductor device as claimed in claim 1, wherein limiting the external electrical connectors to the preselected vertical height comprises: forming the under-bump metal pads having a first critical dimension in the dense region; and forming the under-bump metal pads having a second critical dimension greater than the first critical dimension in the isolated region.

4. The method of manufacturing a semiconductor device as described in claim 3, wherein: The dense region has a first ratio of the under-bump metal pads per unit area, and the isolated region has a second ratio of the under-bump metal pads per unit area, the first ratio being greater than the second ratio.

5. The method of manufacturing a semiconductor device as described in claim 1, wherein: The method of limiting the external electrical connectors to the preselected vertical height includes: forming the under-bump metal pads having a first critical dimension in the dense region; and forming the under-bump metal pads having a second critical dimension greater than the first critical dimension in the isolated region.

6. A method of manufacturing a semiconductor device, comprising: determining an integrated circuit layout design, wherein the integrated circuit layout design includes a dense region and an isolated region, the dense region including a plurality of external electrical connectors densely arranged on a plurality of under-bump metal (UBM) pads, the isolated region including a plurality of isolated external electrical connectors on the plurality of UBM pads, wherein the integrated circuit layout design includes providing a plurality of densely arranged external electrical connectors having a first height on the plurality of UBM pads, and wherein the integrated circuit layout design includes providing the isolated external electrical connectors having a second height equal to the first height on the plurality of UBM pads, wherein the integrated circuit layout design further includes providing a plurality of dummy under-bump pads in the isolated region, and the dummy under-bump pads being disconnected from any electrical path of the integrated circuit layout design; The under-bump metal pads are formed in the dense region and the isolated region, wherein the dense region has a first ratio of multiple under-bump metal pads per unit area, and the isolated region has a combined ratio of multiple under-bump metal pads and multiple dummy under-bump metal pads per unit area, the difference between the first ratio and the combined ratio being within 20%; and multiple external electrical connectors are formed above the under-bump metal (UBM) pads in the dense region and the isolated region.

7. A method of manufacturing a semiconductor device as claimed in claim 6, wherein determining the integrated circuit layout design includes providing under-bump metal (UBM) pads having a first lateral critical dimension in the dense region and providing under-bump metal (UBM) pads having a second lateral critical dimension different from the first lateral critical dimension in the isolated region.

8. A semiconductor die comprising: a dense region including a plurality of first under-bump metal (UBM) pads, wherein the dense region has a first ratio of the plurality of first under-bump metal pads per unit area; a plurality of first external electrical connectors in contact with the first under-bump metal pads, wherein each of the first external electrical connectors has a first vertical height; an isolation region including a plurality of second under-bump metal (UBM) pads, wherein the isolation region has a second ratio of the plurality of second under-bump metal pads per unit area, wherein the first ratio is greater than the second ratio; and a plurality of second external electrical connectors in contact with the second under-bump metal pads, wherein each of the second external electrical connectors has a second vertical height; The semiconductor die is configured such that the first vertical height is equal to the second vertical height, and the isolation region includes a plurality of dummy bump under-metal pads that are disconnected from any electrical path of the semiconductor die. The isolation region has a third ratio of a total plurality of under-bump pads, the total plurality of under-bump pads including the second under-bump pads and the dummy bump under-metal pads per unit area. The third ratio is greater than the second ratio, and the difference between the first ratio and the third ratio is within 20%.

9. The semiconductor die as claimed in claim 8, wherein the first external electrical connectors have a first lateral critical dimension, and wherein the semiconductor die is configured such that the first vertical height is equal to the second vertical height, by providing the second external electrical connectors with a second lateral critical dimension different from the first lateral critical dimension.

10. The semiconductor die as claimed in claim 9 further comprises: a dielectric layer covering the dense region and the isolated region, wherein a plurality of openings are formed in the dielectric layer covering the first under-bump metal pads and covering the second under-bump metal pads, and wherein the openings constrain the first external electrical connectors to the first lateral critical size and the second external electrical connectors to the second lateral critical size.

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