Semiconductor devices

Abstract

This invention provides a semiconductor device with minimal deviation in transistor characteristics. The invention provides a semiconductor device including a transistor, wherein the transistor comprises: a first insulator; a first oxide on the first insulator; a first conductor, a second conductor, and a second oxide disposed between the first conductor and the second conductor on the first oxide; a second insulator on the second oxide; and a third conductor on the second insulator, wherein the top surface of the first oxide in the region overlapping with the third conductor is lower than the top surface of the first oxide in the region overlapping with the first conductor, and in the region overlapping with the third conductor, a curved surface is formed between the side surface and the top surface of the first oxide, the radius of curvature of the curved surface being 1 nm or more and 15 nm or less.

Description

Technical Field

[0001] One embodiment of the present invention relates to a transistor, a semiconductor device, and an electronic device. Another embodiment of the present invention relates to a method for manufacturing a semiconductor device. Another embodiment of the present invention relates to a semiconductor wafer and a module.

[0002] Note that in this specification and other publications, the term "semiconductor device" refers to any device capable of operating by utilizing semiconductor characteristics. In addition to semiconductor elements such as transistors, semiconductor circuits, computing devices, and memory devices are also examples of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting equipment, electro-optical devices, power storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices may also include semiconductor devices.

[0003] Note that an embodiment of the present invention is not limited to the aforementioned technical fields. An embodiment of the invention disclosed in this specification and other disclosures relates to an object, method, or manufacturing method. Alternatively, an embodiment of the present invention relates to a process, machine, product, or composition of matter. Prior Art

[0004] Technology that uses semiconductor thin films formed on an insulating substrate to create transistors is attracting attention. These transistors are widely used in electronic devices such as integrated circuits (ICs) and video display devices (also simply referred to as displays). Silicon-based semiconductor materials are widely known as semiconductor thin films suitable for transistors. Oxide semiconductors are also gaining attention as other materials.

[0005] In oxide semiconductors, CAAC (c-axis aligned crystalline) structures and NC (nanocrystalline) structures, which are neither single crystal nor amorphous, have been discovered (see Non-Patent Documents 1 and 2).

[0006] Non-Patent Documents 1 and 2 disclose a technology for manufacturing a transistor using an oxide semiconductor having a CAAC structure.

[0007] [Non-Patent Literature 1] S. Yamazaki et al., “SID Symposium Digest of Technical Papers”, 2012, volume 43, issue 1, pp. 183-186 [Non-patent document 2] S. Yamazaki et al., “Japanese Journal of Applied Physics”, 2014, volume 53, number 4S, pp. 04ED18-1-04ED18-10 Summary of the Invention

[0008] One object of one embodiment of the present invention is to provide a semiconductor device with small variations in transistor characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device that can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device with good reliability. Another object of one embodiment of the present invention is to provide a semiconductor device with low power consumption.

[0009] Note that the inclusion of these objectives does not preclude the existence of other objectives. An embodiment of the present invention does not necessarily achieve all of the aforementioned objectives. Objectives other than the aforementioned objectives may be readily apparent from the description, drawings, claims, and other aspects, and may be extracted from such description.

[0010] One embodiment of the present invention is a semiconductor device comprising: a transistor, wherein the transistor includes: a first insulator; a first oxide on the first insulator; a first conductor, a second conductor, and a second oxide disposed between the first and second conductors on the first oxide; a second insulator on the second oxide; and a third conductor on the second insulator, wherein a top surface of the first oxide in a region overlapping with the third conductor is lower than a top surface of the first oxide in a region overlapping with the first conductor, and in a region overlapping with the third conductor, a curved surface is provided between a side surface and a top surface of the first oxide, and a radius of curvature of the curved surface is greater than or equal to 1 nm and less than or equal to 15 nm.

[0011] In the above-mentioned semiconductor device, preferably, when the bottom surface of the first insulator is used as a reference, the difference between the height of the top surface of the first oxide in the region overlapping with the third conductor and the height of the top surface of the first oxide in the region overlapping with the first conductor is greater than 1 nm and less than 5 nm.

[0012] In the above-mentioned semiconductor device, it is preferred that, in the channel width direction of the transistor, half of the difference between the length of the bottom surface of the first oxide in the region overlapping with the first conductor and the length of the bottom surface of the first oxide in the region overlapping with the third conductor is greater than 2 nm and less than 10 nm.

[0013] In the above-mentioned semiconductor device, preferably, the transistor includes a third oxide and a fourth oxide, the third oxide is arranged between the first oxide and the first conductor, the fourth oxide is arranged between the first oxide and the second conductor, and in the channel length direction of the transistor, the bottom surface of the second oxide is lower than the bottom surfaces of the third oxide and the fourth oxide.

[0014] Another embodiment of the present invention is a semiconductor device comprising: a plurality of transistors, wherein the plurality of transistors include: a first insulator; a first oxide on the first insulator; a first conductor, a second conductor, and a second oxide disposed between the first and second conductors on the first oxide; a second insulator on the second oxide; and a third conductor on the second insulator, wherein a top surface of the first oxide in a region overlapping with the third conductor is lower than a top surface of the first oxide in a region overlapping with the first conductor, and a curved surface is formed between a side surface and a top surface of the first oxide in the region overlapping with the third conductor, and wherein, in the Id-Vg characteristics of the plurality of transistors, a standard deviation σ of Vsh is less than 60 mV.

[0015] In the above-mentioned semiconductor device, it is preferred that the channel length of the plurality of transistors is greater than or equal to 40 nm and less than or equal to 80 nm, and the channel width of the plurality of transistors is greater than or equal to 40 nm and less than or equal to 80 nm.

[0016] In the above-mentioned semiconductor device, the curvature radius of the curved surface is preferably greater than or equal to 1 nm and less than or equal to 15 nm.

[0017] Another embodiment of the present invention is a semiconductor device comprising: a transistor, wherein the transistor includes: a first insulator; a first oxide on the first insulator; a first conductor, a second conductor, and a second oxide disposed between the first and second conductors on the first oxide; a second insulator on the second oxide; a third conductor on the second insulator; and the third insulator disposed in contact with a top surface of the first conductor, a top surface of the second conductor, and a portion of a side surface of the first oxide. In the channel width direction of the transistor, the length of the bottom surface of the first oxide in a region overlapping with the first conductor is greater than the length of the bottom surface of the first oxide in a region overlapping with the third conductor. In the region overlapping with the third conductor, a curved surface is formed between the side surface and the top surface of the first oxide. The first oxide contains indium, an element M (M is gallium, yttrium, or tin), and zinc. The third insulator contains an element that serves as an impurity of the first oxide. Moreover, the concentration ratio of the element to the element M on the side surface of the first oxide in the region overlapping with the third conductor is lower than the concentration ratio of the element to the element M on the side surface of the first oxide in the region overlapping with the first conductor.

[0018] In the above semiconductor device, the element contained in the third insulator is preferably aluminum.

[0019] In the above-mentioned semiconductor device, the curvature radius of the curved surface is preferably greater than or equal to 1 nm and less than or equal to 15 nm.

[0020] According to one embodiment of the present invention, a semiconductor device with low variation in transistor characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with excellent electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device that can achieve miniaturization or high integration can be provided. According to one embodiment of the present invention, a semiconductor device with excellent reliability can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0021] Note that the inclusion of these effects does not preclude the existence of other effects. An embodiment of the present invention does not necessarily achieve all of the effects described above. Effects other than the above effects may be readily apparent from the description, drawings, and claims, and may be extracted from such description. Simple diagram description

[0022] In the diagram: FIG1A is a top view of a semiconductor device according to an embodiment of the present invention. FIG1B to FIG1D are cross-sectional views of a semiconductor device according to an embodiment of the present invention. [Fig. 2] is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 3A and 3B are perspective views of a semiconductor device according to an embodiment of the present invention. FIG4A is a plan view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG4B to FIG4D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG5A is a top view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG5B to FIG5D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG6A is a top view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG6B to FIG6D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG7A is a top view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG7B to FIG7D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG8A is a top view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG8B to FIG8D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG9A is a top view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG9B to FIG9D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG10A is a top view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG10B to FIG10D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG11A is a top view illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG11B to FIG11D are cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. FIG12A is a top view of a semiconductor device according to an embodiment of the present invention. FIG12B to FIG12D are cross-sectional views of a semiconductor device according to an embodiment of the present invention. 13A and 13B are cross-sectional views of a semiconductor device according to an embodiment of the present invention. FIG14 is a cross-sectional view showing the structure of a memory device according to one embodiment of the present invention. FIG15 is a cross-sectional view showing the structure of a memory device according to one embodiment of the present invention. 16A and 16B are block diagrams showing a configuration example of a memory device according to an embodiment of the present invention. 17A to 17H are circuit diagrams illustrating a configuration example of a memory device according to an embodiment of the present invention. 18A and 18B are schematic diagrams of a semiconductor device according to an embodiment of the present invention. 19A to 19E are schematic diagrams of a memory device according to an embodiment of the present invention. [FIG. 20A] to [FIG. 20H] are diagrams showing an electronic device according to an embodiment of the present invention. [Figure 21] is a diagram showing a normal probability plot of the Shift value of the sample of the embodiment. FIG. 22 is a diagram showing the stress-time dependency of ΔVsh in the +GBT stress test of the embodiment. FIG23A is a graph showing the stress-time dependence of Ion in the +GBT stress test of an embodiment. FIG23B is a graph showing the stress-time dependence of S value in the +GBT stress test of an embodiment. FIG23C is a graph showing the stress-time dependence of μFE in the +GBT stress test of an embodiment. [Figure 24] is a diagram showing the Id-Vg characteristics of the transistor of the embodiment. FIG25A is a diagram showing a normal probability plot of Vsh according to an embodiment. FIG25B is a diagram showing a normal probability plot of Ion according to an embodiment. FIG25C is a diagram showing the Vbg dependency of Vsh according to an embodiment. [ Fig. 26A ] is a graph showing ΔVsh in a +GBT stress test of an embodiment. [ Fig. 26B ] is a graph showing the stress-time dependency of the S value of an embodiment. Implementation Method

[0023] The following describes the embodiments with reference to the drawings. It should be noted that those skilled in the art will readily understand that the embodiments may be implemented in a variety of different forms, and that their methods and details may be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited solely to the following embodiments.

[0024] In the drawings, sizes, layer thicknesses, or regions are sometimes exaggerated for clarity. Therefore, the present invention is not limited to the dimensions shown in the drawings. Furthermore, the drawings schematically illustrate idealized examples, and therefore the present invention is not limited to the shapes or numerical values ​​shown. For example, in actual manufacturing processes, layers or photoresist masks may be unintentionally thinned due to etching or other processes, but this is not reflected in the drawings for ease of understanding. Furthermore, in the drawings, the same reference numerals may be used across different figures to represent the same parts or parts with the same function, omitting any duplicate descriptions. Furthermore, parts with the same function may be represented by the same hatching without any specific reference numerals.

[0025] In addition, in top views (also called plan views) or perspective views, some components may be omitted to facilitate understanding of the invention. In addition, some hidden lines may be omitted.

[0026] In this specification, etc., ordinal numbers such as "first" and "second" are used for convenience, but they do not indicate the order of manufacturing processes or stacking layers. Therefore, for example, "first" can be appropriately replaced with "second" or "third" to provide a more detailed description. Furthermore, the ordinal numbers used in this specification, etc., may not always match the ordinal numbers used to designate an embodiment of the present invention.

[0027] For convenience, terms such as "upper" and "lower" are used in this specification to describe the positional relationships of components with reference to the drawings. The positional relationships of components may vary depending on the orientation in which they are described. Therefore, the terms are not limited to those described in this specification and may be substituted as appropriate depending on the situation.

[0028] For example, in this specification, when it is explicitly stated that "X is connected to Y," this means: X is electrically connected to Y; X is functionally connected to Y; or X is directly connected to Y. Therefore, connections other than those shown in the drawings or text are not limited to those specified. Here, X and Y are objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0029] In this specification and other documents, a transistor refers to a device consisting of at least three terminals: a gate, a drain, and a source. A transistor has a region (hereinafter referred to as a channel-forming region) between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode) where a channel is formed. Current can flow between the source and drain through the channel-forming region. Note that in this specification and other documents, the channel-forming region refers to the region where current primarily flows.

[0030] In addition, when using transistors with different polarities or when the direction of current changes during circuit operation, the functions of the source and drain may be reversed. Therefore, in this specification, etc., the terms source and drain may be reversed.

[0031] Note that the channel length refers to, for example, the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on state) and the gate electrode overlap in a top view of a transistor, or the distance between the source (source region or source electrode) and drain (drain region or drain electrode) in the channel formation region. Furthermore, the channel length of a transistor does not necessarily have the same value in all regions. In other words, the channel length of a transistor is not always limited to a single value. Therefore, in this specification, the channel length refers to any value, maximum value, minimum value, or average value, within the channel formation region.

[0032] The channel width refers to, for example, the area where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in the on state) and the gate electrode overlap in a top view of the transistor, or the length of the channel forming region in a direction perpendicular to the channel length. Furthermore, the channel width of a transistor is not necessarily the same across all regions. In other words, the channel width of a transistor is not always limited to a single value. Therefore, in this specification, the channel width refers to any value, maximum value, minimum value, or average value, within the channel forming region.

[0033] In this specification and other documents, depending on the transistor structure, the actual channel width in the channel-forming region (hereinafter referred to as the "effective channel width") may differ from the channel width shown in a top view of the transistor (hereinafter referred to as the "apparent channel width"). For example, when the gate electrode covers the side surfaces of the semiconductor, the effective channel width may be greater than the apparent channel width, and its effect cannot be ignored. For example, in miniaturized transistors where the gate electrode covers the side surfaces of the semiconductor, a higher proportion of the channel-forming region may be formed on the side surfaces of the semiconductor. In such cases, the effective channel width is greater than the apparent channel width.

[0034] In these situations, it's sometimes difficult to estimate the effective channel width through actual measurement. For example, estimating the effective channel width based on design values ​​requires an assumption: the semiconductor's shape is known. Therefore, accurately measuring the effective channel width is difficult when the semiconductor's shape is uncertain.

[0035] In this specification, when simply referring to "channel width," this may refer to the apparent channel width. Alternatively, when simply referring to "channel width," this may refer to the effective channel width. Note that values ​​for channel length, channel width, effective channel width, and apparent channel width can be determined by analyzing cross-sectional TEM images, etc.

[0036] Note that semiconductor impurities refer to elements other than the main component of the semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity. The presence of impurities can sometimes increase the defect state density of the semiconductor or reduce its crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor's properties include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component of the oxide semiconductor. Examples include hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Note that water can also act as an impurity. Furthermore, for example, the incorporation of impurities can sometimes lead to the formation of oxygen vacancies (also called VO) in the oxide semiconductor.

[0037] Note that in this specification and other documents, "silicon oxynitride" refers to a substance containing more oxygen than nitrogen. Furthermore, "silicon nitride oxide" refers to a substance containing more nitrogen than oxygen.

[0038] Note that in this specification, etc., "insulator" may be referred to as "insulating film" or "insulating layer." Also, "conductor" may be referred to as "conductive film" or "conductive layer." Also, "semiconductor" may be referred to as "semiconductor film" or "semiconductor layer."

[0039] In this specification, etc., "parallel" refers to a state where the angle formed by two straight lines is greater than -10 degrees and less than 10 degrees. Therefore, this also includes a state where the angle is greater than -5 degrees and less than 5 degrees. Furthermore, "substantially parallel" refers to a state where the angle formed by two straight lines is greater than -30 degrees and less than 30 degrees. Furthermore, "perpendicular" refers to a state where the angle between two straight lines is greater than 80 degrees and less than 100 degrees. Therefore, this also includes a state where the angle is greater than 85 degrees and less than 95 degrees. "Substantially perpendicular" refers to a state where the angle formed by two straight lines is greater than 60 degrees and less than 120 degrees.

[0040] In this specification, metal oxide refers to a broad range of metal oxides. Metal oxides are categorized as oxide insulators, oxide conductors (including transparent oxide conductors), and oxide semiconductors (OS). For example, when a metal oxide is used in the semiconductor layer of a transistor, it is sometimes referred to as an oxide semiconductor. In other words, an OS transistor can be referred to as a transistor containing a metal oxide or oxide semiconductor.

[0041] Note that in this specification, etc., "normally off" means that when no potential is applied to the gate or when ground potential is applied to the gate, the drain current flowing through the transistor per channel width of 1 μm is 1 × 10-20 A or less at room temperature, 1 × 10-18 A or less at 85°C, or 1 × 10-16 A or less at 125°C.

[0042] Implementation Method 1 In this embodiment, an example of a semiconductor device including a transistor 200 according to one embodiment of the present invention is described.

[0043] <Structural Example of Semiconductor Device> Figures 1A to 1D are top views and cross-sectional views of a semiconductor device including a transistor 200. Figure 1A is a top view of the semiconductor device. Figures 1B to 1D are cross-sectional views of the semiconductor device. Figure 1B is a cross-sectional view taken along dashed line A1-A2 in Figure 1A , which corresponds to a cross-sectional view along the channel length of transistor 200. Figure 1C is a cross-sectional view taken along dashed line A3-A4 in Figure 1A , which corresponds to a cross-sectional view along the channel width of transistor 200. Figure 1D is a cross-sectional view taken along dashed line A5-A6 in Figure 1A . Note that some components are omitted in the top view of Figure 1A for clarity.

[0044] A semiconductor device according to one embodiment of the present invention includes an insulator 212 on a substrate (not shown), an insulator 214 on insulator 212, a transistor 200 on insulator 214, an insulator 280 on transistor 200, an insulator 282 on insulator 282, an insulator 274 on insulator 283, and an insulator 281 on insulator 274. Insulators 212, 214, 280, 282, 283, 274, and 281 serve as interlayer films. The semiconductor device also includes a conductor 240 (conductor 240a and conductor 240b) electrically connected to transistor 200 and serving as a plug. Furthermore, insulators 241 (insulator 241a and insulator 241b) are provided in contact with the side surfaces of conductor 240 serving as a plug. Furthermore, conductors 246 (conductors 246 a and 246 b ) are provided on the insulator 281 and the conductor 240 , and are electrically connected to the conductor 240 and used as wiring.

[0045] Insulator 241a is disposed in contact with the inner walls of the openings of insulators 254, 280, 282, 283, 274, and 281. A first conductor of conductor 240a is disposed in contact with the side surfaces of insulator 241a, with a second conductor of conductor 240a disposed inside the first conductor. Furthermore, insulator 241b is disposed in contact with the inner walls of the openings of insulators 254, 280, 282, 283, 274, and 281. A first conductor of conductor 240b is disposed in contact with the side surfaces of insulator 241b, with a second conductor of conductor 240b disposed inside the first conductor. The top surface of conductor 240 can be approximately the same height as the top surface of insulator 281. While transistor 200 includes a stack of first and second conductors of conductor 240, the present invention is not limited to this. For example, the conductor 240 may have a single-layer structure or a stacked structure of three or more layers. In the case of a structure having a stacked structure, an ordinal number may be assigned according to the order in which it is formed to distinguish them.

[0046] [Transistor 200] As shown in FIG. 1A to FIG. 1D , transistor 200 includes an insulator 216 on an insulator 214; a conductor 205 (conductor 205a and conductor 205b) disposed in an embedded manner in insulator 216; an insulator 222 on insulator 216 and on conductor 205; an insulator 224 on insulator 222; an oxide 230a on insulator 224; an oxide 230b on oxide 230a; and conductors 242a and 242b on oxide 230b. b and oxide 230c; insulator 250 on oxide 230c; conductor 260 (conductor 260a and conductor 260b) located on insulator 250 and overlapping oxide 230c; insulator 254 in contact with a portion of the top surface of insulator 224, a portion of the side surface of oxide 230a, a portion of the side surface of oxide 230b, the side surface of conductor 242a, the top surface of conductor 242a, the side surface of conductor 242b, and the top surface of conductor 242b. Furthermore, oxide 230c is in contact with the side surfaces of insulator 254, the side surfaces of conductor 242a, and the side surfaces of conductor 242b. Here, as shown in FIG1B , the top surface of conductor 260 is arranged to be substantially aligned with the top surface of insulator 250 and the top surface of oxide 230c. Furthermore, insulator 282 is in contact with the top surfaces of conductor 260, insulator 250, oxide 230c, and insulator 280.

[0047] Openings reaching oxide 230b are provided in insulators 280 and 254. Oxide 230c, insulator 250, and conductor 260 are arranged within these openings. Furthermore, conductor 260, insulator 250, and oxide 230c are provided between conductors 242a and 242b in the channel length direction of transistor 200. Insulator 250 includes a region overlapping with the side surfaces of conductor 260 and a region overlapping with the top surface of conductor 260. Furthermore, within the region overlapping oxide 230b, oxide 230c includes a region in contact with oxide 230b, a region overlapping with the side surfaces of conductor 260 via insulator 250, and a region overlapping with the bottom surface of conductor 260 via insulator 250.

[0048] The transistor 200 preferably uses a metal oxide used as a semiconductor (hereinafter also referred to as an oxide semiconductor) as the oxide 230 (oxide 230a, oxide 230b, and oxide 230c) including the channel formation region.

[0049] The metal oxide used as the semiconductor preferably has a band gap of 2 eV or greater, preferably 2.5 eV or greater. Using a metal oxide with a wider band gap can reduce the off-state current of the transistor.

[0050] Transistors using metal oxides in their channel formation regions have extremely low leakage current when in a non-conducting state, enabling the provision of low-power semiconductor devices. Furthermore, since metal oxides can be formed using methods such as sputtering, they can be used in transistors that form highly integrated semiconductor devices.

[0051] For example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium) is preferably used as the oxide 230. Alternatively, In-Ga oxide or In-Zn oxide may be used as the oxide 230.

[0052] Oxide 230 preferably includes oxide 230a disposed on insulator 224, oxide 230b disposed on oxide 230a, and oxide 230c disposed on oxide 230b, at least a portion of which is in contact with the top surface of oxide 230b. When oxide 230a is disposed below oxide 230b, diffusion of impurities from structures formed below oxide 230a to oxide 230b can be suppressed. When oxide 230c is disposed above oxide 230b, diffusion of impurities from structures formed above oxide 230c to oxide 230b can be suppressed.

[0053] Note that in transistor 200, oxide 230 has a three-layer structure consisting of oxide 230a, oxide 230b, and oxide 230c. However, the present invention is not limited to this structure. For example, oxide 230b may be a single layer, a two-layer structure consisting of oxide 230a and oxide 230b, a two-layer structure consisting of oxide 230b and oxide 230c, or a stacked structure consisting of four or more layers. Oxide 230a, oxide 230b, and oxide 230c may each have a stacked structure.

[0054] Oxide 230a and oxide 230b, and oxide 230b and oxide 230c, preferably contain a common element as a main component in addition to oxygen. This reduces the defect state density at the interface between oxide 230a and oxide 230b, and at the interface between oxide 230b and oxide 230c. Consequently, the effect of interface scattering on carrier conduction is reduced, enabling transistor 200 to achieve high on-state current and high frequency characteristics.

[0055] Conductors 242 (conductors 242a and 242b) are provided on the oxide 230b. The conductors 242a and 242b serve as the source electrode and the drain electrode of the transistor 200, respectively.

[0056] The conductor 260 includes a conductor 260a and a conductor 260b, and the conductor 260a is arranged to surround the bottom and side surfaces of the conductor 260b. The conductor 260 is used as the first gate (also called the top gate) electrode of the transistor 200.

[0057] Figure 2 shows an enlarged cross-sectional view of a portion of transistor 200 shown in Figure 1B . As shown in Figure 2 , oxide 230 includes region 234, which serves as the channel formation region of transistor 200, and regions 231 (regions 231a and 231b), which serve as source or drain regions. Region 231 is a low-resistance region with a high carrier concentration. Region 231 may also include a portion of the aforementioned low-resistance region. Furthermore, region 234 has a lower carrier concentration than region 231. Note that at least a portion of region 231a and at least a portion of region 231b include regions in contact with conductors 242a and 242b, respectively.

[0058] Note that although FIG. 2 shows that region 231 and region 234 are formed in oxide 230 b , this is not limiting. For example, region 231 or region 234 may also be formed in oxide 230 a and oxide 230 b , in oxide 230 b and oxide 230 c , or in oxide 230 a , oxide 230 b , and oxide 230 c .

[0059] 2 shows that the boundary between regions 231 and 234 is substantially perpendicular to the bottom surface of oxide 230 b, but this embodiment is not limited to this. For example, region 234 may extend toward conductor 240 near the surface of oxide 230 b and become narrower near the bottom surface of oxide 230 b.

[0060] In transistors using an oxide semiconductor in the channel formation region, when a low-resistance region is formed in the channel formation region, leakage current (a parasitic channel) is likely to occur between the transistor's source and drain electrodes in this low-resistance region. Furthermore, this parasitic channel can easily lead to transistor characteristics defects such as normally-on transistor behavior, increased leakage current, and fluctuations (drift) in threshold voltage due to applied pressure. Furthermore, when transistor processing accuracy is low, this parasitic channel can vary across the transistor, causing variations in transistor characteristics.

[0061] Furthermore, in transistors using oxide semiconductors, the presence of impurities and oxygen vacancies in the channel formation region of the oxide semiconductor can sometimes reduce the resistance of the oxide semiconductor. This can also cause fluctuations in electrical properties and reduce reliability. Examples of these impurities include aluminum (Al) and silicon (Si). When these impurities enter the channel formation region, they can sometimes form defect states or oxygen vacancies.

[0062] Aluminum and silicon have greater bonding energies with oxygen than indium and zinc. For example, when an In-M-Zn oxide is used as an oxide semiconductor, when aluminum is mixed into the oxide semiconductor, the oxygen contained in the oxide semiconductor is taken away by the aluminum, sometimes forming oxygen vacancies near the indium or zinc.

[0063] When the channel-forming region of a metal oxide contains oxygen vacancies, the transistor tends to exhibit normally-on characteristics. Furthermore, when hydrogen enters an oxygen vacancy in the metal oxide, it sometimes bonds with the hydrogen to form a VOH. The defect (VOH) resulting from the hydrogen entry into the oxygen vacancy serves as a donor, sometimes generating an electron as a carrier. Furthermore, sometimes some of the hydrogen bonds with oxygen atoms bonded to metal atoms, generating electrons as carriers. Therefore, transistors using metal oxides containing a high amount of hydrogen tend to exhibit normally-on characteristics. Furthermore, because hydrogen in metal oxides easily migrates due to pressure from heat, electric fields, and other factors, a high hydrogen content in the metal oxide can reduce transistor reliability.

[0064] Therefore, it is preferable to reduce the impurities and oxygen vacancies as much as possible in the channel formation region and its vicinity of the oxide semiconductor.

[0065] Therefore, the channel forming region of the transistor and the structure in its vicinity are preferably in the shape described below. By making the structure constituting the transistor in the shape described below, the low-resistance region formed in the channel forming region can be reduced, thereby suppressing the generation of parasitic channels. Therefore, the deviation of the transistor characteristics caused by the parasitic channel can be suppressed. Here, the transistor characteristics refer to the current value in the on state (on-state current value), the current value in the off state (off-state current value), the critical voltage, the subthreshold swing value (S value), the field-effect mobility, etc. In addition, by reducing the impurity concentration in the channel forming region of the oxide semiconductor and its vicinity, the reliability of the transistor can be improved.

[0066] <Preferred Shape of the Channel Formation Region and Its Vicinity> The preferred shapes of the channel formation region and the structures in its vicinity are described below. Note that for simplicity, the region of the transistor 200 used as the channel formation region is formed in the oxide 230b.

[0067] FIG3A is a perspective view of transistor 200 and its surroundings shown in FIG1A to FIG1D . FIG3B is an enlarged perspective view of a portion of transistor 200 shown in FIG3A . Note that some components are omitted in the perspective views of FIG3A and FIG3B for clarity.

[0068] Oxide 230b includes a region 231a (not shown in FIG. 3A and FIG. 3B ) in contact with at least a portion of conductor 242a, a region 231b (not shown in FIG. 3A and FIG. 3B ) in contact with at least a portion of conductor 242b, and a region 234 between region 231a and region 231b that serves as a channel formation region for transistor 200. Region 234 includes a region in oxide 230b where oxide 230b overlaps with conductor 260. Hereinafter, the region in oxide 230b where oxide 230b overlaps with conductor 242a may be referred to as region 231a, and the region where oxide 230b overlaps with conductor 242b may be referred to as region 231b.

[0069] As shown in FIG1C and FIG3B , in a cross-section of transistor 200 in the channel width direction, a curved surface is preferably present between the side surfaces of oxide 230 b and the top surface of oxide 230 b in region 234. In other words, the ends of the side surfaces and the top surface are preferably curved (hereinafter also referred to as rounded).

[0070] Here, as shown in FIG2 and FIG3B , in a cross section of transistor 200 in the channel length direction, the distance between the side ends of conductor 242 a and the side ends of conductor 242 b facing each other is L. Note that L can also be considered to be the length of the top surface of oxide 230 b in a region that does not overlap with conductor 242 in the cross section of transistor 200 in the channel length direction.

[0071] 3B , in the cross section of the transistor 200 in the channel width direction, the length of the region without the curved surface on the top surface of the oxide 230 b in the region where the oxide 230 b overlaps with the conductor 260 is W.

[0072] 3B , the radius of curvature of the curved surface is La. Note that in a cross section of transistor 200 in the channel width direction, La is sometimes considered to be the difference between the height of the top surface of oxide 230b in the region where oxide 230b overlaps with conductor 260, with reference to the bottom surface of insulator 224, and the height of the lower end of the region having the curved surface on the side surface of oxide 230b.

[0073] La is preferably greater than 0 nm and less than the thickness of oxide 230b in the region overlapping conductor 242, or less than half the thickness of W. Specifically, La is greater than 0 nm and less than 20 nm, preferably greater than 1 nm and less than 15 nm, and more preferably greater than 2 nm and less than 10 nm. This shape suppresses electric field concentration between the side surface and the top surface, thereby minimizing fluctuations in transistor characteristics. Furthermore, preventing a reduction in W suppresses a decrease in the on-state current and mobility of transistor 200. Consequently, a semiconductor device with excellent electrical characteristics can be provided.

[0074] Furthermore, by adopting this shape, in region 234, the effective channel length on the side surfaces of oxide 230b is greater than the effective channel length on the top surface of oxide 230b, thereby reducing the current flowing through these side surfaces. Consequently, the influence of parasitic channels formed on these side surfaces is suppressed, and the S value of transistor 200 can be reduced. Furthermore, the influence of variations in individual transistors caused by parasitic channels formed on these side surfaces is reduced, thereby providing a semiconductor device with reduced variations in transistor characteristics.

[0075] In a cross-section of transistor 200 along the channel width, the length of the area without a curved surface on the side surface of oxide 230b in the region where oxide 230b overlaps conductor 260 is Lb. Note that when the side surface of oxide 230b in the region where oxide 230b overlaps conductor 260 has a tapered shape, Lb can also be referred to as the length of the tapered portion of oxide 230b. Furthermore, Lb is sometimes considered the difference between the height of the upper end of the area without a curved surface and the height of the lower end of the area without a curved surface, relative to the bottom surface of insulator 224. Lb depends on La, the thickness of oxide 230b, the taper angle of oxide 230b, and other factors. The taper angle here refers to the angle between the side surface of a tapered film and the bottom surface of the film.

[0076] Furthermore, the amount of film reduction on the top surface of oxide 230b in the region where oxide 230b overlaps conductor 260 is Lc. For example, Lc can be calculated as the difference between the height of the top surface of oxide 230b in the region overlapping conductor 242 and the height of the top surface of oxide 230b in the region overlapping conductor 260, with reference to the bottom surface of insulator 222 in a cross section of transistor 200 in the channel width direction.

[0077] As described later, if the conductive layer 242B, disposed on and in contact with the oxide 230b, contains an element that absorbs oxygen from the oxide 230b, a low-resistance region may be partially formed between the oxide 230b and the conductive layer 242B, or near the surface of the oxide 230b. Furthermore, if the insulating film 254A, disposed in contact with the side surfaces of the channel-forming region of the oxide 230b, contains an element that absorbs oxygen from the oxide 230b, a low-resistance region may be partially formed between the oxide 230b and the insulating film 254A, or near the side surfaces of the channel-forming region of the oxide 230b. In other words, these elements may become impurities in the oxide semiconductor. In this case, impurities or impurities (such as hydrogen, nitrogen, or metal elements) that have entered oxygen vacancies in these low-resistance regions serve as donors, increasing the carrier density.

[0078] Furthermore, when impurities are introduced into oxide semiconductors, defect states or oxygen vacancies may form. Consequently, when impurities are introduced into the channel formation region of an oxide semiconductor, the electrical characteristics of transistors using the oxide semiconductor may fluctuate, reducing reliability. Furthermore, when oxygen vacancies are present in the channel formation region, the transistor exhibits a normally-on characteristic (a characteristic in which a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode).

[0079] Therefore, the top surface of oxide 230b in region 234 is preferably lower than the top surface of oxide 230b in the region overlapping conductor 242. For example, Lc is preferably greater than 0 nm and less than the thickness of oxide 230b in the region overlapping conductor 242. Specifically, Lc is greater than 0 nm and less than 15 nm, preferably greater than 0.5 nm and less than 10 nm, and more preferably greater than 1 nm and less than 5 nm. By adopting this shape, the aforementioned impurities are removed, reducing the low-resistance region formed near the top surface of region 234, thereby suppressing the formation of a parasitic channel. Note that the effective channel length at the top surface of region 234 is L + 2 × Lc. Therefore, by reducing Lc, the reduction in the transistor's on-state current can be suppressed.

[0080] Furthermore, the amount of film reduction on the side surface of oxide 230b in the region where oxide 230b overlaps conductor 260 is referred to as We. For example, We can be calculated as the difference between the side surface of oxide 230b in the region overlapping conductor 242 and the side surface of oxide 230b in the region without the curved surface in a cross-section of transistor 200 in the channel width direction. Furthermore, We can be calculated, for example, as half the difference between the length of the bottom surface of oxide 230b in the region overlapping conductor 242 and the length of the bottom surface of oxide 230b in the region not overlapping conductor 242 in a cross-section of transistor 200 in the channel width direction.

[0081] We is preferably greater than 0 nm and equal to or less than the thickness of oxide 230b in the region overlapping conductor 242. Specifically, We is greater than 0 nm and less than 20 nm, preferably greater than 1 nm and less than 15 nm, and more preferably greater than 2 nm and less than 10 nm. By making We greater than 0 nm, impurities near the side surfaces of region 234 are removed, reducing the low-resistance region and thereby suppressing the formation of parasitic channels.

[0082] This reduces the amount of low-resistance regions formed in the channel formation region, thereby suppressing the generation of parasitic channels. Consequently, variations in transistor characteristics caused by the parasitic channels can be suppressed. Furthermore, the impurity concentration in the channel formation region of the oxide semiconductor and its vicinity can be reduced, thereby improving transistor reliability.

[0083] By adopting the above-described shape for the channel formation region of transistor 200 and its surrounding structures, variations in transistor characteristics can be reduced. For example, variations in Vsh can be reduced. In this specification, Vsh is defined as the gate voltage Vg when the drain current Id = 1.0 × 10-12 A on the transistor's Id-Vg curve. For example, variations in Vsh can be evaluated using the standard deviation σ. The standard deviation σ of Vsh for each transistor (n is an integer greater than or equal to 3) is expressed by the following formula.

[0084] [Formula 1]

[0085] In the above formula, xi is the Vsh value of the i-th (i is an integer greater than or equal to 1 and less than or equal to n) transistor, and μ is the average value of the Vsh of n transistors.

[0086] Specifically, in the Id-Vg characteristics of the transistor 200 , the standard deviation σ of Vsh is less than 60 mV, preferably less than 40 mV, and more preferably less than 20 mV.

[0087] Furthermore, by adopting the above-described shape for the structure in and near the channel formation region of the transistor 200, the impurity concentration in the channel formation region of the oxide semiconductor and its vicinity can be reduced. Specifically, the impurity concentration in and near the channel formation region of the oxide semiconductor, as determined by secondary ion mass spectrometry (SIMS), is 1×10 18 atoms / cm 3 or less, preferably 2×10 16 atoms / cm 3 or less. Alternatively, the impurity concentration in and near the channel formation region of the oxide semiconductor, as determined by elemental analysis using energy dispersive X-ray spectroscopy (EDX), is 1.0 atomic % or less. Note that when an oxide containing element M is used as the oxide semiconductor, the concentration ratio of the impurity to element M in and near the channel formation region of the oxide semiconductor is less than 0.10, preferably less than 0.05. The concentration of element M used to calculate the concentration ratio may be the concentration in the same region as the region where the impurity concentration is calculated, or the concentration in the oxide semiconductor.

[0088] Furthermore, the impurity concentration on the side surfaces of the oxide 230 b in the channel formation region is lower than the impurity concentration on the side surfaces of the oxide 230 b in the region overlapping with the conductor 242. Alternatively, the concentration ratio of the impurity to the element M on the side surfaces of the oxide 230 b in the channel formation region is lower than the concentration ratio of the impurity to the element M on the side surfaces of the oxide 230 b in the region overlapping with the conductor 242. Furthermore, the concentration ratio of the impurity to the element M on the top surface of the oxide 230 b in the channel formation region is lower than the concentration ratio of the impurity to the element M on the top surface of the oxide 230 b in the region overlapping with the conductor 242.

[0089] <Detailed Structure of Semiconductor Device> The following describes a detailed structure of a semiconductor device according to an embodiment of the present invention and a transistor 200 included in the semiconductor device.

[0090] Insulators 212, 214, 254, 282, 283, and 281 are preferably used as barrier insulating films to inhibit the diffusion of impurities such as water and hydrogen from the substrate side or above transistor 200 into transistor 200. Therefore, insulators 212, 214, 254, 282, 283, and 281 are preferably made of insulating materials that inhibit the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitric oxide molecules (N2O, NO, NO2, etc.), and copper atoms (those impurities are less likely to permeate). Furthermore, insulating materials that inhibit the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) are preferably used (those oxygen atoms and oxygen molecules are less likely to permeate).

[0091] For example, it is preferable to use silicon nitride or the like for insulators 212, 283, and 281, and aluminum oxide or the like for insulators 214, 254, and 282. This can suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor 200 side through insulators 212 and 214. Furthermore, it can suppress the diffusion of oxygen contained in insulators 224 and the like through insulators 212 and 214 to the substrate side. Furthermore, it can suppress the diffusion of impurities such as water and hydrogen from insulators 280 and conductors 246, etc., located above insulator 254, through insulator 254 to the interior of transistor 200. Thus, it is preferable to surround transistor 200 with insulators 212, 214, 254, 282, and 283, which have the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0092] Furthermore, it is sometimes desirable to lower the resistivity of insulators 212, 283, and 281. For example, by setting the resistivity of insulators 212, 283, and 281 to approximately 1×10 13 Ωcm, insulators 212, 283, and 281 can mitigate charge accumulation on conductors 205, 242, or 260 during processes such as plasma in semiconductor device manufacturing. The resistivity of insulators 212, 283, and 281 is preferably not less than 1×10 10 Ωcm and not more than 1×10 15 Ωcm.

[0093] Furthermore, the dielectric constants of insulators 216, 280, and 274 are preferably lower than that of insulator 214. Using a material with a low dielectric constant for the interlayer film can reduce parasitic capacitance generated between wirings. For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon and nitrogen-doped silicon oxide, or silicon oxide with pores can be suitably used as insulators 216, 280, and 274.

[0094] The conductor 205 is arranged so as to overlap with the oxide 230 and the conductor 260. In addition, the conductor 205 is preferably provided so as to be buried in the insulator 214 or the insulator 216.

[0095] Conductor 260 is sometimes used as the first gate electrode. Conductor 205 is sometimes used as the second gate electrode. In this case, the threshold voltage (Vth) of transistor 200 can be controlled by independently varying the potential supplied to conductor 205, without interlocking it with the potential supplied to conductor 260. In particular, applying a negative potential to conductor 205 increases the Vth of transistor 200 and reduces the off-state current. Therefore, applying a negative potential to conductor 205 reduces the drain current when the potential supplied to conductor 260 is 0V, compared to when no negative potential is applied to conductor 205.

[0096] Furthermore, as shown in FIG1A , conductor 205 is preferably larger than the region of oxide 230 that does not overlap conductors 242a and 242b. In particular, as shown in FIG1C , conductor 205 preferably extends to the region outside the end of oxide 230 that intersects the channel width direction. In other words, conductor 205 and conductor 260 preferably overlap with an insulator interposed therebetween on the outside of the channel width side surfaces of oxide 230. With this structure, the channel-forming region of oxide 230 can be electrically surrounded by the electric field of conductor 260, which serves as the first gate electrode, and the electric field of conductor 205, which serves as the second gate electrode. In this specification, a transistor structure in which the channel-forming region is electrically surrounded by the electric fields of the first and second gate electrodes is referred to as a surrounded channel (S-channel) structure.

[0097] In this specification, etc., an S-channel transistor refers to a transistor structure in which the channel formation region is surrounded by electric fields generated by one and the other of a pair of gate electrodes. Furthermore, in this specification, etc., the S-channel structure has the following characteristics: Like the channel formation region, the side surfaces of oxide 230 in contact with conductors 242a and 242b, which serve as source and drain electrodes, and their surrounding areas are I-type. Furthermore, due to contact with insulator 280, the side surfaces of oxide 230 in contact with conductors 242a and 242b may also be I-type, similar to the channel formation region. In this specification, etc., I-type can be considered to be essentially the same as the high-purity structure described later. Furthermore, the S-channel structure disclosed in this specification, etc., differs from fin-type and planar structures. By adopting an S-channel structure, resistance to short-channel effects can be improved, in other words, a transistor that is less susceptible to short-channel effects can be realized.

[0098] Furthermore, as shown in FIG1C , conductor 205 is extended to serve as wiring. However, the present invention is not limited to this, and a conductor serving as wiring may be provided below conductor 205. Furthermore, conductor 205 need not necessarily be provided for each transistor. For example, conductor 205 may be shared by multiple transistors.

[0099] In transistor 200, conductor 205 comprises a stack of conductors 205a and 205b, but the present invention is not limited to this. For example, conductor 205 may have a single-layer structure or a stacked structure of three or more layers. In the case of a stacked structure, the structures are sometimes numbered according to the order in which they were formed to distinguish them.

[0100] Here, as the conductor 205a, it is preferable to use a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. It is also preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules).

[0101] By using a conductive material that inhibits oxygen diffusion as conductor 205a, oxidation of conductor 205b and a resulting decrease in conductivity can be prevented. Preferred conductive materials that inhibit oxygen diffusion include tantalum, tantalum nitride, ruthenium, ruthenium oxide, and the like. Therefore, conductor 205a can have a single layer or a stacked layer structure of any of these conductive materials. For example, conductor 205a can have a stacked layer structure of tantalum, tantalum nitride, ruthenium, or ruthenium oxide and titanium or titanium nitride.

[0102] As the conductor 205b, it is preferable to use a conductive material with tungsten, copper or aluminum as the main component. In the figure, the conductor 205b has a single-layer structure, but it can also have a stacked structure. For example, a stacked structure of titanium or titanium nitride and the above conductive materials can be used.

[0103] Insulator 222 and insulator 224 are used as gate insulators.

[0104] Insulator 222 preferably has the function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms and hydrogen molecules). Furthermore, insulator 222 is preferably a conductive material that has the function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules). For example, insulator 222 preferably has the function of suppressing the diffusion of one or both of hydrogen and oxygen compared to insulator 224.

[0105] Insulator 222 preferably uses an insulating material containing an oxide of one or both of aluminum and hafnium. Preferred examples of such insulators include aluminum oxide, hafnium oxide, and oxides containing aluminum and hafnium (hafnium aluminate). When such materials are used to form insulator 222, insulator 222 serves as a layer that prevents oxygen from being released from oxide 230 toward the substrate and impurities such as hydrogen from diffusing from the periphery of transistor 200 into oxide 230. Therefore, the provision of insulator 222 prevents impurities such as hydrogen from diffusing into transistor 200, thereby suppressing the formation of oxygen vacancies in oxide 230. Furthermore, it prevents the conductor 205 from reacting with oxygen contained in insulator 224 or oxide 230.

[0106] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to these insulators. Alternatively, the above-mentioned insulators may be nitrided. Furthermore, the insulator 222 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on the above-mentioned insulators.

[0107] Furthermore, as insulator 222, a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST) can be used in a single layer or a stacked layer. As transistors become increasingly miniaturized and integrated, the thinning of gate insulators can sometimes lead to problems such as leakage current. Using a high-k material as the gate insulator reduces the physical thickness while lowering the gate potential during transistor operation.

[0108] Here, it is preferable to remove oxygen from the insulator 224 in contact with the oxide 230 by heating. For example, silicon oxide, silicon oxynitride, or the like can be appropriately used as the insulator 224. Providing an insulator containing oxygen in contact with the oxide 230 can reduce oxygen vacancies in the oxide 230, thereby improving the reliability of the transistor 200.

[0109] Specifically, the insulator 224 is preferably an oxide material from which some oxygen is released upon heating, that is, an insulator material having an excess oxygen region. An oxide film from which oxygen is released upon heating refers to an oxide film in which the amount of oxygen released, calculated as oxygen molecules, as measured by TDS (Thermal Desorption Spectroscopy) analysis is 1.0×10 18 molecules / cm 3 or greater, preferably 1.0×10 19 molecules / cm 3 or greater, and more preferably 2.0×10 19 molecules / cm 3 or greater, or 3.0×10 20 molecules / cm 3 or greater. The surface temperature of the film during the TDS analysis is preferably within a range of 100°C to 700°C, or 100°C to 400°C.

[0110] Alternatively, the insulator having the excess oxygen region and the oxide 230 may be subjected to one or more of heat treatment, microwave treatment, and RF treatment while in contact with each other. This treatment can remove water or hydrogen from the oxide 230. For example, in the oxide 230, a reaction occurs in which hydrogen enters an oxygen vacancy (VOH), breaking the bond. In other words, a "VOH→VO+H" reaction occurs, leading to dehydrogenation. Some of the hydrogen generated may bond with oxygen and be removed from the oxide 230 or the insulator near the oxide 230 as H2O. Furthermore, some of the hydrogen may diffuse into the conductor 242 or be trapped by the conductor 242 (also known as gettering).

[0111] For example, the microwave treatment is preferably performed using an apparatus equipped with a power source for generating high-density plasma or an apparatus equipped with a power source for applying RF to the substrate. For example, by using a gas containing oxygen and high-density plasma, a high density of oxygen radicals can be generated. By applying RF to the substrate, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the oxide 230 or an insulator near the oxide 230. Furthermore, the pressure during the microwave treatment can be set to 133 Pa or higher, preferably 200 Pa or higher, and more preferably 400 Pa or higher. Furthermore, the gases introduced into the microwave treatment apparatus can be oxygen and argon, for example, and the microwave treatment is performed with an oxygen flow ratio (O₂ / (O₂+Ar)) of 50% or lower, preferably 10% or higher and 30% or lower.

[0112] Furthermore, during the manufacturing process of transistor 200, heat treatment is preferably performed while the surface of oxide 230 is exposed. For example, the heat treatment is preferably performed at a temperature of 100°C to 450°C, more preferably 350°C to 400°C. The heat treatment is performed in a nitrogen or inert gas atmosphere, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. For example, the heat treatment is preferably performed in an oxygen atmosphere. This reduces oxygen vacancies by supplying oxygen to oxide 230. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen or inert gas atmosphere, followed by an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replace the released oxygen. Alternatively, the heat treatment can be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, followed by a continuous heat treatment in a nitrogen or inert gas atmosphere.

[0113] By oxidizing oxide 230, the supplied oxygen can fill oxygen vacancies in oxide 230, in other words, promoting the "V O + O → null" reaction. Furthermore, when the supplied oxygen reacts with hydrogen remaining in oxide 230, the hydrogen is removed as H 2 O. This prevents the hydrogen remaining in oxide 230 from recombinating with oxygen vacancies to form V OH.

[0114] In addition, the insulator 222 and the insulator 224 may also have a stacked structure of two or more layers. In this case, they are not limited to stacked structures made of the same material, and may also be stacked structures made of different materials.

[0115] Oxide 230 preferably has a stacked structure of oxides with different chemical compositions. Specifically, the ratio of the number of atoms of element M relative to the main component metal element in the metal oxide used for oxide 230a is preferably greater than the ratio of the number of atoms of element M relative to the main component metal element in the metal oxide used for oxide 230b. Furthermore, the ratio of the number of atoms of element M relative to In in the metal oxide used for oxide 230a is preferably greater than the ratio of the number of atoms of element M relative to In in the metal oxide used for oxide 230b. Furthermore, the ratio of the number of atoms of In relative to M in the metal oxide used for oxide 230b is preferably greater than the ratio of the number of atoms of In relative to M in the metal oxide used for oxide 230a. Metal oxides that can be used for either oxide 230a or oxide 230b can be used for oxide 230c.

[0116] To increase the on-state current of transistor 200, it is preferable to use In-Zn oxide as oxide 230. When using In-Zn oxide as oxide 230, examples include a stacked structure in which In-Zn oxide 230a is used and In-M-Zn oxide is used as oxide 230b and oxide 230c; or a stacked structure in which In-M-Zn oxide is used as oxide 230a and In-Zn oxide is used as either oxide 230b or oxide 230c.

[0117] Furthermore, oxides 230b and 230c are preferably crystalline. For example, CAAC-OS (c-axis aligned crystalline oxide semiconductor), described later, is preferably used. Crystalline oxides such as CAAC-OS have a highly crystalline and dense structure with few impurities and defects (such as oxygen vacancies). Therefore, oxygen extraction from oxide 230b by the source or drain electrodes can be suppressed. Consequently, even during heat treatment, oxygen extraction from oxide 230b can be reduced, making transistor 200 stable against the high temperatures (thermal budget) experienced during the manufacturing process.

[0118] In addition, CAAC-OS is preferably used as oxide 230c. The c-axis of the crystals contained in oxide 230c is preferably aligned substantially perpendicular to the formed surface or top surface of oxide 230c. CAAC-OS has the property of easily allowing oxygen to migrate perpendicular to the c-axis. This allows oxygen contained in oxide 230c to be efficiently supplied to oxide 230b.

[0119] Preferably, the conduction band bottoms of oxides 230a and 230c are closer to the vacuum level than the conduction band bottom of oxide 230b. In other words, the electron affinities of oxides 230a and 230c are preferably lower than that of oxide 230b. In this case, the metal oxide that can be used for oxide 230a is preferably used for oxide 230c. In this case, the primary carrier path is through oxide 230b.

[0120] Here, the conduction band bottom changes gently at the junction of oxide 230a, oxide 230b, and oxide 230c. In other words, the conduction band bottom at the junction of oxide 230a, oxide 230b, and oxide 230c can be expressed as continuously changing or continuously joining. To this end, it is desirable to reduce the defect state density of the mixed layer formed at the interface between oxide 230a and oxide 230b, and at the interface between oxide 230b and oxide 230c.

[0121] Specifically, by having oxide 230a and oxide 230b, and oxide 230b and oxide 230c, contain a common element as a main component in addition to oxygen, a mixed layer with a low defect state density can be formed. For example, if oxide 230b is an In-Ga-Zn oxide, oxide 230a and oxide 230c can be made of In-Ga-Zn oxide, Ga-Zn oxide, gallium oxide, or the like.

[0122] Specifically, the oxide 230a may be a metal oxide having an atomic ratio of In:Ga:Zn = 1:3:4 or an atomic ratio of In:Ga:Zn = 1:1:0.5. Furthermore, the oxide 230b may be a metal oxide having an atomic ratio of In:Ga:Zn = 1:1:1 or an atomic ratio of In:Ga:Zn = 4:2:3. Furthermore, the oxide 230c may be a metal oxide having an atomic ratio of In:Ga:Zn = 1:3:4, In:Ga:Zn = 4:2:3, Ga:Zn = 2:1, or Ga:Zn = 2:5.

[0123] Note that when the metal oxide is formed by sputtering, the above-mentioned atomic number ratio is not limited to the atomic number ratio of the formed metal oxide, but may also be the atomic number ratio of the sputtering target used to form the metal oxide.

[0124] By employing the above structure for oxide 230a and oxide 230c, the defect state density at the interface between oxide 230a and oxide 230b, and at the interface between oxide 230b and oxide 230c, can be reduced. Consequently, the effect of interface scattering on carrier conduction is reduced, enabling transistor 200 to achieve high on-state current and high frequency characteristics.

[0125] For example, conductors 242 (conductors 242a and 242b) preferably use tantalum nitrides, titanium nitrides, molybdenum nitrides, tungsten nitrides, tantalum and aluminum nitrides, and titanium and aluminum nitrides. In one embodiment of the present invention, tantalum nitrides are particularly preferred. Other examples include ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. These materials are preferred because they are electrically conductive materials that are not easily oxidized or maintain conductivity even when absorbing oxygen.

[0126] Note that when the conductor 242 is in contact with the oxide 230b, oxygen in the oxide 230b may diffuse into the conductor 242, causing oxidation of the conductor 242. Oxidation of the conductor 242 may reduce the conductivity of the conductor 242. Note that the diffusion of oxygen from the oxide 230b into the conductor 242 can be alternatively referred to as the conductor 242 absorbing oxygen from the oxide 230b.

[0127] Furthermore, when oxygen in oxide 230b diffuses into conductors 242a and 242b, a layer may form between conductor 242a and oxide 230b, and between conductor 242b and oxide 230b. This layer, because it contains more oxygen than conductors 242a and 242b, is believed to have insulating properties. In this case, the three-layer structure of conductors 242a and 242b, this layer, and oxide 230b can be considered a three-layer structure consisting of metal-insulator-semiconductor, a MIS (metal-insulator-semiconductor) structure, or a diode junction structure primarily based on the MIS structure.

[0128] Note that hydrogen contained in the oxide 230b or the like may diffuse into the conductor 242a or the conductor 242b. In particular, using a tantalum nitride as the conductor 242a or the conductor 242b may facilitate the diffusion of hydrogen contained in the oxide 230b or the like into the conductor 242a or the conductor 242b, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a or the conductor 242b. In other words, hydrogen contained in the oxide 230b or the like may be absorbed by the conductor 242a or the conductor 242b.

[0129] Furthermore, a curved surface may exist between the side surfaces and the top surface of the conductor 242. In other words, the ends of the side surfaces and the top surface may be curved. For example, the radius of curvature of the curved surface at the ends of the conductor 242 may be between 3 nm and 10 nm, preferably between 5 nm and 6 nm. By eliminating corners at the ends, film coverage can be improved in subsequent film formation processes.

[0130] As shown in FIG1B , insulator 254 preferably contacts the top and side surfaces of conductor 242 a, the top and side surfaces of conductor 242 b, the side surfaces of oxide 230 a, the side surfaces of oxide 230 b, and a portion of the top surface of insulator 224. With this structure, insulator 280 is separated from insulator 224, oxide 230 a, and oxide 230 b by insulator 254.

[0131] In addition, insulator 254 preferably has the function of suppressing the diffusion of one or both of hydrogen and oxygen, similar to insulator 222. For example, insulator 254 preferably has the function of suppressing the diffusion of one or both of hydrogen and oxygen, compared to insulator 224 and insulator 280. This can suppress the diffusion of hydrogen contained in insulator 280 into oxide 230a and oxide 230b. Furthermore, by surrounding insulator 222 and insulator 254, the diffusion of impurities such as water and hydrogen into insulator 224 and oxide 230 from the outside can be suppressed. This allows transistor 200 to have excellent electrical characteristics and reliability.

[0132] Insulator 254 is preferably formed by sputtering. By forming insulator 254 using sputtering in an oxygen-containing atmosphere, oxygen can be added to the vicinity of the contact region between insulator 224 and insulator 254. This allows oxygen to be supplied from this region to oxide 230 via insulator 224. By providing insulator 254 with the function of suppressing oxygen diffusion upward, oxygen diffusion from oxide 230 to insulator 280 can be prevented. Furthermore, by providing insulator 222 with the function of suppressing oxygen diffusion downward, oxygen diffusion from oxide 230 to the substrate can be prevented. This allows oxygen to be supplied to the channel formation region in oxide 230. This reduces oxygen vacancies in oxide 230 and prevents the transistor from becoming normally on.

[0133] Insulator 254 can be formed, for example, from an oxide of one or both of aluminum and hafnium. In this case, insulator 254 is formed using atomic layer deposition (ALD). Because ALD offers high coverage, it can prevent disconnection of insulator 254 caused by unevenness.

[0134] For example, an insulator made of aluminum nitride can be used as the insulator 254. This allows the formation of a film having high insulation properties and high thermal conductivity, thereby improving the heat dissipation performance when driving the transistor 200. Alternatively, silicon nitride, silicon oxynitride, or the like can be used.

[0135] Alternatively, an oxide containing gallium can be used as the insulator 254. Oxides containing gallium are preferred because they sometimes inhibit the diffusion of one or both of hydrogen and oxygen. Examples of oxides containing gallium include gallium oxide, gallium zinc oxide, and indium gallium zinc oxide. When indium gallium zinc oxide is used as the insulator 254, a high atomic ratio of gallium to indium is preferred. Increasing this atomic ratio improves the insulating properties of the oxide.

[0136] Furthermore, insulator 254 may have a multilayer structure with two or more layers. When insulator 254 has a two-layer stacked structure, the above-described methods can be used to form the lower and upper layers of insulator 254. Furthermore, the lower and upper layers of insulator 254 may be formed using the same method or different methods. For example, insulator 254 may be formed using sputtering in an oxygen-containing atmosphere, followed by forming the upper layer using ALD. Because ALD provides excellent coverage, it can prevent disconnection caused by unevenness in the first layer.

[0137] The above-mentioned materials can be used for the lower and upper layers of insulator 254, and the materials of the lower and upper layers of insulator 254 can be the same or different. For example, a stacked structure of silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride and an insulator that inhibits the permeation of impurities such as hydrogen and oxygen can be used. Furthermore, as the insulator that inhibits the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing oxides of one or both of aluminum and hafnium can be used.

[0138] Insulator 250 serves as a gate insulator. Insulator 250 is preferably disposed in contact with at least a portion of oxide 230c. Silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, or silicon oxide with pores can be used for insulator 250. Silicon oxide and silicon oxynitride are particularly preferred due to their thermal stability.

[0139] Similar to insulator 224, insulator 250 is preferably formed using an insulator that releases oxygen upon heating. By providing insulator 250, which releases oxygen upon heating, in contact with at least a portion of oxide 230c, oxygen can be efficiently supplied to the channel formation region of oxide 230b, thereby reducing oxygen vacancies in the channel formation region of oxide 230b. Consequently, a transistor with improved reliability can be provided while suppressing fluctuations in electrical characteristics and achieving stable electrical characteristics. Furthermore, similar to insulator 224, the concentration of impurities such as water and hydrogen in insulator 250 is preferably reduced. The thickness of insulator 250 is preferably not less than 1 nm and not more than 20 nm.

[0140] Note that while Figures 1A to 1C illustrate a single-layer structure for insulator 250, it may also have a stacked structure of two or more layers. When insulator 250 has a two-layer stacked structure, it is preferable that the lower layer of insulator 250 be formed using an insulator that releases oxygen upon heating, and the upper layer of insulator 250 be formed using an insulator that inhibits oxygen diffusion. This structure prevents oxygen contained in the lower layer of insulator 250 from diffusing into conductor 260. In other words, a reduction in the amount of oxygen supplied to oxide 230 can be suppressed. Furthermore, oxidation of conductor 260 caused by oxygen contained in the lower layer of insulator 250 can be suppressed. For example, the lower layer of insulator 250 can be formed using a material that can be used for insulator 250 described above, while the upper layer of insulator 250 can be formed using the same material as insulator 222.

[0141] Note that when the lower layer of insulator 250 is formed using materials such as silicon oxide and silicon oxynitride, the upper layer of insulator 250 can also be formed using a high-k insulating material with a high relative dielectric constant. By using a stacked structure of the lower layer of insulator 250 and the upper layer of insulator 250 as the gate insulator, a stacked structure with high relative dielectric constant and thermal stability can be formed. This allows the gate potential supplied during transistor operation to be reduced while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0142] Specifically, as the upper layer of the insulator 250, a metal oxide containing one or more metals selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc., or a metal oxide that can be used for the oxide 230 can be used. In particular, an insulator containing one or both of aluminum and hafnium oxides is preferably used.

[0143] Alternatively, a metal oxide may be provided between insulator 250 and conductor 260. This metal oxide preferably inhibits the diffusion of oxygen from insulator 250 to conductor 260. Providing a metal oxide that inhibits oxygen diffusion inhibits the diffusion of oxygen from insulator 250 to conductor 260. In other words, a decrease in the amount of oxygen supplied to oxide 230 can be suppressed. Furthermore, oxidation of conductor 260 caused by oxygen in insulator 250 can be suppressed.

[0144] Note that the metal oxide is preferably used as part of the first gate electrode. For example, a metal oxide that can be used for the oxide 230 can be used as the metal oxide. In this case, by forming the conductor 260a by sputtering, the resistance of the metal oxide can be reduced, making it a conductor. This conductor can be called an OC (Oxide Conductor) electrode. For example, an oxide semiconductor that can be used for the oxide 230 can be used as the metal oxide by reducing its resistance.

[0145] By providing an upper layer of insulator 250 and / or the aforementioned metal oxide, the on-state current of transistor 200 can be increased without reducing the influence of the electric field from conductor 260. Furthermore, by utilizing the physical thickness of insulator 250 and the aforementioned metal oxide to maintain the distance between conductor 260 and oxide 230, leakage current between conductor 260 and oxide 230 can be suppressed. Furthermore, by providing a stacked structure of insulator 250 and the aforementioned metal oxide, the physical distance between conductor 260 and oxide 230 and the strength of the electric field applied from conductor 260 to oxide 230 can be easily adjusted.

[0146] Conductor 260 preferably includes conductor 260a and conductor 260b disposed on conductor 260a. For example, conductor 260a is preferably disposed so as to surround the bottom and side surfaces of conductor 260b. Note that while Figures 1A to 1C illustrate conductor 260 as having a two-layer structure of conductors 260a and 260b, it may also have a single-layer structure or a stacked structure of three or more layers.

[0147] Conductor 260a preferably uses a conductive material that has the ability to suppress the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, and copper atoms. Furthermore, it is also preferable to use a conductive material that has the ability to suppress the diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules).

[0148] Furthermore, when the conductor 260a has the function of suppressing oxygen diffusion, it is possible to prevent oxygen contained in the insulator 250 from oxidizing the conductor 260b and causing a decrease in conductivity. As conductive materials that have the function of suppressing oxygen diffusion, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used.

[0149] Since conductor 260 also functions as wiring, it is preferable to use a highly conductive material. For example, conductor 260b can be made of a conductive material primarily composed of tungsten, copper, or aluminum. Alternatively, conductor 260b can have a laminated structure, for example, a laminated structure of titanium or titanium nitride and one of the above conductive materials.

[0150] Furthermore, in transistor 200, conductor 260 is formed in a self-aligned manner to fill an opening formed in insulator 280 or the like. By forming conductor 260 in this manner, conductor 260 can be reliably arranged in the region between conductor 242a and conductor 242b without requiring alignment.

[0151] Furthermore, as shown in FIG1C , in the channel width direction of transistor 200, the bottom surface of conductor 260 in the region where conductor 260 does not overlap with oxide 230b is preferably lower than the bottom surface of oxide 230b, relative to the bottom surface of insulator 222. Because conductor 260, serving as a gate electrode, covers the side and top surfaces of the channel-forming region of oxide 230b via insulator 250 and the like, the electric field of conductor 260 can be easily applied to the entire channel-forming region of oxide 230b. Consequently, the on-state current of transistor 200 can be increased, and frequency characteristics can be improved. The difference between the bottom surface height of conductor 260 in the region where oxide 230a and oxide 230b do not overlap with conductor 260, relative to the bottom surface of insulator 222, and the bottom surface height of oxide 230b is preferably 0 nm to 100 nm, preferably 3 nm to 50 nm, and more preferably 5 nm to 20 nm.

[0152] Insulator 280 is disposed on insulator 224, oxide 230a, oxide 230b, conductor 242, and insulator 254. In addition, the top surface of insulator 280 may also be planarized.

[0153] The dielectric constant of insulator 280, used as an interlayer film, is preferably low. Using a material with a low dielectric constant for the interlayer film can reduce parasitic capacitance between wiring lines. Insulator 280 is preferably formed of the same material as insulator 216, for example. Silicon oxide and silicon oxynitride are particularly preferred due to their thermal stability. Silicon oxide, silicon oxynitride, and silicon oxide with pores are particularly preferred because they easily form regions containing oxygen that is released by heating.

[0154] Furthermore, the concentration of impurities such as water and hydrogen in insulator 280 is preferably reduced. Furthermore, insulator 280 preferably includes an excess oxygen region or excess oxygen with a low hydrogen concentration. For example, it can be formed using the same material as insulator 216. Insulator 280 can also have a structure in which the aforementioned materials are stacked. For example, it can have a stacked structure of a silicon oxide film formed by sputtering and a silicon oxynitride film stacked thereon by chemical vapor deposition (CVD). Alternatively, silicon nitride can be stacked thereon.

[0155] Insulator 282 or insulator 283 is preferably used as a barrier insulating film to prevent impurities such as water and hydrogen from diffusing from above into insulator 280. Furthermore, insulator 282 or insulator 283 is used as a barrier insulating film to prevent oxygen permeation. Insulators 282 and 283 can be made of, for example, aluminum oxide, silicon nitride, or silicon oxynitride. For example, aluminum oxide, which has a high barrier property against oxygen, can be used as insulator 282, and silicon nitride, which has a high barrier property against hydrogen, can be used as insulator 283.

[0156] Furthermore, it is preferable to provide an insulator 274 serving as an interlayer film on the insulator 282. As with the insulator 224 and the like, it is preferable that the concentration of impurities such as water and hydrogen in the insulator 274 be reduced.

[0157] The conductors 240a and 240b are preferably made of a conductive material having tungsten, copper, or aluminum as a main component. Furthermore, the conductors 240a and 240b may also have a stacked structure.

[0158] Furthermore, when conductors 240a and 240b have a stacked structure, it is preferable to use a conductive material that inhibits the permeation of impurities such as water and hydrogen as the conductive material in contact with insulators 281, 274, 283, 282, 280, and 254. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide is preferably used. Furthermore, a conductive material that inhibits the permeation of impurities such as water and hydrogen can be used in a single layer or in a stacked layer. Using such a conductive material prevents oxygen added to insulator 280 from being absorbed by conductors 240a and 240b. Furthermore, it prevents impurities such as water and hydrogen contained in the layer above insulator 281 from entering oxide 230 via conductors 240a and 240b.

[0159] Insulators 241a and 241b can be made of, for example, silicon nitride, aluminum oxide, or silicon oxynitride. Since insulators 241a and 241b are disposed in contact with insulator 254, impurities such as water and hydrogen contained in insulator 280 and the like can be prevented from entering oxide 230 through conductors 240a and 240b. Silicon nitride is particularly preferred because of its high barrier properties to hydrogen. Furthermore, oxygen contained in insulator 280 can be prevented from being absorbed by conductors 240a and 240b.

[0160] Conductors 246 (conductors 246a and 246b), serving as wiring, can be arranged in contact with the top surfaces of conductors 240a and 240b. Conductors 246 are preferably made of a conductive material primarily composed of tungsten, copper, or aluminum. Furthermore, these conductors can have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the aforementioned conductive materials. Furthermore, these conductors can be embedded in openings in an insulator.

[0161] <Materials Constituting Semiconductor Devices> The following describes constituent materials that can be used in semiconductor devices.

[0162] <<Substrate>> As the substrate for forming the transistor 200, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate can be used. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (such as yttrium-stabilized zirconia substrates), and resin substrates. Furthermore, examples of semiconductor substrates include semiconductor substrates made of materials such as silicon or germanium, or compound semiconductor substrates composed of materials such as silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Furthermore, examples include semiconductor substrates having an insulating region within the above-mentioned semiconductor substrates, such as SOI (Silicon On Insulator) substrates. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, examples include substrates containing metal nitrides and substrates containing metal oxides. Furthermore, examples include insulating substrates provided with a conductor or semiconductor, semiconductor substrates provided with a conductor or insulator, and conductive substrates provided with a semiconductor or insulator. Alternatively, a substrate having elements disposed on these substrates may be used. Examples of elements disposed on the substrate include capacitors, resistors, switching elements, light-emitting elements, and memory elements.

[0163] <<Insulator>> Insulators include insulating oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides.

[0164] For example, as transistors become increasingly miniaturized and highly integrated, the thinning of gate insulators can sometimes lead to problems such as leakage current. Using high-k materials for gate insulators allows for lower transistor operating voltages while maintaining physical thickness. Conversely, using materials with low relative dielectric constants for interlayer insulators can reduce parasitic capacitance between wiring lines. Therefore, it is best to select the material based on the insulator's function.

[0165] In addition, examples of insulators with relatively high dielectric constants include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0166] Insulators with relatively low dielectric constants include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon and nitrogen-doped silicon oxide, and silicon oxide or resin with pores.

[0167] Furthermore, by surrounding a transistor using a metal oxide with an insulator that inhibits the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. Examples of insulators that inhibit the permeation of impurities such as hydrogen and oxygen include single-layer or stacked insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Specifically, insulators that inhibit the permeation of impurities such as hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride.

[0168] Furthermore, the insulator used as the gate insulator is preferably one containing a region of oxygen that is desorbed by heating. For example, by employing a structure in which silicon oxide or silicon oxynitride, which contains a region of oxygen that is desorbed by heating, is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be filled.

[0169] <<Conductor>> As the conductor, it is preferred to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum, an alloy containing these metal elements, or an alloy combining these metal elements. For example, it is preferred to use tantalum nitride, titanium nitride, tungsten, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel. Furthermore, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, and oxides containing lanthanum and nickel are conductive materials that are not easily oxidized or that maintain conductivity even when absorbing oxygen, and therefore are preferred. Alternatively, a semiconductor having high conductivity, such as polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0170] Alternatively, multiple conductive layers formed from the above-mentioned materials may be stacked. For example, a stacked structure may be formed by combining a material containing the above-mentioned metal element with a conductive material containing oxygen. Alternatively, a stacked structure may be formed by combining a material containing the above-mentioned metal element with a conductive material containing nitrogen. Alternatively, a stacked structure may be formed by combining a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0171] Furthermore, when an oxide is used in the channel formation region of a transistor, the conductive material used as the gate electrode preferably has a stacked structure combining a material containing the aforementioned metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen is preferably positioned on the channel formation region side. Positioning the conductive material containing oxygen on the channel formation region side facilitates the supply of oxygen released from the conductive material to the channel formation region.

[0172] In particular, as the conductor used as the gate electrode, it is preferable to use a conductive material containing the metal element contained in the metal oxide forming the channel and oxygen. Alternatively, a conductive material containing the aforementioned metal element and nitrogen may be used. For example, conductive materials containing nitrogen, such as titanium nitride and tantalum nitride, may also be used. Furthermore, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide doped with silicon may also be used. Furthermore, indium gallium zinc oxide containing nitrogen may also be used. Using these materials may sometimes allow the capture of hydrogen contained in the metal oxide forming the channel. Alternatively, it may also allow the capture of hydrogen entering from an external insulator, etc.

[0173] <<Metal Oxides>> As the oxide 230, a metal oxide used as a semiconductor (oxide semiconductor) is preferably used. Hereinafter, the metal oxide that can be used for the oxide 230 according to one embodiment of the present invention will be described.

[0174] The metal oxide preferably contains at least indium or zinc. Indium and zinc are particularly preferred. Furthermore, it preferably contains aluminum, gallium, yttrium, tin, and the like. Alternatively, it may contain one or more of boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium.

[0175] Here, consider the case where the metal oxide is an In-M-Zn oxide containing indium, an element M, and zinc. Note that the element M is aluminum, gallium, yttrium, or tin. Other elements that can be used as the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. Note that a combination of multiple elements may also be used as the element M.

[0176] Note that in this specification, etc., metal oxides containing nitrogen may also be referred to as metal oxides. Furthermore, metal oxides containing nitrogen may also be referred to as metal oxynitrides.

[0177] [Structure of Metal Oxides] Oxide semiconductors (metal oxides) are classified into single-crystalline oxide semiconductors and non-single-crystalline oxide semiconductors. Examples of non-single-crystalline oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, nanocrystalline oxide semiconductors (nc-OS), amorphous oxide semiconductors (amorphous-like oxide semiconductors), and amorphous oxide semiconductors.

[0178] CAAC-OS has c-axis alignment, with multiple nanocrystals connected along the ab plane, but the crystal structure exhibits distortion. Note that distortion refers to the difference in lattice alignment between regions where multiple nanocrystals are connected and other regions where the lattice alignment is consistent.

[0179] While nanocrystals are generally hexagonal, they are not limited to regular hexagons and may not be regular. Furthermore, distortion can sometimes have pentagonal or heptagonal lattice arrangements. Furthermore, in CAAC-OS, no clear grain boundaries (also known as grain boundaries) are observed even near distortion. This suggests that lattice distortion suppresses the formation of grain boundaries. This is because CAAC-OS tolerates distortion due to factors such as the low density of oxygen atoms in the ab plane and the changes in interatomic bond distances caused by metal element substitution.

[0180] CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) composed of a layer containing indium and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc, and oxygen (hereinafter referred to as an (M, Zn) layer). Indium and the element M are mutually substitutable. When indium replaces the element M in the (M, Zn) layer, the layer can also be represented as an (In, M, Zn) layer. Furthermore, when indium in the In layer is replaced by the element M, the layer can also be represented as an (In, M) layer.

[0181] CAAC-OS is a highly crystalline metal oxide. However, since clear grain boundaries are difficult to observe in CAAC-OS, the decrease in electron mobility caused by these grain boundaries is less likely to occur. Furthermore, the crystallinity of metal oxides can sometimes be reduced by the incorporation of impurities or the formation of defects. Therefore, CAAC-OS is a metal oxide with low levels of impurities and defects (such as oxygen vacancies). Consequently, metal oxides containing CAAC-OS have stable physical properties. Consequently, metal oxides containing CAAC-OS exhibit high heat resistance and reliability.

[0182] In nc-OS, the atomic arrangement within tiny regions (e.g., regions between 1 nm and 10 nm, and particularly between 1 nm and 3 nm) exhibits periodicity. Furthermore, in nc-OS, no regularity in crystal orientation is observed between different nanocrystals. Consequently, no orientation is observed across the entire film. Consequently, nc-OS can sometimes be indistinguishable from a-like OS or amorphous oxide semiconductors using certain analytical methods.

[0183] Furthermore, In-Ga-Zn oxide (hereinafter, IGZO), a type of metal oxide containing indium, gallium, and zinc, may have a stable structure when formed as the aforementioned nanocrystals. In particular, IGZO tends to have difficulty growing in the atmosphere, so small IGZO crystals (such as the aforementioned nanocrystals) may be more structurally stable than large IGZO crystals (herein, crystals measuring several millimeters or centimeters).

[0184] a-like OS is a metal oxide with a structure intermediate between nc-OS and amorphous oxide semiconductors. It contains voids or low-density regions. In other words, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

[0185] Oxide semiconductors (metal oxides) have various structures and properties. The oxide semiconductor according to one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a nc-OS, and a CAAC-OS.

[0186] [Impurities] Here, the influence of various impurities in metal oxides is described.

[0187] When impurities are introduced into an oxide semiconductor, defect state density or oxygen vacancies may occur. Therefore, when impurities are introduced into the channel formation region of an oxide semiconductor, the electrical characteristics of a transistor using the oxide semiconductor may change, reducing reliability. Furthermore, when oxygen vacancies are present in the channel formation region, the transistor may exhibit a normally-on characteristic.

[0188] The electrical properties of transistors using metal oxides vary due to impurities and oxygen vacancies in the metal oxides, and they are prone to exhibiting a normally-on characteristic (a characteristic in which a channel exists and current flows through the transistor even without applying a voltage to the gate electrode). Furthermore, when the transistor is driven when the metal oxide contains excess oxygen, the valence of the excess oxygen atoms may change, causing changes in the transistor's electrical properties and reducing reliability.

[0189] Therefore, it is preferable to use a metal oxide with a low carrier density for the channel-forming region in a transistor. Lowering the carrier concentration of the metal oxide also reduces the impurity concentration and the defect state density. In this specification, a state with both a low impurity concentration and a low defect state density is referred to as "high-purity intrinsic" or "substantially high-purity intrinsic." Note that in this specification, a carrier density of 1×10 16 cm -3 or less in the metal oxide in the channel-forming region is defined as high-purity intrinsic.

[0190] Furthermore, the carrier concentration of the metal oxide in the channel formation region is preferably 1×10 18 cm -3 or less, more preferably 1×10 17 cm -3 or less, further preferably 1×10 16 cm -3 or less, further preferably less than 1×10 13 cm -3, and particularly preferably less than 1×10 12 cm -3. Note that the lower limit of the carrier concentration of the metal oxide in the channel formation region is not particularly limited and may be, for example, 1×10 -9 cm -3.

[0191] Impurities in metal oxides include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. In particular, hydrogen contained in metal oxides reacts with oxygen bound to metal atoms to produce water, sometimes forming oxygen vacancies in the metal oxide. Furthermore, when the channel formation region of a metal oxide semiconductor contains oxygen vacancies, the transistor may exhibit normally-on characteristics. Furthermore, when hydrogen enters an oxygen vacancy in a metal oxide, it may bond with the oxygen vacancy, forming a VOH. The defect (VOH) created by hydrogen entering the oxygen vacancy acts as a donor, sometimes generating electrons as carriers. Furthermore, sometimes, electrons as carriers are generated by some of the hydrogen bonding with oxygen bound to metal atoms. Therefore, transistors using metal oxides containing a high amount of hydrogen tend to exhibit normally-on characteristics. Furthermore, hydrogen in metal oxides is susceptible to changes due to stresses such as heat and electric fields, so high amounts of hydrogen in the metal oxide may reduce transistor reliability.

[0192] In one embodiment of the present invention, it is preferred to minimize VOH in oxide 230, making the oxide 230 intrinsically high-purity or substantially high-purity. To obtain a metal oxide with sufficiently reduced VOH, it is important to remove impurities such as water and hydrogen from the metal oxide (sometimes referred to as dehydration or dehydrogenation) and to supply oxygen to the metal oxide to fill oxygen vacancies (sometimes referred to as overoxidation). Using a metal oxide with sufficiently reduced VOH and other impurities in the channel formation region of a transistor can achieve stable electrical characteristics.

[0193] Defects (VOH) caused by hydrogen entering oxygen vacancies serve as donors in metal oxides. However, quantitative evaluation of these defects is difficult. Consequently, in metal oxides, carrier concentration is sometimes used instead of donor concentration for evaluation. Therefore, in this specification and other documents, the carrier concentration, assuming no electric field is applied, is sometimes used as a parameter for metal oxides, rather than the donor concentration. In other words, the term "carrier concentration" in this specification and other documents can sometimes be replaced with "donor concentration." Furthermore, the term "carrier concentration" in this specification and other documents can be replaced with "carrier density."

[0194] Therefore, it is preferable to minimize the amount of hydrogen in the metal oxide. Specifically, the hydrogen concentration in the metal oxide, as measured by SIMS, should be less than 1×10 20 atoms / cm 3, preferably less than 1×10 19 atoms / cm 3, more preferably less than 5×10 18 atoms / cm 3, and even more preferably less than 1×10 18 atoms / cm 3. By using a metal oxide with sufficiently reduced levels of impurities such as hydrogen in the channel formation region of a transistor, the transistor can have stable electrical characteristics.

[0195] Furthermore, the defect state density mentioned above may include trap levels. Furthermore, charges trapped in the metal oxide's trap levels take a long time to dissipate, sometimes acting like fixed charges. Consequently, the electrical characteristics of transistors containing channel-forming regions within metal oxides with high trap state density may be unstable.

[0196] Furthermore, when the channel formation region of an oxide semiconductor contains impurities, the crystallinity of the channel formation region may be reduced. Furthermore, the crystallinity of the oxide provided in contact with the channel formation region may be reduced. Low crystallinity in the channel formation region can reduce the stability or reliability of the transistor. Low crystallinity in the oxide provided in contact with the channel formation region can create interface energy levels, reducing the stability or reliability of the transistor.

[0197] Therefore, to improve transistor stability and reliability, it is effective to reduce the impurity concentration in the channel formation region of the oxide semiconductor and its vicinity. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Because metal oxides with reduced impurity concentrations have lower defect state density, trap energy levels may also be lowered.

[0198] <<Other semiconductor materials>> Semiconductor materials that can be used for oxide 230 are not limited to the aforementioned metal oxides. Semiconductor materials with a band gap (non-zero band gap semiconductors) can also be used as oxide 230. For example, single element semiconductors such as silicon, compound semiconductors such as gallium arsenide, and layered semiconductor materials (also known as atomic layer materials, two-dimensional materials, etc.) are preferably used as semiconductor materials. In particular, layered semiconductor materials are preferably used as semiconductor materials.

[0199] In this specification and other contexts, layered materials are a general term for materials with a layered crystalline structure. A layered crystalline structure is a structure in which layers, formed by covalent or ionic bonds, are stacked together through bonds weaker than covalent or ionic bonds, such as van der Waals forces. Layered materials have high electrical conductivity per unit layer, meaning they have high two-dimensional conductivity. By using a semiconductor material with high two-dimensional conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0200] Examples of layered materials include graphene, silicene, and sulfides. Sulfides are compounds containing sulfur. Sulfur is a general term for elements belonging to Group 16, which includes oxygen, sulfur, selenium, tellurium, polonium, and lead. Examples of sulfides include transition metal chalcogenides and Group 13 chalcogenides.

[0201] As the oxide 230, for example, a transition metal chalcogenide used as a semiconductor is preferably used. Specifically, examples of transition metal chalcogenides that can be used for the oxide 230 include molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum tellurium (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten tellurium (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), and zirconium selenide (typically ZrSe2).

[0202] <Method for Manufacturing Semiconductor Device> Next, a method for manufacturing the semiconductor device according to one embodiment of the present invention shown in FIG. 1A to FIG. 1D will be described using FIG. 4A to FIG. 11D .

[0203] Figures 4A, 5A, 6A, 7A, 8A, 9A, 10A, and 11A are top views. Figures 4B, 5B, 6B, 7B, 8B, 9B, 10B, and 11B are cross-sectional views corresponding to the portion indicated by the dot-dash line A1-A2 in Figures 4A, 5A, 6A, 7A, 8A, 9A, 10A, and 11A, respectively, and are also cross-sectional views along the channel length of transistor 200. Figures 4C, 5C, 6C, 7C, 8C, 9C, 10C, and 11C are cross-sectional views corresponding to the portion indicated by the dot-dash line A3-A4 in Figures 4A, 5A, 6A, 7A, 8A, 9A, 10A, and 11A, respectively, and are also cross-sectional views along the channel width of transistor 200. 4D, 5D, 6D, 7D, 8D, 9D, 10D, and 11D are cross-sectional views corresponding to the portions indicated by the dot-dash line A5-A6 in FIG4A, 5A, 6A, 7A, 8A, 9A, 10A, and 11A, respectively. Note that some components are omitted in the top views of FIG4A, 5A, 6A, 7A, 8A, 9A, 10A, and 11A for clarity.

[0204] First, a substrate (not shown) is prepared, and an insulator 212 is formed on the substrate. The insulator 212 can be formed by sputtering, CVD, molecular beam epitaxy (MBE), pulsed laser deposition (PLD), or ALD.

[0205] Note that CVD methods can be categorized into plasma-enhanced CVD (PECVD) using plasma, thermal CVD (TCVD) using heat, and photo CVD using light. Furthermore, CVD methods can be categorized into metal CVD (MCVD) and metal organic CVD (MOCVD) based on the source gas used.

[0206] Plasma CVD allows high-quality films to be produced at lower temperatures. Furthermore, because it doesn't use plasma, thermal CVD is a film-forming method that can reduce plasma damage to the substrate being processed. For example, the wiring, electrodes, and components (transistors, capacitors, etc.) included in a semiconductor device sometimes receive charge from plasma, causing charge buildup. This accumulated charge can damage the wiring, electrodes, and components within the semiconductor device. On the other hand, thermal CVD, which doesn't use plasma, avoids this plasma damage, improving the yield of semiconductor devices. Furthermore, thermal CVD avoids plasma damage during film formation, resulting in films with fewer defects.

[0207] The ALD method utilizes the self-regulating properties of atoms to deposit each layer. This allows for the formation of extremely thin films, the formation of films with high aspect ratios, the formation of films with few defects such as pinholes, the formation of films with excellent coverage, and the ability to form films at low temperatures. ALD also includes the plasma-enhanced ALD (PEALD) method. Using plasma allows for film formation at even lower temperatures, which is sometimes preferred. Note that the precursors used in the ALD method sometimes contain impurities such as carbon. Therefore, films formed using the ALD method may contain higher levels of impurities such as carbon than films formed using other film formation methods. Furthermore, X-ray photoelectron spectroscopy (XPS) can be used to quantify impurities.

[0208] Unlike film-forming methods that deposit particles released from a target, CVD and ALD methods form films through reactions on the surface of the workpiece. Therefore, films formed using CVD and ALD are less susceptible to the shape of the workpiece and exhibit excellent step coverage. ALD films, in particular, exhibit excellent step coverage and thickness uniformity, making them suitable for applications such as covering surfaces with high-aspect-ratio openings. Note that ALD has a relatively slow deposition rate, so it is sometimes preferable to combine it with other film-forming methods with faster deposition rates, such as CVD.

[0209] CVD and ALD methods can control the composition of the resulting film by adjusting the source gas flow ratio. For example, using CVD or ALD, a film of any composition can be formed by adjusting the source gas flow ratio. Furthermore, by varying the source gas flow ratio while forming the film, a film with a continuously varying composition can be formed. When forming a film while varying the source gas flow ratio, the time required for transport and stress adjustment is eliminated, reducing film formation time compared to using multiple film formation chambers. This can sometimes improve semiconductor device productivity.

[0210] In this embodiment, silicon nitride is formed using CVD as the insulator 212. By using an insulator such as silicon nitride, which is not easily permeable to copper, as the insulator 212, even if a metal such as copper that easily diffuses is used as the conductor in the layer below the insulator 212 (not shown), diffusion of the metal through the insulator 212 to the layer above can be suppressed. Furthermore, by using an insulator such as silicon nitride, which is not easily permeable to impurities such as water and hydrogen, diffusion of impurities such as water and hydrogen contained in the layer below the insulator 212 can be suppressed.

[0211] Next, an insulator 214 is formed on the insulator 212. The insulator 214 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, aluminum oxide is used as the insulator 214.

[0212] Next, an insulator 216 is formed on the insulator 214. The insulator 216 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0213] Next, an opening is formed in insulator 216 that reaches insulator 214. The opening may include, for example, a groove or a slit. The region where the opening is formed is sometimes referred to as an opening portion. Wet etching can be used to form this opening, but dry etching is preferred for microfabrication. Insulator 214 is preferably selected from an insulator that functions as an etch stop when etching insulator 216 to form the groove. For example, when silicon oxide is used as insulator 216 to form the groove, silicon nitride, aluminum oxide, or hafnium oxide is preferably used for insulator 214.

[0214] As a dry etching device, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching device including parallel plate electrodes can be used. The capacitively coupled plasma etching device including parallel plate electrodes can also adopt a structure in which a high-frequency voltage is applied to one of the parallel plate electrodes. Alternatively, a structure in which multiple different high-frequency voltages are applied to one of the parallel plate electrodes can be adopted. Alternatively, a structure in which a high-frequency voltage of the same frequency is applied to each of the parallel plate electrodes can be adopted. Alternatively, a structure in which high-frequency voltages of different frequencies are applied to each of the parallel plate electrodes can be adopted. Alternatively, a dry etching device having a high-density plasma source can be used. For example, as a dry etching device having a high-density plasma source, an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching device can be used.

[0215] After the opening is formed, a conductive film serving as the conductor 205a is formed. This conductive film preferably includes a conductor that inhibits oxygen transmission. For example, tantalum nitride, tungsten nitride, or titanium nitride can be used. Alternatively, a laminated film of a conductor that inhibits oxygen transmission and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. This conductive film can be formed using sputtering, CVD, MBE, PLD, ALD, or the like.

[0216] In this embodiment, a multilayer structure is employed as the conductive film forming the conductor 205a. First, tantalum nitride is formed by sputtering, and titanium nitride is stacked on top of the tantalum nitride. Using this metal nitride as the lower layer of the conductor 205b prevents diffusion of the metal from the conductor 205a, even when a readily diffusible metal such as copper is used as the conductive film forming the conductor 205b, as described later.

[0217] Next, a conductive film to become the conductor 205b is formed. This conductive film can be formed using electroplating, sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, a low-resistance conductive material such as copper is formed as the conductive film.

[0218] Next, CMP is performed to remove the conductive film that will become the conductor 205a and a portion of the conductive film that will become the conductor 205b, exposing the insulator 216. As a result, only the conductors 205a and 205b remain in the opening. This allows the conductor 205 to have a flat top surface (see Figures 4B to 4D). Note that this CMP process may also remove a portion of the insulator 216.

[0219] Note that in the above process, conductor 205 is formed so as to be embedded in the opening of insulator 216, but this embodiment is not limited to this. For example, conductor 205 may be formed on insulator 214, insulator 216 may be formed on conductor 205, and insulator 216 may be subjected to CMP treatment to remove a portion of insulator 216, thereby exposing the surface of conductor 205.

[0220] Next, insulator 222 is formed over insulator 216 and conductor 205. Insulator 222 is preferably formed from an oxide of one or both of aluminum and hafnium. Insulators containing oxides of one or both of aluminum and hafnium have barrier properties to oxygen, hydrogen, and water. When insulator 222 has barrier properties to hydrogen and water, it can prevent hydrogen and water contained in structures surrounding transistor 200 from diffusing into transistor 200 through insulator 222, thereby suppressing the formation of oxygen vacancies in oxide 230.

[0221] The insulator 222 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0222] Next, heat treatment is preferably performed. The heat treatment can be performed at a temperature of 250°C to 650°C, preferably 300°C to 500°C, and more preferably 320°C to 450°C. The heat treatment is performed in a nitrogen or inert gas atmosphere, or an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas. The heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in a nitrogen or inert gas atmosphere, and then in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas to replace the released oxygen.

[0223] In this embodiment, heat treatment is performed after forming insulator 222 at 400°C for one hour in a nitrogen atmosphere, followed by continuous treatment at 400°C for one hour in an oxygen atmosphere. This heat treatment removes impurities such as water and hydrogen contained in insulator 222. Alternatively, heat treatment can be performed after forming insulator 224.

[0224] Next, an insulator 224 is formed on the insulator 222. The insulator 224 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, a silicon oxynitride film is formed by CVD as the insulator 224.

[0225] Here, in order to form an excess oxygen region in the insulator 224, a plasma treatment containing oxygen may be performed under reduced pressure. For example, the plasma treatment containing oxygen preferably employs a device including a power source for generating high-density plasma using microwaves. Alternatively, a power source may be included that applies RF (Radio Frequency) to one side of the substrate. High-density oxygen radicals can be generated by using high-density plasma, and by applying RF to one side of the substrate, the oxygen radicals generated by the high-density plasma can be efficiently introduced into the insulator 224. Alternatively, after performing plasma treatment containing an inert gas using such a device, a plasma treatment containing oxygen may be performed to replace the released oxygen. Furthermore, by appropriately selecting the conditions for the plasma treatment, impurities such as water and hydrogen contained in the insulator 224 can be removed. In this case, heat treatment may not be performed.

[0226] Here, after forming aluminum oxide on the insulator 224 by sputtering, for example, the aluminum oxide may be subjected to a CMP process until it reaches the insulator 224. This CMP process can flatten and smooth the surface of the insulator 224. Placing the aluminum oxide on the insulator 224 and performing the CMP process makes it easier to detect the endpoint of the CMP process. Furthermore, while the thickness of the insulator 224 may be reduced due to polishing a portion of the insulator 224 during the CMP process, this thickness can be adjusted during the formation of the insulator 224. Planarizing and smoothing the surface of the insulator 224 can sometimes prevent a decrease in coverage by the oxide film formed underneath, thereby preventing a decrease in the yield of the semiconductor device. Furthermore, forming the aluminum oxide on the insulator 224 by sputtering is preferred because oxygen can be added to the insulator 224.

[0227] Next, oxide films 230A and 230B are sequentially formed on insulator 224 (see FIG. 4B to FIG. 4D ). It is preferable to form oxide films 230A and 230B continuously without exposing them to the atmosphere. Forming the oxide films without exposing them to the atmosphere prevents impurities and moisture from the atmosphere from adhering to oxide films 230A and 230B, thereby maintaining a clean surface near the interface between oxide films 230A and 230B.

[0228] The oxide film 230A and the oxide film 230B can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0229] For example, when forming oxide films 230A and 230B by sputtering, oxygen or a mixture of oxygen and a rare gas is used as the sputtering gas. Increasing the oxygen content of the sputtering gas can increase the excess oxygen in the formed oxide films. Furthermore, when forming the oxide films by sputtering, for example, the aforementioned In-M-Zn oxide target can be used.

[0230] In particular, when the oxide film 230A is formed, a portion of the oxygen contained in the sputtering gas may be supplied to the insulator 224. Therefore, the ratio of oxygen contained in the sputtering gas may be 70% or more, preferably 80% or more, and more preferably 100%.

[0231] Furthermore, when the oxide film 230B is formed using a sputtering method, an oxygen-excess oxide semiconductor is formed when the sputtering gas contains an oxygen ratio greater than 30% and less than 100%, preferably greater than 70% and less than 100%, during film formation. While transistors using an oxygen-excess oxide semiconductor in the channel formation region can achieve higher reliability, the present invention is not limited thereto. When the oxide film 230B is formed using a sputtering method, an oxygen-deficient oxide semiconductor is formed when the sputtering gas contains an oxygen ratio greater than 1% and less than 30%, preferably greater than 5% and less than 20%, during film formation. Transistors using an oxygen-deficient oxide semiconductor in the channel formation region can have higher field-effect mobility. Furthermore, by heating the substrate while forming the film, the crystallinity of the oxide film can be improved.

[0232] In this embodiment, oxide film 230A is formed by sputtering using an oxide target with an In:Ga:Zn atomic ratio of 1:3:4. Separately, oxide film 230B is formed by sputtering using an oxide target with an In:Ga:Zn atomic ratio of 4:2:4.1. These oxide films can be formed by appropriately selecting film formation conditions and atomic ratios based on the desired properties of oxide 230a and oxide 230b.

[0233] The insulator 222, the insulator 224, the oxide film 230A, and the oxide film 230B are preferably formed without being exposed to the atmosphere. For example, a multi-chamber film forming apparatus may be used.

[0234] Next, a heat treatment may be performed. The aforementioned heat treatment conditions can be used for this heat treatment. This heat treatment can remove impurities such as water and hydrogen from the oxide films 230A and 230B. In this embodiment, the treatment is performed at 400°C for one hour in a nitrogen atmosphere, followed by a continuous treatment at 400°C for one hour in an oxygen atmosphere.

[0235] Next, a conductive film 242A is formed on the oxide film 230B (see Figures 4B to 4D). The conductive film 242A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Furthermore, a heat treatment may be performed before forming the conductive film 242A. This heat treatment may also be performed under reduced pressure, with the conductive film 242A continuously formed without being exposed to the atmosphere. This treatment removes moisture and hydrogen adhering to the surface of the oxide film 230B, and reduces the moisture and hydrogen concentrations in the oxide films 230A and 230B. The temperature of the heat treatment is preferably not less than 100°C and not more than 400°C. In this embodiment, the heat treatment temperature is set to 200°C.

[0236] Next, photolithography is used to process the oxide films 230A, 230B, and conductive film 242A into island shapes, thereby forming oxide 230a, oxide 230b, and conductive layer 242B (see Figures 5A to 5D). Dry etching, wet etching, or other methods can be used for this process. Dry etching is suitable for microfabrication. Furthermore, the oxide films 230A, 230B, and conductive film 242A can be formed under different conditions. Furthermore, during this process, the thickness of the insulator 224 in the region that does not overlap with the oxide 230a may become thinner.

[0237] In photolithography, photoresist is first exposed through a mask. A developer is then used to remove or leave the exposed areas, forming a photoresist mask. Etching is then performed through this photoresist mask to shape the conductor, semiconductor, insulator, or other material into the desired shape. For example, the photoresist can be exposed using a KrF excimer laser, an ArF excimer laser, or EUV (Extreme Ultraviolet) light to form the photoresist mask. Alternatively, immersion techniques can be used, where the space between the substrate and the projection lens is filled with a liquid (e.g., water). Alternatively, electron beams or ion beams can be used instead of the aforementioned light. Note that a mask is not required when using an electron beam or ion beam. Furthermore, when removing the photoresist mask, either dry etching (such as ashing) or wet etching can be performed. Dry etching can be performed followed by wet etching, or wet etching can be performed followed by dry etching.

[0238] Alternatively, a hard mask made of an insulator or conductor can be used instead of a photoresist mask. When using a hard mask, an insulating film or a conductive film serving as the hard mask material can be formed on the conductive film 242A, and a photoresist mask can be formed thereon. The hard mask material can then be etched to form a hard mask of the desired shape. Etching of the conductive film 242A can be performed either after removing the photoresist mask or without removing the photoresist mask. In the latter case, the photoresist mask may disappear during etching. Alternatively, the hard mask can be removed by etching after etching the conductive film 242A. On the other hand, if the hard mask material does not affect subsequent processes or can be used in subsequent processes, removal of the hard mask is not necessary.

[0239] Here, oxide 230a, oxide 230b, and conductive layer 242B are formed so that at least a portion overlaps conductor 205. Furthermore, the side surfaces of oxide 230a, oxide 230b, and conductive layer 242B are preferably substantially perpendicular to the top surface of insulator 222. When the side surfaces of oxide 230a, oxide 230b, and conductive layer 242B are substantially perpendicular to the top surface of insulator 222, a smaller area and higher density can be achieved when multiple transistors 200 are arranged. Alternatively, a structure can be employed in which the side surfaces of oxide 230a, oxide 230b, and conductive layer 242B form a relatively low angle with the top surface of insulator 222. In this case, the angle formed by the side surfaces of oxide 230a, oxide 230b, and conductive layer 242B with the top surface of insulator 222 is preferably greater than 60 degrees and less than 70 degrees. This configuration improves coverage with insulator 254 and the like during subsequent manufacturing processes and reduces defects such as voids.

[0240] Furthermore, a curved surface is formed between the side surface and the top surface of the conductive layer 242B. Specifically, the ends of the side surface and the top surface are preferably curved. For example, at the ends of the conductive layer 242B, the curved surface has a radius of curvature of 3 nm to 10 nm, more preferably 5 nm to 6 nm. When the ends lack corners, the film coverage during subsequent film formation processes can be improved.

[0241] Next, an insulating film 254A is formed over the insulator 224, the oxide 230a, the oxide 230b, and the conductive layer 242B (see FIG. 6B to FIG. 6D).

[0242] The insulating film 254A can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Preferably, the insulating film 254A uses an insulating film that inhibits oxygen permeation. For example, aluminum oxide, silicon nitride, silicon oxide, or gallium oxide can be deposited using a sputtering method or an ALD method. Alternatively, aluminum oxide can be deposited using a sputtering method and then deposited on top of the aluminum oxide using an ALD method.

[0243] Next, an insulating film, serving as insulator 280, is formed on insulating film 254A. This insulating film can be formed using a sputtering method, CVD method, MBE method, PLD method, ALD method, or the like. In this embodiment, a silicon oxide film is formed as the insulating film using CVD or sputtering method. Note that heat treatment may be performed before forming this insulating film. Heat treatment may also be performed under reduced pressure, allowing the insulating film to be continuously formed without exposure to the atmosphere. This treatment removes moisture and hydrogen adhering to the surface of insulating film 254A and reduces the moisture and hydrogen concentrations in oxides 230a and 230b and insulator 224. The heat treatment conditions described above can be used for the heat treatment.

[0244] Furthermore, the insulating film may have a multilayer structure. For example, a silicon oxide film may be formed by sputtering and a silicon oxide film may be formed on the silicon oxide film by CVD.

[0245] Next, the insulating film is subjected to CMP treatment to form an insulator 280 having a flat top surface (see FIG. 6B to FIG. 6D ).

[0246] Microwave treatment can also be performed. Microwave treatment is preferably performed in an oxygen-containing atmosphere and under reduced pressure. Microwave treatment applies the electric field generated by the microwaves to insulator 280, oxide 230b, oxide 230a, and the like, causing VOH in oxide 230b and oxide 230a to separate into oxygen vacancies (VO) and hydrogen (H). Sometimes, some of the separated hydrogen bonds with oxygen contained in insulator 280 and is removed as water molecules. Furthermore, sometimes, some of the hydrogen is gettered into conductive layer 242B through insulating film 254A.

[0247] Alternatively, heat treatment can be performed after microwave treatment while maintaining reduced pressure. This treatment can effectively remove hydrogen from insulator 280, oxide 230b, and oxide 230a. Note that the heat treatment temperature is preferably 300°C or higher and 500°C or lower.

[0248] Furthermore, by performing microwave treatment to modify the film quality of insulator 280, the diffusion of hydrogen, water, and impurities can be suppressed. Therefore, by performing post-processing or heat treatment after forming insulator 280, the diffusion of hydrogen, water, and impurities through insulator 280 into oxide 230 can be suppressed.

[0249] Next, a portion of insulator 280, a portion of insulating film 254A, and a portion of conductive layer 242B are processed to form an opening that reaches oxide 230b. This opening is preferably formed so as to overlap conductor 205. This opening forms insulator 254, conductor 242a, and conductor 242b (see Figures 7A to 7D).

[0250] At this time, it is preferable to thin the oxide 230b in the region overlapping the opening. The amount of film reduction in this region corresponds to Lc shown in FIG3B . Thinning the oxide 230b in this region can suppress the formation of a low-resistance region near the top surface of the channel formation region and the generation of a parasitic channel. Consequently, variations in transistor characteristics caused by the parasitic channel can be suppressed.

[0251] Furthermore, it is preferable to remove a portion of the side surface of oxide 230b in the region overlapping the opening. The amount of film reduction in this region corresponds to We shown in FIG3B . This prevents the formation of low-resistance regions near the side surfaces of the channel formation region and the generation of parasitic channels. Consequently, variations in transistor characteristics caused by parasitic channels can be suppressed.

[0252] Alternatively, a portion of the insulator 280, a portion of the insulating film 254A, and a portion of the conductive layer 242B may be processed under different conditions. For example, a portion of the insulator 280 may be processed using dry etching, a portion of the insulating film 254A may be processed using wet etching, and a portion of the conductive layer 242B may be processed using dry etching.

[0253] Here, it is preferable to remove impurities that adhere to the surface of oxide 230a, oxide 230b, etc. or diffuse into the interior. Examples of such impurities include impurities derived from components contained in insulator 280, insulating film 254A, and conductive layer 242B, components contained in components used in the apparatus used to form the aforementioned openings, and components contained in the gas or liquid used for etching. Examples of such impurities include aluminum, silicon, tantalum, fluorine, and chlorine.

[0254] In order to remove the above impurities, a cleaning process may be performed. Examples of cleaning methods include wet cleaning using a cleaning solution, plasma treatment using plasma, and cleaning using a heat treatment, and these cleaning methods may be appropriately combined.

[0255] For wet cleaning, aqueous solutions of ammonia, oxalic acid, phosphoric acid, hydrofluoric acid, etc. diluted with carbonated water or pure water, pure water, carbonated water, etc. can be used for cleaning. Alternatively, ultrasonic cleaning can be performed using these aqueous solutions, pure water, or carbonated water. Furthermore, these cleaning methods can be appropriately combined.

[0256] Next, heat treatment may be performed. This heat treatment is preferably performed in an oxygen-containing atmosphere. Alternatively, this heat treatment can be performed under reduced pressure without exposure to the atmosphere to continuously form oxide film 230C (see Figures 8A to 8D). This treatment removes moisture and hydrogen adhering to the surface of oxide 230b and reduces the moisture and hydrogen concentrations in oxides 230a and 230b. The heat treatment temperature is preferably 100°C to 400°C. In this embodiment, the heat treatment temperature is set to 200°C.

[0257] Oxide film 230C can be formed using a sputtering method, CVD method, MBE method, PLD method, ALD method, or the like. Oxide film 230C can be formed using the same method as oxide film 230A or oxide film 230B, depending on the desired properties of oxide film 230C. In this embodiment, oxide film 230C is formed using a sputtering method using an oxide target having an In:Ga:Zn atomic ratio of 4:2:4.1.

[0258] Note that the oxide film 230C may be a stacked layer. For example, a film may be formed by sputtering using an oxide target having an In:Ga:Zn ratio of 4:2:4.1 (atomic ratio), and then a film may be formed continuously using an oxide target having an In:Ga:Zn ratio of 1:3:4 (atomic ratio).

[0259] When forming oxide film 230C, some of the oxygen contained in the sputtering gas may be supplied to oxide 230a and oxide 230b. Alternatively, when forming oxide film 230C, some of the oxygen contained in the sputtering gas may be supplied to insulator 280. Therefore, the ratio of oxygen contained in the sputtering gas for oxide film 230C may be 70% or higher, preferably 80% or higher, and more preferably 100%.

[0260] Next, heat treatment may be performed. Heat treatment can also be performed to continuously form insulating film 250A under reduced pressure without exposure to the atmosphere (see Figures 8A to 8D). This treatment removes moisture and hydrogen adhering to the surface of oxide film 230C, and reduces the moisture and hydrogen concentrations in oxide 230a, oxide 230b, and oxide film 230C. The heat treatment temperature is preferably 100°C or higher and 400°C or lower.

[0261] The insulating film 250A can be formed using sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, silicon oxynitride is deposited using CVD as the insulating film 250A. Note that the formation temperature of the insulating film 250A is preferably 350°C or higher and lower than 450°C, particularly preferably around 400°C. Forming the insulating film 250A at 400°C allows for the formation of an insulating film with fewer impurities.

[0262] When insulator 250 has a two-layer stacked structure, the insulating film forming the lower layer of insulator 250 and the insulating film forming the upper layer of insulator 250 are preferably formed continuously without being exposed to the atmosphere. Forming the insulating film without being exposed to the atmosphere prevents impurities and moisture from the atmosphere from adhering to the insulating film forming the lower layer of insulator 250 and the insulating film forming the upper layer of insulator 250, thereby maintaining cleanliness near the interface between the insulating film forming the lower layer of insulator 250 and the insulating film forming the upper layer of insulator 250.

[0263] Here, after forming the insulating film 250A, microwave treatment can also be performed in an oxygen-containing atmosphere and under reduced pressure. Microwave treatment applies an electric field generated by the microwaves to the insulating film 250A, the oxide film 230C, the oxide 230b, the oxide 230a, and the like, thereby separating the VOH in the oxide film 230C, the oxide 230b, and the oxide 230a into VO and hydrogen. Some of the separated hydrogen bonds with oxygen and is sometimes removed from the insulating film 250A, the oxide film 230C, the oxide 230b, and the oxide 230a as H2O. Furthermore, some of the hydrogen may be gettered by the conductor 242 (conductors 242a and 242b). Thus, microwave treatment can reduce the hydrogen concentration in the insulating film 250A, the oxide film 230C, the oxide 230b, and the oxide 230a. In addition, by supplying oxygen to VO generated by separating VOH in the oxide 230a, the oxide 230b, and the oxide film 230c into VO and hydrogen, VO can be repaired or filled.

[0264] Alternatively, after microwave treatment, the reduced pressure state may be maintained while heat treatment is performed. This treatment can effectively remove the hydrogen concentration in the insulating film 250A, the oxide film 230C, the oxide 230b, and the oxide 230a. Furthermore, some hydrogen may be gettered by the conductor 242 (conductors 242a and 242b). Alternatively, after microwave treatment, the reduced pressure state may be maintained while heat treatment is repeated. Repeated heat treatment can more effectively remove the hydrogen concentration in the insulating film 250A, the oxide film 230C, the oxide 230b, and the oxide 230a. The heat treatment temperature is preferably 300°C or higher and 500°C or lower.

[0265] Furthermore, by performing microwave treatment to change the film quality of insulating film 250A, the diffusion of hydrogen, water, impurities, etc. can be suppressed. This can prevent hydrogen, water, impurities, etc. from diffusing through insulator 250 to oxide 230b, oxide 230a, etc. during post-processing such as film formation of the conductive film that will become conductor 260 or post-processing such as heat treatment.

[0266] Next, a conductive film 260A and a conductive film 260B are sequentially formed (see FIG9A to FIG9D ). The conductive film 260A and the conductive film 260B can be formed using sputtering, CVD, MBE, PLD, ALD, or the like. In this embodiment, the conductive film 260A is formed using ALD, and the conductive film 260B is formed using CVD.

[0267] Next, oxide film 230C, insulating film 250A, conductive film 260A, and conductive film 260B are polished using a CMP process until insulator 280 is exposed, forming oxide 230c, insulator 250, and conductors 260 (conductors 260a and 260b) (see Figures 10A to 10D). Thus, oxide 230c is arranged to cover the inner walls (side walls and bottom surface) of the opening that reaches oxide 230b. Furthermore, insulator 250 is arranged to cover the inner walls of the opening via oxide 230c. Furthermore, conductor 260 is arranged to fill the opening via oxide 230c and insulator 250.

[0268] Next, heat treatment may be performed. In this embodiment, the treatment is performed at 400°C for one hour in a nitrogen atmosphere. This heat treatment can reduce the moisture concentration and hydrogen concentration in the insulators 250 and 280.

[0269] Next, insulator 282 is formed on oxide 230c, insulator 250, conductor 260, and insulator 280 (see Figures 11B to 11D). Insulator 282 can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. For example, an aluminum oxide film preferably formed by sputtering is preferable as insulator 282. By forming insulator 282 in an oxygen-containing atmosphere using sputtering, oxygen can be added to insulator 280 during film formation. In this case, it is preferable to form insulator 282 while the substrate is being heated. Furthermore, forming insulator 282 in contact with the top surface of conductor 260 is preferable because it prevents oxygen contained in insulator 280 from being absorbed by conductor 260 during the subsequent heat treatment.

[0270] Next, an insulator 283 is formed on the insulator 282 (see FIG. 11B to FIG. 11D ). The insulator 283 can be formed by sputtering, CVD, MBE, PLD, ALD, or the like. Silicon nitride or silicon oxynitride is preferably used as the insulator 283.

[0271] Next, heat treatment may be performed. In this embodiment, treatment is performed at 400°C for one hour in a nitrogen atmosphere. This heat treatment allows oxygen added during the formation of insulator 282 to diffuse into insulator 280 and be supplied to oxides 230a and 230b via oxide 230c. Note that this heat treatment can be performed not only after forming insulator 283 but also after forming insulator 282.

[0272] Next, the insulator 274 may be formed on the insulator 283. The insulator 274 may be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0273] Next, an insulator 281 may be formed on the insulator 274. The insulator 281 may be formed by sputtering, CVD, MBE, PLD, ALD, or the like. For example, a silicon nitride film is preferably formed by sputtering as the insulator 281.

[0274] Next, openings reaching the conductors 242a and 242b are formed in the insulators 254, 280, 282, 283, 274, and 281. Photolithography can be used to form these openings.

[0275] Next, an insulating film serving as insulator 241 (insulator 241a and insulator 241b) is formed and anisotropically etched to form insulator 241. This insulating film can be formed using methods such as sputtering, CVD, MBE, PLD, and ALD. It is preferable to use an insulating film that inhibits oxygen permeation as this insulating film. For example, silicon nitride is preferably formed using the PEALD method. Silicon nitride is preferred because it has high hydrogen barrier properties.

[0276] Furthermore, dry etching, for example, can be used for anisotropic etching of the insulating film that becomes insulator 241. Providing insulator 241 on the sidewalls of the opening suppresses the permeation of oxygen from the outside, thereby preventing oxidation of conductors 240a and 240b to be formed subsequently. Furthermore, impurities such as water and hydrogen can be prevented from diffusing from conductors 240a and 240b to the outside.

[0277] Next, a conductive film is formed to serve as the conductors 240a and 240b. This conductive film preferably has a stacked structure including a conductive material that inhibits the permeation of impurities such as water and hydrogen. For example, a stacked structure of tantalum nitride, titanium nitride, or the like with tungsten, molybdenum, copper, or the like can be used. This conductive film can be formed using sputtering, CVD, MBE, PLD, ALD, or the like.

[0278] Next, a CMP process is performed to remove a portion of the conductive film that will become the conductors 240a and 240b, exposing the insulator 281. As a result, the conductive film remains only in the opening, allowing the conductors 240a and 240b to have flat top surfaces (see FIG. 1A to FIG. 1D ). Note that the CMP process may also remove a portion of the insulator 281.

[0279] Next, a conductive film is formed to become the conductor 246. This conductive film can be formed by sputtering, CVD, MBE, PLD, ALD, or the like.

[0280] Next, the conductive film to be the conductor 246 is processed by photolithography to form a conductor 246a in contact with the top surface of the conductor 240a and a conductor 246b in contact with the top surface of the conductor 240b (see FIG. 1A to FIG. 1D ).

[0281] Through the above-described process, a semiconductor device including the transistor 200 shown in Figures 1A to 1D can be manufactured. As shown in Figures 4A to 11D, the transistor 200 can be manufactured by using the method for manufacturing a semiconductor device described in this embodiment.

[0282] <Modification Example of Semiconductor Device> An example of a semiconductor device according to one embodiment of the present invention will be described below with reference to FIG. 12A to FIG. 12D and FIG. 13A and FIG. 13B .

[0283] [Variation Example 1 of Semiconductor Device] FIG12A is a top view of the semiconductor device. FIG12B is a cross-sectional view taken along the dashed line A1-A2 in FIG12A. FIG12C is a cross-sectional view taken along the dashed line A3-A4 in FIG12A. FIG12D is a cross-sectional view taken along the dashed line A5-A6 in FIG12A. For clarity, some components are omitted from the top view of FIG12A.

[0284] Note that in the semiconductor devices shown in Figures 12A to 12D , components having the same functions as those in the semiconductor device described in "Structural Example of Semiconductor Device" are denoted by the same reference numerals. Note that the materials used to constitute the semiconductor devices in this section can also be those described in detail in "Structural Example of Semiconductor Device."

[0285] The semiconductor device shown in Figures 12A to 12D is a modified example of the semiconductor device shown in Figures 1A to 1D . The semiconductor device shown in Figures 12A to 12D differs from the semiconductor device shown in Figures 1A to 1D in the shape of insulator 283. Furthermore, the device includes oxide 243 (oxide 243a and oxide 243b). Figures 12A to 12D also illustrate that both oxide 230c and insulator 254 have a two-layer stacked structure.

[0286] In the semiconductor device shown in Figures 12A to 12D, insulators 214, 216, 222, 224, 254 (insulators 254a and 254b), 280, and 282 are patterned, and insulator 283 covers these insulators. Specifically, insulator 283 contacts the top and side surfaces of insulator 282, the side surfaces of insulator 280, the side surfaces of insulator 254, the side surfaces of insulator 224, the side surfaces of insulator 222, the side surfaces of insulator 216, the side surfaces of insulator 214, and the top surface of insulator 212. As a result, oxide 230, etc., insulators 214, insulator 216, insulator 222, insulator 224, insulator 254, insulator 280, and insulator 282 are shielded from the outside world by insulator 283 and insulator 212. In other words, the transistor 200 is disposed in a region sealed by the insulator 283 and the insulator 212.

[0287] Insulators 212 and 283 preferably have a high ability to inhibit the diffusion of hydrogen (e.g., at least one of hydrogen atoms and hydrogen molecules) or water molecules. For example, silicon nitride or silicon oxynitride, which have higher hydrogen barrier properties, is preferably used as insulators 212 and 283.

[0288] With the above structure, it is possible to suppress the hydrogen contained outside the above sealed area from mixing into the above sealed area.

[0289] 12A to 12D illustrate that insulators 212, 214, and 283 comprise a single layer, but the present invention is not limited thereto. For example, insulators 212, 214, and 283 may also comprise a stacked structure of two or more layers.

[0290] Furthermore, transistor 200 shown in Figures 12A to 12D includes oxide 243 (oxide 243a and oxide 243b) between conductor 242 (conductor 242a and conductor 242b) and oxide 230, which functions to inhibit oxygen permeation. Disposing oxide 243, which functions to inhibit oxygen permeation, between conductor 242 (which serves as a source or drain electrode) and oxide 230b is advantageous because it reduces the resistance between conductor 242 and oxide 230b. This structure improves the electrical characteristics and reliability of transistor 200.

[0291] A metal oxide containing element M can also be used as oxide 243. In particular, aluminum, gallium, yttrium, or tin can be used as element M. The concentration of element M in oxide 243 is preferably higher than that in oxide 230b. Gallium oxide can also be used as oxide 243. Alternatively, metal oxides such as In-M-Zn oxide can be used as oxide 243. Specifically, the atomic ratio of element M relative to In in the metal oxide used for oxide 243 is preferably greater than the atomic ratio of element M relative to In in the metal oxide used for oxide 230b. Furthermore, the thickness of oxide 243 is preferably 0.5 nm to 5 nm, more preferably 1 nm to 3 nm, and even more preferably 1 nm to 2 nm. Furthermore, oxide 243 is preferably crystalline. Crystalline oxide 243 can appropriately suppress the release of oxygen from oxide 230. For example, when oxide 243 has a hexagonal crystal structure, the release of oxygen from oxide 230 can sometimes be suppressed.

[0292] Note that in a cross-section of transistor 200 along the channel length, the bottom surface of oxide 230c in the region overlapping conductor 260 is preferably equal to or lower than the bottom surface of oxide 243 (oxide 243a and oxide 243b). This shape removes impurities near the interface between oxide 230b and oxide 230c, thereby reducing the low-resistance region formed near the top surface of region 234. For example, in a cross-section of transistor 200 along the channel length, the difference in height between the bottom surface of oxide 243 and the bottom surface of oxide 230c in the region overlapping conductor 260, relative to the bottom surface of insulator 224, is preferably 0 nm to 10 nm, preferably 0 nm to 5 nm, and more preferably 0 nm to 3 nm.

[0293] In addition, in the transistor 200 shown in FIG. 12A to FIG. 12D , the oxide 230c has a stacked structure of an oxide 230c1 and an oxide 230c2.

[0294] Oxide 230c2 preferably includes at least one of the metal elements that constitute the metal oxide used for oxide 230c1, and more preferably includes all of the aforementioned metal elements. For example, preferably, In-Ga-Zn oxide or In-Zn oxide is used as oxide 230c1, and In-Ga-Zn oxide, Ga-Zn oxide, or gallium oxide is used as oxide 230c2. This can reduce the defect state density at the interface between oxide 230c1 and oxide 230c2.

[0295] Preferably, the conduction band bottoms of oxides 230a and 230c2 are closer to the vacuum level than the conduction band bottoms of oxides 230b and 230c1. In other words, the electron affinities of oxides 230a and 230c2 are preferably lower than those of oxides 230b and 230c1. In this case, a metal oxide suitable for oxide 230a is preferably used for oxide 230c2, and a metal oxide suitable for oxide 230b is preferably used for oxide 230c1. In this case, in addition to oxide 230b, oxide 230c1 may also become a major carrier path. By using a metal oxide suitable for oxide 230b for oxide 230c1, an increase in the effective channel length at the top surface of the channel formation region can be suppressed, thereby preventing a decrease in the on-state current of transistor 200.

[0296] To be specific, as the oxide 230c1, a metal oxide with In:Ga:Zn=4:2:3 [atomic ratio] or In:Ga:Zn=5:1:6 [atomic ratio], or In-Zn oxide can be used, and as the oxide 230c2, a metal oxide with In:Ga:Zn=1:3:4 [atomic ratio], Ga:Zn=2:1 [atomic ratio], Ga:Zn=2:5 [atomic ratio] or gallium oxide can be used.

[0297] Furthermore, oxide 230c2 is preferably a metal oxide that suppresses oxygen diffusion or permeation more than oxide 230c1. Providing oxide 230c2 between insulator 250 and oxide 230c1 can suppress the diffusion of oxygen contained in insulator 280 into insulator 250. This allows oxygen to be efficiently supplied to oxide 230b via oxide 230c1.

[0298] Furthermore, by making the atomic ratio of In relative to the main metal element in the metal oxide used for oxide 230c2 smaller than the atomic ratio of In relative to the main metal element in the metal oxide used for oxide 230c1, diffusion of In into insulator 250 can be suppressed. Since insulator 250 functions as a gate insulator, infiltration of In into insulator 250 can lead to poor transistor characteristics. Therefore, by providing oxide 230c2 between oxide 230c1 and insulator 250, a highly reliable semiconductor device can be provided.

[0299] Note that the oxide 230c1 may be provided in each transistor 200. In other words, the oxide 230c1 of the transistor 200 may not contact the oxide 230c1 of the transistor 200 adjacent to the transistor 200. Furthermore, the oxide 230c1 of the transistor 200 may be separated from the oxide 230c1 of the transistor 200 adjacent to the transistor 200. In other words, the oxide 230c1 may not be disposed between the transistor 200 and the transistor 200 adjacent to the transistor 200.

[0300] When a semiconductor device having the above structure has multiple transistors 200 arranged in the channel width direction, oxide 230c is independently provided in each transistor 200. This prevents the generation of parasitic transistors between a transistor 200 and adjacent transistors 200, thereby suppressing the generation of the aforementioned leakage path. Consequently, a semiconductor device having excellent electrical characteristics and capable of miniaturization or high integration can be provided.

[0301] For example, when L1 represents the distance between the side edge of the oxide 230c1 of the transistor 200 and the side edge of the oxide 230c1 of the transistor 200 adjacent to the transistor 200, L1 is set to be greater than 0 nm. Furthermore, when L2 represents the distance between the side edge of the oxide 230a of the transistor 200 and the side edge of the oxide 230a of the transistor 200 adjacent to the transistor 200, the ratio of L1 to L2 (L1 / L2) is preferably greater than 0 and less than 1, more preferably 0.1 to 0.9, and even more preferably 0.2 to 0.8. Alternatively, L2 may be the distance between the side edge of the oxide 230b of the transistor 200 and the side edge of the oxide 230b of the transistor 200 adjacent to the transistor 200.

[0302] By reducing the ratio of L1 to L2 (L1 / L2), even if a misalignment occurs in a region between the transistor 200 and the transistor 200 adjacent to the transistor 200 where the oxide 230c1 is not provided, the oxide 230c1 of the transistor 200 and the oxide 230c1 of the transistor 200 adjacent to the transistor 200 can be separated.

[0303] Furthermore, by increasing the ratio of L1 to L2 (L1 / L2), even if the spacing between the transistor 200 and the transistor 200 adjacent to the transistor 200 is reduced, the minimum feature size can be ensured, thereby further miniaturizing or increasing the integration of the semiconductor device.

[0304] Note that the conductor 260, insulator 250, and oxide 230c2 are all shared between adjacent transistors 200. In other words, the conductor 260 of a transistor 200 has a region where it is continuously provided with the conductor 260 of a transistor 200 adjacent to that transistor 200. Furthermore, the insulator 250 of a transistor 200 has a region where it is continuously provided with the insulator 250 of a transistor 200 adjacent to that transistor 200. Furthermore, the oxide 230c2 of a transistor 200 has a region where it is continuously provided with the oxide 230c2 of a transistor 200 adjacent to that transistor 200.

[0305] Furthermore, by adopting the above structure, the oxide 230c2 has a region in contact with the insulator 224 between the transistor 200 and the transistor 200 adjacent to the transistor 200.

[0306] In addition, similar to the oxide 230c1, the oxide 230c2 of the transistor 200 can also be separated from the oxide 230c2 of the transistor 200 adjacent to the transistor 200. In this case, the insulator 250 has a region in contact with the insulator 224 between the transistor 200 and the transistor 200 adjacent to the transistor 200.

[0307] In transistor 200 shown in FIG. 12A to FIG. 12D , insulator 254 has a structure in which insulators 254 a and 254 b are stacked. Note that for descriptions of the materials and formation methods of insulators 254 a and 254 b , refer to the descriptions of the lower layer of insulator 254 and the upper layer of insulator 254 described in <Detailed Structure of Semiconductor Device>.

[0308] Alternatively, an insulator serving as a barrier layer may be provided between the top surface of conductor 242 and insulator 280, rather than insulator 254. This structure prevents conductor 242 from absorbing excess oxygen contained in insulator 280. Furthermore, by suppressing oxidation of conductor 242, an increase in contact resistance between transistor 200 and wiring can be suppressed. Consequently, transistor 200 can have excellent electrical characteristics and reliability.

[0309] Therefore, the insulator preferably has a function of suppressing the diffusion of oxygen. For example, the insulator preferably has a higher function of suppressing the diffusion of oxygen than the insulator 280.

[0310] The above-mentioned insulator can be formed, for example, from an oxide of one or both of aluminum and hafnium. In particular, aluminum oxide is preferably deposited using the ALD method. ALD deposition allows for the formation of a dense film with few defects such as cracks and pinholes and a uniform thickness. Alternatively, an insulator composed of aluminum nitride can be used.

[0311] [Variation Example 2 of Semiconductor Device] FIG13A and FIG13B illustrate a structure in which multiple transistors (transistors 200_1 through 200_n) are surrounded and sealed by insulators 283 and 212. Note that in FIG13A and FIG13B , transistors 200_1 through 200_n are arranged along the channel length, but this is not limiting. Transistors 200_1 through 200_n may also be arranged along the channel width, arranged in a matrix, or arranged in a random pattern.

[0312] As shown in Figure 13A, a portion (hereinafter sometimes referred to as a sealing portion 265) where insulator 283 contacts insulator 212 is formed outside multiple transistors (transistors 200_1 through 200_n). Sealing portion 265 is formed to surround the multiple transistors (also referred to as a transistor group). This structure allows the multiple transistors to be surrounded by insulators 283 and 212. In other words, the four sides and top of the multiple transistors can be surrounded by insulators 283 and 281, while the bottom of the multiple transistors can be surrounded by insulator 212. In this way, the multiple transistor groups surrounded by sealing portion 265 are provided on the substrate.

[0313] Here, the distance between the sealing portion 265 and the oxide 230 closest to the sealing portion 265 is preferably short. For example, the distance between the sealing portion 265 and the oxide 230 closest to the sealing portion 265 is preferably 1 μm or less, and more preferably 500 nm or less. By adopting this structure, the volume of the insulator 280 sealed by the insulator 283 and the like can be reduced, thereby reducing the amount of hydrogen contained in the insulator 280.

[0314] In addition, a cutting line (sometimes also referred to as a dividing line, a separation line, or a cutting line) may be provided so as to overlap with the sealing portion 265. The substrate is separated along the cutting line, and the transistor group surrounded by the sealing portion 265 is taken out as a single wafer.

[0315] FIG13A shows an example where multiple transistors (transistors 200_1 through 200_n) are surrounded by a single sealing portion 265, but the present invention is not limited thereto. As shown in FIG13B , multiple transistors (transistors 200_1 through 200_n) may also be surrounded by multiple sealing portions. In FIG13B , the multiple transistors are surrounded by sealing portion 265a and also by outer sealing portion 265b.

[0316] In this way, by surrounding the multiple transistors (transistors 200_1 to 200_n) with multiple sealing portions, the contact area between the insulator 283 and the insulator 212 increases, thereby further improving the adhesion between the insulator 283 and the insulator 212. This allows the multiple transistors to be more securely sealed.

[0317] At this time, the cutting line may be provided so as to overlap with the sealing portion 265a or the sealing portion 265b or the cutting line may be provided between the sealing portion 265a and the sealing portion 265b.

[0318] Note that insulator 212 shown in FIG13A and FIG13B has a structure in which a lower layer of insulator 212 and an upper layer of insulator 212 are stacked. For example, silicon nitride is deposited as the lower layer of insulator 212 using PECVD, and silicon nitride is deposited as the upper layer of insulator 212 using sputtering. This allows the lower layer of insulator 212 to be formed faster than the upper layer of insulator 212, thereby improving productivity. Furthermore, the upper layer of insulator 212, which is closer to oxide 230 than the lower layer of insulator 212, has a lower hydrogen concentration than the lower layer of insulator 212. Thus, by using an insulator 212 that is not easily permeable to impurities such as water and hydrogen, such as silicon nitride, diffusion of impurities such as water and hydrogen from the lower layer (not shown) of insulator 212 can be suppressed. Furthermore, by using an insulator such as silicon nitride, which is not easily permeable to copper, as the insulator 212, even if a metal such as copper that easily diffuses is used as the conductor under the insulator 212, diffusion of the metal through the insulator 212 to the upper side can be suppressed.

[0319] Note that the structure is not limited to the above, and a single-layer structure may be employed in which either the lower layer of the insulator 212 or the upper layer of the insulator 212 is provided. Furthermore, although the structure in which the insulator 214 is provided is employed in FIG13A and FIG13B , the present invention is not limited to this, and a structure in which the insulator 214 is not provided may also be employed.

[0320] According to one embodiment of the present invention, a semiconductor device with low variation in transistor characteristics can be provided. According to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. According to one embodiment of the present invention, a semiconductor device with excellent electrical characteristics can be provided. According to one embodiment of the present invention, a semiconductor device that can achieve miniaturization or high integration can be provided. According to one embodiment of the present invention, a semiconductor device with excellent reliability can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided.

[0321] As described above, the structures, methods, etc. described in this embodiment mode can be implemented in combination with the structures, methods, etc. described in other embodiments and examples as appropriate.

[0322] Implementation Method 2 In this embodiment, one embodiment of a semiconductor device is described with reference to FIG. 14 and FIG. 15 .

[0323] [Memory device 1] FIG14 illustrates an example of a semiconductor device (memory device) using a semiconductor device according to one embodiment of the present invention. In the semiconductor device according to one embodiment of the present invention, transistor 200 is provided above transistor 300, and capacitor 100 is provided above transistor 300 and transistor 200. Furthermore, transistor 200 described in the above embodiment can be used as transistor 200. Therefore, reference can be made to the description of the above embodiment regarding transistor 200 and the layers including transistor 200.

[0324] Transistor 200 is a transistor whose channel is formed in a semiconductor layer containing an oxide semiconductor. Because transistor 200 has a low off-state current, its use in a memory device allows for long-term retention of stored data. In other words, since refresh operations are unnecessary or performed at an extremely low frequency, the memory device's power consumption can be significantly reduced.

[0325] In the semiconductor device shown in FIG14 , wiring 1001 is electrically connected to the source of transistor 300, and wiring 1002 is electrically connected to the drain of transistor 300. Furthermore, wiring 1003 is electrically connected to one of the source and drain of transistor 200, wiring 1004 is electrically connected to the first gate of transistor 200, and wiring 1006 is electrically connected to the second gate of transistor 200. Furthermore, the gate of transistor 300 and the other of the source and drain of transistor 200 are electrically connected to one electrode of capacitor 100, and wiring 1005 is electrically connected to the other electrode of capacitor 100.

[0326] Furthermore, by arranging the memory devices shown in FIG. 14 in a matrix, a memory cell array can be formed.

[0327] <Transistor 300> Transistor 300 is disposed on substrate 311 and includes a conductor 316 serving as a gate, an insulator 315 serving as a gate insulator, a semiconductor region 313 formed as a portion of substrate 311, and low-resistance regions 314a and 314b serving as source and drain regions. Transistor 300 can be either a p-channel or n-channel type.

[0328] In transistor 300 shown in FIG14 , semiconductor region 313 (a portion of substrate 311) forming the channel has a convex shape. Furthermore, conductor 316 is provided to cover the side and top surfaces of semiconductor region 313 via insulator 315. Conductor 316 can be made of a material that adjusts the work function. Because it utilizes a convex portion of the semiconductor substrate, this type of transistor 300 is also called a FIN-type transistor. Alternatively, an insulator may be provided in contact with the top surface of the convex portion to form a mask for the convex portion. While this example illustrates the convex portion being formed by processing a portion of the semiconductor substrate, a semiconductor film having a convex portion can also be formed by processing an SOI substrate.

[0329] Note that the structure of the transistor 300 shown in FIG14 is only an example and is not limited to the above structure. An appropriate transistor can be used according to the circuit structure or driving method.

[0330] <Capacitor 100> The capacitor 100 is disposed above the transistor 200. The capacitor 100 includes a conductor 110 serving as a first electrode, a conductor 120 serving as a second electrode, and an insulator 130 serving as a dielectric.

[0331] Furthermore, for example, the conductor 112 provided on the conductor 240 may be formed simultaneously with the conductor 110. The conductor 112 serves as a plug or wiring for electrically connecting the capacitor 100, the transistor 200, or the transistor 300.

[0332] In FIG14 , conductors 112 and 110 have a single-layer structure, but this is not limiting and may also have a stacked structure of two or more layers. For example, a conductor having high contact with the barrier conductor and the highly conductive conductor may be formed between the barrier conductor and the highly conductive conductor.

[0333] In addition, the insulator 130 can be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, or the like, and can be provided in a stacked layer or a single layer.

[0334] For example, insulator 130 preferably has a laminated structure using a material with a high dielectric strength, such as silicon oxynitride, and a high-k dielectric material. By adopting this structure, capacitor 100 can include a high-k dielectric to ensure sufficient capacitance, and an insulator with a high dielectric strength to improve dielectric strength, thereby suppressing electrostatic damage to capacitor 100.

[0335] Note that insulators that are high-k materials (materials with a high relative dielectric constant) include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0336] On the other hand, materials with high dielectric strength (materials with low relative dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon and nitrogen-doped silicon oxide, porous silicon oxide, and resins.

[0337] <Wiring Layer> A wiring layer, including interlayer films, wiring, and plugs, may be provided between the various structures. Furthermore, the wiring layer may be provided in multiple layers depending on the design. Here, in the case of a conductor that functions as a plug or a wiring, the same reference numeral may be used to represent multiple structures. Furthermore, in this specification and other text, a wiring and a plug electrically connected to the wiring may be considered a single component. This means that a portion of a conductor may function as wiring, and a portion of the conductor may function as a plug.

[0338] For example, on transistor 300, insulators 320, 322, 324, and 326 are stacked in this order as interlayer films. Furthermore, conductors 328 and 330, which are electrically connected to capacitor 100 and transistor 200, are embedded in insulators 320, 322, 324, and 326. Conductors 328 and 330 serve as plugs or wiring.

[0339] Furthermore, the insulator used as an interlayer film can also be used as a planarization film to cover the uneven surface underneath. For example, to improve the flatness of the top surface of the insulator 322, a planarization process such as chemical mechanical polishing (CMP) can be used to achieve planarization.

[0340] A wiring layer may be provided on insulator 326 and conductor 330. For example, in FIG14 , insulator 350, insulator 352, and insulator 354 are stacked in this order. Furthermore, conductor 356 is formed between insulator 350, insulator 352, and insulator 354. Conductor 356 serves as a plug or wiring.

[0341] Similarly, insulators 210, 212, 214, and 216 are filled with conductors 218 and the conductors (conductors 205) that constitute transistor 200. Conductor 218 serves as a plug or wiring for electrically connecting capacitor 100 or transistor 300. Furthermore, insulator 150 is provided on conductors 120 and insulator 130.

[0342] Here, similar to the insulator 241 shown in the previous embodiment, insulator 217 is provided so as to contact the side surface of conductor 218, which serves as a plug. Insulator 217 is provided so as to contact the inner walls of the openings formed in insulators 210, 212, 214, and 216. In other words, insulator 217 is provided between conductor 218 and insulators 210, 212, 214, and 216. Note that since conductor 205 can be formed parallel to conductor 218, insulator 217 may be provided so as to contact the side surface of conductor 205.

[0343] Insulator 217 can be made of, for example, silicon nitride, aluminum oxide, or silicon oxynitride. Since insulator 217 is provided in contact with insulators 210, 212, 214, 216, and 222, it can prevent impurities such as water and hydrogen contained in insulators 210 and 216 from entering oxide 230 via conductor 218. Silicon nitride is particularly preferred because of its high barrier properties to hydrogen. Furthermore, it can prevent oxygen contained in insulators 210 and 216 from being absorbed by conductor 218.

[0344] The insulator 217 can be formed by the same method as the insulator 241. For example, a silicon nitride film can be formed by PEALD, and an opening reaching the conductor 356 can be formed by anisotropic etching.

[0345] Insulators that can be used as interlayer films include insulating oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, metal oxynitrides, and the like.

[0346] For example, using a material with a low relative dielectric constant for an insulator used as an interlayer film can reduce parasitic capacitance generated between wirings. Therefore, it is best to select the material based on the function of the insulator.

[0347] For example, insulators 150, 210, 352, and 354 are preferably insulators with a low relative dielectric constant. For example, the insulator preferably contains silicon oxynitride, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon and nitrogen-doped silicon oxide, silicon oxide with pores, or a resin. Alternatively, the insulator preferably has a laminated structure comprising silicon oxide, silicon oxynitride, silicon oxynitride, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon and nitrogen-doped silicon oxide, or silicon oxide with pores, and a resin. Because silicon oxide and silicon oxynitride are thermally stable, combining them with a resin can achieve a thermally stable laminated structure with a low relative dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (nylon, aromatic polyamide, etc.), polyimide, polycarbonate, and acrylic.

[0348] Furthermore, by surrounding a transistor using an oxide semiconductor with an insulator that inhibits the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. Therefore, insulators that inhibit the permeation of impurities such as hydrogen and oxygen can be used as insulators 214, 212, and 350.

[0349] As insulators that inhibit the permeation of impurities such as hydrogen and oxygen, for example, insulators containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum can be used in a single layer or a stacked layer. Specifically, as insulators that inhibit the permeation of impurities such as hydrogen and oxygen, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, silicon oxynitride, and silicon nitride can be used.

[0350] Conductors suitable for wiring and plugs are preferably materials containing one or more metal elements selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, and ruthenium. Furthermore, highly conductive semiconductors, such as polycrystalline silicon containing impurity elements such as phosphorus, and silicides such as nickel silicide may also be used.

[0351] For example, conductors 328, 330, 356, 218, and 112 can be formed using conductive materials such as metals, alloys, metal nitrides, and metal oxides, formed from the aforementioned materials, either as a single layer or in a stacked layer. High-melting-point materials such as tungsten or molybdenum, which offer both heat resistance and electrical conductivity, are preferably used, with tungsten being particularly preferred. Alternatively, low-resistance conductive materials such as aluminum and copper are preferably used. Using low-resistance conductive materials can reduce wiring resistance.

[0352] <Wiring or Plug Provided with an Oxide Semiconductor Layer> Note that when an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided near the oxide semiconductor. In this case, it is preferable to provide an insulator having a barrier property between the insulator having the excess oxygen region and the conductor provided within the insulator having the excess oxygen region.

[0353] For example, in FIG14 , insulator 241 is preferably provided between insulator 224 and insulator 280, which contain excess oxygen, and conductor 240. By providing insulator 241 in contact with insulators 222 and 254, insulator 224 and transistor 200 can be sealed by a barrier insulator. Furthermore, insulator 241 is preferably in contact with a portion of insulator 280. Extending insulator 241 to insulator 274 further suppresses the diffusion of oxygen and impurities.

[0354] In other words, the provision of the insulator 241 can prevent excess oxygen contained in the insulators 224 and 280 from being absorbed by the conductor 240. Furthermore, the provision of the insulator 241 can prevent hydrogen, an impurity, from diffusing through the conductor 240 into the transistor 200.

[0355] Furthermore, as insulator 241, it is preferable to use an insulating material that has the function of inhibiting the diffusion of impurities such as water and hydrogen, as well as oxygen. For example, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, etc. are preferably used. Silicon nitride is particularly preferred due to its high barrier properties to hydrogen. Alternatively, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide may be used.

[0356] The above describes an example structure. By adopting this structure, semiconductor devices using transistors containing oxide semiconductors can suppress variations in electrical characteristics while improving reliability. Furthermore, a transistor containing an oxide semiconductor with high on-state current can be provided. Furthermore, a transistor containing an oxide semiconductor with low off-state current can be provided. Furthermore, a semiconductor device with reduced power consumption can be provided.

[0357] [Memory device 2] FIG15 shows an example of a memory device using the semiconductor device according to one embodiment of the present invention. The memory device shown in FIG15 includes a transistor 400 in addition to the semiconductor device including the transistor 200, the transistor 300, and the capacitor 100 shown in FIG14.

[0358] Transistor 400 can control the second gate voltage of transistor 200. For example, a structure is employed in which the first and second gates of transistor 400 are connected to a source diode, and the source of transistor 400 is connected to the second gate of transistor 200. In this structure, when the second gate of transistor 200 is held at a negative potential, the voltage between the first gate and source, and the voltage between the second gate and source, of transistor 400 are both 0V. In transistor 400, since the drain current is very low when the second gate voltage and the first gate voltage are 0V, the negative potential of the second gate of transistor 200 can be maintained for a long period of time, even when power is not supplied to transistors 200 and 400. Consequently, a memory device including transistors 200 and 400 can retain stored data for a long period of time.

[0359] Therefore, in FIG15 , wiring 1001 is electrically connected to the source of transistor 300, and wiring 1002 is electrically connected to the drain of transistor 300. Furthermore, wiring 1003 is electrically connected to one of the source and drain of transistor 200, wiring 1004 is electrically connected to the gate of transistor 200, and wiring 1006 is electrically connected to the second gate of transistor 200. Furthermore, the gate of transistor 300 and the other of the source and drain of transistor 200 are electrically connected to one electrode of capacitor 100, and wiring 1005 is electrically connected to the other electrode of capacitor 100. Wiring 1007 is electrically connected to the source of transistor 400, wiring 1008 is electrically connected to the gate of transistor 400, wiring 1009 is electrically connected to the second gate of transistor 400, and wiring 1010 is electrically connected to the drain of transistor 400. Here, wiring 1006, wiring 1007, wiring 1008, and wiring 1009 are electrically connected.

[0360] Furthermore, by arranging the memory device shown in FIG15 in a matrix similar to the memory device shown in FIG14 , a memory cell array can be formed. Note that one transistor 400 can control the second gate voltages of multiple transistors 200. Therefore, it is preferable to have fewer transistors 400 than transistors 200.

[0361] <Transistor 400> Transistor 400 is formed on the same layer as transistor 200, allowing them to be manufactured simultaneously. Transistor 400 includes: conductor 460 (conductor 460a and conductor 460b) serving as a first gate; conductor 405 serving as a second gate; insulators 222, 224, and 450 serving as gate insulating layers; oxide 430c comprising a channel formation region; conductor 442a, oxide 431a, and oxide 431b serving as a source; conductor 442b, oxide 432a, and oxide 432b serving as a drain; conductor 440 (conductor 440a and conductor 440b) serving as a plug; and insulator 441 (insulator 441a and insulator 441b) serving as a blocking insulating film for conductor 440.

[0362] Conductor 405 is formed in the same layer as conductor 205. Oxide 431a and oxide 432a are formed in the same layer as oxide 230a, and oxide 431b and oxide 432b are formed in the same layer as oxide 230b. Conductors 442a and 442b are formed in the same layer as conductor 242. Oxide 430c is formed in the same layer as oxide 230c. Insulator 450 is formed in the same layer as insulator 250. Conductor 460 is formed in the same layer as conductor 260. Conductor 440 is formed in the same layer as conductor 240. Insulator 441 is formed in the same layer as insulator 241.

[0363] Note that structures formed in the same layer can be formed simultaneously. For example, the oxide 430c can be formed by processing an oxide film that becomes the oxide 230c.

[0364] Similar to oxide 230 and the like, oxygen vacancies and impurities such as hydrogen and water are reduced in oxide 430c, which serves as the active layer of transistor 400. Therefore, the threshold voltage of transistor 400 can be increased, the off-state current can be reduced, and the drain current can be made very small when the second gate voltage and the first gate voltage are 0V.

[0365] <cutting line> The following describes the dicing lines (also called dividing lines, separation lines, or cut lines) used when dividing a large-area substrate into individual semiconductor elements to produce multiple wafer-shaped semiconductor devices. For example, in some cases, the substrate is first formed with grooves (dicing lines) to separate the semiconductor elements. The substrate is then cut along the dicing lines to produce multiple separated (divided) semiconductor devices.

[0366] Here, for example, as shown in FIG15 , it is preferable to design the insulator 254 so that the area in contact with the insulator 222 forms a cut line. Specifically, an opening is provided in the insulator 224 near the area forming the cut line, which is located at the edge of the memory cell including the plurality of transistors 200 and the transistor 400. Furthermore, the insulator 254 is provided so as to cover the side surfaces of the insulator 224.

[0367] That is, insulator 222 and insulator 254 are in contact within the opening provided in insulator 224. For example, insulator 222 and insulator 254 can be formed using the same material and method. Using the same material and method to form insulator 222 and insulator 254 improves adhesion. For example, aluminum oxide is preferably used.

[0368] By adopting this structure, insulator 222 and insulator 254 can surround insulator 224, transistor 200, and transistor 400. Since insulator 222 and insulator 254 have the function of suppressing the diffusion of oxygen, hydrogen, and water, even if the substrate is divided into multiple wafers after forming a circuit region of a semiconductor element as described in this embodiment, impurities such as hydrogen and water can be prevented from entering from the side surfaces of the divided substrates and diffusing into transistor 200 or transistor 400.

[0369] This structure prevents excess oxygen in insulator 224 from diffusing to the outside through insulator 254 and insulator 222. Consequently, excess oxygen in insulator 224 is efficiently supplied to the oxide forming the channel in transistor 200 or transistor 400. This oxygen reduces oxygen vacancies in the oxide forming the channel in transistor 200 or transistor 400. Consequently, the oxide forming the channel in transistor 200 or transistor 400 can be made into an oxide semiconductor with a low defect state density and stable characteristics. This means that fluctuations in the electrical characteristics of transistor 200 or transistor 400 can be suppressed while improving reliability.

[0370] The configuration, method, and the like described in this embodiment mode can be implemented in combination with the configuration, structure, method, and the like described in other embodiments and examples as appropriate.

[0371] Implementation 3 In this embodiment, a memory device (hereinafter referred to as an OS memory device) using a transistor using an oxide as a semiconductor (hereinafter sometimes referred to as an OS transistor) and a capacitor (hereinafter sometimes referred to as an OS memory device) according to one embodiment of the present invention is described with reference to Figures 16A and 16B and Figures 17A to 17H. An OS memory device includes at least a capacitor and an OS transistor that controls the charging and discharging of the capacitor. Because the off-state current of the OS transistor is extremely low, the OS memory device has excellent retention characteristics, making it suitable for use as non-volatile memory.

[0372] <Memory Device Configuration Example> 16A shows an example of the structure of an OS memory device. Memory device 1400 includes peripheral circuits 1411 and a memory cell array 1470. Peripheral circuits 1411 include row circuits 1420, column circuits 1430, output circuits 1440, and control logic circuits 1460.

[0373] Column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, and a write circuit. The precharge circuit precharges the wiring. The sense amplifier amplifies the data signal read from the memory cell. Note that the wiring described above is connected to the memory cells included in memory cell array 1470, and details are described below. The amplified data signal is output as data signal RDATA to the outside of memory device 1400 via output circuit 1440. Furthermore, row circuit 1420 includes, for example, a row decoder and a word line driver circuit, and selects the row to be accessed.

[0374] The memory device 1400 is externally supplied with a low power supply voltage (VSS) as a power supply voltage, a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470. Furthermore, control signals (CE, WE, RE), an address signal ADDR, and a data signal WDATA are externally input to the memory device 1400. The address signal ADDR is input to the row decoder and the column decoder, and the data signal WDATA is input to the write circuit.

[0375] Control logic circuit 1460 processes external control signals (CE, WE, RE) to generate control signals for the row and column decoders. Control signal CE is the chip enable signal, control signal WE is the write enable signal, and control signal RE is the read enable signal. The signals processed by control logic circuit 1460 are not limited to these; other control signals may be input as needed.

[0376] Memory cell array 1470 includes a plurality of memory cells MC arranged in rows and columns and a plurality of wirings. Note that the number of wirings connecting memory cell array 1470 and row circuit 1420 depends on the structure of the memory cell MCs, the number of memory cells MCs included in a column, and other factors. Furthermore, the number of wirings connecting memory cell array 1470 and column circuit 1430 depends on the structure of the memory cell MCs, the number of memory cells MCs included in a row, and other factors.

[0377] Although FIG16A shows an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane, this embodiment is not limited to this. For example, as shown in FIG16B , the memory cell array 1470 may be provided so as to overlap a portion of the peripheral circuit 1411. For example, a sense amplifier may be provided so as to overlap below the memory cell array 1470.

[0378] 17A to 17H illustrate an example of a structure of a memory cell that can be applied to the memory cell MC described above.

[0379] [DOSRAM] Figures 17A to 17C illustrate circuit configuration examples of DRAM memory cells. In this specification and other publications, DRAM using a 10S transistor-capacitor memory cell is sometimes referred to as DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). The memory cell 1471 shown in Figure 17A includes a transistor M1 and a capacitor CA. Furthermore, transistor M1 includes a gate (sometimes called a top gate) and a back gate.

[0380] The first terminal of transistor M1 is connected to the first terminal of capacitor CA, the second terminal of transistor M1 is connected to wiring BIL, the gate of transistor M1 is connected to wiring WOL, and the back gate of transistor M1 is connected to wiring BGL. The second terminal of capacitor CA is connected to wiring CAL.

[0381] Wiring BIL serves as a bit line, and wiring WOL serves as a word line. Wiring CAL is used to apply a specified potential to the second terminal of capacitor CA. When writing or reading data, a low potential is preferably applied to wiring CAL. Wiring BGL is used to apply a potential to the back gate of transistor M1. By applying a desired potential to wiring BGL, the threshold voltage of transistor M1 can be increased or decreased.

[0382] Here, memory cell 1471 shown in FIG17A corresponds to the memory device shown in FIG14 . That is, transistor M1 corresponds to transistor 200, capacitor CA corresponds to capacitor 100, wiring BIL corresponds to wiring 1003, wiring WOL corresponds to wiring 1004, wiring BGL corresponds to wiring 1006, and wiring CAL corresponds to wiring 1005. Note that transistor 300 shown in FIG14 corresponds to a transistor provided in peripheral circuit 1411 of memory device 1400 shown in FIG16B .

[0383] Furthermore, memory cell MC is not limited to memory cell 1471; its circuit structure can be varied. For example, memory cell MC can also employ a structure in which the back gate of transistor M1 is connected to wiring WOL instead of wiring BGL, as in memory cell 1472 shown in FIG17B . Furthermore, memory cell MC can also employ a structure in which, for example, the back gate of transistor M1 is connected to wiring WOL, as in memory cell 1473 shown in FIG17C , a single-gate transistor, that is, a transistor M1 that does not include a back gate.

[0384] When the semiconductor device described in the above embodiment is used in memory cell 1471 or the like, transistor 200 can be used as transistor M1, and capacitor 100 can be used as capacitor CA. Using an OS transistor as transistor M1 allows for extremely low leakage current in transistor M1. In other words, because transistor M1 can retain written data for a long time, the frequency of memory cell refreshes can be reduced. Furthermore, memory cell refreshes can be eliminated. Furthermore, due to the extremely low leakage current, multi-valued data or analog data can be retained in memory cells 1471, 1472, and 1473.

[0385] Furthermore, in DOSRAM, when a sense amplifier is provided so as to overlap below the memory cell array 1470 as described above, the bit line can be shortened. This reduces the bit line capacitance, thereby reducing the storage capacitance of the memory cell.

[0386] [NOSRAM] Figures 17D to 17G illustrate an example circuit structure of a two-transistor, one-capacitor gain-unit memory cell. Memory cell 1474 shown in Figure 17D includes transistor M2, transistor M3, and capacitor CB. Transistor M2 also includes a top gate (sometimes simply referred to as a gate) and a back gate. In this specification and other documents, a memory device including a gain-unit memory cell that uses an OS transistor for transistor M2 is sometimes referred to as a NOSRAM (Nonvolatile Oxide Semiconductor RAM).

[0387] The first terminal of transistor M2 is connected to the first terminal of capacitor CB, the second terminal of transistor M2 is connected to wiring WBL, the gate of transistor M2 is connected to wiring WOL, and the back gate of transistor M2 is connected to wiring BGL. The second terminal of capacitor CB is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring RBL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M3 is connected to the first terminal of capacitor CB.

[0388] Wiring WBL serves as a write bit line, wiring RBL serves as a read bit line, and wiring WOL serves as a word line. Wiring CAL is used to apply a specified potential to the second terminal of capacitor CB. When writing, retaining, and reading data, a low potential is preferably applied to wiring CAL. Wiring BGL is used to apply a potential to the back gate of transistor M2. By applying any potential to wiring BGL, the threshold voltage of transistor M2 can be increased or decreased.

[0389] Here, memory cell 1474 shown in FIG17D corresponds to the memory device shown in FIG14 . That is, transistor M2 corresponds to transistor 200 , capacitor CB corresponds to capacitor 100 , transistor M3 corresponds to transistor 300 , wiring WBL corresponds to wiring 1003 , wiring WOL corresponds to wiring 1004 , wiring BGL corresponds to wiring 1006 , wiring CAL corresponds to wiring 1005 , wiring RBL corresponds to wiring 1002 , and wiring SL corresponds to wiring 1001 .

[0390] Furthermore, memory cell MC is not limited to memory cell 1474; its circuit structure can be modified as appropriate. For example, memory cell MC can also adopt a structure in which the back gate of transistor M2 is not connected to wiring BGL but to wiring WOL, as in memory cell 1475 shown in FIG17E . Alternatively, memory cell MC can also be a memory cell composed of a single-gate transistor, i.e., a transistor M2 that does not include a back gate, as in memory cell 1476 shown in FIG17F . Furthermore, memory cell MC can also have a structure in which wiring WBL and wiring RBL are combined into a single wiring BIL, as in memory cell 1477 shown in FIG17G .

[0391] When the semiconductor device described in the above embodiment is used in memory cell 1474 or the like, transistor 200 can be used as transistor M2, transistor 300 can be used as transistor M3, and capacitor 100 can be used as capacitor CB. Using an OS transistor as transistor M2 allows for extremely low leakage current in transistor M2. This allows transistor M2 to retain written data for a long period of time, reducing the frequency of memory cell refreshes. Furthermore, memory cell refreshes can be eliminated. Furthermore, due to the extremely low leakage current, multi-valued data or analog data can be retained in memory cell 1474. The same applies to memory cells 1475 through 1477.

[0392] Alternatively, transistor M3 may be a transistor containing silicon in the channel formation region (hereinafter sometimes referred to as a Si transistor). Si transistors can have either an n-channel or p-channel conductivity type. Si transistors sometimes have higher field-effect mobility than OS transistors. Therefore, a Si transistor may be used as the readout transistor for transistor M3. Furthermore, by using a Si transistor for transistor M3, transistor M2 can be stacked on top of transistor M3, thereby reducing the area occupied by the memory cell and enabling higher integration of the memory device.

[0393] Alternatively, transistor M3 may be an OS transistor. When OS transistors are used for transistors M2 and M3, only n-type transistors may be used to form a circuit in memory cell array 1470.

[0394] FIG17H shows an example of a gain unit-type memory cell with three transistors and one capacitor. Memory cell 1478 shown in FIG17H includes transistors M4 to M6 and capacitor CC. Capacitor CC can be provided as needed. Memory cell 1478 is electrically connected to wiring BIL, wiring RWL, wiring WWL, wiring BGL, and wiring GNDL. Wiring GNDL is a wiring that supplies a low-level potential. Alternatively, memory cell 1478 can be electrically connected to wiring RBL and wiring WBL without being electrically connected to wiring BIL.

[0395] The transistor M4 is an OS transistor including a back gate, which is electrically connected to the wiring BGL. Alternatively, the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 may not include a back gate.

[0396] Alternatively, transistors M5 and M6 can each be an n-channel Si transistor or a p-channel Si transistor. Alternatively, transistors M4 through M6 can all be OS transistors. In this case, only n-type transistors can be used to construct the circuit in memory cell array 1470.

[0397] When the semiconductor device described in the above embodiment is used in the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistor M5 and the transistor M6, and the capacitor 100 can be used as the capacitor CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made extremely low.

[0398] Note that the structures of the peripheral circuit 1411, memory cell array 1470, and the like described in this embodiment are not limited to those described above. The configuration or function of these circuits, wiring connected to these circuits, circuit elements, and the like may be changed, removed, or added as needed.

[0399] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and examples as appropriate.

[0400] Implementation 4 In this embodiment mode, an example of a wafer 1200 on which a semiconductor device of the present invention is mounted is described with reference to FIG18A and FIG18B. Multiple circuits (systems) are mounted on wafer 1200. This technology of integrating multiple circuits (systems) on a single wafer is sometimes referred to as a system on a chip (SoC).

[0401] As shown in FIG18A , the chip 1200 includes a CPU 1211 , a GPU 1212 , one or more computing units 1213 , one or more memory controllers 1214 , one or more interfaces 1215 , one or more network circuits 1216 , and the like.

[0402] Chip 1200 is provided with bumps (not shown), which, as shown in FIG18B , are connected to the first surface of a printed circuit board (PCB) 1201. Furthermore, a plurality of bumps 1202 are provided on the back side of the first surface of PCB 1201, which are connected to a motherboard 1203.

[0403] Alternatively, a memory device such as a DRAM 1221 or a flash memory 1222 may be provided on the motherboard 1203. For example, the DOS RAM described in the above embodiment may be applied to the DRAM 1221. Alternatively, the NOS RAM described in the above embodiment may be applied to the flash memory 1222.

[0404] CPU 1211 preferably has multiple CPU cores. Furthermore, GPU 1212 preferably has multiple GPU cores. Furthermore, CPU 1211 and GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory shared by CPU 1211 and GPU 1212 may be provided on chip 1200. The aforementioned NOSRAM or DOSRAM may be used for this memory. Furthermore, GPU 1212 is suitable for parallel computing of multiple data, and can be used for image processing or sum-of-product operations. By providing an image processing circuit or sum-of-product operation circuit using the oxide semiconductor of the present invention as GPU 1212, image processing and sum-of-product operations can be performed with low power consumption.

[0405] In addition, because the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened, and data can be transferred from the CPU 1211 to the GPU 1212, data can be transferred between the memories of the CPU 1211 and the GPU 1212, and the calculation results can be transferred from the GPU 1212 to the CPU 1211 after the calculation in the GPU 1212 is completed at high speed.

[0406] The analog operation unit 1213 includes one or both of an analog / digital (A / D) conversion circuit and a digital / analog (D / A) conversion circuit. Furthermore, the aforementioned product-sum operation circuit may also be provided in the analog operation unit 1213.

[0407] The memory controller 1214 includes a circuit serving as a controller for the DRAM 1221 and a circuit serving as an interface for the flash memory 1222 .

[0408] Interface 1215 includes circuitry for interfacing with external devices such as a display device, speaker, microphone, camera, and controller. Controllers include mice, keyboards, and game console controllers. Examples of these interfaces include universal serial bus (USB) and high-definition multimedia interface (HDMI) (registered trademark).

[0409] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network) and may also include a network security circuit.

[0410] The above circuits (systems) can be formed on the chip 1200 through the same process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the process, and the chip 1200 can be manufactured at a low cost.

[0411] The motherboard 1203 including the PCB 1201 on which the chip 1200 having the GPU 1212 is provided, the DRAM 1221 , and the flash memory 1222 may be referred to as a GPU module 1204 .

[0412] Because the GPU module 1204 utilizes chip 1200 using SoC technology, its size can be reduced. Furthermore, due to its high image processing capabilities, the GPU module 1204 is suitable for portable electronic devices such as smartphones, tablets, laptops, and portable game consoles. Furthermore, by utilizing the product-sum operation circuits of the GPU 1212, methods such as deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), autoencoders, deep Boltzmann machines (DBMs), and deep belief networks (DBNs) can be executed. This allows the chip 1200 to be used as an AI chip, or the GPU module to be used as an AI system module.

[0413] The structure described in this embodiment mode can be implemented in combination with the structures described in other embodiment modes, examples, etc. as appropriate.

[0414] Implementation 5 In this embodiment, an application example of a memory device using the semiconductor device described in the above embodiment is described. The semiconductor device described in the above embodiment can be applied to, for example, memory devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book reader terminals, digital cameras (including video cameras), video recording and playback devices, navigation systems, etc.). Note that here, computers include tablet computers, notebook computers, desktop computers, and mainframe computers such as server systems. Alternatively, the semiconductor device described in the above embodiment can be applied to various removable storage devices such as memory cards (e.g., SD cards), USB memories, and SSDs (solid-state drives). Figures 19A to 19E schematically illustrate several structural examples of removable storage devices. For example, the semiconductor device described in the above embodiment is processed into a packaged memory chip and used in various memory devices or removable memories.

[0415] FIG19A is a schematic diagram of a USB memory. USB memory 1100 includes a housing 1101, a cover 1102, a USB connector 1103, and a substrate 1104. Substrate 1104 is housed in housing 1101. For example, a memory chip 1105 and a controller chip 1106 are mounted on substrate 1104. The semiconductor devices described in the previous embodiment modes can be incorporated into memory chip 1105 and the like.

[0416] Figure 19B is a schematic diagram of the external appearance of an SD card, and Figure 19C is a schematic diagram of the internal structure of an SD card. An SD card 1110 includes a housing 1111, a connector 1112, and a substrate 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are mounted on the substrate 1113. By also placing the memory chip 1114 on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Alternatively, a wireless chip with wireless communication capabilities can be placed on the substrate 1113. This allows wireless communication between the host device and the SD card 1110 to read and write data from the memory chip 1114. The semiconductor devices described in the above embodiments can be incorporated into the memory chip 1114, for example.

[0417] Figure 19D is a schematic diagram of the SSD's exterior, and Figure 19E is a schematic diagram of the SSD's internal structure. SSD 1150 includes a housing 1151, a connector 1152, and a substrate 1153. Substrate 1153 is housed in housing 1151. For example, memory chip 1154, memory chip 1155, and controller chip 1156 are mounted on substrate 1153. Memory chip 1155 serves as working memory for controller chip 1156 and, for example, can be a DOSRAM chip. By also providing memory chip 1154 on the back side of substrate 1153, the capacity of SSD 1150 can be increased. The semiconductor devices described in the above embodiments can be incorporated into memory chip 1154 and the like.

[0418] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and examples as appropriate.

[0419] Implementation Method 6 The semiconductor device according to one embodiment of the present invention can be applied to a processor or chip such as a CPU or GPU. 20A to 20H illustrate specific examples of an electronic device having a processor or chip such as a CPU or GPU according to one embodiment of the present invention.

[0420] <Electronic Devices and Systems> A GPU or chip according to an embodiment of the present invention can be incorporated into a variety of electronic devices. Examples of electronic devices include televisions, displays for notebook information terminals, digital signage, large-scale gaming machines such as pinball machines, and other electronic devices with large screens. Other examples include digital cameras, digital video cameras, digital photo frames, e-book readers, mobile phones, portable game consoles, portable information terminals, and audio playback devices. Furthermore, incorporating a GPU or chip according to an embodiment of the present invention into an electronic device can provide the device with artificial intelligence.

[0421] An electronic device according to one embodiment of the present invention may also include an antenna. By receiving signals through the antenna, images or information can be displayed on a display unit. Furthermore, when an electronic device includes an antenna and a secondary battery, the antenna can be used for contactless power transmission.

[0422] An electronic device according to one embodiment of the present invention may also include a sensor (the sensor having the function of measuring the following factors: force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, electricity, radiation, flow, humidity, inclination, vibration, odor or infrared).

[0423] An electronic device according to one embodiment of the present invention can have various functions. For example, it can have the following functions: displaying various information (static images, dynamic images, text images, etc.) on a display unit; using a touch panel; displaying a calendar, date, or time; executing various software (programs); conducting wireless communications; and reading programs or data stored in a storage medium. Figures 20A to 20H illustrate examples of electronic devices.

[0424] [Information Terminal] Figure 20A shows a mobile phone (smartphone) as one of the information terminals. The information terminal 5100 includes a housing 5101 and a display portion 5102. The display portion 5102 has a touch panel as an input interface, and buttons are provided on the housing 5101.

[0425] By applying a chip according to one embodiment of the present invention to information terminal 5100, applications utilizing artificial intelligence can be executed. Examples of artificial intelligence applications include applications that recognize conversations and display the contents of those conversations on display unit 5102, applications that recognize text or graphics input by a user into a touch panel provided on display unit 5102 and display those text or graphics on display unit 5102, and applications that perform biometric authentication such as fingerprint or voiceprint authentication.

[0426] 20B shows a notebook information terminal 5200. The notebook information terminal 5200 includes an information terminal body 5201, a display portion 5202, and a keyboard 5203.

[0427] Similar to the aforementioned information terminal 5100, by incorporating a chip according to one embodiment of the present invention into the notebook information terminal 5200, applications utilizing artificial intelligence can be executed. Examples of artificial intelligence applications include design support software, text proofreading software, and automatic menu generation software. Furthermore, the use of the notebook information terminal 5200 enables the development of novel artificial intelligence technologies.

[0428] Note that in the above examples, FIG20A and FIG20B illustrate smartphones and notebook-type information terminals, respectively, as examples of electronic devices. However, information terminals other than smartphones and notebook-type information terminals can also be used. Examples of information terminals other than smartphones and notebook-type information terminals include PDAs (Personal Digital Assistants), desktop information terminals, and workstations.

[0429] [Game console] Figure 20C shows a portable game console 5300 as an example of a game console. Portable game console 5300 includes a housing 5301, a housing 5302, a housing 5303, a display unit 5304, a connector 5305, and operation keys 5306. Housing 5302 and housing 5303 are detachable from housing 5301. By attaching connector 5305 provided in housing 5301 to another housing (not shown), the image output to display unit 5304 can be output to another video display device (not shown). In this case, housing 5302 and housing 5303 can each be used as a controller. This allows multiple players to play games simultaneously. The chip described in the above embodiments can be embedded in a chip or the like provided on the substrates of housing 5301, housing 5302, and housing 5303.

[0430] 20D shows a stationary gaming machine 5400, which is one of the gaming machines. The stationary gaming machine 5400 is connected to a controller 5402 via a wireless or wired connection.

[0431] By applying a GPU or chip according to an embodiment of the present invention to gaming consoles such as the portable gaming console 5300 and the stationary gaming console 5400, low-power gaming consoles can be realized. Furthermore, low power consumption reduces heat generated by the circuits, thereby minimizing the negative effects of heat on the circuits themselves, peripheral circuits, and modules.

[0432] Furthermore, by applying the GPU or chip of one embodiment of the present invention to the portable game console 5300, a portable game console 5300 equipped with artificial intelligence can be realized.

[0433] The progression of a game, the behavior of creatures appearing in the game, and the phenomena that occur in the game are typically dictated by the game's program. However, by applying artificial intelligence to the portable game console 5300, it is possible to achieve a display that is not limited to the game's program. For example, it is possible to display the content of a player's questions, the progress of the game, the time, and the changes in the behavior of characters appearing in the game.

[0434] Furthermore, when using the portable game console 5300 to play a game requiring multiple players, artificial intelligence can be used to create an anthropomorphic player, thereby allowing the artificial intelligence player to be used as an opponent, allowing one person to play a multi-player game.

[0435] While FIG20C and FIG20D illustrate portable and stationary game consoles as examples of game consoles, game consoles employing a GPU or chip according to an embodiment of the present invention are not limited thereto. Examples of game consoles employing a GPU or chip according to an embodiment of the present invention include arcade game consoles installed in entertainment facilities (such as game centers and amusement parks) and batting practice pitching machines installed in sports facilities.

[0436] [Mainframe Computer] The GPU or chip according to one embodiment of the present invention can be applied to a mainframe computer.

[0437] Fig. 20E shows a supercomputer 5500 as an example of a large-scale computer. Fig. 20F shows a rack-mounted computer 5502 included in the supercomputer 5500.

[0438] Supercomputer 5500 includes a rack 5501 and multiple rack-mounted computers 5502. Note that multiple computers 5502 are housed in rack 5501. Computer 5502 also includes multiple substrates 5504 on which the GPUs or chips described in the above embodiments can be mounted.

[0439] The supercomputer 5500 is a large-scale computer primarily suited for scientific computing. Scientific computing requires high-speed, complex calculations, resulting in high power consumption and high chip heat generation. By incorporating a GPU or chip according to an embodiment of the present invention into the supercomputer 5500, a low-power supercomputer can be realized. Furthermore, low power consumption reduces heat generated by the circuits, thereby minimizing the negative impact of heat generation on the circuits themselves, peripheral circuits, and modules.

[0440] While FIG20E and FIG20F illustrate a supercomputer as an example of a mainframe computer, mainframe computers employing a GPU or chip according to an embodiment of the present invention are not limited thereto. Examples of mainframe computers employing a GPU or chip according to an embodiment of the present invention include computers providing services (servers) and large general-purpose computers (mainframes).

[0441] [Mobile Object] The GPU or chip according to one embodiment of the present invention can be applied to a vehicle as a mobile object and the vicinity of a driver's seat of the vehicle.

[0442] Fig. 20G is a diagram showing the periphery of the front windshield in a car interior, which is an example of a mobile object. Fig. 20G shows a display panel 5701, a display panel 5702, a display panel 5703 attached to the instrument panel, and a display panel 5704 attached to a pillar.

[0443] Display panels 5701 through 5703 can provide various other information by displaying the speedometer, tachometer, distance traveled, fuel gauge, gear status, and air conditioning settings. Furthermore, users can customize the display content and layout of the display panels to enhance design. Display panels 5701 through 5703 can also function as lighting.

[0444] By displaying images captured by a camera installed in the vehicle (not shown) on display panel 5704, it is possible to fill in blind spots blocked by pillars. In other words, by displaying images captured by cameras installed outside the vehicle, blind spots can be filled in, thereby improving safety. Furthermore, by displaying images that fill in unseen areas, safety confirmation can be made more natural and comfortable. Display panel 5704 can also function as a lighting device.

[0445] Because the GPU or chip according to one embodiment of the present invention can be used as an artificial intelligence component, for example, the chip can be used in an autonomous driving system for a car. The chip can also be used in systems that perform navigation, hazard prediction, and the like. Furthermore, navigation, hazard prediction, and other information can be displayed on display panels 5701 to 5704.

[0446] While the above examples illustrate automobiles as an example of a mobile object, mobile objects are not limited to automobiles. Examples of mobile objects include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (UAVs), airplanes, and rockets). A chip according to an embodiment of the present invention can be applied to these mobile objects to provide systems utilizing artificial intelligence.

[0447] [Electrical appliances] 20H shows an electric refrigerator-freezer 5800, which is an example of an electrical appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a freezer door 5803, and the like.

[0448] By applying a chip according to one embodiment of the present invention to an electric refrigerator-freezer 5800, an electric refrigerator-freezer 5800 equipped with artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator-freezer 5800 can automatically generate a menu based on the food stored in the refrigerator-freezer 5800 or the expiration date of the food, and can automatically adjust the temperature of the refrigerator-freezer 5800 according to the stored food.

[0449] An electric refrigerator-freezer has been described as an example of an electrical appliance. However, other electrical appliances include vacuum cleaners, microwave ovens, electric ovens, electric cookers, water heaters, IH cookers, water dispensers, air conditioners including air conditioners, washing machines, dryers, and audio-visual equipment.

[0450] The electronic device, its functions, artificial intelligence application examples, and its effects, etc. described in this embodiment can be implemented in combination with the description of other electronic devices as appropriate.

[0451] This embodiment mode can be implemented in combination with the configurations described in other embodiment modes and examples as appropriate. Example 1

[0452] In this embodiment, a plurality of transistors 200 including an oxide semiconductor as shown in FIG. 1A to FIG. 1D are manufactured in the same process, and transistor characteristics are measured and variations in the transistor characteristics are evaluated.

[0453] The semiconductor device including transistor 200 shown in FIG. 1A to FIG. 1D is referred to as sample 1A. The semiconductor device fabricated as the sample includes 161 transistors manufactured using the same process. In sample 1A, the design values ​​for the channel length and channel width are each 60 nm.

[0454] Next, sample 1A is described.

[0455] In Sample 1A, oxide 230a is formed by sputtering an In—Ga—Zn oxide film using an oxide target with an atomic ratio of In:Ga:Zn = 1:3:4. Oxide 230b is formed by sputtering an In—Ga—Zn oxide film using an oxide target with an atomic ratio of In:Ga:Zn = 4:2:4.1. The films used as oxide 230a and oxide 230b are formed by sequential deposition.

[0456] In addition, the oxide 230c is formed using a stacked structure of the following films: an In-Ga-Zn oxide film deposited by sputtering using an oxide target with an In:Ga:Zn=4:2:4.1 [atomic ratio] and an In-Ga-Zn oxide film deposited by sputtering using an oxide target with an In:Ga:Zn=1:3:4 [atomic ratio].

[0457] The conductor 242 is formed using a tantalum nitride film, and the insulator 250 is formed using a silicon oxynitride film.

[0458] Conductor 260a is formed using a titanium nitride film. Conductor 260b is formed using a tungsten film. The film used as conductor 260a and the film used as conductor 260b are formed by continuous deposition.

[0459] <Characteristics of Transistors Included in Sample 1A> First, sample 1A was heat treated at 400°C for 4 hours in a nitrogen atmosphere. The electrical characteristics of the 161 transistors included in sample 1A were then measured. Furthermore, the Id-Vg characteristics were measured by setting the drain voltage Vd to 1.2V and varying the gate voltage Vg from -4V to +4V.

[0460] Here, in the Id-Vg transistor characteristics, the gate voltage Vg value when the drain current Id=1.0×10-12A is the shift value (Vsh).

[0461] FIG21 shows a normal probability plot of the electrical characteristics of the 161 transistors included in sample 1A. In FIG21 , the horizontal axis represents the shift value (Vsh) [V], and the vertical axis represents the estimated cumulative probability [%].

[0462] Note that methods for calculating the estimated cumulative probability (also called cumulative relative frequency) include the median-rank method, the mean-rank method, the symmetrical sample cumulative distribution method, and the Kaplan-Meier method. You can select any method as appropriate. In this example, the median-rank method is used to calculate the estimated cumulative probability.

[0463] According to Figure 21, in sample 1A, the average value of the Shift value is -0.231V and the standard deviation σ is 0.056V.

[0464] As described above, it can be seen that the electrical characteristics of the transistor 200 of the present invention have small deviations.

[0465] At least a part of the structure, method, etc. described in this embodiment can be implemented in combination with other embodiment modes described in this specification as appropriate. Example 2

[0466] In this example, the semiconductor device shown in Figures 12A to 12D was fabricated, and the reliability evaluation of transistor 200 and the results of investigating the time-dependence of stress were described. The reliability evaluation was performed on four transistors, Samples A to D, on a single substrate. On the substrates including Samples A and D, a 2 nm thick oxide 243 was formed at a substrate temperature of 200°C using a sputtering method using a target with an In:Ga:Zn atomic ratio of 1:3:4. The substrate was then heat treated at 400°C for 8 hours in a nitrogen atmosphere. The reliability evaluation was performed using a +GBT (Gate Bias Temperature) stress test with a stress temperature of 150°C. The set temperature was set to 150°C, with the drain potential Vd, source potential Vs, and bottom gate potential Vbg set to 0V, and the top gate potential Vg set to +3.63V. The transistor dimensions for samples A through D were 60nm in channel length and 60nm in channel width (both design values). Furthermore, in this stress test, the stress duration at which ΔVsh exceeded ±100mV was defined as the transistor lifetime. Changes in Ion, S value, and μFE over time were also evaluated.

[0467] Figure 22 shows the results of the +GBT stress test. In Figure 22, the horizontal axis represents stress time (hr), and the vertical axis represents ΔVsh (mV). As shown in Figure 22, Sample A achieved a lifespan of 1230 hours, Sample B achieved a lifespan of 1410 hours, Sample C achieved a lifespan of 1240 hours, and Sample D achieved a lifespan of 1230 hours. All four samples achieved excellent lifespans exceeding 1200 hours.

[0468] Compared to the +GBT stress test with a set temperature of 125°C, the deterioration rate at the +GBT stress test evaluated in this example, at a set temperature of 150°C, is estimated to be approximately 24 times higher. Therefore, the lifespan at a stress temperature of 125°C can be estimated to be over 28,000 hours.

[0469] Fig. 23A shows the change in Ion over time for samples A to D. Fig. 23B shows the change in S value over time for samples A to D. Fig. 23C shows the change in μFE over time for samples A to D.

[0470] Note that Ion (A) is the Id value at Vd = +1.2V and Vg = +3.3V. The S value (mV / dec) is the Vg value required to achieve a single-digit change in Id in the subthreshold region at Vd = +1.2V. μFE (cm² / Vs) is calculated using the linear region equation for the ramp channel approximation.

[0471] As shown in Figures 23A to 23C , for samples A to D, the changes in Ion, S value, and μFE over stress time were all small.

[0472] Based on the above results, it was confirmed that the transistor 200 according to one embodiment of the present invention has high reliability.

[0473] This embodiment can be implemented in combination with the configurations, structures, methods, etc. shown in other embodiment modes and other embodiments as appropriate. Example 3

[0474] In this embodiment, a semiconductor device including the transistor 200 shown in FIG. 12A to FIG. 12D is manufactured, and transistor characteristics are measured and variations in the transistor characteristics are evaluated.

[0475] Note that the semiconductor device including the manufactured transistor 200 includes 215 transistors manufactured in the same process. Note that the design values ​​of the channel length and channel width are 60 nm, respectively.

[0476] <Electrical Characteristics of Transistors> First, the fabricated semiconductor device was heat treated at 400°C for 8 hours in a nitrogen atmosphere. The electrical characteristics of the 215 transistors included in the semiconductor device were then measured. Note that the Id-Vg characteristics were measured by setting Vd to 0.1V or 1.2V and varying Vg from -4V to +4V.

[0477] FIG24 is a graph showing the Id-Vg characteristics of 215 transistors included in the semiconductor device. In FIG24 , the horizontal axis represents Vg (V) and the vertical axis represents Id (A).

[0478] Figure 25A also shows a normal probability distribution graph for Vsh. In Figure 25A, the horizontal axis represents Vsh (V) and the vertical axis represents the estimated cumulative probability (%). Figure 25B also shows a normal probability distribution graph for Ion. In Figure 25B, the horizontal axis represents Ion (μA) and the vertical axis represents the estimated cumulative probability (%). Figure 25C also shows a graph showing the Vsh-to-Vbg dependence of nine transistors.

[0479] Note that methods for calculating the estimated cumulative probability (also called cumulative relative frequency) include the median-rank method, the mean-rank method, the symmetric sample cumulative distribution method, and the Kaplan-Meier method. You can choose any method as appropriate. In this example, the median-rank method is used to calculate the estimated cumulative probability.

[0480] FIG24 shows the Id-Vg characteristics of 215 transistors overlapped with each other.

[0481] As shown in FIG25A , the standard deviation σ of the Vsh of the 215 transistors is approximately 64 mV.

[0482] As shown in FIG25B , the average Ion of the 215 transistors is approximately 7.78 μA, and the standard deviation σ is approximately 6.71 μA.

[0483] This confirms that the transistor 200 according to one embodiment of the present invention has good electrical characteristics and small variations. Furthermore, it can be confirmed that Vsh can be controlled by Vbg.

[0484] At least a part of the structure, method, etc. described in this embodiment can be implemented in combination with other embodiment modes and other examples described in this specification as appropriate. Example 4

[0485] In this embodiment, reliability evaluation is performed on two transistors (element A and element B) in the semiconductor device including transistor 200 used in Embodiment 2.

[0486] <Transistor Reliability> Reliability evaluation is performed using a +GBT stress test. In this embodiment, the +GBT stress test is performed at a set temperature of 150°C, with Vd = Vs = Vbg = 0V and Vg = +3.63V. Note that Vs is the drain potential and Vbg is the bottom gate potential.

[0487] During the +GBT stress test, an Id-Vg test was performed at regular intervals. The Id-Vg test was performed with the transistor's Vd = 1.2V, Vs = 0V, and Vbg = 0V, with Vg swept from -3.3V to +3.3V. Note that a semiconductor parameter analyzer manufactured by Keysight Technologies was used for the Id-Vg test. Furthermore, during the +GBT stress test, ΔVsh, representing the change in Vsh from the start of measurement, was used as an indicator of the fluctuation in the transistor's electrical characteristics. Furthermore, the fluctuation in the S value over time was evaluated.

[0488] 26A shows the results of the +GBT stress test of device A and device B. In FIG26A , the horizontal axis represents stress time (hr) and the vertical axis represents ΔVsh (mV).

[0489] As shown in Figure 26A , even after 490 hours of application of the aforementioned stress, the change in drift voltage ΔVsh for both Component A and Component B remained below 100 mV. Specifically, Component A's ΔVsh after 490 hours was -16 mV, and Component B's ΔVsh after 490 hours was -23 mV.

[0490] FIG26B shows the changes in the S value of the +GBT stress test for device A and device B. In FIG26B , the horizontal axis represents stress time (hr) and the vertical axis represents the S value (mV / dec).

[0491] As shown in FIG. 26B , even after 490 hours of application of the above stress, the S value of element A and element B does not fluctuate within the range of 100 mV / dec to 140 mV / dec.

[0492] Based on the above results, it was confirmed that the transistor 200 using one embodiment of the present invention has high reliability.

[0493] At least a part of the structure, method, etc. described in this embodiment can be implemented in combination with other embodiment modes and other examples described in this specification as appropriate.

[0494] 100:Capacitor 110: Conductor 112: Conductor 120: Conductor 130:Insulator 150:Insulator 200: Transistor 200_1: Transistor 200_2: Transistor 200_n: transistor 205: Conductor 205a: Conductor 205b: Conductor 210: Insulator 212: Insulator 214: Insulator 216: Insulator 217: Insulator 218: Conductor 222: Insulator 224: Insulator 230: Oxide 230a: Oxide 230A: Oxide film 230b: oxide 230B: oxide film 230c: oxide 230c1: oxide 230c2: oxide 230C: oxide film 231: Area 231a: Area 231b: Area 234: Area 240: Conductor 240a: Conductor 240b: Conductor 241:Insulator 241a: Insulator 241b: Insulator 242: Conductor 242a: Conductor 242A: Conductive film 242b: Conductor 242B: conductive layer 243: Oxide 243a: Oxide 243b: Oxide 246: Conductor 246a: Conductor 246b: Conductor 250:Insulator 250A:Insulating film 254:Insulator 254a: Insulator 254A: Insulating film 254b: Insulator 260: Conductor 260a: Conductor 260A: Conductive film 260b: Conductor 260B: Conductive film 265: Sealing part 265a: Sealing part 265b: Sealing part 274:Insulator 280:Insulator 281:Insulator 282:Insulator 283:Insulator 300: Transistor 311:Substrate 313:Semiconductor area 314a: low resistance area 314b: low resistance area 315: Insulator 316: Conductor 320: Insulator 322: Insulator 324: Insulator 326: Insulator 328: Conductor 330: Conductor 350:Insulator 352: Insulator 354: Insulator 356: Conductor 400: Transistor 405: Conductor 430c: oxide 431a: Oxide 431b: Oxide 432a: Oxide 432b: Oxide 440: Conductor 440a: Conductor 440b: Conductor 441:Insulator 441a: Insulator 441b: Insulator 442a: Conductor 442b: Conductor 450:Insulator 460: Conductor 460a: Conductor 460b: Conductor 1001: Wiring 1002: Wiring 1003: Wiring 1004: Wiring 1005: Wiring 1006: Wiring 1007: Wiring 1008: Wiring 1009: Wiring 1010: Wiring 1100:USB memory 1101: Shell 1102: lid 1103:USB connector 1104:Substrate 1105:Memory chip 1106: controller chip 1110: SD card 1111: Shell 1112: Connector 1113:Substrate 1114:Memory chip 1115: controller chip 1150:SSD 1151: Shell 1152: Connector 1153:Substrate 1154:Memory chip 1155:Memory chip 1156: controller chip 1200: Chip 1201:PCB 1202: Bump 1203: Motherboard 1204:GPU module 1211:CPU 1212:GPU 1213: Analog Operation Unit 1214:Memory Controller 1215: Interface 1216: Network Circuit 1221:DRAM 1222: Flash memory 1400:Memory device 1411: Peripheral circuit 1420: Line circuit 1430: Column Circuit 1440: Output circuit 1460: Control logic circuit 1470:Memory cell array 1471:Memory Unit 1472:Memory Unit 1473:Memory Unit 1474:Memory Unit 1475:Memory Unit 1476:Memory Unit 1477:Memory Unit 1478:Memory Unit 5100: Information Terminal 5101: Shell 5102: Display unit 5200: Notebook Information Terminal 5201: Main body 5202: Display unit 5203:Keyboard 5300: Portable game console 5301: Shell 5302: Shell 5303: Shell 5304: Display unit 5305:Connection 5306: Operation keys 5400: Fixed game console 5402:Controller 5500:Supercomputer 5501:Rack 5502: Computer 5504:Substrate 5701: Display panel 5702: Display panel 5703: Display panel 5704: Display panel 5800: Electric refrigerator-freezer 5801: Shell 5802:Refrigerator door 5803: Freezer door

Claims

1. A semiconductor device comprising: a plurality of transistors; each transistor comprising: a first conductor; a first insulator; a first metal oxide on the first insulator; a second conductor and a third conductor on the first metal oxide; a second metal oxide located above the first metal oxide and including a region between the second conductor and the third conductor; a second insulator on the second metal oxide; and a fourth conductor on the second insulator; wherein... The first metal oxide and the second metal oxide each contain indium; the top surface of the first metal oxide in the region overlapping with the fourth conductor is lower than the top surface of the first metal oxide in the region overlapping with the second conductor and the top surface of the first metal oxide in the region overlapping with the third conductor; and the first metal oxide contains a curved surface between the side surface and the top surface.

2. The semiconductor device as claimed in claim 1, wherein, The channel length of each transistor is 40 nm to 80 nm; the channel width of each transistor is 40 nm to 80 nm.

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