Systems, methods, and devices for power domain management

Abstract

A system, method, and apparatus for power domain management are provided. The method includes: in response to receiving a memory command associated with a storage location coupled to a memory controller, activating a first power domain of the memory controller; and executing a first portion of an operation sequence determined based on the memory command, the first portion being executed using a first plurality of processing elements included in the first power domain. The method further includes: activating a second power domain of the memory controller based on timing determined based on the operation sequence; and executing a second portion of the operation sequence using a second plurality of processing elements included in the second power domain.

Description

Technical Field

[0001] The present invention relates to power domain management, and more particularly, the present invention relates to enhancing the management of power domains associated with memory. Prior Art

[0002] A memory module may include components such as a memory controller and a memory array. The memory controller may receive commands from other components and process those commands to perform read and write operations associated with the memory array. Thus, the memory controller may include processing logic configured to perform such read and write operations. Prior art for implementing such memory controllers remains limited because these memory controllers remain inefficient in terms of power consumption associated with the use of such processing logic. Simple diagram description

[0003] FIG. 1 illustrates an example of a system configured for power domain management according to some embodiments. FIG. 2 illustrates an example of an apparatus configured for power domain management according to some embodiments. FIG. 3 illustrates another example of an apparatus configured for power domain management according to some embodiments. FIG. 4 illustrates an additional example of an apparatus configured for power domain management according to some embodiments. 5 illustrates an image of a timing diagram for executing commands and operations associated with power domain management according to some embodiments. FIG. 6 illustrates a flow chart of an example implementation of a method for power domain management according to some implementations. FIG. 7 illustrates a flow chart of another example of performing a method for power domain management according to some embodiments. Implementation

[0004] In the following description, numerous specific details are set forth to provide a thorough understanding of the concepts presented. The concepts presented may be implemented without some or all of these specific details. In other cases, well-known processing operations are not described in detail to avoid unnecessarily obscuring the concepts described. Although some concepts will be described in conjunction with specific examples, it should be understood that these examples are not intended to be limiting.

[0005] A memory controller may include processing logic configured to perform various operations associated with memory access. Thus, different portions of such processing logic may be configured to perform different operations associated with a particular memory command. For example, a read command may be issued to request that data be read from a memory. Such a read command may include a plurality of different memory operations, such as a read operation and a data verification operation. In various embodiments, these operations may be performed consecutively as the data is read from the memory array before being verified by the memory controller. Prior art techniques for implementing such memory commands are still limited because the processing logic used for the different operations is still powered even when not in use, resulting in less efficient power consumption of the memory controller and relatively high leakage current from the unused processing logic that is still powered.

[0006] Embodiments disclosed herein provide for dynamic implementation and activation of different power domains for different portions of memory operations. As discussed in more detail below, different power domains may correspond to different operations associated with a memory command, and these power domains may be dynamically activated depending on their use within the execution context of the memory command. Thus, as discussed in more detail below, when the power domains are invoked, the power domains are dynamically used, and the overall power consumption of the memory controller executing the memory command is reduced. Additionally, such leakage current is also reduced, where leakage current may be associated with a processing element that is powered even during a standby mode.

[0007] FIG. 1 illustrates an example of a system for power domain management configured in accordance with some embodiments. As similarly discussed above, a system (e.g., system 100) can include and manage multiple power domains to stagger the activation of these power domains when reading data from memory. As discussed in more detail below, increased granularity in power domain control and activation during memory operations improves the efficiency of use of these power domains and the power consumption caused by such power domain use and associated leakage currents.

[0008] As shown in FIG. 1 , the system 100 includes a host processor 108 configured to execute one or more processing operations that may be associated with a host application or other user applications. In one example, the host processor 108 may be a microcontroller configured to execute commands that may include user-defined commands. Thus, commands may be generated by the host processor 108 and may be communicated to another component, such as the memory module 102, via the bus 111. For example, the host processor 108 may require data for a processing operation and may issue a read command to the memory module 102 to retrieve the data.

[0009] Thus, the system 100 further includes a memory module 102 configured to provide data storage for the system 100. In various embodiments, the memory module 102 includes a memory array 106 configured to store data values in storage locations. Thus, the memory array 106 may be a non-volatile memory array that includes an arrangement of addressable memory cells configured to store the data values. In one example, the memory array 106 may be a resistive random access memory (RRAM). The memory array 106 may have associated processing logic included in the memory controller 104. Thus, the memory controller 104 may include elements configured to select memory cells based on memory addresses, such as processing logic and multiplexers. In addition, the memory controller 104 is configured to perform operations performed on the memory array 106, such as read and write operations to read data from the memory array 106 and write data to the memory array 106.

[0010] In various embodiments, the memory controller 104 includes various different power domains, such as power domain 105, configured to perform such operations. As disclosed herein, power domains may be defined based on the configuration of power provided to the implemented logic blocks. For example, a first group of logic blocks implemented in the processing logic of the memory controller coupled to a first power supply may be a first power domain. Additionally, a second group of logic blocks implemented in the processing logic of the memory controller coupled to a second power supply may be a second power domain. It should be understood that the first power supply and the second power supply in this example may refer to different couplings to the same power supply, such as may occur via selective activation of a coupling switch. Further details and examples of these power domains and power supplies will be discussed in more detail below with reference to FIGS. 3 and 4.

[0011] As will also be discussed in more detail below, power domains can be independently managed and dynamically activated based on received commands and based on power received from a power source (e.g., power supply 110). Managing power domains in this manner improves the efficiency of their power usage by reducing the amount of time that the power domains are active and not being used. In addition, the power domains can be powered on and off based on whether the system 100 is in standby mode or active mode. Thus, the wakeup and activation of power domains during transitions from standby mode to active mode can also be managed to improve the efficiency of such wakeup operations by staggering the activation of components of the memory controller 104 and reducing the amount of time that such components are active and not being used.

[0012] FIG. 2 illustrates an example of an apparatus for power domain management configured in accordance with some embodiments. Thus, as similarly discussed above, an apparatus such as memory module 200 may include a memory array 202 and a memory controller 206. As shown in FIG. 2 , memory array 202 may include various rows and columns of memory cells, which may be included in addressable blocks such as memory segments 204. Memory module 200 may communicate with one or more additional components such as a host processor via a communication interface such as interface 212.

[0013] As also shown in FIG. 2 , the memory controller 206 includes various different power domains that can be configured to perform various operations supported by the memory controller 206. For example, the memory controller 206 can include a first power domain 208, a second power domain 209, and a third power domain 210, which can be configured to implement a power domain scheme defined by a standby mode and an active mode. For example, the first power domain 208 and the second power domain 209 can be included in a first power domain group 207 that is still powered during the standby mode and the active mode. The memory controller 206 can also include a third power domain 210, which can be included in a second power domain group 211 that is powered off during the standby mode and powered during the active mode.

[0014] As will be discussed in more detail below, the power domains included in the first power domain group 207 can be further configured such that the power domains are selectively enabled and disabled based on commands received via the interface 212. Such selective activation of the power domains included in the first power domain group 207 allows the power domains to be activated at a higher level of granularity than a general and full domain transition from a standby mode to an active mode, and allows the power domains to be activated in a staggered manner. As will be discussed in more detail below, when transitioning from a standby mode to an active mode, delaying the activation of some power domains until the power domains are invoked by the received command reduces the power consumption of the memory module 200 and also reduces the leakage current caused by the power domains.

[0015] As will also be discussed in more detail below, processing logic 213 included in memory controller 206 may be configured to generate and apply control signals to manage activation and deactivation of various power domains. Thus, processing logic 213 may be a processing device that includes a processing element implemented in firmware or a programmable logic device, or a combination thereof. Furthermore, processing logic 213 may be configured to receive and interpret commands received from another system element (e.g., a host processor) via interface 212. Processing logic 213 may be further configured to generate control signals in response to received commands, wherein such control signals activate power domains when appropriate based on a portion of the received commands.

[0016] In various embodiments, the generation of control signals and activation of power domains may be performed based on a specified mapping of portions of a command to power domains. More specifically, a data structure may be stored in the memory controller 206 that identifies which power domain and when it should be activated for each type of command received at the memory controller 226. Thus, the data structure may include an identifier configured to identify the power domain and may also include timing information for each type of received command, wherein the timing information identifies the time when the identified power domain is activated or powered down. In this way, the memory controller 206 may generate an operation sequence based on the identified type of received command using the specified mapping and also generate a sequence of control signals to implement the operation sequence. In various embodiments, the specified mapping may be determined by an entity such as a manufacturer and may be stored to the memory module 200 during the manufacturing process or as part of an update.

[0017] FIG3 illustrates another example of an apparatus for power domain management configured in accordance with some embodiments. As similarly discussed above, apparatus 300 may include a memory controller 301, which may be coupled to one or more power supplies, such as power supply 306. In addition, memory controller 301 includes one or more power domains, such as a first power domain 302 and a second power domain 304, which may be included in a first power domain group identified in a standby operating mode. Thus, during the standby operating mode, power supply 306 continues to provide power to first power domain 302 and second power domain 304, although other power domains (e.g., those included in a second power domain group identified in an active operating mode) are powered off.

[0018] As shown in FIG3 , the memory controller 301 is additionally configured to include one or more switches, such as a switch 308 that may be coupled between the power supply 306 and the second power domain 304. Thus, the switch 308 is configured to provide additional control over the activation and deactivation of the second power domain 304, which is in addition to the control provided by the power supply 306. As discussed above, the control signal that controls the operation of the switch 308 may be generated by the processing logic 310 of the memory controller 301. In this way, different power domains included in the standby power domain group may be independently managed using management of the control of the switch (e.g., the switch 308).

[0019] As will be discussed in more detail below with reference to FIG5 , different power domains may be used for different operations performed in response to receiving commands. For example, the first power domain 302 may include components such as logic, multiplexers, and buffers for reading data values from a memory array. Additionally, the second power domain 304 may include components such as logic and buffers for error correction code (ECC) calculations and data output operations. Thus, the multiplexer and ECC logic may be implemented in different power domains.

[0020] In response to receiving a read command, the memory controller 301 may first activate the first power domain 302 to read data, and may then activate the second power domain 304 to perform ECC operations and data output operations. Such staggered activation of the second power domain 304 may be implemented through the use of the switch 308. In addition, the delay in the activation of the second power domain 304 reduces the total amount of power consumed by the second power domain 304 to execute the received command. In the absence of the switch 308 and the control signal provided by the logic 310, the second power domain 304 will continue to consume power.

[0021] In some embodiments, the implementation of control logic within the memory controller 301 enables the creation and implementation of various configurable sub-domains based on portions of received commands. More specifically, portions of commands that identify blocks of operation may be mapped to different power domains, and control signals for switches associated with those power domains may have timings configured based on the identified blocks of operation. As similarly discussed above, such control signals may be signals for controlling switches for activating and de-energizing power domains.

[0022] FIG. 4 illustrates an additional example of an apparatus for power domain management configured according to some embodiments. As similarly discussed above, apparatus 400 may include a memory controller 401, which may include one or more power domains, such as a first power domain 402 and a second power domain 404. As similarly discussed above, first power domain 402 and second power domain 404 may be included in a first power domain group identified by a standby operating mode. Therefore, one or more of first power domain 402 and second power domain 404 may continue to receive power.

[0023] As shown in FIG. 4 , the memory controller 401 may be coupled to one or more power supplies, such as a first power supply 406 and a second power supply 408. Thus, according to some embodiments, different power domains within the first power domain group may each have their own power supplies, and the power supplies may be configured to operate independently based on a sequence of operations associated with commands received by the memory controller 401. Thus, instead of the operation of switches via control signals, the operation of independent power supplies may be used to interleave the activation and use of power domains in a standby mode of operation. In some embodiments, the first power supply 406 and the second power supply 408 may be configured to receive control signals from the processing logic 410 and schedule their operations based on such control signals. In this way, the memory controller 401 may determine the sequence and timing of the operations of the first power supply 406 and the second power supply 408.

[0024] FIG. 5 illustrates an image of a timing diagram of commands and operations associated with power domain management performed in accordance with some embodiments. As shown in diagram 500, different power domains may be activated at different times to perform different portions of a sequence of operations of a received command at a memory module. For example, as indicated by CMD 501, a command may be received and detected at a memory module. In response to detecting the command, a first domain activation 502 may occur, wherein a first power domain is activated and transitions from a powered off state to a powered on state. As discussed above, this may occur via activation of a switch or activation of a power supply, or a combination thereof.

[0025] The processing logic of the memory module may recognize a first portion 503 of the command that identifies a read operation and a read address. Thus, such information may be used by the first power domain during a first operation 504. Thus, the read circuitry implemented in the first power domain may be used to read data from the memory array. In various embodiments, the second power domain may be activated during a second domain activation 508. As shown in diagram 500, in anticipation of ECC operations and data output operations performed by logic and circuitry included in the second power domain, such activation may begin before the read operation is terminated. In various embodiments, timing information for activation and deactivation of power domains may be determined by the memory controller based at least in part on data included in a received memory command and information about a specified sequence of events and / or operations, as discussed in more detail below.

[0026] Once power is turned on, the second power domain may be used to perform a second operation 506, which may include an ECC operation and a data output operation. In various embodiments, the second operation 506 and the timing of the second operation 506 may be identified based on a specified sequence of operations, as similarly discussed above and as will be discussed in more detail below. As also shown in Figure 500, the second power domain is powered down during an inactive period 510 and is dynamically activated in response to a determination made based on a received command. Therefore, power consumption associated with the second power domain is reduced because it remains powered down when not in use during the execution of commands by the memory module. It should be understood that the associated leakage current is also reduced because the processing logic (e.g., gates) used to implement components such as multiplexers can be powered down when not in use, thereby reducing its associated leakage current.

[0027] FIG6 illustrates a flow chart of an example of a method for power domain management performed according to some embodiments. Thus, a method such as method 600 may be performed to manage multiple power domains when executing commands at a memory module. As will be discussed in more detail below, increasing control over the startup and shutdown of these power domains improves the efficiency of the use of these power domains and the power consumption and leakage current caused by the use of such power domains.

[0028] Method 600 may perform operation 602, during which a first power domain of a memory device may be activated. As similarly discussed above, the first power domain may be activated in response to receiving a command at a memory controller. The first power domain may include a processing element configured to read data from an associated memory array. In various embodiments, activation may include transitioning the first power domain from a power-off mode or a standby mode to an active mode.

[0029] Method 600 may perform operation 604 during which a read operation may be performed on a memory array included in the memory device. Thus, a processing element implemented in the first power domain may be used to read data from the memory array. As similarly discussed above, the retrieved data may be identified based on, for example, an address included in the received command.

[0030] Method 600 may perform operation 606, during which a second power domain of the memory device may be activated. In various embodiments, the second power domain may be activated in response to a portion of the received command being executed. For example, the second power domain may be activated in response to a read operation being executed. In various embodiments, activation may include transitioning the second power domain from a powered-off state to a powered-on state. Thus, the second power domain may be completely powered-off prior to activation, and once activated, may transition to a powered-on state.

[0031] Method 600 may proceed to operation 608, during which a data validation operation may be performed on the data read from the memory array. Thus, the processing element implemented in the second power domain may be used to perform a data validation operation on the data read from the memory array. Additionally, one or more data output operations may be performed to provide the retrieved data to another element, such as a host processor.

[0032] FIG7 illustrates a flow chart of another example of a power domain management method performed according to some embodiments. Thus, a method such as method 700 may be performed to manage multiple power domains when executing commands at a memory module. As discussed in more detail below, received commands may be partitioned and handled by different power domains to facilitate efficient use of those power domains.

[0033] Method 700 may perform operation 702, during which a read command may be detected. As similarly discussed above, commands may be received at a memory controller from various other associated components that are requesting read and / or write access to a memory. Thus, during operation 702, a command may be received at a memory controller via a communication interface, which may be a communication bus. The command may include information such as an identifier that specifies the command and associated data (e.g., a memory address or other storage location identifier).

[0034] Method 700 may perform operation 704 during which a first portion and a second portion of a read command may be identified. In some implementations, the memory controller may identify portions of the command corresponding to different operations. For example, the read command may have a specified sequence of events or operations that may be specified by an entity such as a manufacturer. Thus, in response to receiving the command, the memory controller may identify portions corresponding to each of the specified operations and may also identify power domains associated with those specified operations.

[0035] Although the embodiments disclosed herein refer to portions of a command, it should be understood that these portions may be a specified sequence of operations determined based on the received command. As similarly discussed above, a read command may be received and used to identify a sequence of operations including a read operation and a subsequent data verification operation. Thus, an initial portion of a read command may be used to identify a sequence of multiple operations, and these operations may be implemented using staggered activation of power domains, as discussed in more detail below.

[0036] Method 700 may perform operation 706, during which a first power domain of a memory controller may be activated based on the first portion. As similarly discussed above, the first power domain may be activated in response to receiving a command at the memory controller and identifying the first portion of the sequence of operations as a read operation. The first power domain may include a processing element configured to read data from an associated memory array. Additionally, during operation 706, the memory array itself may be activated and awakened. Thus, in response to identifying the read operation, the memory controller may activate the first power domain by transitioning the first power domain from a standby mode or a power-off mode to an active mode.

[0037] Method 700 may proceed to operation 708, during which a read operation may be performed on a memory array coupled to a memory controller. Thus, a processing element implemented in a first power domain may be used to read out data from the memory array. As similarly discussed above, the retrieved data may be identified based on, for example, an address included in a received command. In some implementations, the read data may be temporarily stored in a register of the memory controller.

[0038] Method 700 may perform operation 710, during which a second power domain of the memory controller may be activated based on the second portion. In various embodiments, the second power domain may be activated in response to the first portion of the received command being executed. For example, the second power domain may be activated in response to a read operation being executed and specifying a sequence of events / operations and / or the second portion. As similarly discussed above, the memory controller may have a specified sequence of operations to be performed for a requested read command. Also as discussed above, the specified sequence of operations may be defined by an entity such as a manufacturer or user or by a memory standard. The specified sequence may include performing an ECC calculation after completing the read operation, and these sequences may have associated timings stored as timing information. Thus, in response to a read operation being initially identified based on the received command, and in response to the first portion of the command being executed, the second power domain may be activated. In another example, the second portion of the command may identify one or more data verification operations to be performed, such as an ECC calculation, and the second power domain may be identified and activated based on the operations specified in the second portion of the received command. As discussed above, activation may include transitioning the second power domain from a powered-off state to a powered-on state.

[0039] As similarly discussed above with reference to FIG. 5 , the initiation of activation of the second power domain may occur prior to the data verification operation and in parallel with the read operation. In this way, the second power domain is made available prior to the time at which the data verification operation is to be performed, as may be determined based on the specified sequence of operations. Thus, the timing of activation of the second power domain is implemented such that the latency of the data verification operation following the read operation is reduced or eliminated.

[0040] Method 700 may proceed to operation 712, during which a data validation operation may be performed on the data read from the memory array. Thus, as similarly discussed above, the processing element implemented in the second power domain may be used to perform a data validation operation on the data read from the memory array. Additionally, one or more data output operations may be performed to provide the retrieved data to another element, such as a host processor.

[0041] Although the foregoing concepts have been described in some detail for purposes of clarity, it will be apparent that certain changes and modifications may be practiced within the scope of the appended claims. It should be noted that there are many alternative ways to implement processes, systems, and devices. Therefore, the present examples are to be considered illustrative rather than restrictive.

[0042] 100: System 102, 200: Memory module 104, 204, 301, 401: memory controller 105: Power Domain 106, 202: Memory array 108: Main processor 110, 306: Power supply 111: Bus 204:Memory segment 207: First power domain group 208, 302, 402: first power domain 209, 304, 404: Second power domain 210: The third power domain 211: Second power domain group 212: Interface 213, 310: Processing logic 300, 400: device 308: Switch 406: First Power Source 408: Second power supply 410: Processing logic 500: Timing diagram 501:CMD 502: First domain started 503: Part 1 504: First Operation 506: Second Operation 508: Second domain started 510: Inactive period 600: Power Domain Management Method 602: Start the first power domain of the memory device 604: Perform a read operation on a memory array included in the memory device 606: Start the second power domain of the memory device 608: Use the second power domain to perform a data verification operation on the data read from the memory array 700: Power Domain Management Method 702: Detection read command 704: Identify the first and second parts of the read command 706: Start the first power domain of the memory controller based on the first part 708: Execute a read operation on a memory array coupled to a memory controller 710: Starting the second power domain of the memory controller based on the second part 712: Use the second power domain to perform a data verification operation on the data read from the memory array

Claims

1. A method for power domain management, comprising: In response to receiving a memory command associated with a storage location coupled to a memory controller, a first power domain of the memory controller is activated; Execute a first part of an operation sequence determined based on the memory command, the first part being executed using a first plurality of processing elements included in a first power domain; start a second power domain of the memory controller based on a timing determined based on the operation sequence; and execute a second part of the operation sequence using a second plurality of processing elements included in the second power domain; wherein the start and read operations of the second power domain are executed in parallel.

2. The method as described in claim 1, wherein the memory command is a read command that identifies data to be read from the storage location.

3. The method as described in claim 2, wherein the first part identifies the read operation, and wherein the second part identifies a data verification operation.

4. The method as described in claim 3, wherein the data verification operation includes: Based on the data read from this storage location, calculate an error correction code (ECC).

5. The method as described in claim 1, wherein the startup of the first power domain and the startup of the second power domain further comprise: The process transitions from a power outage state to a power supply state.

6. The method as described in request item 1, wherein, The association between the operation sequence and the first power domain and the second power domain is stored by the memory controller in a specified mapping.

7. The method as described in claim 1, further comprising: Timing information for the startup of the second power domain is determined, at least in part, based on data representing the sequence of operations.

8. The method as described in claim 1, further comprising: Receive a command to attach memory; Start a third power domain of the memory controller; And using a third plurality of processing elements included in the third power domain, execute at least some of the commands in the additional memory commands.

9. A system for power domain management, comprising: A non-volatile memory array; A memory controller configured to: initiate a first power domain in response to receiving a memory command associated with the non-volatile memory array; execute a first portion of an operation sequence determined based on the memory command, the first portion being executed using a first plurality of processing elements included in the first power domain; initiate a second power domain based on a timing determined based on the operation sequence; and execute a second portion of the operation sequence using a second plurality of processing elements included in the second power domain; wherein the initiation and read operations of the second power domain are executed in parallel.

10. The system as described in claim 9, further comprising: A first power supply, coupled to the first power domain and configured to power the first power domain in response to a first control signal received from the memory controller; And a second power supply coupled to the second power domain and configured to power the second power domain in response to a second control signal received from the memory controller.

11. The system as claimed in claim 9, wherein the first part identifies the read operation, and wherein the second part identifies a data verification operation.

12. The system as claimed in claim 11, wherein the data verification operation includes calculating an error correction code (ECC) based on data read from the non-volatile memory array.

13. The system of claim 9, wherein the association between the operation sequence and the first power domain and the second power domain is stored by the memory controller in a specified mapping.

14. An apparatus for power domain management, comprising: A memory controller configured to: initiate a first power domain in response to receiving a memory command associated with a non-volatile memory array; Execute a first portion of an operation sequence determined based on the memory command, the first portion being executed using a first plurality of processing elements included in a first power domain; start a second power domain based on a timing determined based on the operation sequence; and execute a second portion of the operation sequence using a second plurality of processing elements included in the second power domain; wherein the start and read operations of the second power domain are executed in parallel.

15. The apparatus of claim 14, wherein the nonvolatile memory array is a resistive random access memory (RRAM) array.

16. The apparatus of claim 14, wherein the first portion identifies the read operation, and wherein the second portion identifies a data verification operation.

17. The apparatus of claim 16, wherein the data verification operation includes calculating an error correction code (ECC) based on data read from the non-volatile memory array.

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