Light-emitting element and display device including the same

Abstract

A light-emitting element and a display device thereof. The light-emitting element includes a first semiconductor layer, first electrodes disposed on one side and the other side of the first semiconductor layer, a light-emitting layer located on the first semiconductor layer and between the first electrodes, a second semiconductor layer located on the first semiconductor layer, a second electrode located on the second semiconductor layer, and a passivation layer covering at least a portion of the first semiconductor layer and at least a portion of the light-emitting layer; and at least a portion of the second semiconductor layer located on the passivation layer, wherein a first opening portion exposes a portion of the top surface and a portion of the side surface of each first electrode. Therefore, the height of the top surface of the passivation layer around the first electrodes of the light-emitting element is reduced.

Description

Light-emitting element and display device including the light-emitting element This specification relates to a light-emitting element and a display device comprising the light-emitting element, and more particularly, to a light-emitting element capable of minimizing or at least reducing disconnection defects and a display device comprising such a light-emitting element. As display devices used in computer monitors, televisions (TVs), mobile phones, etc., there are organic light-emitting displays (OLEDs) that are configured to emit their own light and liquid crystal displays (LCDs) that require a separate light source. The applications of display devices range from computer monitors and TVs to personal mobile devices. Currently, research is underway on display devices that are large in size, small in volume, and lightweight. Furthermore, display devices including light-emitting diodes (LEDs) have recently garnered significant attention as next-generation display devices. Because LEDs are made of inorganic materials rather than organic materials, they are more reliable and have a longer lifespan than liquid crystal displays or organic light-emitting displays. In addition, LEDs can be quickly switched on and off, possess excellent luminous efficiency, high shock resistance, and great stability, and can display high-brightness images. The objective of this specification is to provide a light-emitting element (light-emitting diode) in which electrode disconnection defects are minimized. Another objective of this specification is to provide a display device in which the suppression of disconnection defects of light-emitting elements is suppressed, thereby minimizing or at least reducing pixel defects. The objects disclosed herein are not limited to those described above, and other objects not mentioned above may be clearly understood by those skilled in the art from the following description. The light-emitting element according to an embodiment of this specification includes: a first semiconductor layer; a plurality of first electrodes disposed on one side and the other side of the first semiconductor layer; a light-emitting layer disposed on the first semiconductor layer and between the plurality of first electrodes; a second semiconductor layer disposed on the light-emitting layer; a second electrode disposed on the second semiconductor layer; a passivation layer configured to cover at least a portion of the first semiconductor layer, at least a portion of the light-emitting layer, and at least a portion of the second semiconductor layer; and a plurality of first openings exposing a portion of the top surface and a portion of the side surface of the plurality of first electrodes, the first openings being disposed on the passivation layer. Therefore, disconnection defects of the first electrodes of the display device can be minimized. A display device according to another embodiment of this specification includes: a substrate defining pixels comprising a plurality of sub-pixels; a plurality of light-emitting elements located in the sub-pixels, the light-emitting elements comprising a plurality of first electrodes and second electrodes, each of the light-emitting elements comprising: a first semiconductor layer; a plurality of first electrodes located on one side and the other side of the first semiconductor layer; a light-emitting layer located on the first semiconductor layer and between the plurality of first electrodes; a second semiconductor layer located on the light-emitting layer; a second electrode located on the second semiconductor layer; and a passivation layer covering at least a portion of the first semiconductor layer, at least a portion of the light-emitting layer, and at least a portion of the second semiconductor layer, wherein a plurality of first opening portions exposing a portion of a top surface and a portion of a side surface of one of the first electrodes are located on the passivation layer. Therefore, it is possible to minimize or at least reduce disconnection defects in the light-emitting elements, thereby improving the luminous efficiency of the display device. A light-emitting element according to another embodiment of this specification includes: a first semiconductor layer; a plurality of first electrodes disposed on one side and the other side of the first semiconductor layer; a light-emitting layer disposed on the first semiconductor layer and disposed between the plurality of first electrodes; a second semiconductor layer disposed on the light-emitting layer; a second electrode disposed on the second semiconductor layer; and a passivation layer configured to cover the first semiconductor layer, the plurality of first electrodes, the second semiconductor layer and the second electrode, the passivation layer including portions of different thicknesses. Further details of the exemplary embodiments are contained in the detailed description and drawings. According to one embodiment of this specification, if the passivation layer is not disposed on a portion of the top surface or a portion of the side surface of each of the plurality of first electrodes disposed on one side and the other side of the light-emitting element, the height of the top surface of the passivation layer disposed around the first electrodes can be reduced. According to one embodiment of this specification, the height of the top surface of the passivation layer on the top surface or a portion of the side surface of the first electrode is reduced, which can suppress the problem of damage to the connecting electrode disposed on the passivation layer and connected to the first electrode during the manufacturing process. According to one embodiment of this specification, a disconnection defect that occurs between the first electrode and the connecting electrode during etching of the first electrode can be suppressed. According to one embodiment of this specification, a light-emitting element in which a portion of a plurality of first electrodes is exposed and a display device including the first electrodes can minimize or at least reduce the occurrence of pixel defects due to the disconnection of the first electrodes. The effects disclosed herein are not limited to those illustrated above; many more effects are included in this specification. The advantages, features, and methods for achieving these advantages and features will become apparent from the exemplary embodiments described in detail below and the accompanying drawings. However, this disclosure is not limited to the exemplary embodiments described herein, but will be implemented in various forms. Exemplary embodiments are provided by way of example only to enable those skilled in the art to fully understand the content and scope of this disclosure. The shapes, dimensions, scales, angles, and numbers disclosed in the drawings to illustrate embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Similar reference numerals generally denote similar elements throughout the specification. Furthermore, in the following description of this disclosure, detailed descriptions of known related technologies may be omitted to avoid obscuring the essential points of this disclosure. When terms such as "comprising," "having," and "including" are used herein, they may be used with other parts unless they are used in conjunction with the term "only." Terms such as "comprising," "having," and "including" as used in this statement are generally intended to allow for the addition of other components. Unless otherwise stated, terms in the singular form may include plural cases. In the process of explaining the components, although the error or tolerance range is not explicitly stated, the components are interpreted as including common error ranges. In the description of positional relationships, for example, when the positional relationship between two components is described as "above", "over", "below" and "below", one or more other components may be arranged between the two components unless more restrictive terms such as "just" or "directly" are used. When one element or layer is placed "on" another element or layer, other layers or elements can be directly inserted into the other element or between the elements. Although terms such as "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. Therefore, the first component mentioned below may be a second component in the technical concept disclosed herein. Similar reference numerals generally indicate similar components throughout the specification. For ease of description, the dimensions and thickness of each component shown in the figures are described, and this disclosure is not limited to the dimensions and thickness of the components shown. As will be fully understood by those skilled in the art, the features of the embodiments of this disclosure may be coupled or combined in part, and may interact and influence each other in various ways. The embodiments may be implemented independently of each other or in combination with each other. The embodiments of this disclosure will now be described in detail with reference to the drawings. Figure 1 is a top view of a light-emitting element according to an embodiment of this specification. Figure 2 is a cross-sectional view obtained along line II-II' in Figure 1 according to an embodiment of this specification. Referring to Figures 1 and 2, the light-emitting element LED according to the embodiments of this specification includes a first semiconductor layer NL, a plurality of first electrodes NE, a light-emitting layer EL, a second semiconductor layer PL, a second electrode PE, and a passivation layer PAS. The first semiconductor layer NL can be a layer formed by doping a specific material containing an n-type dopant or a p-type dopant. For example, the first semiconductor layer NL can be a layer formed by doping a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs) with an n-type dopant. The n-type dopant may be silicon (Si), germanium, tin (Sn), etc. However, this specification is not limited to this. Multiple first electrodes NE are disposed on one side and the other side of the first semiconductor layer NL. For example, these first electrodes may be a plurality of n-type electrodes. These first electrodes may be electrodes used for electrically connecting the driving transistor DT to the first semiconductor layer NL. These first electrodes NE are disposed on the top surface of the opposite two side portions of the first semiconductor layer NL exposed by the light-emitting layer EL and the second semiconductor layer PL. Each of these first electrodes NE can have a fan-shaped planar shape. In this case, the apex of the planar shape of each of the plurality of first electrodes NE can be positioned near the light-emitting layer EL. An arc-shaped side having the planar shape of each of the plurality of first electrodes NE can be provided on the outer side away from the light-emitting layer EL. This specification is not limited thereto. The first electrode NE can be circular, elliptical, or polygonal. At least a portion of the side surface of each of the first electrodes NE and at least a portion of the top surface of each of the plurality of first electrodes NE may be covered by the passivation layer PAS described below. Furthermore, another portion of the side surface of each of the plurality of first electrodes NE and another portion of the top surface of each of the plurality of first electrodes NE may be exposed without being covered by the passivation layer PAS. Specifically, at least a portion of the side surface of each of the plurality of first electrodes NE adjacent to the light-emitting layer EL and at least a portion of the top surface of each of the plurality of first electrodes NE may be covered by the passivation layer PAS. Therefore, at least a portion of the side surface of each of the plurality of first electrodes NE and another portion of the top surface of each of the plurality of first electrodes NE may be exposed without being covered by the passivation layer PAS. Multiple first electrodes NE can be configured such that the distance between the side closest to the light-emitting layer EL and the side of the light-emitting layer EL is shorter than the distance between the side furthest from the light-emitting layer EL and the end of the first semiconductor layer NL in a cross-sectional view. The multiple first electrodes NE can be configured to be closer to the light-emitting layer EL than the end of the first semiconductor layer NL. The multiple first electrodes NE can be made of conductive materials, such as transparent conductive materials like indium tin oxide (ITO) or indium zinc oxide (IZO), or opaque conductive materials like titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof. However, this specification is not limited to these. A light-emitting layer EL is disposed on a first semiconductor layer NL and between a plurality of first electrodes NE. The light-emitting layer EL emits light by receiving holes and electrons from the first semiconductor layer NL and the second semiconductor layer PL, as described below. The light-emitting layer EL can be configured as a single-layer or multi-quantum well (MQW) structure. For example, the light-emitting layer EL can be made of indium gallium nitride (InGaN), gallium arsenide (GaAs), gallium nitride (GaN), or the like. However, this specification is not limited thereto. A second semiconductor layer PL is disposed on the light-emitting layer EL. The second semiconductor layer PL can be formed by doping a p-type dopant into a specific material. For example, the second semiconductor layer PL can be a layer formed by doping a p-type dopant into a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). In this case, the p-type dopant can be magnesium, zinc (Zn), beryllium (Be), or similar substances. However, this specification is not limited to this. The second electrode PE is disposed on the second semiconductor layer PL. The second electrode PE can be used to electrically connect a power line to an electrode of the second semiconductor layer PL. The side surface of the second electrode PE can be covered by a passivation layer PAS, which will be described below. In addition, at least a portion of the top surface of the second electrode PE can be covered by the passivation layer PAS. Therefore, another portion of the top surface of the second electrode PE is not covered by the passivation layer PAS and is exposed. The planar shape of the second electrode PE can be circular, elliptical, or polygonal. The second electrode PE can be disposed on the center portion of the top surface of the second semiconductor layer PL. The second electrode PE can be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material, such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof. However, this specification is not limited to these. Meanwhile, either the first electrode NE or the second electrode PE of the light-emitting element LED can contain ferromagnetic element materials such as iron (Fe), cobalt (Co), or nickel (Ni). Therefore, the light-emitting element LED can be moved by a magnetic field. However, this specification is not limited to this. The passivation layer PAS covers at least a portion of the first semiconductor layer NL, at least a portion of the light-emitting layer EL, and at least a portion of the second semiconductor layer PL. The passivation layer PAS can cover the side surface of the first semiconductor layer NL. In addition, the passivation layer PAS can cover at least a portion of the top surface of the first semiconductor layer NL. The passivation layer PAS can include a first opening portion OA1 that exposes at least a portion of the top surface of the first semiconductor layer NL. Therefore, on the top surface of the first semiconductor layer NL, a portion of the end of the passivation layer PAS can be adjacent to the top surface of the first semiconductor layer NL. In addition, the exposed portion of the top surface of the first semiconductor layer NL can be set to be farther from the light-emitting layer EL than the first electrode NE. At least a portion of the end of the passivation layer PAS adjacent to the top surface of the first semiconductor layer NL can be separated from the first electrode NE. At least a portion of the planar shape of the first opening portion OA1 may include an arc or a polygon. In this case, the arc may be a convex shape facing away from the light-emitting layer EL. The arc-shaped side of the first opening portion OA1 may be disposed outside the arc-shaped side of the first electrode NE. At least one end of the first opening portion OA1 may be disposed outside at least one end of the first electrode NE. Therefore, the exposed first semiconductor layer NL may be disposed between the arc-shaped side of the first opening portion OA1 and the arc-shaped side of the first electrode NE. Therefore, the planar shape of the top surface of a portion of the first semiconductor layer NL exposed through the first opening portion OA1 may include arcs located on opposite sides. The passivation layer PAS can expose a portion of the top surface and a portion of the side surface of each of the plurality of first electrodes NE through the first opening portion OA1. Specifically, the passivation layer PAS can expose a portion of the arcuate side surface of the first electrode NE. The passivation layer PAS can cover a portion of the top surface of the first electrode NE connected to the straight side surface of the first electrode NE. The passivation layer PAS can expose a portion of the top surface of the first electrode NE connected to the arcuate side surface of the first electrode NE. The area of ​​the exposed top surface of the first electrode NE can be larger than the area of ​​the exposed top surface of the first semiconductor layer NL. A passivation layer PAS covers the side surface of the light-emitting layer EL. Furthermore, the passivation layer PAS covers the side and top surface of the second semiconductor layer PL. The passivation layer PAS covering the side and top surface of the second semiconductor layer PL and the side surface of the light-emitting layer EL can be connected to a portion of the side and top surface of the first electrode NE. Therefore, a portion of the side surface and a portion of the top surface of the first electrode NE adjacent to the light-emitting layer EL can be covered by the passivation layer PAS. The passivation layer PAS can cover the straight edge side surface of the first electrode NE and the portion of the top surface adjacent to the straight edge side surface. The side surface of the first electrode NE closest to the light-emitting layer EL can be set to be closer to the light-emitting layer EL than the side surface of the first opening portion OA1 closest to the light-emitting layer EL. The passivation layer PAS can cover the side surface of the second electrode PE. Furthermore, the passivation layer PAS can cover a portion of the top surface of the second electrode PE. Therefore, the passivation layer PAS can include a second opening portion OA2 exposing a portion of the top surface of the second electrode PE. The second opening portion OA2 can be located at the center of the top surface of the second electrode PE. The planar shape of the second opening portion OA2 can be circular or elliptical. The planar shape of the second opening portion OA2 can correspond to the planar shape of the top surface of the second electrode PE. The planar area of ​​the second opening portion OA2 can be smaller than the planar area of ​​the second electrode PE. The passivation layer PAS can be disposed on the second electrode PE and surround the second opening portion OA2. The second opening portion OA2 can be disposed between a plurality of first opening portions OA1. The distances from the second opening portion OA2 to the plurality of first opening portions OA1 can be equal to each other. Hereinafter, a display device 100 including a light-emitting element according to an embodiment of this specification will be described with reference to FIGS. 3 to 6. Figure 3 is a schematic diagram of the structure of a display device according to an embodiment of this specification. For ease of description, Figure 3 shows the display panel PN, gate driver GD, data driver DD, and timing controller TC among the various components of the display device 100. Furthermore, since the light-emitting elements (LEDs) of the display device 100 in Figures 3 to 6 are the same as those in Figures 1 to 2, further description of the light-emitting elements is unnecessary. Referring to FIG3, the display device 100 includes a display panel PN comprising a plurality of sub-pixels SP, a gate driver GD and a data driver DD configured to provide various types of signals to the display panel PN, and a timing controller TC configured to control the data driver DD and the gate driver GD. The gate driver GD responds to multiple gate control signals provided by the timing controller TC by providing multiple scan signals to multiple scan lines SL. Figure 1 shows a single gate driver GD configured to be separate from one side of the display panel PN. However, the number and arrangement of gate drivers GD are not limited in this respect. In response to multiple data control signals from the timing controller TC, the data driver DD converts the image data input from the timing controller TC into a data voltage using a reference gamma voltage. The data driver DD can then supply the converted data voltage to multiple data lines DL. The timing controller TC aligns the externally input image data and provides the image data to the data driver DD. The timing controller TC can utilize externally input synchronization signals, namely dot clock signals, data enable signals, and horizontal / vertical synchronization signals, to generate gate control signals and data control signals. Furthermore, the timing controller TC can control the gate driver GD and the data driver DD by providing the generated gate control signals and data control signals to them. The display panel PN is configured to display an image to the user and includes a plurality of subpixels SP. In the display panel PN, multiple scan lines SL and multiple data lines DL intersect each other, and each of the multiple subpixels SP is connected to both the scan lines SL and the data lines DL. Furthermore, although not shown in the diagram, the multiple subpixels SP can be connected to high-potential power lines, low-potential power lines, reference lines, etc., respectively. The display panel PN may have a display area AA and a non-display area NA configured to surround the display area AA. The display area AA is the area in the display device 100 where an image is displayed. The display area AA may include a plurality of sub-pixels SP constituting a plurality of pixels PX, and circuitry configured to operate the plurality of sub-pixels SP. These sub-pixels SP are the smallest units constituting the display area AA. n sub-pixels SP can constitute a single pixel PX. Light-emitting elements LEDs and thin-film transistors for operating the light-emitting elements LEDs may be provided in each of the plurality of sub-pixels SP. Depending on the type of display panel PN, the plurality of light-emitting elements LEDs may be defined in different ways. For example, in the case where the display panel PN is an inorganic light-emitting display panel PN, the light-emitting elements LEDs may be light-emitting diodes (LEDs) or micro light-emitting diodes (micro-LEDs). A plurality of signal lines are provided in the display area AA for transmitting various types of signals to multiple sub-pixels SP. For example, these signal lines may include multiple data lines DL for providing data voltage to the multiple sub-pixels SP, and multiple scan lines SL for providing gate voltage to the multiple sub-pixels SP. The multiple scan lines SL may extend in one direction within the display area AA and connect to the multiple sub-pixels SP. The multiple data lines DL may extend in a direction different from this direction within the display area AA and connect to the multiple sub-pixels SP. In addition, low-potential power lines, high-potential power lines, etc., may be further provided in the display area AA. However, this specification is not limited to this. The non-display area NA can be defined as an area where no image is displayed, i.e., an area extending from the display area AA. The non-display area NA may include link lines and pad electrodes for transmitting signals to the sub-pixels SP in the display area AA. Alternatively, the non-display area NA may include driver circuitry such as gate driver circuitry and data driver circuitry. Meanwhile, the non-display area NA can be located on the rear surface of the display panel PN, i.e., on the surface where there are no sub-pixels SP. Alternatively, the non-display area NA can be excluded. However, the instruction manual is not limited to the configuration shown in the figures. Meanwhile, drivers such as gate drivers (GD), data drivers (DD), and timing controllers (TC) can be connected to the display panel PN in various ways. For example, the gate driver (GD) can be installed in the non-display area NA using a gate-in-panel (GIP) method, or between multiple sub-pixels (SP) in the display area AA using a gate-in-active area (GIA) method. For example, the data driver (DD) and timing controller (TC) can be formed on separate flexible films and printed circuit boards, and electrically connected to the display panel PN by bonding the flexible film and printed circuit board to pad electrodes formed in the non-display area NA of the display panel PN. When the gate driver (GD) is installed using the GIP method and the data driver (DD) and timing controller (TC) transmit signals to the display panel PN through the pad electrodes in the non-display area NA, it is necessary to ensure sufficient space in the non-display area NA to accommodate the gate driver (GD) and the pad electrodes, which may increase the bezel size. Alternatively, in a scenario where the gate driver GD is mounted within the display area AA using the GIA method, forming an edge line SRL connecting the signal lines on the front surface of the display panel PN to the pad electrodes on the rear surface of the display panel PN to bond the flexible film and printed circuit board to the rear surface of the display panel PN, the non-display area NA on the front surface of the display panel PN can be minimized or at least reduced. In other words, if the gate driver GD, data driver DD, and timing controller TC are connected to the display panel PN using the aforementioned method, a virtually bezel-less design can be achieved. A more detailed description will follow with reference to Figures 4A and 4B. Figure 4A is a partial cross-sectional schematic diagram of a display device according to an embodiment of this specification. Figure 4B is a perspective schematic diagram of a tiled display device according to an embodiment of this specification. First, referring to FIG4A, a plurality of pad electrodes for transmitting various types of signals to multiple sub-pixels SP are provided in the non-display area NA of the display panel PN. For example, a first pad electrode PAD1 configured to transmit signals to multiple sub-pixels SP is provided in the non-display area NA on the front surface of the display panel PN. A second pad electrode PAD2 electrically connected to a drive assembly such as a flexible film and a printed circuit board is provided in the non-display area NA on the rear surface of the display panel PN. In this case, although not shown in the diagram, various types of signal lines, such as scan lines SL and data lines DL, connected to multiple sub-pixels SP, can extend from the display area AA to the non-display area NA and be electrically connected to the first pad electrode PAD1. Furthermore, a side line SRL is provided along the side of the display panel PN. The side line SRL electrically connects the first pad electrode PAD1 on the front surface of the display panel PN to the second pad electrode PAD2 on the rear surface of the display panel PN. Therefore, signals received from the driving components on the rear surface of the display panel PN can be transmitted to multiple sub-pixels SP through the second pad electrode PAD2, the side line SRL, and the first pad electrode PAD1. Thus, a signal transmission path is defined from the front surface of the display panel PN to the side and rear surfaces, and this signal transmission path can minimize or at least reduce the area of ​​the non-display area NA of the display panel PN. Furthermore, referring to FIG4B, a tiled display device TD with a large screen can be realized by connecting multiple display devices 100. In this case, as shown in FIG4A, when the tiled display device TD is realized by using display devices 100 with minimized bezels, the seam area between the display devices 100 where no image is displayed can be minimized or at least reduced, thereby improving display quality. For example, multiple sub-pixels SP can constitute a single pixel PX. The spacing between the outermost pixel PX of one display device 100 and the outermost pixel PX of another adjacent display device 100 can be made equal to the spacing between pixels PX in one display device 100. Therefore, by achieving a constant spacing between pixels PX between display devices 100, the seam area can be minimized. However, as shown in Figures 4A and 4B, the display device 100 according to the embodiments of this specification can be a general display device 100 with a bezel. However, this specification is not limited thereto. Figure 5 is a cross-sectional schematic diagram of a sub-pixel of a display device according to an embodiment of this specification. Referring to FIG5, a substrate 110, a buffer layer 111, a gate insulating layer 112, a first interlayer insulating layer 113, a second interlayer insulating layer 114, a first planarization layer 115, a bonding layer 116, a second planarization layer 117, a third planarization layer 118, a driving transistor DT, a light-emitting element LED, a plurality of reflective electrodes RE, a plurality of first connecting electrodes CE1, second connecting electrodes CE2, a light-blocking layer LS, and an auxiliary electrode LE may be disposed on each of the plurality of sub-pixels SP of the display panel PN of the display device 100 according to an embodiment of this specification. First, the substrate 110 is an assembly for supporting various components included in the display device 100 and may be made of an insulating material. For example, the substrate 110 may be made of glass, resin, or similar materials. Furthermore, the substrate 110 may contain a plastic such as a polymer and may be made of a flexible material. A light-blocking layer LS may be disposed on each of the plurality of sub-pixels SP on the substrate 110. The light-blocking layer LS prevents light from entering the active layer ACT of the driving transistor DT, which will be described below, from the underside of the substrate 110. The light-blocking layer LS can block light entering the active layer ACT of the driving transistor DT, thereby minimizing or at least reducing the leakage current. A buffer layer 111 may be disposed on the substrate 110 and the light-blocking layer LS. The buffer layer 111 can reduce the penetration of moisture or dopants through the substrate 110. For example, the buffer layer 111 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, this specification is not limited thereto. However, depending on the type of substrate 110 or the type of transistor, the buffer layer 111 may be excluded. However, this specification is not limited thereto. The driving transistor DT is disposed on the buffer layer 111. The driving transistor DT may include an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. The active layer ACT can be disposed on the buffer layer 111. The active layer ACT can be made of a semiconductor material such as oxide semiconductor, amorphous silicon, or polycrystalline silicon. However, this specification is not limited thereto. The buffer layer 111 may include contact holes for connecting the auxiliary electrode LE and the photoblocking layer LS. Gate insulating layer 112 may be disposed on active layer ACT. Gate insulating layer 112 is an insulating layer that insulates active layer ACT from gate electrode GE. Gate insulating layer 112 may include contact holes for connecting auxiliary electrode LE and barrier layer LS. Furthermore, gate insulating layer 112 may further include contact holes for connecting source electrode SE and active layer ACT. For example, gate insulating layer 112 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, this specification is not limited thereto. The gate electrode GE may be disposed on the gate insulating layer 112. The gate electrode GE may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof. However, this specification is not limited thereto. An auxiliary electrode LE may be disposed on the gate insulating layer 112. The auxiliary electrode LE is an electrode that electrically connects the light-blocking layer LS disposed below the buffer layer 111 to either the source electrode SE or the drain electrode DE on the second interlayer insulating layer 114. For example, the light-blocking layer LS may be electrically connected to either the source electrode SE or the drain electrode DE through the auxiliary electrode LE, preventing it from operating as a floating gate, thereby minimizing or at least reducing the threshold voltage variation of the driving transistor DT caused by the floating light-blocking layer LS. As shown, the light-blocking layer LS is connected to the source electrode SE. However, the light-blocking layer LS may be connected to the drain electrode DE. However, this specification is not limited to this. A first interlayer insulating layer 113 may be disposed on the gate electrode GE and the auxiliary electrode LE. The first interlayer insulating layer 113 may include contact holes for connecting the source electrode SE and the auxiliary electrode LE. Furthermore, the first interlayer insulating layer 113 may include contact holes for connecting the source electrode SE and the active layer ACT. The first interlayer insulating layer 113 is an insulating layer for protecting components disposed beneath it. The first interlayer insulating layer 113 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, this specification is not limited thereto. The conductive layer TM may be disposed on the first interlayer insulating layer 113. The conductive layer TM may be disposed on the gate electrode GE. The conductive layer TM and the gate electrode GE may together form a storage capacitor (not shown in the figure). However, according to the embodiment, the conductive layer TM may be omitted. The second interlayer insulating layer 114 may be disposed on the conductive layer TM. Contact holes may be formed in the second interlayer insulating layer 114, through which the source electrode SE and drain electrode DE are connected to the active layer ACT. The second interlayer insulating layer 114 may be an insulating layer for protecting devices disposed beneath it. The second interlayer insulating layer 114 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, this specification is not limited thereto. The source electrode SE and drain electrode DE, electrically connected to the active layer ACT, may be disposed on the second interlayer insulating layer 114. The source electrode SE may be connected to the active layer ACT and the auxiliary electrode LE through contact holes contained in the gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114. The drain electrode DE may be connected to the active layer ACT through contact holes contained in the gate insulating layer 112, the first interlayer insulating layer 113, and the second interlayer insulating layer 114. Each of the source electrode SE and the drain electrode DE may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof. However, this specification is not limited thereto. The first planarization layer 115 can be disposed on the driving transistor DT. The first planarization layer 115 can planarize the upper part of the substrate 110 on which the driving transistor DT is disposed. The first planarization layer 115 may include contact holes for connecting the reflective electrode RE and the drain electrode DE. The first planarization layer 115 can be configured as a single layer or multiple layers and is made of, for example, photoresist or acrylic-based organic materials. However, this specification is not limited thereto. At least one reflective electrode RE may be provided on the first planarization layer 115. The reflective electrode RE may be connected to the drain electrode DE of the driving transistor DT through a contact hole included in the first planarization layer 115. Furthermore, multiple reflective electrodes RE may electrically connect the light-emitting element LED to a power line (not shown in the figure). In addition, the reflective electrode RE may be disposed below the light-emitting element LED and serve as a reflector for reflecting light emitted from the light-emitting element LED upwards to the upper part of the light-emitting element LED. Multiple reflective electrodes RE may be made of a conductive material with excellent reflective properties and reflect light emitted from the light-emitting element LED upwards to the upper part of the light-emitting element LED. A bonding layer 116 may be disposed on the reflective electrode RE. The bonding layer 116 may be coated on the front surface of the substrate 110, and the bonding layer 116 may fix the light-emitting element LED disposed on the bonding layer 116. The bonding layer 116 may include contact holes for connecting the first connecting electrode CE1 and the reflective electrode RE, and the bonding layer 116 may be made of an organic material. In this case, for example, the bonding layer 116 may be made of any material selected from adhesive polymers, epoxy resists, UV resins, polyimide-based materials, acrylate-based materials, polyurethane-based materials, and polydimethylsiloxane (PDMS). However, this specification is not limited thereto. Multiple light-emitting elements (LEDs) can be provided on the bonding layer 116 and disposed on each of the multiple sub-pixels SP. These LEDs can be elements configured to emit light by using current, and include LEDs configured to emit red, green, blue, etc. The multiple LEDs can achieve various colors of light, including white light, by using combinations of red, green, blue, etc. For example, each of the multiple LEDs can be a light-emitting diode (LED) or a micro-LED. However, this specification is not limited to this. The second planarization layer 117 may be disposed on the bonding layer 116. In this case, the second planarization layer 117 may be disposed around the first semiconductor layer NL disposed beneath the plurality of first electrodes NE of the plurality of light-emitting elements LED. Therefore, the plurality of LED light-emitting elements can be fixed and protected. The second planarization layer 117 may expose the top surface of the first semiconductor layer NL. The second planarization layer 117 may include at least one contact hole for connecting the first connecting electrode CE1 and the reflective electrode RE. For example, the second planarization layer 117 may be made of photoresist or acrylic-based organic material. However, this specification is not limited thereto. Multiple first connection electrodes CE1 may be disposed on the second planarization layer 117. These multiple first connection electrodes CE1 are electrodes respectively disposed on multiple sub-pixels SP and electrically connected to the light-emitting element LED and the driving transistor DT. These first connection electrodes CE1 may be connected to the reflective electrode RE through contact holes formed in the second planarization layer 117 and the bonding layer 116. Therefore, the multiple first connection electrodes CE1 may be electrically connected to either the source electrode SE or the drain electrode DE of the driving transistor DT through the reflective electrode RE; however, this specification is not limited to this. A single first connection electrode CE1 may be directly electrically connected to either the source electrode SE or the drain electrode DE of the driving transistor DT. Multiple first connection electrodes CE1 can be respectively connected to multiple first electrodes NE of multiple light-emitting elements (LEDs). Multiple first connection electrodes CE1 can be formed to cover the top surface and part of the side surface of the first semiconductor layer NL. In this case, the multiple first connection electrodes CE1 can be connected to a portion of the top surface of the first semiconductor layer NL through multiple first openings OA1 of the multiple light-emitting elements (LEDs). Furthermore, the multiple first connection electrodes CE1 can cover the end of the passivation layer PAS disposed on a portion of the top surface of the first semiconductor layer NL. Therefore, the first connection electrodes CE1 can be disposed outside the multiple light-emitting elements (LEDs) and on the top surface of the passivation layer PAS disposed on the top surface of the first semiconductor layer NL. In other words, the first semiconductor layer NL, the passivation layer PAS, and the first connection electrodes CE1 can be stacked sequentially outside the multiple light-emitting elements (LEDs). The first semiconductor layer NL and the first connection electrodes CE1 can be stacked sequentially in the region adjacent to the multiple light-emitting elements (LEDs). Simultaneously, the first connection electrodes CE1 can be provided as a single first connection electrode CE1, and the single first connection electrode CE1 can be electrically connected to the multiple first electrodes NE. Multiple first connecting electrodes CE1 can be disposed within multiple light-emitting elements (LEDs) and cover multiple first electrodes NE. Specifically, the multiple first connecting electrodes CE1 can be adjacent to a portion of the upper surface and side surface of each of the multiple first electrodes NE exposed by multiple first openings OA1, and directly adjacent to the upper surface of the first semiconductor layer NL exposed through the first openings OA1 in FIG. 2. Furthermore, each of the multiple first connecting electrodes CE1 can be disposed on a passivation layer PAS disposed on a portion of the top surface of each of the multiple first electrodes NE. In other words, the multiple first electrodes NE, the passivation layer PAS, and the first connecting electrodes CE1 can be stacked sequentially within the multiple light-emitting elements (LEDs). In addition, the multiple first electrodes NE and the multiple first connecting electrodes CE1 can be stacked sequentially in the region adjacent to the multiple light-emitting elements (LEDs). Multiple first connecting electrodes CE1 may be respectively disposed on a portion of the top surface of the first semiconductor layer NL and a portion of the side surface of the second semiconductor layer PL. The multiple first connecting electrodes CE1 may be disposed at a position lower than the top surface of the second semiconductor layer PL. In other words, the highest top surface of the multiple first connecting electrodes CE1 may be lower than the top surface of the second semiconductor layer PL. Meanwhile, the first connection electrode CE1 connecting the driving transistor DT, which is disposed on each of the plurality of sub-pixels SP, and the light-emitting element LED can be independently disposed on each of the plurality of sub-pixels SP. A third planarization layer 118 may be disposed on a plurality of first connecting electrodes CE1 and a second planarization layer 117. The third planarization layer 118 may include contact holes for connecting the second connecting electrode CE2 to a power line (not shown). The third planarization layer 118 may expose at least a portion of the top surface of the second semiconductor layer PL of the plurality of light-emitting elements LEDs. Furthermore, the third planarization layer 118 may expose the second electrode PE by exposing a second opening portion OA2. The third planarization layer 118 may be configured to surround the side surface of the second semiconductor layer PL, and the third planarization layer 118 may cover all of the first connecting electrodes among the plurality of first connecting electrodes CE1. Therefore, the height of the top surface of the third planarization layer 118 may be greater than the height of the highest top surface among the plurality of first connecting electrodes CE1. The second connecting electrode CE2 can be disposed on the third planarization layer 118. The second connecting electrode CE2 can be connected to the second electrode PE of each of the plurality of light-emitting elements (LEDs). Although not shown in the figures, the second connecting electrode CE2 can be electrically connected to a power line (not shown) through a reflective electrode RE. The second connecting electrode CE2 can be disposed on the plurality of light-emitting elements (LEDs) and cover the second opening portion OA2. Therefore, the second connecting electrode CE2 can be adjacent to the top surface of the second electrode PE exposed in the second opening portion OA2. The second connecting electrode CE2 can cover the top surface of the uppermost passivation layer PAS disposed on each of the plurality of light-emitting elements (LEDs). Furthermore, the second connecting electrode CE2 can be formed to fill the second opening portion OA2. Therefore, the second connecting electrode CE2 can be adjacent to the side surface of the passivation layer PAS adjacent to the second opening portion OA2. The second connecting electrode CE2 and the first connecting electrode CE1 can be disposed on different layers. The second connecting electrode CE2 can be disposed at a higher position than the first connecting electrode CE1. Therefore, the highest point of the top surface of the first connecting electrode CE1 can be lower than the bottom surface of the second connecting electrode CE2. The first connecting electrode CE1 and the second connecting electrode CE2 can be spaced apart from each other in the vertical direction. The embankment BB can be disposed on the third planarization layer 118. The embankment BB is a component used to separate adjacent sub-pixels SP. The embankment BB can be configured not to overlap with the light-emitting layer EL of each of the plurality of light-emitting elements LED. The embankment BB can be disposed on and partially overlap with the plurality of first connecting electrodes CE1. Conversely, the embankment BB can be configured to be spaced apart from the second connecting electrode CE2. The embankment BB can be made of acrylic resin, benzocyclobutene (BCB)-based resin, or polyimide, and further contains a black component. However, this specification is not limited thereto. A light-emitting element can be a semiconductor light-emitting element that emits light when an electric current is applied to it. In this case, the light-emitting element emits light when electrons and holes injected from different electrodes meet in the light-emitting layer. In this case, the different electrodes of the light-emitting element are connected to a driving transistor or a power line. For example, when one electrode of the light-emitting element is connected to a driving transistor, the other electrode is connected to a power line. As mentioned above, the light-emitting element comprises at least two different electrodes. In this case, the two different electrodes may sometimes be disposed on the same plane, or the two different electrodes may be disposed on different planes. For example, one electrode may be disposed on a plane higher than the other electrode. As mentioned earlier, separate connecting electrodes can be used to connect different electrodes of the light-emitting element to the driving transistor or power line. In this case, if the different electrodes of the light-emitting element are placed on different planes, the multiple connecting electrodes connected to the different electrodes are also placed in different positions. In this case, a problem may occur: the connecting electrodes may be damaged during the process of placing different connecting electrodes on different electrodes. The above problems will be described in detail below with reference to Figures 6A and 6B. Figures 6A and 6B are scanning electron microscope (SEM) images of the light-emitting element during the steps of applying photoresist and etching photoresist after processing the first connecting line in the manufacturing process of the comparative example display device. Referring to Figures 6A and 6B, when one electrode PE of the light-emitting element is disposed on a plane higher than the other electrode NE, considering the manufacturing process, the first connecting electrode CE1 is disposed on the electrode NE disposed on the lower plane. In this case, the first connecting electrode CE1 is disposed on a layer to cover the components disposed below the first connecting electrode CE1. Therefore, in light-emitting elements exposing different electrodes NE and PE, the first connecting electrode CE1 is disposed not only on the electrode NE disposed on the lower plane, but also on the other electrode PE disposed on the higher plane. However, as mentioned earlier, since the two electrodes (first electrode NE and second electrode PE) of the light-emitting element need to be subjected to different voltages, it is not necessary to provide a common connection electrode on the first electrode NE on the lower plane and the second electrode PE on the higher plane. Therefore, it is necessary to provide another connection electrode on the second electrode PE located on the higher plane to apply a voltage different from that of the first electrode NE located on the lower plane. Therefore, it is necessary to remove the connection electrode CE provided on the second electrode PE on the higher plane, which was formed during the process of forming the first connection electrode CE1 on the first electrode NE on the lower plane of the light-emitting element. In this case, since it is necessary to maintain the first connection electrode CE1 connected to the first electrode NE on the lower plane of the light-emitting element and prevent it from being damaged, a photoresist PR is applied to the first electrode NE and the first connection electrode CE1 connected to it to protect the first electrode NE on the lower plane and the first connection electrode CE1 connected to it. The photoresist PR is set to initially cover the entire light-emitting element. Then, in order to remove the first connection electrode CE1 connected to the electrode PE on the higher plane of the light-emitting element, the photoresist PR is etched until the first connection electrode CE1 is exposed. Meanwhile, due to material properties, the top surface of the photoresist PR is not applied unevenly. In other words, when the height of the upper surface of the photoresist PR applied to the high plane of the light-emitting element differs from the height of the upper surface of the photoresist PR applied to the low plane, a predetermined level difference occurs. In this case, the height of the top surface of the photoresist PR decreases from the high plane of the light-emitting element to the low plane, and decreases further with increasing distance from the light-emitting element. In other words, as shown in FIG6A, the height H1 between the top surface of the photoresist PR disposed on the side of the first connecting electrode CE1 disposed on the low plane of the light-emitting element adjacent to the high plane and the first connecting electrode CE1 is greater than the height H2 between the top surface of the photoresist PR disposed on the side away from the high plane of the light-emitting element and the first connecting electrode CE1. Therefore, as shown in Figure 6B, during the etching of the photoresist PR, the top surface height of the photoresist PR gradually decreases with position. Thus, the top surface height H2' of the photoresist PR on the side furthest from the high plane of the light-emitting element is lower than the top surface height H1' of the photoresist PR closer to the high plane of the light-emitting element. Therefore, when the photoresist PR is etched, the first connection electrode CE1 located on the first electrode NE on the low plane of the light-emitting element is exposed (A) in the first connection electrode CE1. Therefore, since a portion of the first connection electrode CE1 is exposed by the photoresist PR (A), the process of continuously etching the photoresist PR and removing unnecessary first connection electrodes CE1 during the etching process can lead to the disconnection problem of the first connection electrode CE1 being damaged. Therefore, according to the embodiments of this specification, the light-emitting element LED and the display device 100 including the light-emitting element LED are not provided on a portion of the top surface and a portion of the side surface of the plurality of first electrodes NE disposed on the low plane of the light-emitting element LED. As mentioned above, the fact that the passivation layer PAS is not provided on a portion of the top surface of the plurality of first electrodes NE allows for a reduction in the height of a portion of the top surface of the passivation layer PAS. Since the height of the top surface of the passivation layer PAS is reduced as mentioned above, considering this process, the distance between the top surface of the photoresist PR and the top surface of the passivation layer PAS increases. Therefore, it is possible to prevent the underlying components from being exposed by etching the photoresist PR in this process. Furthermore, it is also possible to prevent damage to the underlying components when they are exposed. Furthermore, according to the embodiments of this specification, the light-emitting element LED and the display device 100 including the light-emitting element LED, compared to the end of the first semiconductor layer NL (for example, the end in the horizontal direction, i.e., the lateral direction or side direction, of the first semiconductor layer NL as shown in FIG. 2) to the light-emitting layer EL, the plurality of first electrodes NE can be positioned closer to the light-emitting layer EL. In other words, the plurality of first electrodes NE can be respectively disposed within the light-emitting element LED to which a relatively high height of photoresist PR is applied. Therefore, the exposure of the plurality of first electrodes NE can be prevented by the etching process of photoresist PR, thereby preventing damage to the first electrodes NE. In addition, since the plurality of first electrodes NE are disposed inside the light-emitting element LED, it is possible to ensure that the passivation layer PAS is directly disposed in the space on the top surface of the first semiconductor layer NL adjacent to the end of the first semiconductor layer NL. Therefore, the passivation layer PAS and some of the first electrodes among the plurality of first electrodes NE can be spaced apart from each other. Therefore, it is easier to reduce a portion of the height of the top surface of the passivation layer PAS. Figure 7 is a top plan view of a light-emitting element according to another embodiment of this specification. Figure 8 is a cross-sectional view obtained along line VIII-VIII' in Figure 7 according to an embodiment of the present invention. Except for the provision of the passivation layer PAS, the light-emitting elements LED' in Figures 7 and 8 are substantially the same in configuration as the light-emitting elements LED in Figures 1 and 2. Therefore, repeated descriptions of the same components will be omitted. Referring to Figures 7 and 8, a light-emitting element LED' according to another embodiment of this specification includes: a first semiconductor layer NL, a plurality of first electrodes NE disposed on one side and the other side of the first semiconductor layer NL, a light-emitting layer EL disposed on the first semiconductor layer NL and disposed between the plurality of first electrodes NE, a second semiconductor layer PL disposed on the light-emitting layer EL, a second electrode PE disposed on the second semiconductor layer PL, and a passivation layer PAS configured to cover the first semiconductor layer NL, the plurality of first electrodes NE, the second semiconductor layer PL, and the second electrode PE. In other words, the passivation layer PAS can be provided to cover all elements disposed below the passivation layer PAS. Furthermore, the passivation layer PAS comprises at least one portion with different thicknesses. The passivation layer PAS may comprise three or more portions with different thicknesses. For example, the passivation layer PAS may comprise a first portion T1-1, T1-2, T1-3 with the smallest thickness, a second portion T2-1, T2-2 with medium thickness, and a third portion T3-1, T3-2, T3-3, T3-4 with the largest thickness. However, this specification is not limited thereto. In addition to the above-mentioned multiple portions, the passivation layer PAS may further comprise at least one portion with different thicknesses. This structure is described more specifically with reference to FIG8. In the top surface of the first semiconductor layer NL, the passivation layer PAS is disposed on the top surface of the first semiconductor layer NL disposed outside these first electrodes NE. In this case, the passivation layer PAS may comprise at least one portion with different thicknesses. For example, the passivation layer PAS disposed on the first semiconductor layer NL outside the multiple first electrodes NE may comprise a first portion T1-1 with a small thickness and a third portion T3-1 with a large thickness; that is, the second portion with a medium thickness may be omitted. Furthermore, the thinner first portion T1-1 can be located near the first electrode NE, and the thicker third portion T3-1 can be located away from the first electrode NE. Therefore, by setting the thinner first portion T1-1 away from the light-emitting layer EL, the first electrode NE exists between the first portion T1-1 and the light-emitting layer EL, and the first portion T1-1 can be set to surround at least a portion of the first electrode NE. The passivation layer PAS disposed on a plurality of first electrodes NE may include at least one portion with different thicknesses. For example, the passivation layer PAS disposed on a plurality of first electrodes NE may include a first portion T1-2 with a small thickness and a third portion T3-2 with a large thickness. In this case, the third portion T3-2 with a large thickness can be disposed near the light-emitting layer EL. The first portion T1-2 with a small thickness disposed on a plurality of first electrodes NE may extend to a portion of the side of each of the plurality of first electrodes NE and connect to the first portion T1-1 with a smaller thickness disposed on a passivation layer PAS disposed on a first semiconductor layer NL. Therefore, the thickness of the first portion T1-1 with a small thickness disposed on a passivation layer PAS disposed on a first semiconductor layer NL and the thickness of the first portion T1-2 with a small thickness disposed on each of the plurality of first electrodes NE are substantially the same or similar. However, this specification is not limited thereto. Furthermore, the thickness of the third portion T3-2 of the passivation layer PAS with a large thickness on the plurality of first electrodes NE can be substantially equal to or similar to the thickness of the third portion T3-1 of the passivation layer PAS with a large thickness on the first semiconductor layer NL. However, this specification is not limited thereto. The passivation layer PAS disposed on the second electrode PE may include a first portion T1-3 of small thickness and a third portion T3-4 of large thickness. In this case, the first portion T1-3 of small thickness may be disposed on the central portion of the second electrode PE, and the third portion T3-4 of large thickness may be disposed on the second electrode PE and disposed along the edge of the second electrode PE. The third portion T3-4 of the passivation layer PAS with large thickness may be disposed on the second electrode PE and surround the first portion T1-3 of small thickness. In the passivation layer PAS on the second electrode PE, the third portion T3-4 of large thickness may extend beyond the second electrode PE and connect to the passivation layer PAS on the second semiconductor layer PL. The passivation layer PAS on the second semiconductor layer PL may extend along the side of the second semiconductor layer PL and connect to the thick third portion T3-2 of the passivation layer PAS on the plurality of first electrodes NE. Therefore, the thickness of the third portion T3-4 of the passivation layer PAS on the second electrode PE, the thickness of the third portion T3-3 of the passivation layer PAS on the second semiconductor layer PL, and the thickness of the third portion T3-2 of the passivation layer PAS on the plurality of first electrodes NE can be substantially equal to or similar to each other. However, this specification is not limited thereto. The first portions T1-1, T1-2, and T1-3 of the passivation layer PAS disposed on the first semiconductor layer NL outside the plurality of first electrodes NE, on the first electrodes NE, and on the second electrode PE, may be substantially equal or similar in thickness. However, this specification is not limited thereto. Furthermore, the first portions T1-1, T1-2, and T1-3 of the passivation layer PAS disposed on the first semiconductor layer NL outside the plurality of first electrodes NE, on the first electrodes NE, and on the second electrode PE, may be thinner than the thicknesses of the second portions T2-1 and T2-2 disposed on the first semiconductor layer NL outside the plurality of first electrodes NE, on the first electrodes NE, and on the second electrode PE. Furthermore, the first portions T1-1, T1-2, and T1-3 of the passivation layer PAS disposed on the first semiconductor layer NL outside the first semiconductor layer NL, on the first electrodes NE, and on the second electrode PE, may be the thinnest of the entire passivation layer PAS. These components can be used to protect multiple first electrodes NE and second electrodes PE, and can be removed if necessary. For example, during the manufacturing of a display device, if necessary, the first portions T1-1 and T1-2 of the passivation layer PAS disposed on the first semiconductor layer NL outside the multiple first electrodes NE can be removed as needed. Therefore, multiple first opening portions OA1 can be formed by removing the first portions T1-1 and T1-2. Multiple first connecting electrodes CE1 can be connected to the multiple first electrodes NE through the aforementioned formed first opening portions OA1. Furthermore, if necessary, the first portion T1-3 of the passivation layer PAS disposed on the second electrode PE can be removed, thereby forming a second opening portion OA2. The second connecting electrode CE2 can be connected to the second electrode PE through the aforementioned formed second opening portion OA2. Meanwhile, the thickness of the third portion T3-1, the third portion T3-2, and the third portion T3-4 of the passivation layer PAS disposed on the outer side of the multiple first electrodes NE, on the multiple first electrodes NE, and on the second electrode PE can be greater than the thickness of the second portion T2-1 and the second portion T2-2 of the passivation layer PAS disposed on the side of the first semiconductor layer NL and the side of the second semiconductor layer PL. A light-emitting element comprises at least two distinct electrodes to be connected to a driving transistor or a power supply line. In this case, the two distinct electrodes may sometimes be disposed on the same plane, but they may also be disposed on different planes. Since the aforementioned two distinct electrodes need to be electrically connected to the driving transistor or the power supply line, it is necessary to expose at least partially the two distinct electrodes of the light-emitting element. In this case, in the light-emitting element LED' according to another embodiment of this specification, the passivation layer PAS on the plurality of first electrodes NE and second electrodes PE may include portions of different thicknesses. Therefore, the passivation layer PAS on the plurality of first electrodes NE and second electrodes PE includes first portions T1-2 and first portions T1-3 of small thickness, thereby making the corresponding portions easier to remove. Thus, the plurality of first electrodes NE and second electrodes PE can be easily at least partially exposed. Furthermore, in another embodiment of the light-emitting element LED' according to this specification, the passivation layer PAS disposed on the first semiconductor layer NL outside the plurality of first electrodes NE may comprise multiple portions with different thicknesses. Therefore, a first portion T1-1 of the passivation layer PAS with a small thickness is disposed on the first semiconductor layer NL outside the plurality of first electrodes NE. Thus, at least a portion of the first semiconductor layer NL disposed outside the plurality of first electrodes NE can be easily exposed. Furthermore, a thin first portion T1-1 of the passivation layer PAS can be disposed on the first semiconductor layer NL disposed outside the plurality of first electrodes NE, and the first portion T1-1 can be positioned adjacent to the plurality of first electrodes NE. Therefore, by removing the thin first portion T1-1 of the passivation layer PAS from the first semiconductor layer NL disposed outside the plurality of first electrodes NE, at least one side portion of each of the plurality of first electrodes NE and a distal end of the passivation layer PAS can be spaced apart from each other. Therefore, the plurality of first electrodes NE can be disposed inside the light-emitting element LED' adjacent to the light-emitting layer EL. Therefore, damage to the plurality of first electrodes NE can be suppressed. The exemplary embodiments disclosed herein can also be described as follows: According to one aspect of this disclosure, the light-emitting element includes: a first semiconductor layer; a plurality of first electrodes disposed on one side and the other side of the first semiconductor layer; a light-emitting layer disposed on the first semiconductor layer and between the plurality of first electrodes; a second semiconductor layer disposed on the light-emitting layer; a second electrode disposed on the second semiconductor layer; a passivation layer configured to cover at least a portion of the first semiconductor layer, at least a portion of the light-emitting layer and at least a portion of the second semiconductor layer; and a plurality of first openings exposing a portion of the top surface and a portion of the side surface of the plurality of first electrodes, the first openings being disposed on the passivation layer. A portion of the side surface of each of the plurality of first electrodes opposite to the light-emitting layer is covered by a passivation layer, and the remaining portion of the side surface of each of the plurality of first electrodes can be exposed by the passivation layer. A portion of one end of the passivation layer may be adjacent to the top surface of the first semiconductor layer. A portion of the top surface of the first semiconductor layer can be exposed by the first opening. A portion of the top surface of the first semiconductor layer exposed by the first opening can be configured to be farther from the light-emitting layer than the first electrode. The passivation layer may include a second opening portion configured to expose a portion of the top surface of the second electrode. Multiple first electrodes can be arranged to be closer to the light-emitting layer than the end of the first semiconductor layer. According to another aspect of the present disclosure, a display device includes: a substrate having pixels comprising a plurality of sub-pixels defined thereon; a plurality of light-emitting elements located in the sub-pixels, the light-emitting elements comprising a plurality of first electrodes and second electrodes, each of the light-emitting elements comprising: a first semiconductor layer; a plurality of first electrodes located on one side and the other side of the first semiconductor layer; a light-emitting layer located on the first semiconductor layer and between the plurality of first electrodes; a second semiconductor layer located on the light-emitting layer; a second electrode located on the second semiconductor layer; and a passivation layer covering at least a portion of the first semiconductor layer, at least a portion of the light-emitting layer, and at least a portion of the second semiconductor layer, wherein a plurality of first openings exposing a portion of a top surface and a portion of a side surface of one of the first electrodes are located on the passivation layer. The display device may also include a plurality of first connecting electrodes respectively connected to a plurality of first electrodes, and a second connecting electrode connected to a second electrode. Multiple first connecting electrodes and second connecting electrodes can be disposed on different layers. Multiple first connecting electrodes may be configured to be adjacent to the top and side surfaces of the first electrodes exposed through these first openings. Multiple first connection electrodes are adjacent to the top surface of one of the first semiconductor layers exposed through the first opening. The second opening portion of the portion exposing the top surface of the second electrode is located on the passivation layer, and the second connecting electrode is adjacent to the top surface of the second electrode exposed through the second opening portion. A light-emitting element according to another embodiment of the present disclosure includes: a first semiconductor layer; a plurality of first electrodes disposed on one side and the other side of the first semiconductor layer; a light-emitting layer disposed on the first semiconductor layer and disposed between the plurality of first electrodes; a second semiconductor layer disposed on the light-emitting layer; a second electrode disposed on the second semiconductor layer; and a passivation layer configured to cover the first semiconductor layer, the plurality of first electrodes, the second semiconductor layer and the second electrode, the passivation layer including portions of different thicknesses. Sections with different thicknesses can be set to three or more sections. The passivation layers on the first semiconductor layer, the first electrode, and the second electrode located outside these first electrodes each contain at least one portion with different thicknesses. In the portions with varying passivation layer thicknesses, one of the portions with the largest thickness is located on these first electrodes and positioned adjacent to the light-emitting layer. Among the portions with different passivation layer thicknesses, the portion with the largest thickness is located on the first semiconductor layer disposed outside the first electrode and disposed away from the first electrode in the first electrode. In the portions with different passivation layer thicknesses, the portion with the largest thickness can be arranged on the second electrode along the edge of the second electrode. In the portion of passivation layer with different thicknesses, the portion with the largest thickness and the portion with a smaller thickness can be configured to be close to the plurality of first electrodes and disposed on the first semiconductor layer disposed outside the plurality of first electrodes. In portions with varying passivation layer thicknesses, portions with smaller thicknesses can be disposed on multiple first electrodes and positioned away from the light-emitting layer. In the portions with different passivation layer thicknesses, the portion with a smaller thickness can be located on the central portion of the second electrode. The thickness of a portion of the passivation layer disposed on the first semiconductor layer, the first electrode, and the second electrode outside the first electrode is less than the thickness of the passivation layer disposed on the side surface of the first semiconductor layer and the side surface of the second semiconductor layer. The thickness of a portion of the passivation layer disposed on the outer side of the plurality of first electrodes, on the first electrode, and on the second electrode, having the maximum thickness, is greater than the thickness of the passivation layer disposed on one side of the first semiconductor layer and one side of the second semiconductor layer. Although exemplary embodiments of this disclosure have been described in detail with reference to the accompanying drawings, this disclosure is not limited thereto and can be embodied in many different forms without departing from the technical concept of this disclosure. Therefore, the exemplary embodiments of this disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of this disclosure. The scope of the technical concept of this disclosure is not limited thereto. Therefore, it should be understood that the foregoing exemplary embodiments are illustrative in all respects and do not limit this disclosure. The scope of protection of this disclosure should be interpreted based on the following claims, and all technical concepts within the equivalent scope should be interpreted as falling within the scope of the concept. LED,LED': Light-emitting element; EL: Light-emitting layer; PAS: Passivation layer; NL: First semiconductor layer; PL: Second semiconductor layer; DT: Driving transistor; NE: First electrode; PE: Second electrode; SRL: Edge line; SL: Scan line; DL: Data line; AA: Display area; NA: Non-display area; ACT: Active layer; GE: Gate electrode; SE: Source electrode; DE: Drain electrode; TD: Tiled display device; TM: Conductive layer; RE: Reflective electrode; CE1: First connecting electrode; CE2: Second connecting electrode; LS: Light-blocking layer; LE: Auxiliary electrode; OA1: First opening portion; OA2: Second opening portion; SP: Sub-pixel; PN: Display Panel PR: Photoresist GD: Gate Driver DD: Data Driver TC: Timing Controller LED: Light Emitting Element PAD1: First Bonding Electrode PAD2: Second Bonding Electrode H1', ​​H2': Top Height 110: Substrate 111: Buffer Layer 112: Gate Insulating Layer 113: First Interlayer Insulating Layer 114: Second Interlayer Insulating Layer 115: First Planarization Layer 116: Bonding Layer 117: Second Planarization Layer 118: Third Planarization Layer T1-1, T1-2, T1-3: First Part T2-1, T2-2: Second Part T3-1, T3-2, T3-3, T3-4: Third Part The foregoing and other aspects, features and advantages of this disclosure will become clearer through the following detailed description in conjunction with the figures, wherein: Figure 1 is a top view of a light-emitting element according to an embodiment of this specification; Figure 2 is a schematic cross-sectional view obtained along line II-II' in Figure 1 according to an embodiment of this specification; Figure 3 is a schematic diagram of the structure of a display device according to an embodiment of this specification; Figure 4A is a partial cross-sectional schematic diagram of a display device according to an embodiment of this specification; Figure 4B is a perspective view of a tiled display device according to an embodiment of this specification; Figure 5 is a cross-sectional schematic diagram of a sub-pixel of a display device according to an embodiment of this specification; Figures 6A and 6B are scanning electron microscope (SEM) images of the light-emitting element during the steps of applying photoresist and etching photoresist after processing the first connecting line in the manufacturing process of the comparative example display device. Figure 7 is a top plan view of a light-emitting element according to another embodiment of this specification; and Figure 8 is a schematic cross-sectional view obtained along line VIII-VIII' in Figure 7 according to an embodiment of the present invention. LED: Light-emitting element EL: Light-emitting layer PAS: Passivation layer NL: First semiconductor layer PL: Second semiconductor layer NE: First electrode PE: Second electrode OA1: First opening section OA2: Second opening section

Claims

1. A light-emitting element comprising: a first semiconductor layer; a plurality of first electrodes located on one side and the other side of the first semiconductor layer; a light-emitting layer located on the first semiconductor layer and between the first electrodes; a second semiconductor layer located on the light-emitting layer; a second electrode located on the second semiconductor layer; and a passivation layer covering at least a portion of the first semiconductor layer, at least a portion of the light-emitting layer, and at least a portion of the second semiconductor layer, wherein a plurality of first openings exposing a portion of a top surface and a portion of a side surface of each of the first electrodes are located on the passivation layer, wherein the side surface of the first electrodes facing the light-emitting layer is covered by the passivation layer, and the opposite side surface of the side surface of the first electrodes is spaced apart from the passivation layer; and wherein... The first semiconductor layer is exposed at the location opposite to the side of the first electrodes and spaced apart from the passivation layer.

2. The light-emitting element as claimed in claim 1, wherein a portion of one end of the passivation layer is adjacent to a top surface of the first semiconductor layer.

3. The light-emitting element as claimed in claim 1, wherein a portion of the top surface of the first semiconductor layer is exposed through one of the first opening portions.

4. The light-emitting element as claimed in claim 3, wherein the portion of the top surface of the first semiconductor layer exposed through the first opening is farther from the light-emitting layer than one of the first electrodes.

5. The light-emitting element as claimed in claim 1, wherein the passivation layer includes a second opening portion that exposes a portion of the top surface of one of the second electrodes.

6. The light-emitting element as claimed in claim 1, wherein each of the first electrodes is closer to the light-emitting layer than the end of the first semiconductor layer.

7. A display device comprising: a substrate defining a pixel comprising a plurality of sub-pixels; and a plurality of light-emitting elements located in the sub-pixels, the light-emitting elements comprising a plurality of first electrodes and a second electrode, wherein each of the light-emitting elements comprises: a first semiconductor layer; a plurality of first electrodes located on one side and another side of the first semiconductor layer; a light-emitting layer located on the first semiconductor layer and between the first electrodes; a second semiconductor layer located on the light-emitting layer; a second electrode located on the second semiconductor layer; and a passivation layer covering at least a portion of the first semiconductor layer, at least a portion of the light-emitting layer, and at least a portion of the second semiconductor layer, wherein a plurality of first openings exposing a portion of a top surface and a portion of a side surface of each of the first electrodes are located on the passivation layer, wherein the side surface of the first electrodes facing the light-emitting layer is covered by the passivation layer, and the opposite side surface of the side surface of the first electrodes is spaced apart from the passivation layer; and wherein... The first semiconductor layer is exposed at the location opposite to the side of the first electrodes and spaced apart from the passivation layer.

8. The display device as claimed in claim 7, further comprising: a plurality of first connection electrodes, each connected to the first electrodes; and a second connection electrode, connected to the second electrodes.

9. The display device as claimed in claim 8, wherein the first connection electrodes and the second connection electrodes are located on different layers.

10. The display device as claimed in claim 8, wherein the first connecting electrodes are adjacent to a plurality of top surfaces and a plurality of side surfaces of the first electrodes exposed through the first opening portions.

11. The display device as claimed in claim 8, wherein the first connection electrodes are adjacent to a top surface of one of the first semiconductor layers exposed through the first openings.

12. The display device as claimed in claim 8, wherein a second opening portion of a portion of the top surface of one of the second electrodes is located on the passivation layer, and the second connecting electrode is adjacent to the top surface of one of the second electrodes exposed through the second opening portion.

13. A light-emitting element comprising: a first semiconductor layer; a plurality of first electrodes located on one side and another side of the first semiconductor layer; a light-emitting layer located on the first semiconductor layer and between the first electrodes; a second semiconductor layer located on the light-emitting layer; a second electrode located on the second semiconductor layer; and a passivation layer covering the first semiconductor layer, the first electrodes, the second semiconductor layer, and the second electrode, wherein the passivation layer comprises a plurality of portions of different thicknesses, wherein the side of the first electrodes facing the light-emitting layer is covered by the passivation layer, and the opposite side of the side of the first electrodes is spaced apart from the passivation layer; and wherein... The first semiconductor layer is exposed at the location opposite to the side of the first electrodes and spaced apart from the passivation layer.

14. The light-emitting element as claimed in claim 13, wherein the portions having different thicknesses comprise three or more portions.

15. The light-emitting element as claimed in claim 13, wherein the passivation layer on the first semiconductor layer, on the first electrodes, and on the second electrode located outside the first electrodes each comprises at least a portion of different thicknesses.

16. The light-emitting element as claimed in claim 15, wherein among the portions of the passivation layer with different thicknesses, a portion having a maximum thickness is located on the first electrodes and is configured to be adjacent to the light-emitting layer.

17. The light-emitting element as claimed in claim 15, wherein among the portions of the passivation layer having different thicknesses, a portion having a maximum thickness is located on the first semiconductor layer disposed outside the first electrodes and disposed away from one of the first electrodes.

18. The light-emitting element as claimed in claim 15, wherein among the portions of the passivation layer having different thicknesses, a portion having a maximum thickness is located on the second electrode along one edge of the second electrode.

19. The light-emitting element as claimed in claim 15, wherein among the portions of the passivation layer with different thicknesses, a portion having a minimum thickness is adjacent to the first electrodes and located on the first semiconductor layer disposed outside the first electrodes.

20. The light-emitting element as claimed in claim 15, wherein among the portions of the passivation layer with different thicknesses, a portion having a minimum thickness is located on the first electrodes and configured to be away from the light-emitting layer.

21. The light-emitting element as claimed in claim 15, wherein among the portions of the passivation layer with different thicknesses, a portion having a minimum thickness is located on the central portion of one of the second electrodes.

22. The light-emitting element as claimed in claim 15, wherein the thickness of a portion of the passivation layer having a minimum thickness disposed on the first semiconductor layer outside the first electrodes, on the first electrodes, and on the second electrodes is less than the thickness of the passivation layer disposed on one side of the first semiconductor layer and on one side of the second semiconductor layer.

23. The light-emitting element as claimed in claim 15, wherein the thickness of a portion having a maximum thickness of the passivation layer disposed on the first semiconductor layer outside the first electrodes, on the first electrodes, and on the second electrodes is greater than the thickness of the passivation layer disposed on one side of the first semiconductor layer and one side of the second semiconductor layer.

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