Memory apparatus, method for operating a cross-point memory structure, and memory system

Abstract

A technique for programming selector-only memory cells in a cross-point memory structure. Threshold-switching memory elements may include, but are not limited to, omonic threshold switches (OTS). The memory system removes Vth drift in the threshold-switching memory elements before programming. This Vth drift is removed by applying a first voltage and a second voltage of opposite polarities to all SOM cells to be programmed. Then, two programming voltages of two polarities are applied to program the cells into two states.

Description

[Technical Field]

[0001] This invention relates to a selector-only memory write operation. [Previous Technology]

[0002] Memory systems are widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, non-mobile computing devices, and data servers. Memory can include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when it is not connected to a power source (e.g., a battery pack).

[0003] Memory cells can reside in a cross-point memory array. In a memory array with a cross-point architecture, one set of conductive lines travels across the surface of the substrate, and another set of conductive lines is formed above this set of conductive lines, traveling in an orthogonal direction relative to the initial layer. The memory cells are located at the intersection of the two sets of conductive lines. Cross-point memory arrays are sometimes called cross-bar memory arrays.

[0004] One type of memory cell contains programmable resistive memory elements, such as magnetoresistive memory elements. Magnetoresistive random access memory (MRAM) cells use magnetization to represent stored data. Data bits are written to the MRAM cell by changing the magnetization direction of a magnetic element ("free layer") within the MRAM cell, and a bit is read by measuring the resistance of the MRAM cell, which varies with the magnetization direction. However, crosspoint memory arrays can have other types of memory cells. For example, crosspoint memory arrays can have memory cells using other technologies such as ReRAM, Phase Change Memory (PCM), or FeRAM.

[0005] In some crosspoint memory architectures, each memory cell contains a threshold selector connected in series with a programmable resistive memory element. In such an architecture, the programmable resistive memory element is programmed to store data, and the threshold selector is used to select the memory cell. The threshold selector has a high resistance (off or non-conductive) until it is biased to a voltage higher than its threshold voltage (Vt) or a current higher than its threshold current (It), and until its voltage bias drops below Vhold ("Voffset") or its current drops below the holding current Ihold. After crossing the threshold selector beyond Vt and simultaneously beyond Vhold, the threshold selector has a relatively low resistance (on or conductive). The threshold selector remains on until its current drops below the holding current Ihold, or its voltage drops below the holding voltage Vhold. When this occurs, the threshold selector returns to the off (higher) resistance state. One example of a threshold switching selector is a bidirectional threshold switch (OTS). Other examples of threshold switching selectors include, but are not limited to, volatile conductive bridges (VCBs), metal-insulator-metals (MIMs), or other materials that provide a highly nonlinear dependence of current on the selected voltage.

[0006] In some cross-point architectures, memory cells contain threshold switching selectors that function as both selectors and programmable memory elements. Such architectures may be referred to as selector-only memory (SOM) cells or self-selecting memory cells. When read at a voltage of a given polarity, the threshold voltage (Vth) of the SOM cell can depend on the polarity of the write voltage used to program the SOM cell. An SOM cell written and read at the same polarity voltage may exhibit a lower Vth than if written and read at the opposite polarity voltage. The memory system can assign a preset polarity to the read voltage, which allows the SOM cell to be programmed to a first state using a first polarity write voltage and to a second state using a second polarity write voltage opposite to the first polarity.

[0007] However, over time, the Vth of the threshold switching selector may drift, posing a technical challenge. Figure 1A depicts the threshold voltage of the SOM cell changing over time. Figure 1B is a table showing a conventional programming scheme used in conjunction with the SOM cell. In this programming scheme, W0 writes with a voltage of the same polarity as the read voltage. However, state W1 writes with a voltage of the opposite polarity to the read voltage. Reads can be performed with a preset polarity voltage. The polarity of the read voltage can be selected by the memory system, but it will be the same for each read. Row 60 shows the last voltage applied to the memory cell that causes the cell to activate (e.g., turn on the selector). The up and down arrows in the table in Figure 1B are used to indicate the relative polarity of the voltage. Row 62 shows the new data to be written to the cell.

[0008] Referring now to Figure 1A, an SOM cell programmed to state W0 (with a "downward polarity write voltage") and immediately read (with a "downward polarity read voltage") will have a Vth close to star 20. An SOM cell programmed to state W1 (with an "upward polarity write voltage") and immediately read (with a "downward polarity read voltage") will have a Vth close to star 22. Line 10 shows the upward drift of Vt for the W0 state cell. If read after a significant time delay (with a downward polarity read voltage), the W0 cell may have a Vth close to the B-bit quasi-Vth, as indicated by arrow 30. If read after a significant time delay (with a downward polarity read voltage), the W1 cell may have a Vth close to the A-bit quasi-Vth, as indicated by arrow 32. Row 64 of the table in Figure 1B summarizes the Vth of a particular cell, which depends on the relative polarity of the last excitation voltage (row 60) and the polarity of the write voltage (row 62). Cells with the last excitation of W1 and new data of W1 have the same polarity voltage for both voltages; therefore, writing new data W1 uses the low Vth of B. However, cells with the last excitation of W1 and new data of W0 have opposite polarity voltages for both voltages; therefore, writing new data W0 uses the high Vth of A. Cells with the last excitation of W0 (or R0) and new data of W1 have opposite polarity voltages for both voltages; therefore, writing new data W1 uses the high Vth of A. Cells with the last excitation of W0 (or R0) and new data of W0 have the same polarity voltage for both voltages; therefore, writing new data W0 uses the low Vth of B.

[0009] Reading or programming memory cells in a crossbar switch architecture can encounter a "half-select" problem. When programming memory cells, the full programming voltage is applied across (multiple) selected memory cells. The memory system may apply 0V across some unprogrammed cells ("completely unselected cells"). However, in some technologies, the memory system applies half the programming voltage across an unprogrammed cell. Such a cell is called a "half-selected cell". Depending on the Vth of the half-selected cell, the threshold switching selector may turn on unintentionally during programming operations. A similar half-select problem may occur during read operations.

[0010] Referring again to Figure 1A, which shows the half-select (HS) margin. The HS margin can be calculated as Vth_Max / 2 – Vth_Min. In the example of Figure 1A, Vth_Max is the maximum value of line 12 (“A”), and Vth_Min is the minimum value of line 10. Therefore, the HS margin is the difference between dashed lines 42 and 44. [Summary of the Invention]

[0011] A technique for programming selector-only memory cells in a crosspoint memory structure. The threshold-switching memory element may include, but is not limited to, an omonic threshold switch (OTS). The memory system removes Vth drift in the threshold-switching memory element before programming. This Vth drift is removed by applying a first voltage and a second voltage of opposite polarities to all SOM cells to be programmed. Then, two programming voltages of two polarities are applied to program the cells into two states.

Implementation Method

[0013] This invention discloses a technique for programming selector-only memory cells in a crosspoint memory structure. The threshold-switching memory element may include, but is not limited to, an ovonic threshold switch (OTS). In one embodiment, the memory system removes Vth drift in the threshold-switching memory element before programming. Removing Vth drift allows the memory system to use a lower programming voltage. A lower programming voltage reduces unintentional selection of the semi-selected memory cell. In one embodiment, Vth drift is removed by applying a first voltage and a second voltage of opposite polarity to all SOM cells to be programmed. Then, two programming voltages of two polarities are applied to program the cells into two states. Furthermore, the magnitude of the voltage used to remove Vth drift can be selected based on factors such as the expected Vth drift of the SOM cell.

[0014] Referring again to Figure 1B, the high (or A)Vth in row 64 of Vth is a problematic threshold voltage that could potentially lead to unintentional selection of the half-select memory cell. This is because the HS margin decreases as the "A-level" increases. Implementations of the programming procedure can reduce the Vth of the cell before programming, thus eliminating this problem. Therefore, the magnitude of the programming voltage can be reduced while still maintaining sufficient HS margin. Thus, unintentional selection of the half-select memory cell is prevented or at least reduced.

[0015] In one embodiment, the memory system includes SOM cells residing in a cross-point memory array structure. In a memory array with a cross-point architecture, one set of conductive lines travels across the surface of a substrate, and another set of conductive lines is formed above this set of conductive lines and travels on the substrate in a direction perpendicular to this set of conductive lines. The memory cells are located at the cross-point junction of the two sets of conductive lines. Cross-point memory arrays are sometimes referred to as cross-bar memory arrays.

[0016] The terms “top” and “bottom”, “upper” and “lower”, and “vertical” and “horizontal” and their forms used herein are for illustrative purposes only, and are not intended to limit the description of the technology, as the items referred to can be interchanged in position and orientation. Furthermore, as used herein, the terms “substantially,” “approximately,” and / or “about” mean that the specified dimensions or parameters may vary within acceptable tolerances for a given application.

[0017] Figure 2 is a block diagram of one embodiment of a non-volatile memory system (or more simply, a "memory system") 100 connected to the host system 120. In one embodiment, the memory cell has an adjacency switching selector such as an OTS. Many types of memory systems can be used with the techniques presented herein. Examples of memory systems include dual in-line memory modules (DIMMs), solid-state drives ("SSDs"), memory cards, and embedded memory devices; however, other types of memory systems may also be used.

[0018] The memory system 100 of FIG2 includes a memory controller 102, a memory 104 for storing data, and local memory 140 (e.g., SOM, MRAM, ReRAM, DRAM). Local memory 140 may be non-volatile and retain data after power is turned off. Local memory 140 may be volatile and not expected to retain data after power is turned off. In one embodiment, local memory 140 contains SOM cells. In one embodiment, local memory does not need to retain data after power is turned off. However, local memory may retain data after power is turned off. In one embodiment, memory controller 102 and / or local memory controller 164 provide access to the SOM cells in local memory 140. For example, memory controller 102 may provide access to a cross-point array of SOM cells in local memory 140. In another embodiment, memory controller 102 or interface 126 or both are removed, and the memory package is directly connected to host 120 via a bus such as DDRn. Alternatively, it may be connected to the host memory management unit (MMU). In another case, the memory controller 102 or part thereof may be moved to the memory 104 to directly connect the memory 104 to the host, such as by providing parity bits, ECC, and wear leveling on the memory 104, as well as DDRn interfaces to / from the host or MMU. As used throughout this document, the term "memory system" is not limited to memory system 100. For example, local memory 140, or a combination of local memory 140 and local memory controller 164, may be considered a memory system. Similarly, host memory 124, or a combination of host processor 122 and host memory 124, may be considered a memory system.

[0019] The components of the memory system 100 depicted in Figure 2 are circuits. The memory controller 102 has a host interface 152, a processor 156, an ECC engine 158, a memory interface 160, a local memory controller 164, regeneration logic 172, and a loss balancing 174. The host interface 152 is connected to and communicates with the host 120. The host interface 152 is also connected to the network-on-chip (NOC) 154. The NOC is a communication subsystem on an integrated circuit. The NOC can span synchronous and asynchronous clock domains or use time-independent asynchronous logic. NOC technology applies network theory and methods to on-chip communication and brings significant improvements beyond conventional bus and crossbar interconnects. Compared to other designs, NOC improves the scalability of systems on a chip (SoC) and the power efficiency of complex SoCs. The wires and links of the NOC are shared by many signals. Because all links in the NOC can operate simultaneously on different data packets, a high degree of parallelism is achieved. Therefore, as the complexity of integrated subsystems continues to grow, the NOC offers enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signaling wires, shared buses, or segmented buses with bridges). In other embodiments, the NOC 154 may be replaced by a bus. The processor 156, ECC engine 158, memory interface 160, local memory controller 164, regeneration logic 172, and wear leveling 174 are connected to and communicate with the NOC 154. The local memory controller 164 is used to operate and communicate with local high-speed memory 140 (e.g., MRAM). In other embodiments, the local high-speed memory 140 may be DRAM, SRAM, or another type of volatile memory.

[0020] The ECC engine 158 performs error correction services. For example, the ECC engine 158 performs encoding and decoding of data provided on memory or in memory-unavailable co-bits as part of a code word for error correction of data retrieved from memory 140 or 104. In one embodiment, the ECC engine 158 is implemented by software-programmable circuitry. For example, the ECC engine 158 may be a programmable processor. In other embodiments, the ECC engine 158 is implemented by custom-designed hardware circuitry without any software. In one embodiment, the functionality of the ECC engine 158 is implemented by processor 156. In one embodiment, local memory 140 has an ECC engine with or without a wear-leveling engine. In one embodiment, memory 104 has an ECC engine with or without a wear-leveling engine.

[0021] Processor 156 performs various controller memory operations, such as programming, erasing, reading, and memory management procedures including wear leveling. A separate wear leveling 174 is depicted, but wear leveling 174 can be implemented by processor 156. Additionally, renewal logic 172 is depicted, but renewal logic can also be implemented by processor 156. In one embodiment, processor 156 is programmed via firmware. In other embodiments, processor 156 is a custom-designed hardware circuit without any software. Processor 156 also implements a translation module as either software / firmware or as dedicated hardware circuitry. In many systems, the non-volatile memory system uses physical addresses associated with one or more memory chips to internally address the storage system. However, the host system will use logical addresses to address various memory locations. This allows the host to assign data to consecutive logical addresses, and the storage system can freely store data between locations of one or more memory chips as desired. To implement this system, memory controller 102 (e.g., translation module) performs address translation between logical addresses used by the host and physical addresses used by the memory die. One implementation is a maintenance table (i.e., the L2P table mentioned above) that identifies the current translation between logical and physical addresses. Entries in the L2P table may include the identification of the logical address and the corresponding physical address. Although the logical address-to-physical address table (or L2P table) includes the word "table," it does not need to be a table literally. Rather, the logical address-to-physical address table (or L2P table) can be any type of data structure. In some instances, the memory space of the storage system is so large that the local memory 140 cannot hold all the L2P tables. In such cases, the entire set of L2P tables is stored in memory 104, and a subset of the L2P tables is cached (the L2P cache) in local high-speed memory 140.

[0022] The memory interface 160 communicates with the memory 104. In one embodiment, the memory 104 includes SOM cells in a cross-point array. In one embodiment, the memory 104 includes NAND memory cells. In one embodiment, the memory interface provides a toggle mode interface. Other interfaces may also be used. In some example implementations, the memory interface 160 (or another part of the controller 102) implements a scheduler and buffer for transferring data to one or more memory chips and receiving data from the one or more memory chips.

[0023] In one embodiment, local memory 140 has an ECC engine. Local memory 140 can be used to assist in performing other functions, such as wear leveling. Further details of on-chip memory maintenance are described in U.S. Patent No. 10,545,692, entitled "Memory Maintenance Operations During Refresh Window," and U.S. Patent No. 10,885,991, entitled "Data Rewrite During Refresh Window," both of which are incorporated herein by reference in their entirety. In one embodiment, local memory 140 is synchronous. In one embodiment, local memory 140 is asynchronous.

[0024] In one embodiment, the memory 104 includes a plurality of memory packages. Each memory package includes one or more memory chips. Therefore, the memory controller 102 is connected to one or more memory chips. In one embodiment, the memory package may include other types of memory, such as storage-class memory (SCM) based on programmable resistive random access memory (such as SOM, ReRAM, MRAM, FeRAM, or RRAM) or phase change memory (PCM). In one embodiment, the memory controller 102 provides access to memory cells in a cross-point array in the memory 104.

[0025] The memory controller 102 communicates with the host system 120 via an interface 152 implementing a protocol such as Compute Express Link (CXL). Alternatively, such a controller can be removed, and the memory package can be placed directly on the host bus, such as DDRn or CXL. To work with the memory system 100, the host system 120 includes a host processor 122, host memory 124, and interface 126 connected along bus 128. The host memory 124 is the host's physical memory and can be SOM, DRAM, SRAM, ReRAM, MRAM, non-volatile memory, or another type of memory. In one embodiment, the host memory 124 includes a crosspoint array of programmable resistive memory cells, wherein each memory cell includes a threshold switching selector used as an SOM cell.

[0026] The host system 120 is external to and separate from the memory system 100. In one embodiment, the memory system 100 is embedded in the host system 120. The host memory 124 may be referred to herein as the memory system. In this document, the combination of the host processor 122 and the host memory 124 may be referred to as the memory system. In one embodiment, such host memory may be a cross-point memory using SOM cells.

[0027] FIG3A is a block diagram depicting an example of a memory die 292 that may implement the techniques described herein. In one embodiment, the memory die 292 is included in local memory 140, and in another embodiment, the memory die 292 is included in storage 104. In one embodiment, the memory die 292 is included in host memory 124. The memory die 292 includes a memory structure 202, which may include any of the memory cells described below. The memory structure 202 may include one or more memory arrays. The array terminal lines of the memory structure 202 include various layers(s) of word lines organized into columns and various layers(s) of bit lines organized into rows. However, other orientations may also be implemented, including, for example, a diagonal pattern to save space. The memory die 292 includes a column control circuitry 220, the outputs 208 of which are connected to the individual word lines of the memory structure 202. The column control circuitry 220 receives a group of M column address signals and one or more various control signals from the system control logic circuitry 260, and generally includes circuitry such as a column decoder 222, a column driver 224, and a block selection circuitry 226 for both read and write operations. The column control circuitry 220 may also include a read / write circuitry system. In one embodiment, the column decoding and control circuitry 220 has sense amplifiers 228, each containing circuitry for sensing the condition (e.g., voltage) of the word lines of the memory structure 202. In one embodiment, the condition or bit state of a memory cell (e.g., a SOM cell) in the cross-point array is determined by sensing the word line voltage directly by comparing the accessed memory cell voltage with a reference voltage using the sense amplifiers. The memory die 292 also includes a row decoding and control circuitry 210, whose inputs / outputs 206 are connected to the respective bit lines of the memory structure 202. Although only a single block is shown for memory structure 202, the memory die may include multiple arrays or "tiles" that can be accessed individually. The row control circuitry 210 receives a group of N row address signals and one or more various control signals from system control logic 260, and generally may include circuitry such as row decoder 212, row decoder and driver 214, block selection circuitry 216, read / write circuitry, and I / O multiplexer circuitry.

[0028] System control logic 260 receives data and commands from the host system and provides output data and status to the host system. In other embodiments, system control logic 260 receives data and commands from a separate controller circuit and provides output data to that controller circuit, which communicates with the host system. Such a controller system may implement interfaces such as DDR, DIMM, CXL, PCIe, and others. In another embodiment, such data and commands are sent and received directly from the memory package to the host without a separate controller, and any required controller is within the individual die or within the die added to the multi-chip memory package. In some embodiments, system control logic 260 may include a state machine 262 that provides die-level control for memory operation. In one embodiment, state machine 262 may be software-programmable. In other embodiments, state machine 262 is implemented entirely in hardware (e.g., circuitry) without using software. In another embodiment, state machine 262 is replaced by a microcontroller or microprocessor. System control logic 260 may also include a power control module 264 that controls the power, current source current, and voltage supplied to the columns and rows of memory structure 202 during memory operation, and may include charge pump and regulator circuitry for generating regulated voltages, and on / off control of word line bit line selection for memory cells. In some embodiments, power control 264 includes one or more current sources. The current sources(s) can be used to provide read and / or write currents. System control logic 260 includes a memory 266 that can be used to store parameters for operating memory structure 202. System control logic 260 also includes refresh logic 272 and loss balancing logic 274. Such system control logic can be commanded by host 120 or memory controller 102 to refresh logic 272, which can load on-chip stored column and row addresses (indicators) that can be incremented after refresh. Only such address(s) bits(s) can be selected (to refresh OTS). Alternatively, such addresses can be read, corrected via ECC engine 269, and then stored in a "spare" location. This is also incremented (therefore, under the control of wear leveling logic 274, all codewords are periodically read, corrected, and relocated throughout the chip) to achieve wear leveling, resulting in more even use of each bit on the chip. This operation can be more directly controlled by an external controller, such as a PCIe, CXL, or DDRn controller located separately from or on the memory chip.

[0029] Commands and data are transferred between the memory controller 102 and the memory die 292 via the memory controller interface 268 (also referred to as the "communication interface"). This interface may be, for example, PCIe, CXL, or DDRn. The memory controller interface 268 is an electrical interface for communicating with the memory controller 102. Examples of the memory controller interface 268 also include a dual-state thixotropic interface. Other I / O interfaces may also be used. For example, the memory controller interface 268 may implement a dual-state thixotropic interface connected to the memory interfaces 228 / 258 of the memory controller 102. In one embodiment, the memory controller interface 268 includes a set of input and / or output (I / O) pins connected to the controller 102. In another embodiment, the interface is a JEDEC standard DDRn or LPDDRn (such as DDR5 or LPDDR5) or a subset thereof with smaller page sizes and / or more lenient timings.

[0030] The system control logic 260 in the controller located on the memory die within the memory package may include an error correction code (ECC) engine 269. The ECC engine 269 may be referred to as an on-die ECC engine because it resides on the same semiconductor die as the memory cell. That is, the on-die ECC engine 269 can be used to encode data and corresponding bits to be stored in the memory structure 202, and to decode and correct errors in the decoded data. The encoded data may be referred to herein as a codeword or an ECC codeword. The ECC engine 269 can be used to execute decoding algorithms and perform error correction. Therefore, the ECC engine 269 can decode ECC codewords. In one embodiment, the ECC engine 269 can decode data more quickly by direct decoding, without iteration. Having the ECC engine 269 on the same die as the memory cell allows for faster decoding. The ECC Engine 269 can use a variety of decoding algorithms, including but not limited to Reed Solomon, Bose-Chaudhuri-Hocquenghem (BCH), and low-density parity check (LDPC).

[0031] In some embodiments, all elements of memory die 292 (including system control logic 260) may be formed as part of a single die. In other embodiments, some or all of the system control logic 260 may be formed on different dies (e.g., an external controller chip).

[0032] In one embodiment, the memory structure 202 comprises a three-dimensional memory array of non-volatile or volatile memory cells, wherein multiple memory layers are formed over a single substrate (such as a wafer). The memory structure may contain any type of non-volatile or volatile memory formed monolithically in one or more solid layers of memory cells, such memory having an active region disposed over a silicon (or other type) substrate on silicon or an insulator. In another embodiment, the memory structure 202 comprises a two-dimensional memory array of non-volatile memory cells.

[0033] The exact type of memory array architecture or memory cell included in memory structure 202 is not limited to the examples described above. Many different types of memory array architectures or memory technologies can be used to form memory structure 202. For the purposes of the new claimed embodiments presented herein, no specific non-volatile memory technology is required. Examples of suitable technologies for the memory cell architecture of memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, and the like.

[0034] One example of a SOM crosspoint memory includes an OTS selector / memory element configured in a crosspoint array accessed via X and Y lines (e.g., word lines and bit lines). In another embodiment, the memory cell may include a conductive bridge memory element. A conductive bridge memory element may also be referred to as a programmable metallized cell. The conductive bridge memory element can be used as a state-change element based on the physical relocation of ions within a solid electrolyte. In some cases, the conductive bridge memory element may include two solid metal electrodes (one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper)) having a solid electrolyte film between the two electrodes. As temperature increases, ion mobility also increases, resulting in a decrease in the programmability threshold of the conductive bridge memory cell. Therefore, the conductive bridge memory element has a wide range of programmability thresholds over a temperature range.

[0035] In some embodiments, the memory structure incorporates phase change memory (PCM). PCM utilizes the unique behavior of sulfide glasses. One embodiment uses a GeTe-Sb₂Te₃ superlattice to achieve a non-thermal phase change by simply altering the coordination state of germanium atoms using laser pulses (or light pulses from another source). The memory cell is programmed or switches between amorphous and crystalline states by altering the common coordination of the PCM material via current pulses. Note that the use of "pulse" in this document does not necessarily refer to a square pulse, but includes (continuous or discontinuous) vibrations or bursts of sound, current, voltage, light, or other waves. Furthermore, the current forced for writing can, for example, be rapidly driven to a peak and then linearly sloping down at, for example, an edge rate of 500 ns. Such peak current force can be limited by a zoned voltage compliance that varies along the position of the memory cell along the word line or bit line. In one embodiment, the phase-change memory cell has a phase-change memory element connected in series with a threshold switching selector (such as an OTS).

[0036] Those skilled in the art will recognize that the techniques described herein are not limited to a single specific memory structure, memory construction, or material composition, but are encompassed within the spirit and scope of the techniques described herein and understood by those skilled in the art.

[0037] The components in Figure 3A can be divided into two parts: the memory structure 202 and the peripheral circuitry, including all other components. An important characteristic of the memory circuitry is its capacity, which can be increased by increasing the area allocated to the memory die 292 of the memory structure 202; however, this reduces the area available for the peripheral circuitry on the memory die, or increases the cost associated with the chip area. This can place significant limitations on these peripheral components. For example, the need to fit the sense amplifier circuitry within the available area can be a significant limitation on the sense amplifier design architecture. Regarding the system control logic 260, the reduced area availability can limit the available functionality that can be implemented on the chip. Therefore, the fundamental trade-off in the design of the memory die 292 is the trade-off between the amount of area dedicated to the memory structure 202 and the amount of area dedicated to the peripheral circuitry. Such trade-offs can result in a larger IR drop due to the use of a larger xy memory array between the word lines and bit lines, which in turn can benefit more from the use of voltage limiting and partitioning of the constant current output voltage according to the memory cell location along the word lines and bit lines.

[0038] Another reason why the memory structure 202 and its peripheral circuitry are often inconsistent is due to the processing involved in forming these regions, as these regions often involve different processing techniques and trade-offs between different techniques on a single die. For example, components in the system control logic 260 (such as sense amplifier circuits, charge pumps, logic elements in state machines, and other peripheral circuitry) typically employ PMOS devices. In some cases, the memory structure will be based on CMOS devices. The processing operations used to manufacture CMOS dies will differ in many ways from those optimized for NMOS technology alone.

[0039] To mitigate these limitations, the embodiments described below can separate the elements of FIG3A onto separately formed dies that are subsequently bonded together. FIG3B depicts an integrated memory assembly 270 having a memory structure die 280 and a control die 290. A memory structure 202 is formed on the memory structure die 280, and some or all of the peripheral circuitry elements (including one or more control circuits) are formed on the control die 290. For example, the memory structure die 280 may be formed solely of memory elements, such as an array of SOM cells or other memory types. Some or all of the peripheral circuitry (including even elements such as decoders, current sources, and sense amplifiers) may then be moved to the control die. This allows each semiconductor die to be individually optimized according to its technology. This allows for more space to be used for peripheral elements, which can now be combined with additional capabilities that were previously limited by the margin of maintaining identical dies in the memory cell array. The two dies can then be bonded together in a bonded multi-die integrated memory assembly, wherein an array on one die is connected to peripheral elements on the other die. While the following will focus on an integrated memory assembly with one memory die and one control die, other embodiments may use more dies, such as two memory dies and one control die.

[0040] Similar to memory die 292 in FIG. 3A, memory structure die 280 in FIG. 3B includes memory structure 202, which may include multiple independently accessible arrays or "blocks". System control logic 260, column control circuitry 220, and row control circuitry 210 are located in control die 290. In some embodiments, all or part of the row control circuitry 210 and all or part of the column control circuitry 220 are located on memory structure die 280. In some embodiments, some circuitry in system control logic 260 is located on memory structure die 280.

[0041] Figure 3B shows that the row control circuitry system 210 on the control die 290 is coupled to the memory structure 202 on the memory structure die 280 via an electrical path 293. For example, the electrical path 293 can provide electrical connections between the row decoder 212, the row driver circuitry system 214, and the block select 216 and the bit lines of the memory structure 202. The electrical path can extend from the row control circuitry system 210 in the control die 290 through pads on the control die 290 that bond to corresponding pads on the memory structure die 280, which are connected to the bit lines of the memory structure 202. Each bit line of the memory structure 202 can have a corresponding electrical path connected to the row control circuitry system 210 in the electrical path 293 (including a pair of bonding pads). Similarly, the column control circuitry system 220, including the column decoder 222, column driver 224, block selector 226, and sense amplifier 228, is coupled to the memory structure 202 via electrical paths 294. Each of the electrical paths 294 may correspond to, for example, a word line. Additional electrical paths may also be provided between the control die 290 and the memory structure die 280.

[0042] For the purposes of this document, the phrase "a control circuit" may include one or more of the following: memory controller 102, local memory controller 164, processor 156, system control logic 260, row control circuit system 210, column control circuit system 220, host processor 122, microcontroller, state machine, and / or other control circuit system, or other similar circuitry for controlling non-volatile memory. A control circuit may include hardware only or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. A control circuit may include a processor, FPGA, ASIC, integrated circuit, or other type of circuitry. Such a control circuit system may include a driver that drives to a fixed voltage (such as a power supply), such as via a connection through a node of a fully conducting transistor (gate to power supply). Such a control circuit system may include a current source driver.

[0043] For the purposes of this document, the term "apparatus" may include, but is not limited to, one or more of the following: memory system 100, local memory 140, local memory controller 164 and / or a combination of memory controller 102 and local memory 140, storage 104, memory chip 292, integrated memory assembly 270, and / or control chip 290.

[0044] In the following discussion, the memory structure 202 of Figures 3A and 3B will be discussed in the context of a cross-point architecture. In a cross-point architecture, a first set of conductive lines or wires (such as word lines) travels in a first direction relative to the underlying substrate; and a second set of conductive lines or wires (such as bit lines) travels in a second direction relative to the underlying substrate. Memory cells are located at the intersections of word lines and bit lines. Memory cells at these cross-points can be formed according to any of a variety of techniques (including those described above). The following discussion will primarily focus on embodiments based on a cross-point architecture using SOM cells, each SOM cell having a threshold switching selector (such as a bidirectional threshold switch (OTS)) to form selectable memory bits. However, the embodiments are not limited to the selector system being an OTS.

[0045] FIG4A depicts an embodiment of a portion of a memory array 402 forming an intersection architecture in oblique view. The memory array 402 of FIG4A is an example of an embodiment of the memory structure 202 in FIG3A or FIG3B, wherein the memory die 292 or memory structure die 280 may include a plurality of such memory arrays 402. The memory array 402 may be included in local memory 140 or host memory 124. Bit lines BL1 to BL5 are arranged in a first direction relative to the substrate below the die (not shown) (but indicated as rows entering the drawing), and word lines WL1 to WL5 are arranged in a second direction perpendicular to the first direction, or diagonally to provide an intersection of memory cells interconnected between WL and BL. Figure 4A shows an example of a horizontal crossover structure, where word lines WL 1 to WL 5 and BL 1 to BL 5 both extend horizontally relative to the substrate, while memory cells (two of which are indicated by 401) are oriented such that current flows vertically through the memory cells (e.g., shown as I cells). In memory arrays with additional memory cell layers, such as those discussed below in relation to Figure 4D, there will be additional corresponding layers of bit lines and word lines. For example, one pattern would be derived from the bottom layer: WL, memory cell, BL, memory cell, WL, WL, memory cell, BL memory cell, WL.

[0046] As depicted in Figure 4A, the memory array 402 includes a plurality of memory cells 401. Memory cells 401 may include rewritable memory elements, such as those implemented using a threshold switching selector, which can be operated to have programmable resistance. Memory cell 401 may be referred to herein as a programmable resistive memory cell. Memory cell 401 may also be referred to herein as a self-selecting memory cell or a selector-only memory cell. The threshold switching selector may be implemented using a bidirectional threshold switch (OTS), a volatile conductive bridge (VCB), a metal-insulator-metal (MIM), or other materials with a highly nonlinear dependence on providing current or resistance for varying selection voltages. The following discussion will focus on memory cells composed of OTS memory cells, although much of the discussion is applicable more generally. Current in the memory cells of the first memory level is shown as flowing upwards, as indicated by arrow I cell, but current can flow in either direction to read or write the memory cell bit state, as discussed in more detail below.

[0047] Figures 4B and 4C present a side view and a top view of the intersection structure in Figure 4A, respectively. The side view of Figure 4B shows a bottom conductor (or word line) WL1 and top conductors (or bit lines) BL1 to BLn. At the intersection of each top conductor and bottom conductor is an SOM memory cell 401. Figure 4C is a top view illustrating the intersection structure of M bottom conductors WL1 to WLM and N top conductors BL1 to BLN. In a binary embodiment, the SOM cell at each intersection can be programmed into one of two resistance states: high and low. Further details of embodiments of the SOM memory cell design and techniques for programming thereof are given below. In some embodiments, such sets of conductors are arranged consecutively into "blocks", and such blocks can be adjacent in the word line (WL) direction and orthogonally paired in the bit line direction to form a module. Such modules can consist of 2 x 2 blocks to form a four-block combination, where the WL driver between these blocks is "center driven" between the blocks, and the WL travels continuously above the transistor driver at approximately the center of the line. Similarly, the BL driver can be located between paired block pairs in the BL direction for center driving, whereby the transistor driver and its area are shared between a pair of blocks. Copper or other types of low-resistance vias can decode the transistor driver / selector and connect it to the WL or BL. In addition to memory elements, series select elements, such as OTS, can also be included between the WL and BL in the memory cell.

[0048] Figure 4A illustrates an embodiment with a single layer of word lines and bit lines, wherein the SOM or other memory technology for the memory cell is located at the intersection of two sets of conductive lines. To increase the storage density of the memory die, multiple layers of such memory cells and conductive lines can be formed. Figure 4D illustrates a two-layer example.

[0049] FIG4D depicts an embodiment of a portion of a second-order memory array forming a cross-point architecture in a perspective view. Similar to FIG4A, FIG4D shows a first layer 418 of memory cells 401 of memory array 403, which is connected at the intersection of the first layer word lines WL 1,1 to WL 1,4 and the bit lines BL 1 to BL 5 above. Memory array 403 may be included in memory structure 202 of FIG3A or FIG3B. Second layer memory cells 420 are formed above bit lines BL 1 to BL 5 and between these bit lines and the second set of word lines WL 2,1 to WL 2,4. In fact, BL is shared. In an alternative, the second layer may include another stack of BL located above the shown BL and below the second stack of WL. Although Figure 4D shows two layers 418 and 420 of memory cells, the structure can extend upwards through additional alternating layers of word lines and bit lines in a similar pattern. Depending on the embodiment, the word lines and bit lines of the array of Figure 4D can be biased for read or programmed operations, such that current flows from the word line layer to the bit line layer, or vice versa, in each layer. The two layers can be structured to have current flow in the same direction in each layer for a given operation, or to have current flow in opposite directions by driver selection in positive or negative directions. Memory cells can be placed in the same orientation within the first and second layers, thereby enabling the use of current in opposite directions for read or write operations layer by layer. Alternatively, memory cells can be placed in the opposite or flipped orientation when placed between BL and WL in the second layer (thereby enabling the use of current in the same direction as for read or write operations in the memory cells within the first layer). It will be apparent to those skilled in the art that two layers can be extended to three or more layers.

[0050] The use of a crosspoint architecture allows for arrays with a small footprint, and several such arrays can be formed on a single die. Memory cells formed at each crosspoint can be resistor-type memory cells, where data values ​​are encoded into different resistance levels. Depending on the embodiment, the memory cell can be a binary value having a low-resistance state or a high-resistance state, or it can be a multi-level cell (MLC) with additional resistance between the low-resistance and high-resistance states. The crosspoint array described herein can be used in memory die 292 of FIG. 3A, local memory 140 of FIG. 2, and / or host memory 124 of FIG. 2, or any other configuration in which additional memory is applicable. Resistor-type memory cells can be formed according to many of the techniques mentioned herein, such as OTS. The following discussion is presented primarily in the context of memory arrays using crosspoint architecture with OTS memory cells having binary values, but most of the discussion can be applied more generally to other memory elements in memory cells within crosspoint arrays or other configurations that are obvious to those of ordinary knowledge in the art.

[0051] FIG5 illustrates the structure of an embodiment of the SOM cell. The SOM cell 401 can be used as, for example, the programmable resistive memory cell 401 in FIGS. 4A to 4D. The SOM cell includes a bottom electrode 501, spacers 512, a threshold switching selector (TSS) memory element 502, spacers 514, and a top electrode 511. In some embodiments, the bottom electrode 501 is a word line and the top electrode 511 is a bit line. In other embodiments, the bottom electrode 501 is a bit line and the top electrode 511 is a word line. The state of the memory cell is based on the state of the TSS memory element 502.

[0052] Data is written to the SOM memory cell by programming the TSS memory element 502 using a programming (or write) signal (e.g., programming current, programming voltage) with a desired polarity. In one embodiment, the SOM memory cell is programmed to a first state (W0) using a first polarity programming signal and to a second state (W1) using a second polarity programming signal. The SOM memory cell can be read using a read signal (e.g., read current, read voltage). The polarity of the read signal relative to the polarity of the programming signal can affect the Vth of the SOM cell. In one embodiment, a read signal with the same polarity as the programming signal results in a lower Vth than a read signal with the opposite polarity to the programming signal. Typically, the memory system selects the polarity of the read signal and then aligns it with that polarity when determining the state of the SOM cell. Therefore, when reading with a selected polarity read signal, the polarity of the programming signal will actually result in a higher / lower Vth.

[0053] The threshold switching selector 502 can also be used as a selector for selecting memory cells used in memory operations. The threshold switching selector 502 has a high resistance (in an off or non-conductive state) until it is biased to a voltage higher than its threshold voltage (Vth) or a current higher than its threshold current, and until its voltage bias drops below Vhold (also called "Voffset") or its current drops below Ihold. After crossing Vth and simultaneously crossing Vhold, the switching selector has a low resistance (in a conducting or conductive state). The threshold switching selector remains conducting until its current drops below the holding current Ihold, or its voltage drops below the holding voltage Vhold. When this occurs, the threshold switching selector returns to the off (higher) resistance state. Therefore, to select a memory cell at the crossover point, a voltage or current sufficient to turn on the associated threshold switching selector is applied. One example of a threshold switching selector is a bidirectional threshold switching material for a bidirectional threshold switch (OTS). Examples of threshold switching materials include Ge-Se, Ge-Se-N, Ge-Se-As, Ge-Se-Sb-N, Ge58Se42, GeTe6, Si-Te, Zn-Te, C-Te, B-Te, Ge-As-Te-Si-N, Ge-As-Se-Te-Si, and Ge-Se-As-Te, wherein the atomic percentage of each element ranges from a fractional percentage to more than 90%. In one embodiment, the threshold switching selector is a two-terminal device. The threshold switching selector 502 may also contain additional conductive layers. For example, a spacer 514 is depicted between the switching selector 502 and the top electrode 511. The spacer layer 514 may be a single conductive layer or composed of multiple conductive layers. The threshold switching selector 502 may also contain additional conductive layers at the interface with the bottom electrode 501. For example, a spacer 512 is depicted between the switching selector 502 and the bottom electrode 501. The spacer layer 512 at the interface with the bottom electrode 501 may consist of a single conductive layer or multiple conductive layers. Examples of conductive layers adjacent to the OTS include carbon, carbon nitride, carbon silicate, tungsten carbide, titanium, titanium nitride, tungsten, tungsten nitride, tantalum, tantalum nitride, and others. The threshold voltage switch has a threshold voltage (Vt) above which the resistance of the device changes from insulating or quasi-insulating to substantially conductive.

[0054] FIG. 6A depicts an embodiment of a memory array 600 with a cross-point architecture. The memory array 600 may be included in the memory structure 202 of FIG. 3A or FIG. 3B. The array 600 has a set of first conductive lines 606a to 606h and a set of second conductive lines 608a to 608d. In one embodiment, the set of first conductive lines 606a to 606h are word lines, and the set of second conductive lines 608a to 608b are bit lines. For ease of discussion, the set of first conductive lines 606a to 606h may be referred to as word lines, and the set of second conductive lines 608a to 608b may be referred to as bit lines. However, the set of first conductive lines 606a to 606h may be bit lines, and the set of second conductive lines 608a to 608b may be word lines.

[0055] The memory array 600 has several programmable resistive memory cells 401. The programmable resistive memory cells 401 may be referred to as self-select memory cells or selector-only memory cells. In one embodiment, each cell 401 has a structure similar to that of the cells in FIG. 5. Each memory cell 401 is connected between one of the first conductive lines 606 and one of the second conductive lines 608 (e.g., at the intersection of one of the first conductive lines 606 and one of the second conductive lines 608). Each SOM cell 401 has a threshold switching selector (not depicted in FIG. 6A). The threshold switching selector 502 becomes conductive in response to a voltage level exceeding its threshold voltage and remains conductive with lower resistance until the current through the switching selector 502 decreases below the selector holding current Ihold. The threshold switching selector 502 may be a two-terminal device. In one embodiment, the threshold switching selector 502 includes an OTS.

[0056] Techniques for programming SOM cells are disclosed. For discussion purposes, memory cell 401a is selected for memory operations such as read or write. An example of a programming threshold switching selector 502 will be discussed. The selected memory cell 401a is located at the intersection of the selected word line 606g and the selected bit line 608b. A selected memory cell means a memory cell selected for memory operations such as read or write. The selected memory cell is connected between the selected word line and the selected bit line. In one embodiment, to program the selected memory cell 401, a selection voltage, such as near ground, is provided to the selected bit line (e.g., bit line 608b) and a programming (or write) voltage (Vs) is applied to the selected word line (e.g., word line 606g). A selected word line means that the word line is connected to at least one selected memory cell. Alternatively, a memory cell can be selected by applying a selection voltage to the select word line while simultaneously applying a program voltage (Vs) to the select bit line.

[0057] In one method, word lines not connected to the selected memory cell may be driven by a voltage approximately half the magnitude of the voltage across the selected cell. As depicted in FIG6A, word lines 606a, 606b, 606c, 606d, 606e, 606f, and 606h each have a voltage applied thereto called a half-select voltage (Vs / 2). The half-select voltage (Vs / 2) has approximately half the magnitude of the voltage (Vs) across the selected cell. For programming, voltage Vs may be called programming voltage. For example, voltage Vs may be called read voltage.

[0058] In one method, bit lines not connected to the selected memory cell may be driven by a voltage approximately half the magnitude of the voltage across the selected cell. As depicted in FIG6A, bit lines 608a, 608c, and 608d each have a voltage applied thereto called a half-select voltage (Vs / 2). As described above, the half-select voltage (Vs / 2) has approximately half the magnitude of the voltage (Vs) across the selected cell.

[0059] Some of the memory cells connected to the select word line are referred to herein as half-select memory cells. The voltage on the half-select memory cell is approximately half the voltage on the select memory cell. Each half-select memory cell 401b connected to the select word line has a Vs applied to the select word line and a Vs / 2 applied to its respective bit line. Therefore, each half-select memory cell 401b has a Vs / 2 applied to the memory cell.

[0060] Some of the memory cells connected to the select bit lines are referred to herein as half-select memory cells. The voltage on these half-select memory cells is approximately half the voltage on the select memory cell. Each half-select memory cell 401c connected to the select bit lines has 0V applied to the select bit lines and Vs / 2 applied to each of their respective word lines. Therefore, each half-select memory cell 401c has Vs / 2 applied to the memory cell.

[0061] The threshold switching selector 502 in such radius-select memory cells 401b, 401c should not be turned on during operation (such as reading or writing). However, if the Vth of the threshold switching selector 502 is less than Vs / 2, the threshold switching selector 502 may be turned on during memory operation. This document discloses techniques for preventing the threshold switching selector 502 in the radius-select memory cells 401b, 401c from being turned on (or at least reducing its chance) during memory operation (such as reading or writing). In one embodiment, the Vth drift is removed from the memory cell before programming, which allows the programming voltage to have a lower value. Using a lower value for the programming voltage will reduce the value of Vs / 2, which reduces the probability of unintentionally selecting a radius-select memory cell.

[0062] No other memory cells are selected, which means that they have approximately 0V on the memory cells. Figure 6A shows a completely unselected memory cell 401d. In this example, each completely unselected memory cell 401d has Vs / 2 applied to its word line and Vs / 2 applied to its bit line.

[0063] In the example of FIG6A, there are more word lines than bit lines in the crosspoint array. In another embodiment, there are more bit lines than word lines in the crosspoint array. In another embodiment, the number of bit lines in the crosspoint array is equal to the number of word lines. In the example of FIG6A, there are up to twice as many word lines as bit lines in the crosspoint array; however, different ratios can be used. Thus, different block sizes can be implemented. For example, a block may have 1024 BL x 2048 WL, which can be configured into a module of 2048 x 4096 units by means of WL and BL between four blocks driven by a center. In one embodiment, a read or write is performed on a group of memory units by, for example, selecting a memory unit from among several blocks. In some embodiments, more than one memory unit from a block may be selected for reading.

[0064] Figure 6A is shown and described using a voltage forcing method, wherein a voltage is provided to the selected word line. In one embodiment, a current forcing method is used to access the SOM cell. The current forcing method can be used to read or write to the SOM cell. Figure 6B depicts an example of the current forcing method. In the current forcing method, an access current (e.g., I access) is driven to (or sinks from) the selected word line, depending on the direction of I access. The selected bit line may remain grounded. As a result, the current charges the voltage on the selected word line. In one embodiment, the maximum magnitude of the selected word line voltage is limited to Vs. Alternatively, the selected bit line may be maintained at a higher voltage, wherein the current sinks from the selected word line. The unselected word line and the unselected bit line have voltages applied to them. The magnitude of the voltages applied to the unselected word line and the unselected bit line may be similar to the example of Figure 6A. The half-selection problem discussed in conjunction with the voltage forcing method may also occur in the current forcing method. In this document, terms such as "program signal" may include both program voltage and program current. Similarly, terms such as "read signal" may include both read voltage and read current.

[0065] Figure 7 is a flowchart of one embodiment of a program 700 for a SOM cell 401 in a programmable crosspoint array. The program 700 can be used to program the SOM cell 401 (such as one discussed in Figure 5). In one embodiment, the SOM cell 401 includes an OTS used as a programmable resistive memory cell. The program 700 can be executed in parallel on a number of memory cells, such as in selected memory cells in different blocks 600. In one embodiment, the program 700 is executed by one or more control circuits, such as, but not limited to, a memory controller 102, system control logic 260, row control circuitry 210, column control circuitry 220, a microcontroller, a state machine, a host processor 122, and / or other control circuitry systems, or one or more other similar circuits for controlling non-volatile memory.

[0066] Step 702 includes selecting a first polarity for a future read signal applied to SOM unit 401. If the selection of the first polarity has already been established and does not need to be changed, step 702 can be omitted. The first polarity can be positive or negative. The current polarity can be defined based on the voltage caused by the current on the battery. Here, positive or negative polarity can be defined relative to, for example, the select word line and the select bit line.

[0067] Step 704 includes determining whether to store the first bit value or the second bit value in the SOM unit 401. As an example, the first bit value is "0" and the second bit value is "1". As another example, the first bit value is "1" and the second bit value is "0". However, the bit value can be the opposite of this example.

[0068] If the first element value is to be stored, then step 706 is executed. Step 706 includes applying a programming (or writing) signal with a first polarity to SOM cell 401. Therefore, if the cell is read in the future, the programming signal in step 706 has the same polarity as the read signal.

[0069] If the second bit value is to be stored, then step 708 is executed. Step 708 includes applying a programmed signal with a second polarity to the SOM unit 401. The second polarity is opposite to the first polarity. Therefore, the programmed signal in step 708 has a polarity opposite to the future read signal. In steps 702, 706, and 708, current-forced or voltage-forced techniques can be used to apply the signal.

[0070] Figure 8 depicts an example Vth distribution of a group of SOM cells 402 after being programmed using program 700. Figure 8 depicts two "Vth distributions" of SOM cells 401, as they will be measured when read using a read signal of the first polarity discussed in program 700. Vth distribution 810 represents SOM cell 401 storing the first bit value. Vth distribution 820 represents SOM cell 401 storing the second bit value. The vertical axis represents the number of memory cells and is on a logarithmic scale. The horizontal axis represents the Vth of the threshold switching selector, assuming that SOM cell 401 is read using a read voltage with a pre-assigned first polarity. A reference resistor R_ref is depicted between the two Vth distributions 810 and 820. In one embodiment, R_ref is used to divide the two Vth distributions. It should be noted that if the SOM cell is read instead using a read signal with a second polarity, the Vth distributions 810 and 820 can be reversed.

[0071] Figure 9A is Table 950 showing details of an embodiment of the SOM cell in a programmed crosspoint memory structure. Before programming, the memory cell may be in a W0 state or a W1 state. "Last Activation" row 952 refers to the last signal that activates (e.g., turns on) the memory cell to be programmed. The last activation may be a write signal or a read signal. In this example, for a normal read operation, the read signal has the same polarity as the write signal used to program to the W0 state. The arrows in Table 950 depict the relative polarities of the read and write signals. The normal read signal is called R0 because it has the same polarity as the signal used to program to the W0 state. The read and write signals may be voltage or current. "New Data" row 954 indicates how the memory cell will be programmed. In this example, a cell currently in the W1 state may be programmed to either the W1 state or the W0 state. A cell currently in the W0 state may be programmed to either the W1 state or the W0 state.

[0072] Step 1 in this example is called "read down," which refers to the downward arrow in Step 1 of Table 950. The "up arrow" and "down arrow" in Table 950 refer to the relative polarity of the signal. Step 2 in this example is called "read up," which refers to the upward arrow in Step 2 of Table 950. The term "read" is used for Step 1 and Step 2 because the signal magnitude is similar to a normal read signal (and less than a typical programming voltage). However, the memory system does not need to determine the state of the memory cell in response to the application of the "read signal." In Step 1 and Step 2, the read signal can be applied to all memory cells in the group to be programmed. Step 3 in this example encompasses both "write down" and "write up." Write down refers to the downward arrow in Step 3 of Table 950. Write up refers to the upward arrow in Step 3 of Table 950. The write signal is selectively applied only to those memory cells to be programmed into the state associated with the write signal. Steps 1 and 2, referred to as reading, are performed before the programming in step 3. However, the reading order in steps 1 and 2 can be interchanged. Write-up and write-down can be divided into separate write-up and write-down steps.

[0073] Table 950 will be discussed in more detail with reference to FIG. 9B. FIG. 9B depicts the change of threshold voltage over time in an embodiment of operating SOM cells in a crosspoint memory structure. A memory cell programmed to state W0 may have a Vth of approximately C_ low immediately after programming (t0). A memory cell programmed to state W1 may have a Vth of approximately C_ high immediately after programming (t0). It was previously assumed that a read was performed using an R0 signal with the same polarity as the signal used to program to W0. Here, the terms "low Vth state" and "high Vth state" are used to refer to two such states with different threshold voltages (programmed with different polarity programming voltages), assuming a preset polarity read signal. Line 906 depicts the upward drift of Vth of the threshold switch selector in the SOM cell programmed to state W0. By t1, the Vth of the W0 cell has drifted to "B". Figure 908 depicts the upward drift of Vth of the limit switch selector in the SOM cell programmed to state W1. By t1, Vth of the W1 cell has drifted to "A". The Vth drift shown in Figure 9B is quite large, but even a small Vth drift can cause problems such as half-selection issues.

[0074] Table 950 in Figure 9A, row 956, summarizes the Vth of a specific cell, which depends on the relative polarity of the last excitation voltage (row 952) and the polarity of the write voltage (row 954). A cell with a last excitation W1 and new data W1 has the same polarity voltage for both voltages; therefore, during the write of new data, the cell has a low Vth (B). However, a cell with a last excitation W1 and new data W0 has opposite polarity voltages for these two voltages; therefore, during the write of new data, the cell has a high Vth (A). A cell with a last excitation W0 (or R0) and new data W1 has opposite polarity voltages for these two voltages; therefore, during the write of new data, the cell has a high Vth (A). A cell with a last excitation W0 (or R0) and new data W0 has the same polarity voltage for these two voltages; therefore, during the write of new data, the cell has a low Vth (B).

[0075] Referring now to an embodiment of the programming process, step 1 may include applying a down read signal to all cells in a group of cells to be programmed. For ease of discussion, the read signal will be referred to as the read voltage. However, the read signal may be a read current that increases (or decreases) the select word line voltage to generate a voltage across the selected memory cell (this voltage may be clamped or otherwise limited to a maximum read voltage). Step 1 activates (turns on) all memory cells whose Vth is equal to or lower than the maximum read voltage value. Referring to FIG. 9B, the maximum read voltage may be "MaxV for reading". This down read voltage will turn on the selector in the last cell of the first series W0. Furthermore, activating the selector may reset Vth, causing Vth to decrease from B to C. Referring to graph 906 in FIG. 9B, Vth resets from bit B (at t1) to bit C (at t0). However, the Vth of cell W1 is higher than the MaxV for reading, and therefore will not be triggered (activated) by the down read voltage. Therefore, the W1 unit will not be rebuilt.

[0076] Step 2 is an upward read, which activates (turns on) the memory cell finally programmed as W1. This upward read signal can be applied to all memory cells in the group to be programmed. Note that the polarity of the upward read is the same as the W1 signal. Therefore, it has a lower Vth effect on the W1 cell. Therefore, step 2 shows that the W1 cell has Vth B. As shown in Figure 9B, the maximum value of the read voltage can be "MaxV for read". However, the polarity of the read voltage is opposite to the polarity of the read voltage in step 1. This upward read voltage will turn on the selector in the last first-order W1 cell. Therefore, graph 908 can be regarded as a graph of the assumed downward read Vth. However, applying the upward read voltage can be regarded as moving the W1 cell from graph 906 to graph 908. As a result, the upward read voltage has a sufficient value to turn on (activate) the selector in the W1 cell. Therefore, the selector in the W1 cell can be refreshed. Vth can be reduced from B to C. Referring to curve 906 in Figure 9B, assuming that Vth can be read from bit B (at t1) to bit C (at t0) by using an upward read voltage to reread the cell, however, using a downward read voltage to reread the cell may result in Vth being C high.

[0077] Step 3 in this example encompasses both write-down and write-up. The write-down signal is applied only to cells that are in the W0 state. By definition, all cells written with the write-down signal end in the C_low state, assuming the default read signal will be a write-down signal. The write-up signal is applied only to cells that are in the W1 state. By definition, all cells written with the write-up signal end in the C_high state, assuming the default read signal will be a write-down signal.

[0078] The programming process allows for a reduction in the value of the programmed voltage while still maintaining sufficient HS margin. Referring to Figure 9B, some example values ​​are illustrated below. The value of C_low can be approximately 2.5V. The value of C_high can be approximately 3.5V. The Vth drift during the example time period can be approximately 0.5V (for both states). Therefore, the maximum drift value in the high Vth state can be approximately 4.0V, and the maximum drift value in the low Vth state can be approximately 3.0V. In this example, the value of MaxV used for reading can be approximately 3.25V. Therefore, the MaxV used for reading can be the midpoint between the maximum drift value in the low Vth state and the maximum drift value in the high Vth state. Applying +3.25V across cells will activate the threshold switching selector in the low Vth state. Applying -3.25V across cells will activate the threshold switching selector in the high Vth state. Assuming the cell used for the high Vth state is refreshed to approximately 3.5V (positive for the preset read polarity in this example), a programmed voltage of approximately 3.7V can be used to allow for a safety margin. The programmed voltages for both states can have the same value but opposite polarities.

[0079] Figure 10 is a flowchart of an embodiment of program 1000 for SOM cells in a programmed crosspoint memory structure. Each SOM cell has a threshold switching selector, such as, but not limited to, OTS. Program 1000 may employ voltage forcing techniques such as those in Figure 6A or current forcing techniques such as those in Figure 6B. Step 1002 includes applying a first signal having a first polarity to a set of memory cells selected for programming. In one embodiment, the set contains one memory cell in each of several blocks. The first signal activates the threshold switching selector in the first set of memory cells. The first set of memory cells may be, for example, the memory cells last programmed as W0. In one embodiment, the memory cells last programmed as W1 will not be activated (e.g., the threshold switching selector will not be activated). Step 1002 may re-activate the Vth of the threshold switching selector in the first set of new cells. Referring to line 906 in Figure 9B as an example, Vth can be changed from bit B to bit C. Referring to Figure 6A, voltage Vs can be replaced by Vread. Step 1002 may include applying Vread to the selected word line while applying 0V to the selected bit line. Referring to Figure 6B, Iaccess can be replaced by Iread and Vs can be replaced by Vread. Step 1002 may include applying Iread to the selected word line while applying 0V to the selected bit line. In both the voltage-forced and current-forced examples, a positive voltage will exist across the selected unit from the selected word line to the selected bit line. Furthermore, in step 1002, Vread / 2 can be applied to the unselected word line and the unselected bit line.

[0080] Step 1004 includes applying a second signal having a second polarity to the set of memory cells selected for programming. The second signal activates a threshold switching selector in the second set of memory cells. The second set of memory cells may be, for example, the memory cells last programmed as W1. The second signal may have the same magnitude as the first signal (but with the opposite polarity). Step 1004 may apply Vth to the threshold switching selector in the second set of new cells. Step 1004 may include applying Vread to the selected bit line while applying 0V to the selected word line. Step 1004 may include applying a negative read current to the selected word line while applying Vs to the selected bit line. Here, a negative read current means that the current driver can draw current from the selected word line. And, in step 1004, Vread / 2 may be applied to the unselected word line and the unselected bit line. In both the voltage-forced and current-forced instances, a negative voltage will exist across the selection unit from the select word line to the select bit line.

[0081] Step 1006 includes applying a third signal with a first polarity to a third set of the memory cells after applying both the first signal and the second signal to the group of memory cells. The third signal programs the threshold switching selector of the memory cells in the third set to a first state. The third set of cells may include, for example, cells to be programmed to W0. Referring to FIG9A, the third set may include some cells with a last excitation 952 (before reading) having W1 and some cells with a last excitation 952 (before reading) having W0. Referring to FIG6A, the voltage Vs can be replaced by Vwrite. Step 1006 may include applying Vwrite to the selected word line while applying 0V to the selected bit line. Referring to FIG6B, Iaccess can be replaced by Iwrite and Vs can be replaced by Vwrite. Step 1006 may include applying Iwrite to the selected word line while applying 0V to the selected bit line. And, in step 1006, Vwrite / 2 may be applied to the unselected word line and the unselected bit line. In both the voltage-forced and current-forced instances, a positive voltage will exist across the selection unit from the selected word line to the selected bit line.

[0082] Step 1008 includes applying both the first signal and the second signal to the group of memory cells, and then applying a fourth signal of second polarity to a fourth set of the group of memory cells. The fourth signal programs the threshold switching selector of the memory cells in the fourth set to a second state. The fourth set of cells may include, for example, cells to be programmed as W1. Referring to FIG9A, the fourth set may include some cells with a last excitation 952 (before reading) having W1 and some cells with a last excitation 952 (before reading) having W0. Referring to FIG6A, step 1008 may include applying Vwrite to the selected bit line and applying 0V to the selected word line. For unselected word lines and unselected bit lines, Vs can be replaced by Vwrite. Referring to Figure 6B, Iaccess can be replaced with Iwrite, which has a negative value (e.g., the current driver draws Iwrite from the selected word line 606g). Vs can be replaced with Vwrite. Furthermore, in step 1008, Vwrite / 2 can be applied to the unselected word line and the unselected bit line. In both the voltage-forced and current-forced examples, a negative voltage will exist across the selected cell from the selected word line to the selected bit line.

[0083] In one embodiment, steps 1006 and 1008 are performed simultaneously. For example, selected SOM cells in each of the first set of blocks may be written in step 1006, while selected SOM cells in each of the second set of blocks may be written in step 1008. In one embodiment, step 1006 is performed before step 1008. In one embodiment, step 1008 is performed before step 1006.

[0084] Figure 11 is a flowchart of an embodiment of program 1100 for a SOM cell in a programmed crosspoint memory structure. Each SOM cell has a threshold switching selector, such as, but not limited to, OTS. Program 1100 provides further details of an embodiment of program 1000. In one embodiment, the group of cells to be programmed contains a memory cell in each of several blocks. Program 1100 may employ voltage forcing techniques such as those in Figure 6A or current forcing techniques such as those in Figure 6B. Step 1102 includes applying a first read signal to the group of memory cells to trigger a cell programmed to a first state rather than a second state. As an example, the first read signal may trigger a cell programmed to W0, but not the other cells programmed to W1. The triggering cell turns on the threshold switching selector, which may re-establish the Vth of the threshold switching selector. Step 1102 may include applying Vread to the selected word line while applying 0V to the selected bit line. Step 1102 may include applying Iread to the selected word line while simultaneously applying 0V to the selected bit line. When Iread is applied, the voltage across each memory cell may be limited or capped.

[0085] Step 1104 includes applying a second read signal to the memory cell group. The second read signal has the opposite polarity to the first read signal. Applying the second read signal results in the same maximum voltage across the memory cells as applying the first read signal. The second signal activates a threshold switching selector in at least a second set of memory cells. The second set of memory cells may be, for example, the memory cells last programmed as W1. Step 1104 may set the threshold switching selector Vth in the second set of new cells. Step 1104 may include applying Vread to the selected bit line while applying 0V to the selected word line. Step 1104 may include drawing Iread from the selected word line while applying a selection voltage to the selected bit line. When Iread is applied, the voltage across each memory cell may be limited or capped.

[0086] Step 1106 includes applying a first write signal to a first set of cells in the group to write the first set to the first state. The first write signal has the same polarity as the first read signal. The first set of cells may include, for example, cells to be programmed as W0. Step 1106 may include applying Vwrite to the selected word line while applying 0V to the selected bit line. Step 1106 may include applying Iwrite to the selected word line while applying 0V to the selected bit line.

[0087] Step 1108 includes applying a second write signal to a second set of cells in the group to write the second set to the second state. The second write signal has the opposite polarity to the first write signal. The second set of cells may include, for example, cells to be programmed as W1. Step 1108 may include applying Vwrite to the selected bit line while applying 0V to the selected word line. Step 1108 may include drawing Iwrite from the selected word line while applying a selection voltage to the selected bit line.

[0088] In one embodiment, steps 1106 and 1108 are performed simultaneously. In one embodiment, step 1106 is performed before step 1108. In one embodiment, step 1108 is performed before step 1106.

[0089] Figure 12 is a flowchart of an embodiment of program 1200 for SOM cells in a programmed cross-point memory structure. Each SOM cell has a threshold switching selector, such as, but not limited to, OTS. Program 1200 provides further details of an embodiment of program 1000. In one embodiment, the group of SOM cells to be programmed contains a memory cell in each of several blocks. Program 1200 may employ voltage forcing techniques such as those in Figure 6A or current forcing techniques such as those in Figure 6B. Step 1202 includes forming a first voltage across each cell in the group of memory cells to reduce threshold voltage drift of the threshold switching selector in the memory cells in the group that were most recently programmed to a first state. The first set of memory cells may be, for example, the memory cells last programmed to WO. Step 1202 may include applying a first voltage to a select word line while applying 0V to a select bit line. Step 1202 may include applying current to the selected word line while simultaneously applying 0V to the selected bit line to generate a first voltage across the cells. In one embodiment, the first voltage has a maximum value. In a current-forced method, a fixed amount of current may be used to charge the selected word line, but the word line voltage may be limited to a maximum voltage.

[0090] Step 1204 includes forming a second voltage across each cell in the group of memory cells after the first voltage. The second voltage has the same magnitude but opposite polarity as the first voltage. The second voltage can reduce the threshold voltage drift of the threshold switching selector in the memory cells of the group that have recently been programmed to the second state (e.g., W1). Step 1204 may include applying the second voltage to the select bit line while applying 0V to the select word line. Step 1204 may include drawing current from the select word line while applying a high voltage to the select bit line to generate the second voltage across the cells. In a current-forced method, the select word line and the select bit line may each be pre-charged to about half the final voltage of the select bit line (e.g., 1.65V). The select bit line can then be raised to a higher voltage (e.g., 3.3V) using the current used to reduce the voltage on the select word line. In this example, the lowest voltage that the select word line can reach is 0V. Therefore, the voltage across the selection unit is limited to the maximum voltage.

[0091] Step 1206 includes forming a third voltage of a first polarity across each cell in the first set of memory cells to write an adjacency switching selector in the first set of memory cells to a first state. The first set of cells may include, for example, cells to be programmed as W0. Step 1206 may include applying Vwrite to the select word line while applying 0V to the select bit line. Step 1206 may include applying a write current to the select word line while applying 0V to the select bit line to generate the third voltage across the cells.

[0092] Step 1208 includes forming a fourth voltage of a second polarity across each cell in the second set of memory cells to write the threshold switching selector in the second set of memory cells to a second state. The second set of cells may include, for example, cells to be programmed as W1. Step 1208 may include applying Vwrite to the select bit line while applying 0V to the select word line. Step 1208 may include drawing write current from the select word line while applying a high voltage to the select bit line to generate the fourth voltage across the cells.

[0093] In one embodiment, steps 1206 and 1208 are performed simultaneously. In one embodiment, step 1206 is performed before step 1208. In one embodiment, step 1208 is performed before step 1206.

[0094] In view of the foregoing, it can be seen that, according to one embodiment, a device includes one or more control circuits configured to be connected to a cross-point structure having self-selecting memory cells. Each selected memory cell has an adjacency switching selector. The one or more control circuits are configured to apply a first signal having a first polarity to a set of memory cells selected for programming. The first signal activates the adjacency switching selectors in a first set of the memory cells. The one or more control circuits are configured to apply a second signal having a second polarity to the set of memory cells selected for programming. The second signal activates the adjacency switching selectors in a second set of the memory cells. After applying both the first signal and the second signal to the set of memory cells, the one or more control circuits are configured to apply a third signal having the first polarity to a third set of the set of memory cells. The third signal programs the adjacency switching selectors in the third set of the memory cells to a first state. The one or more control circuits are configured to apply a fourth signal of the second polarity to a fourth set of the memory cells after both the first signal and the second signal are applied to the group of memory cells. The fourth signal programs the threshold switching selectors in the fourth set of the memory cells to a second state.

[0095] In a further embodiment, the one or more control circuits are configured to establish a value of the first signal to generate a maximum voltage across the memory cells in the group, the maximum voltage being between a first maximum drift threshold voltage of one of the memory cells in the group most recently programmed to the first state and a second maximum drift threshold voltage of one of the memory cells in the group most recently programmed to the second state.

[0096] In a further embodiment, the one or more control circuits are configured to establish a value of the first signal to generate a maximum voltage across the memory cells in the group, the maximum voltage being at a midpoint between a first maximum drift threshold voltage of a memory cell in the group programmed to a low threshold voltage state and a second maximum drift threshold voltage of a memory cell in the group programmed to a high threshold voltage state.

[0097] In a further embodiment, the first set of memory cells has recently been programmed into the first state. The first signal has a magnitude and polarity that activate the threshold switching selectors of the memory cells recently programmed into the first state, but does not activate the threshold switching selectors of the memory cells recently programmed into the second state.

[0098] In a further embodiment, the first signal has a magnitude and polarity to remove the drift of the threshold voltage of the threshold switching selectors of the first set of memory cells, but does not turn on the threshold switching selectors of the second set of memory cells.

[0099] In a further embodiment, the second signal has a magnitude and polarity to remove the drift of the threshold voltage of the threshold switching selectors of the second set of memory cells that have recently been programmed into the second state.

[0100] In a further embodiment, the first signal has a value to distinguish the first state from the second state. The second signal has the same value to distinguish the first state from the second state.

[0101] In a further embodiment, the one or more control circuits are configured to simultaneously apply the third signal to the third set of the group of memory cells and apply the fourth signal to the fourth set of the group of memory cells.

[0102] In a further embodiment, the one or more control circuits are configured to apply the third signal to the third set of the memory cells and the fourth signal to the fourth set of the memory cells without responding to the first signal or the second signal to determine the state of the memory cells.

[0103] In a further embodiment, the first signal and the second signal are voltages of substantially the same magnitude.

[0104] In a further embodiment, the first signal and the second signal are currents of substantially the same magnitude.

[0105] One embodiment includes a method for operating a cross-point memory structure having one of its self-selecting memory cells. The method includes applying a first read signal to a group of memory cells, the first read signal triggering a memory cell most recently programmed to a first state but not triggering a memory cell most recently programmed to a second state. The first read signal has a first polarity and generates a first maximum voltage across each specific cell in the group. The method includes, after applying the first read signal to the group of memory cells, applying a second read signal to the group. The second read signal has a second polarity opposite to the first polarity and generates the first maximum voltage across each specific cell in the group. The method includes, after applying both the first read signal and the second read signal to the group of memory cells, applying a first write signal to a first set of one of the group of memory cells to write the first set to the first state. The first write signal has the first polarity. The method includes applying both the first read signal and the second read signal to the group of memory cells, and then applying a second write signal to a second set of one of the group of memory cells to write the second set into the second state. The second write signal has the second polarity.

[0106] One embodiment includes a memory system comprising a crosspoint memory structure having first conductive lines, second conductive lines, and memory cells. Each memory cell is located at a junction of one of the first conductive lines and one of the second conductive lines. Each memory cell has a threshold switching selector. The memory system has one or more control circuits communicating with the crosspoint memory structure. The one or more control circuits are configured to cause a first voltage across each memory cell in a set of memory cells selected for programming. The first voltage has a first maximum value and a first polarity that reduces the threshold voltage drift of the threshold switching selectors in the set of memory cells most recently programmed to a first state. The one or more control circuits are configured to cause a second voltage across each memory cell in the set of memory cells after causing the first voltage across the set of memory cells. The second voltage substantially has the first maximum value and a second polarity opposite to the first polarity. The one or more control circuits are configured to generate a third voltage of the first polarity across each memory cell in a first set of memory cells in the group, to write the threshold switching selectors of the memory cells in the first set into the first state. The third voltage is generated after both the first voltage and the second voltage are generated. The one or more control circuits are configured to generate a fourth voltage of the second polarity across each memory cell in a second set of memory cells in the group, to write the threshold switching selectors of the memory cells in the second set into a second state. The fourth voltage is generated after both the first voltage and the second voltage are generated.

[0107] For the purposes of this document, references to "an embodiment", "one embodiment", "some embodiments" or "another embodiment" in this specification may be used to describe different or the same embodiments.

[0108] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when an element is referred to as a connection or coupling to another element, the element may be directly connected to the other element or indirectly connected to the other element via an intermediary element. When an element is referred to as a direct connection to another element, there is no intermediary element between the element and the other element. If two devices are directly or indirectly connected such that they can transmit electronic signals between them, the devices are "in communication".

[0109] For the purposes of this document, the term "based on" may be interpreted as "based at least in part on".

[0110] For the purposes of this document, without additional context, the use of numerical terms (such as “first” object, “second” object, and “third” object) may not imply the order of objects, but may be used instead for identification purposes to identify different objects.

[0111] The terms “top” and “bottom”, “upper” and “lower”, and “vertical” and “horizontal” and their forms used herein are for illustrative purposes only, and are not intended to limit the description of the technique, as the items referred to can be interchanged in position and orientation. Furthermore, as used herein, the terms “substantially” and / or “about” mean that the specified dimensions or parameters may vary within acceptable tolerances for a given application.

[0112] The above embodiments have been provided for purposes of illustration and description. They are not intended to be exhaustive or limited to the precise forms disclosed. In view of the above teachings, many modifications and variations are possible. The described embodiments have been selected to best explain the principles and practical application of the proposed technology, thereby enabling those skilled in the art to best utilize it in various embodiments and to contemplate various modifications suitable for that particular purpose. It is intended that this scope be defined by the appended claims. [Simplified Explanation of the Diagram]

[0012] Components with similar numbers refer to common components in different diagrams. [Fig. 1A] A graph depicting the threshold voltage of an SOM cell changing over time. [Fig. 1B] A table showing a conventional programming scheme used in conjunction with an SOM cell. [Fig. 2] A block diagram of an embodiment of a non-volatile memory system connected to a host computer. [Fig. 3A] A block diagram of an embodiment of a memory die. [Fig. 3B] A block diagram of an embodiment of an integrated memory assembly containing control dies and memory structure dies. [Fig. 4A] An embodiment of a memory array forming a crosspoint architecture depicted in perspective. [Fig. 4B] and [Fig. 4C] A side view and a top view of the crosspoint structure in Fig. 4A, respectively. [Fig. 4D] An embodiment of a second-order memory array forming a crosspoint architecture depicted in perspective. [Fig. 5] An embodiment of the structure of an SOM memory cell. [Figure 6A] and [Figure 6B] illustrate an embodiment for accessing a selected SOM cell in a crosspoint memory structure. [Figure 7] is a flowchart of an embodiment of a program for a two-terminal threshold switching selector memory cell in a programmable crosspoint array. [Figure 8] illustrates two "Vth distributions" of an embodiment of a programmable SOM cell. [Figure 9A] is a table showing details of an embodiment of a SOM cell in a programmable crosspoint memory structure. [Figure 9B] depicts the change of threshold voltage over time in an embodiment of operating a SOM cell in a crosspoint memory structure. [Figure 10] is a flowchart of an embodiment of a program for a SOM cell in a programmable crosspoint memory structure. [Figure 11] is a flowchart of an embodiment of a program for a SOM cell in a programmable crosspoint memory structure. [Figure 12] is a flowchart of an embodiment of a program for a SOM cell in a programmable crosspoint memory structure.

Claims

1. A memory device comprising: one or more control circuits configured to be connected to a cross-point structure having self-selectable memory cells, each selected memory cell having an adjacency switching selector, the one or more control circuits being configured to: apply a first signal having a first polarity to a set of memory cells selected for programming, the first signal activating the adjacency switching selectors in a first set of the memory cells; and apply a second signal having a second polarity to the set of memory cells selected for programming, the second signal activating the adjacency switching selectors in a second set of the memory cells; After applying both the first signal and the second signal to the group of memory cells, a third signal having the first polarity is applied to a third set of the group of memory cells, the third signal programming the threshold switching selectors in the third set of the memory cells to a first state; and after applying both the first signal and the second signal to the group of memory cells, a fourth signal having the second polarity is applied to a fourth set of the group of memory cells, the fourth signal programming the threshold switching selectors in the fourth set of the memory cells to a second state.

2. The memory device of claim 1, wherein the one or more control circuits are configured to establish a value of the first signal to generate a maximum voltage across the memory cells in the group, the maximum voltage being between a first maximum drift threshold voltage of one of the memory cells in the group most recently programmed to the first state and a second maximum drift threshold voltage of one of the memory cells in the group most recently programmed to the second state.

3. The memory device of claim 1, wherein the one or more control circuits are configured to establish a value of the first signal to generate a maximum voltage across the memory cells in the group, the maximum voltage being at a midpoint between a first maximum drift threshold voltage of a memory cell in the group programmed to a low threshold voltage state and a second maximum drift threshold voltage of a memory cell in the group programmed to a high threshold voltage state.

4. The memory device of claim 1, wherein the first set of the memory cells has recently been programmed to the first state, and the first signal has a magnitude and polarity that enables the threshold switching selectors of the memory cells recently programmed to the first state, but does not enable the threshold switching selectors of the memory cells recently programmed to the second state.

5. The memory device of claim 1, wherein the first signal has a magnitude and polarity to remove the drift of the threshold voltage of the threshold switching selectors of the first set of memory cells, but does not turn on the threshold switching selectors of the second set of memory cells.

6. The memory device of claim 5, wherein the second signal has a magnitude and polarity to remove the drift of the threshold voltage of the threshold switching selectors of the second set of memory cells that have recently been programmed into the second state.

7. The memory device as requested in item 1, wherein: The first signal has a value to distinguish the first state from the second state; and the second signal has the same value to distinguish the first state from the second state.

8. The memory device of claim 1, wherein the one or more control circuits are configured to simultaneously apply the third signal to the third set of the group of memory cells and apply the fourth signal to the fourth set of the group of memory cells.

9. The memory device of claim 1, wherein the one or more control circuits are configured to: apply a third signal to the third set of the memory cells and apply a fourth signal to the fourth set of the memory cells without responding to the first signal or the second signal to determine the state of the memory cells.

10. The memory device of claim 1, wherein the first signal and the second signal are voltages having substantially the same magnitude.

11. The memory device of claim 1, wherein the first signal and the second signal are currents having substantially the same magnitude.

12. A method for operating a cross-point memory structure having one of self-selecting memory cells, the method comprising: applying a first read signal to a group of memory cells, the first read signal triggering a memory cell most recently programmed to a first state but not triggering a memory cell most recently programmed to a second state, the first read signal having a first polarity and generating a first maximum voltage across each specific cell in the group; after applying the first read signal to the group of memory cells, applying a second read signal to the group, the second read signal having a second polarity opposite to the first polarity and generating the first maximum voltage across each specific cell in the group; After applying both the first read signal and the second read signal to the group of memory cells, a first write signal is applied to a first set of the group of memory cells to write the first set to the first state, the first write signal having the first polarity; and after applying both the first read signal and the second read signal to the group of memory cells, a second write signal is applied to a second set of the group of memory cells to write the second set to the second state, the second write signal having the second polarity.

13. The method of claim 12, further comprising: establishing a magnitude of the first read signal to generate a maximum voltage across the memory cells in the group, the maximum voltage being between a first maximum drift threshold voltage of one of the memory cells in the group most recently programmed to the first state and a second maximum drift threshold voltage of one of the memory cells in the group most recently programmed to the second state.

14. The method of claim 12, further comprising: establishing a magnitude of the first read signal to generate a maximum voltage across the memory cells in the group, the maximum voltage being at a midpoint between a first maximum drift threshold voltage of a memory cell programmed to a low threshold voltage state and a second maximum drift threshold voltage of a memory cell programmed to a high threshold voltage state.

15. The method of claim 12, wherein applying the first write signal to the first set of the group and applying the second write signal to the second set of the group is performed without determining the memory cell state in response to the first read signal or the second read signal.

16. A memory system comprising: a crosspoint memory structure having first conductive lines, second conductive lines, and memory cells, each memory cell being located at a junction of one of the first conductive lines and one of the second conductive lines, each memory cell having a threshold switching selector; one or more control circuits communicating with the crosspoint memory structure, the one or more control circuits being configured to: cause a first voltage across each memory cell in a set of memory cells selected for programming, the first voltage having a first maximum value and a first polarity, reducing threshold voltage drift of the threshold switching selectors in the memory cells in the set of memory cells most recently programmed to a first state; after causing the first voltage across the set of memory cells, cause a second voltage across each memory cell in the set of memory cells, the second voltage substantially having the first maximum value and a second polarity opposite to the first polarity; A third voltage of the first polarity is generated in each memory cell of the first set of memory cells in the group, to write the threshold switching selectors of the memory cells in the first set into the first state, the third voltage being generated after the first voltage and the second voltage are generated; and a fourth voltage of the second polarity is generated in each memory cell of the second set of memory cells in the group, to write the threshold switching selectors of the memory cells in the second set into a second state, the fourth voltage being generated after the first voltage and the second voltage are generated.

17. The memory system of claim 16, wherein the one or more control circuits are configured to form the first maximum value of the first voltage, the first voltage being between a first maximum drift threshold voltage of one of the memory cells most recently programmed to the first state and a second maximum drift threshold voltage of one of the memory cells most recently programmed to the second state.

18. The memory system of claim 16, wherein the one or more control circuits are configured to form the first maximum value of the first voltage, the first voltage being at a midpoint between a first maximum drift threshold voltage of a memory cell programmed to a low threshold voltage state and a second maximum drift threshold voltage of a memory cell programmed to a high threshold voltage state.

19. The memory system of claim 16, wherein the one or more control circuits are configured to: cause the first maximum value of the first voltage to re-establish the drift threshold voltage of the memory cells most recently programmed to the first state, without triggering the threshold switching selector in the memory cells most recently programmed to the second state.

20. The memory system of claim 16, wherein the one or more control circuits are configured to: simultaneously cause the third voltage across memory cells in the first set and the fourth voltage across memory cells in the second set.

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