Memory apparatus, method for seasoning threshold switching selectors, and memory system

Abstract

A technique for modulating (forming) threshold switching selectors in a crossbar switch array is disclosed. The Vth of these threshold switching selectors in the crossbar switch array is progressively reduced over several modulation cycles. A memory cell selected for modulating the threshold switching selector has a modulation signal applied to that cell. The magnitude of the modulation signal is progressively reduced over each modulation cycle. Since the Vth of these threshold switching selectors is only fully formed after several modulation cycles, this progressive reduction of the Vth of these threshold switching selectors "partially forms" the threshold switching selectors within each cycle.

Description

[Technical Field]

[0001] This invention relates to a technique for modulating (or forming) a limit switching selector in a cross switch array. [Previous Technology]

[0002] Memory systems are widely used in various electronic devices, such as cellular phones, digital cameras, personal digital assistants, medical electronic devices, mobile computing devices, non-mobile computing devices, and data servers. Memory can include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when it is not connected to a power source (e.g., a battery pack). Non-volatile memory can be made non-volatile, at least for a limited time, by adding a battery pack back to the power supply outside the memory chip.

[0003] Memory cells can reside in a cross-point memory array. In a memory array with a cross-point architecture, one set of conductive lines travels across the surface of the substrate, and another set of conductive lines is formed above this set of conductive lines, traveling in an orthogonal direction relative to the initial layer. The memory cells are located at the intersection of the two sets of conductive lines. Cross-point memory arrays are sometimes called cross-bar memory arrays.

[0004] Programmable resistive memory cells have a material with programmable resistance. In a binary approach, a programmable resistive memory cell can be programmed into one of two resistance states: a high resistance state (HRS) and a low resistance state (LRS). In some approaches, more than two resistance states can be used. One type of programmable resistive memory cell is a magnetoresistive random access memory (MRAM) cell. Compared to some other memory technologies that use electron charge (DRAM) or voltage (SRAM) to store data, MRAM cells use magnetization to indicate that data has been stored. One bit of data is written to the MRAM cell by changing the magnetization direction of the magnetic elements ("free layer") within the MRAM cell, and one bit is read by measuring the resistance of the MRAM cell, which varies with the magnetization direction. However, crosspoint memory arrays can have other types of memory cells. For example, cross-point memory arrays can have memory cells using other technologies such as ReRam, PCM (phase change memory), and FeRam.

[0005] In a crosspoint memory array, each memory cell may contain a threshold switching selector connected in series with a material having a programmable resistor. The threshold switching selector has a high resistance (off or non-conductive) until it is biased to a voltage higher than its threshold voltage (Vt) or a current (It) higher than its threshold current, and until its voltage bias drops below Vhold ("Voffset") or its current drops below the holding current Ihold. After crossing the threshold switching selector beyond Vt and simultaneously beyond Vhold, the threshold switching selector has a relatively low resistance (on or conductive). The threshold switching selector remains on until its current drops below the holding current Ihold, or its voltage drops below the holding voltage Vhold. When this occurs, the threshold switching selector returns to the off (higher) resistance state. To read a memory cell, the threshold switching selector is activated by turning it on before determining the resistance state of the memory. One example of a threshold switching selector is a dual threshold switch (OTS). Other examples of threshold switching selectors include, but are not limited to, volatile conductive bridges (VCBs), metal-insulator-metals (MIMs), or other materials that provide a highly nonlinear dependence of current on the selected voltage. [Summary of the Invention]

[0006] A technique for modulating (forming) threshold switching selectors in a crossbar switch array is disclosed. The Vth of the threshold switching selectors in the crossbar switch array is progressively reduced over several modulation cycles. A memory cell selected for modulating the threshold switching selector has a modulation signal applied to that cell. The magnitude of the modulation signal is progressively reduced over each modulation cycle. Since the Vth of the threshold switching selectors is only fully formed after several modulation cycles, the progressive reduction of the Vth of the threshold switching selectors "partially forms" the threshold switching selectors over each cycle.

Implementation Method

[0008] A technique for modulating (or forming) a threshold switching selector in a crossbar switch array is disclosed. When the threshold switching selector is first turned on during the lifetime of the memory device, the threshold voltage (Vth) is substantially higher than during normal operation (such as reading or writing). The voltage required to turn on the selector during initial use (referred to as the first discharge voltage) is substantially higher than the target voltage range required to turn on the selector during normal operation. This is due to a transformation that occurs on the threshold switching selector during a process referred to as "seasoning" or "forming," which reduces the Vth of the threshold switching selector. The state of the selector can be transformed from an initial amorphous state with an initial threshold voltage (Vinit) to an operating state with an operating threshold voltage (Vop) lower than the initial threshold voltage. This transformation results in a permanent reduction in the threshold voltage (Vth) of the selector. This transformation results in a structural change, which may be due to the thermal effects of the selector material.

[0009] In one embodiment, the Vth of the threshold switching selectors in the crossbar switch array is progressively reduced over several modulation cycles. Since the Vth of the threshold switching selector is only fully formed after several modulation cycles, progressively reducing the Vth of the threshold switching selector can be referred to as "partially forming" the threshold switching selector. In one embodiment, the memory cell selected for modulating the threshold switching selector has a modulation voltage (Vs) applied to that cell. A half-select voltage can be applied to some memory cells in the crossbar switch array, and these memory cells are referred to as "half-selected cells". The half-select voltage (Vs / 2) has a value approximately half that of the modulation voltage. In one embodiment, the progressive reduction of the Vth of the threshold switching selector makes the Vth of the threshold switching selector greater than the half-select voltage (Vs / 2). Therefore, such half-selected cells will not cause their individual threshold switching selectors to erroneously turn on during the modulation procedure. A faulty conduction of a half-selected cell can prevent modulation of the threshold switching selector in the selected memory cell. Furthermore, the Vth of the threshold switching selector can be progressively reduced so that, during each cycle of the modulation procedure, the Vth of the threshold switching selector is lower than the modulation voltage (Vs).

[0010] In one embodiment, the memory system includes programmable resistive memory cells residing in a crosspoint memory array. In a memory array with a crosspoint architecture, one set of conductive lines travels across the surface of a substrate, and another set of conductive lines is formed above this set of conductive lines and travels on the substrate in a direction perpendicular to the set of conductive lines. The memory cells are located at the crosspoint junction of the two sets of conductive lines. Crosspoint memory arrays are sometimes referred to as cross-bar memory arrays. In one embodiment, each memory cell has a magnetoresistive memory element connected in series with an OTS, which may be referred to as an MRAM memory cell. However, crosspoint memory arrays may have other types of memory cells. For example, crosspoint memory arrays may have memory cells using other technologies such as ReRAM, PCM (phase-change memory), and FeRAM. Furthermore, the threshold switching selector does not need to be an OTS and may have a pair of diodes from anode to cathode.

[0011] In some embodiments, the programmable resistive memory cell has a magnetoresistive random access memory (MRAM) element. As used herein, the magnetization direction is the direction in which the magnetic moment is oriented relative to a reference direction set by another element of the MRAM ("reference layer"). In some embodiments, low resistance is referred to as parallel or P state or LRS, and high resistance is referred to as antiparallel or AP state or HRS. The MRAM can use spin-transfer torque effect to change the magnetization direction from P state to AP state and vice versa, which generally requires bipolar (bidirectional write) operation for writing. However, the SRR of the programmable resistive memory cell as disclosed herein is not limited to memory cells having MRAM elements or OTS elements.

[0012] FIG1 is a block diagram of one embodiment of a non-volatile memory system (or more simply, a "memory system") 100 connected to a host system 120. The memory system 100 may implement the techniques presented herein for a system that modulates a threshold switching selector in a programmable resistive memory cell. In one embodiment, the memory cell has a programmable resistive memory element (e.g., an MRAM element) connected in series with a threshold switching selector, such as an OTS. Many types of memory systems can be used with the techniques presented herein. Example memory systems include dual in-line memory modules (DIMMs), solid-state drives ("SSDs"), memory cards, and embedded memory devices; however, other types of memory systems may also be used.

[0013] The memory system 100 of FIG1 includes a memory controller 102, a memory 104 for storing data, and local memory 140 (e.g., MRAM, ReRAM, DRAM). Local memory 140 may be non-volatile and retain data after power is turned off. Local memory 140 may be volatile and not expected to retain data after power is turned off. In one embodiment, local memory 140 is MRAM. In one embodiment, local memory MRAM does not need to retain data after power is turned off. However, local memory MRAM may retain data after power is turned off. In one embodiment, memory controller 102 and / or local memory controller 164 provide access to programmable resistive memory cells in local memory 140. For example, memory controller 102 may provide access to an array of cross-point MRAM cells in local memory 140. In another embodiment, memory controller 102 or interface 126, or both, are removed, and the memory package is directly connected to host 120 via a bus such as DDRn, or connected to the host memory management unit (MMU). In another case, memory controller 102 or part thereof is moved to memory 104 to directly connect memory 104 to the host, such as by providing parity bits, ECC, and wear leveling on memory 104, and a DDRn interface to / from the host or MMU. As used throughout this document, the term "memory system" is not limited to memory system 100. For example, local memory 140, or a combination of local memory 140 and local memory controller 164, can be considered a memory system. Similarly, host memory 124, or a combination of host processor 122 and host memory 124, can be considered a memory system.

[0014] The components of the memory system 100 depicted in Figure 1 are circuits. The memory controller 102 has a host interface 152, a processor 156, an ECC engine 158, a memory interface 160, a local memory controller 164, regeneration logic 172, and a loss balancing 174. The host interface 152 is connected to and communicates with the host 120. The host interface 152 is also connected to the network-on-chip (NOC) 154. The NOC is a communication subsystem on an integrated circuit. The NOC can span synchronous and asynchronous clock domains or use asynchronous logic. NOC technology applies network theory and methods to on-chip communication and brings significant improvements beyond conventional bus and crossbar interconnects. Compared to other designs, the NOC improves the scalability of systems on a chip (SoC) and the power efficiency of complex SoCs. The wires and links of the NOC are shared by many signals. Because all links in the NOC can operate simultaneously on different data packets, a high degree of parallelism is achieved. Therefore, as the complexity of integrated subsystems continues to grow, the NOC offers enhanced performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signaling wires, shared buses, or segmented buses with bridges). In other embodiments, the NOC 154 may be replaced by a bus. The processor 156, ECC engine 158, memory interface 160, local memory controller 164, regeneration logic 172, and wear leveling 174 are connected to and communicate with the NOC 154. The local memory controller 164 is used to operate and communicate with local high-speed memory 140 (e.g., MRAM). In other embodiments, the local high-speed memory 140 may be DRAM, SRAM, or another type of volatile memory.

[0015] The ECC engine 158 performs error correction services. For example, the ECC engine 158 performs encoding and decoding of data provided on memory or in memory but not in memory, as part of a code word for error correction of data retrieved from memory 140 or 104. In one embodiment, the ECC engine 158 is implemented by software-programmable circuitry. For example, the ECC engine 158 may be a programmable processor. In other embodiments, the ECC engine 158 is implemented by custom-designed hardware circuitry without any software. In one embodiment, the functionality of the ECC engine 158 is implemented by processor 156. In one embodiment, local memory 140 has an ECC engine with or without a wear-leveling engine. In one embodiment, memory 104 has an ECC engine with or without a wear-leveling engine.

[0016] Processor 156 performs various controller memory operations, such as programming, erasing, reading, and memory management procedures including wear leveling. Processor 156 can be used for modulation operations of threshold switching selectors for memory cells. A separate wear leveling 174 is depicted, but wear leveling 174 can be implemented by processor 156. Additionally, refresh logic 172 is depicted, but refresh logic can also be implemented by processor 156. In one embodiment, processor 156 is programmed via firmware. In other embodiments, processor 156 is implemented without any custom-designed hardware circuitry requiring any software. Processor 156 also implements a translation module as either software / firmware or as dedicated hardware circuitry. In many systems, the non-volatile memory system uses physical addresses associated with one or more memory chips to internally address the storage system. However, the host system will use logical addresses to address various memory locations. This allows the host to assign data to consecutive logical addresses, while the storage system can freely store data across one or more memory chips as desired. To implement this system, the memory controller 102 (e.g., a translation module) performs address translation between logical addresses used by the host and physical addresses used by the memory chips. One implementation is a maintenance table (i.e., the L2P table mentioned above) that identifies the current translation between logical and physical addresses. Entries in the L2P table may include the identification of the logical address and the corresponding physical address. Although the logical address-to-physical address table (or L2P table) includes the word "table," it does not need to be a table literally. Instead, the logical address-to-physical address table (or L2P table) can be any type of data structure. In some instances, the memory space of the storage system is so large that the local memory 140 cannot maintain all L2P tables. In this case, the entire L2P table is stored in memory 104, and a subset of the L2P table is cached (L2P cache) in local high-speed memory 140.

[0017] The memory interface 160 communicates with the memory 104. In one embodiment, the memory 104 includes programmable resistive memory cells in a crosspoint array. In one embodiment, the memory 104 includes NAND memory cells. In one embodiment, the memory interface provides a toggle mode interface. Other interfaces may also be used. In some example implementations, the memory interface 160 (or another part of the controller 102) implements a scheduler and buffer for transferring data to one or more memory chips and receiving data from the one or more memory chips.

[0018] In one embodiment, local memory 140 has an ECC engine. Local memory 140 can be used to assist in performing other functions, such as wear leveling. Further details of on-chip memory maintenance are described in U.S. Patent No. 10,545,692, entitled "Memory Maintenance Operations During Refresh Window," and U.S. Patent No. 10,885,991, entitled "Data Rewrite During Refresh Window," both of which are incorporated herein by reference in their entirety. In one embodiment, local memory 140 is synchronous. In one embodiment, local memory 140 is asynchronous.

[0019] In one embodiment, the memory 104 includes a plurality of memory packages. Each memory package includes one or more memory chips. Therefore, the memory controller 102 is connected to one or more memory chips. In one embodiment, the memory package may include other types of memory, such as storage-class memory (SCM) based on programmable resistor random access memory (such as ReRAM, MRAM, FeRAM, or RRAM) or phase change memory (PCM). In one embodiment, the memory controller 102 provides access to memory cells in a cross-point array in the memory 104.

[0020] The memory controller 102 communicates with the host system 120 via an interface 152 implementing a protocol such as Compute Express Link (CXL). Alternatively, such a controller can be removed, and the memory package can be placed directly on the host bus, such as DDRn or CXL. To work with the memory system 100, the host system 120 includes a host processor 122, host memory 124, and interface 126 connected along bus 128. The host memory 124 is the host's physical memory and can be DRAM, SRAM, ReRAM, MRAM, non-volatile memory, or another type of memory. In one embodiment, the host memory 124 includes a crosspoint array of programmable resistive memory cells, wherein each memory cell includes a threshold switching selector connected in series with the programmable resistive memory element.

[0021] The host system 120 is external to and separate from the memory system 100. In one embodiment, the memory system 100 is embedded in the host system 120. The host memory 124 may be referred to herein as the memory system. Hereinafter, the combination of the host processor 122 and the host memory 124 may be referred to as the memory system. In one embodiment, this host memory may be a cross-point memory using MRAM.

[0022] FIG2 is a block diagram depicting an example of a memory die 292 that may implement the techniques described herein. In one embodiment, the memory die 292 is included in local memory 140, and in another embodiment, the memory die 292 is included in storage 104. In one embodiment, the memory die 292 is included in host memory 124. The memory die 292 includes a memory structure 202, which may include any of the memory cells described below. The memory structure 202 may include one or more memory arrays. The array terminal lines of the memory structure 202 include various layers(s) of word lines organized into columns and various layers(s) of bit lines organized into rows. However, other orientations may also be implemented, including, for example, a diagonal pattern to save space. The memory die 292 includes a column control circuitry 220, the outputs 208 of which are connected to the individual word lines of the memory structure 202. The column control circuitry 220 receives a set of M column address signals and one or more various control signals from the system control logic circuitry 260, and generally includes circuitry such as a column decoder 222, a column driver 224, and a block selection circuitry 226 for both read and write operations. The column control circuitry 220 may also include a read / write circuitry system. In one embodiment, the column decoding and control circuitry 220 has sense amplifiers 228, each containing circuitry for sensing the condition (e.g., voltage) of the word lines of the memory structure 202. In one embodiment, determining the condition or bit state of memory cells in the cross-point array by sensing word line voltage is done directly by comparing the voltage of the accessed memory cell with a reference voltage using a sense amplifier. Alternatively, a less direct approach involves first accessing the memory cell and storing the read voltage generated by forcing a read current through the cell and adjusting it up or down by 150mV (or half the voltage difference resulting from a change in bit state), then writing the cell to the AP state, accessing the memory cell again with the read current, and comparing the resulting voltage with the stored voltage adjusted, for example, by 150mV (or half the voltage difference resulting from two different bit states). The memory die 292 also includes a row decoding and control circuitry system 210, whose inputs / outputs 206 are connected to the individual bit lines of the memory structure 202. Although only a single block is shown for the memory structure 202, the memory die may include multiple arrays or "tiles" that can be individually accessed. The line control circuitry 210 receives a group of N line address signals and one or more various control signals from the system control logic 260, and generally may include circuitry such as a line decoder 212, a line decoder and driver 214, a block selection circuitry 216, a read / write circuitry, and an I / O multiplexer.

[0023] System control logic 260 receives data and commands from the host system and provides output data and status to the host system. In other embodiments, system control logic 260 receives data and commands from a separate controller circuit and provides output data to that controller circuit, which communicates with the host system. Such a controller system may implement interfaces such as DDR, DIMM, CXL, PCIe, and others. In another embodiment, such data and commands are sent and received directly from the memory package to the host without a separate controller, and any required controller is within the individual die or within the die added to a multi-chip memory package. In some embodiments, system control logic 260 may include a state machine 262 that provides die-level control for memory operation. In one embodiment, state machine 262 may be software-programmable. In other embodiments, state machine 262 is implemented entirely in hardware (e.g., circuitry) without using software. In another embodiment, state machine 262 is replaced by a microcontroller or microprocessor. System control logic 260 may also include a power control module 264 that controls the power, current source current, and voltage supplied to the columns and rows of memory structure 202 during memory operation, and may include charge pump and regulator circuitry for generating regulated voltages, and on / off control for word line bit line selection of memory cells. In some embodiments, power control 264 includes one or more current sources. The current sources(s) can be used to provide read and / or write currents. System control logic 260 includes a memory 266 that can be used to store parameters for operating memory structure 202. System control logic 260 also includes refresh logic 272 and loss balancing logic 274. Such system control logic can be commanded by host 120 or memory controller 102 to refresh logic 272, which can load on-chip stored column and row addresses (indicators) that can be incremented after refresh. Only such address(s) bits(s) can be selected (to refresh OTS). Alternatively, such addresses can be read, corrected via ECC engine 269, and then stored in a "spare" location. This is also incremented (therefore, under the control of wear leveling logic 274, all codewords are periodically read, corrected, and relocated throughout the chip) to achieve wear leveling, resulting in more even use of each bit on the chip. This operation can be more directly controlled by an external controller, such as a PCIe, CXL, or DDRn controller located separately from or on the memory chip.

[0024] Commands and data are transferred between the memory controller 102 and the memory die 292 via the memory controller interface 268 (also referred to as the "communication interface"). This interface may be, for example, PCIe, CXL, or DDRn. The memory controller interface 268 is an electrical interface for communicating with the memory controller 102. Examples of the memory controller interface 268 also include a dual-state thixotropic interface. Other I / O interfaces may also be used. For example, the memory controller interface 268 may implement a dual-state thixotropic interface connected to the memory interfaces 228 / 258 of the memory controller 102. In one embodiment, the memory controller interface 268 includes a set of input and / or output (I / O) pins connected to the controller 102. In another embodiment, the interface is a JEDEC standard DDRn or LPDDRn (such as DDR5 or LPDDR5) or a subset thereof with smaller page sizes and / or more lenient timings.

[0025] The system control logic 260 in the controller located on the memory die within the memory package may include an error correction code (ECC) engine 269. The ECC engine 269 may be referred to as an on-die ECC engine because it resides on the same semiconductor die as the memory cell. That is, the on-die ECC engine 269 can be used to encode data and corresponding bits to be stored in the memory structure 202, and to decode and correct errors in the decoded data. The encoded data may be referred to herein as a codeword or an ECC codeword. The ECC engine 269 can be used to execute decoding algorithms and perform error correction. Therefore, the ECC engine 269 can decode ECC codewords. In one embodiment, the ECC engine 269 can decode data more quickly by direct decoding, without iteration. Having the ECC engine 269 on the same die as the memory cell allows for faster decoding. The ECC Engine 269 can use a variety of decoding algorithms, including but not limited to Reed Solomon, Bose-Chaudhuri-Hocquenghem (BCH), and low-density parity check (LDPC).

[0026] In some embodiments, all elements of memory die 292 (including system control logic 260) may be formed as part of a single die. In other embodiments, some or all of the system control logic 260 may be formed on different dies (e.g., external controller chips).

[0027] In one embodiment, the memory structure 202 comprises a three-dimensional memory array of non-volatile or volatile memory cells, wherein multiple memory layers are formed over a single substrate (such as a wafer). The memory structure may contain any type of non-volatile or volatile memory formed monolithically in one or more physical layers of memory cells, such memory having an active region disposed over a silicon (or other type) substrate on silicon or an insulator. In another embodiment, the memory structure 202 comprises a two-dimensional memory array of non-volatile memory cells.

[0028] The exact type of memory array architecture or memory cell included in memory structure 202 is not limited to the examples described above. Many different types of memory array architectures or memory technologies can be used to form memory structure 202. For the purposes of the new claimed embodiments presented herein, no specific non-volatile memory technology is required. Other examples of suitable technologies for memory cells of memory structure 202 include ReRAM memory (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), FeRAM, phase change memory (e.g., PCM), and the like. Examples of suitable technologies for memory cell architecture of memory structure 202 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bit line arrays, and the like.

[0029] One example of a ReRAM or MRAM crosspoint memory includes a programmable resistance switching element configured in series with an OTS selector in a crosspoint array accessed via X and Y lines (e.g., word lines and bit lines). In another embodiment of the crosspoint, it is a PCM connected in series with the OTS selector. In another embodiment, the memory cell may include a conductive bridge memory element. The conductive bridge memory element may also be referred to as a programmable metallized cell. The conductive bridge memory element can be used as a state-change element based on the physical relocation of ions within a solid electrolyte. In some cases, the conductive bridge memory element may include two solid metal electrodes (one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper)) having a solid electrolyte film between the two electrodes. As temperature increases, ion mobility also increases, resulting in a decrease in the programmability threshold of the conductive bridge memory cell. Therefore, conductive bridge memory elements have a wide range of programmed limits in terms of temperature.

[0030] Magnetoresistive random access memory (MRAM) uses magnetic storage elements to store data. The element is formed of two ferromagnetic layers separated by a thin insulating layer, each of which can remain magnetized. For field-controlled MRAM, one of the two layers is set as a permanent magnet of a specific polarity; the magnetization of the other layer can be changed by applying an external field to store memory. Other types of MRAM cells are possible. The memory device can be constructed from a grid of MRAM cells or as a SOT magnetoresistive memory. MRAM-based memory embodiments will be discussed in more detail below.

[0031] Phase change memory (PCM) utilizes the unique behavior of sulfide glasses. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve a non-thermal phase change by simply altering the coordination state of germanium atoms using laser pulses (or light pulses from another source). The memory cell is programmed or switches between amorphous and crystalline states by altering the common coordination of the PCM material via current pulses. Note that the use of "pulse" in this document does not require a square pulse, but includes (continuous or discontinuous) vibrations or bursts of sound, current, voltage, light, or other waves. Furthermore, the current forced for writing can, for example, be rapidly driven to a peak and then linearly sloping down at, for example, an edge rate of 500 ns. Such peak current force can be limited by a zoned voltage compliance that varies along the position of the memory cell along the word line or bit line. In one embodiment, the phase change memory cell has a phase change memory element connected in series with a threshold switching selector (such as an OTS).

[0032] Those skilled in the art will recognize that the techniques described herein are not limited to a single specific memory structure, memory construction, or material composition, but are encompassed within the spirit and scope of the techniques described herein and understood by those skilled in the art.

[0033] The components in Figure 2 can be divided into two parts: the memory structure 202 and the peripheral circuitry, including all other components. An important characteristic of the memory circuitry is its capacity, which can be increased by increasing the area allocated to the memory die 292 of the memory structure 202; however, this reduces the area available for the peripheral circuitry on the memory die, or increases the cost associated with the chip area. This can place significant limitations on these peripheral components. For example, the need to fit the sense amplifier circuitry within the available area can be a significant limitation on the sense amplifier design architecture. Regarding the system control logic 260, the reduced area availability can limit the available functionality that can be implemented on the chip. Therefore, the fundamental trade-off in the design of the memory die 292 is the trade-off between the amount of area dedicated to the memory structure 202 and the amount of area dedicated to the peripheral circuitry. Such trade-offs can result in a larger IR drop due to the use of a larger xy memory array between the word lines and bit lines, which in turn can benefit more from the use of voltage limiting and partitioning of the constant current output voltage according to the memory cell location along the word lines and bit lines.

[0034] Another reason why the memory structure 202 and its peripheral circuitry are often inconsistent is due to the processing involved in forming these regions, as these regions often involve different processing techniques and trade-offs between different techniques on a single die. For example, components in the system control logic 260 (such as sense amplifier circuits, charge pumps, logic elements in state machines, and other peripheral circuitry) typically employ PMOS devices. In some cases, the memory structure will be based on CMOS devices. The processing operations used to manufacture CMOS dies will differ in many ways from those optimized for NMOS technology alone.

[0035] To mitigate these limitations, the embodiments described below can separate the elements of FIG2 onto separately formed dies that are subsequently bonded together. FIG3 depicts an integrated memory assembly 270 having a memory structure die 280 and a control die 290. A memory structure 202 is formed on the memory structure die 280, and some or all of the peripheral circuitry elements (including one or more control circuits) are formed on the control die 290. For example, the memory structure die 280 may be formed solely of memory elements, such as an array of memory cells of MRAM, PCM, ReRAM, or other memory types. Some or all of the peripheral circuitry (including even elements such as decoders, current sources, and sense amplifiers) may then be moved to the control die. This allows each semiconductor die to be individually optimized according to its technology. This allows for more space to be used for peripheral elements, which can now be combined with additional capabilities that were previously limited by the margin of identical dies in the memory cell array. The two dies can then be bonded together in a bonded multi-die integrated memory assembly, wherein an array on one die is connected to peripheral elements on the other die. While the following will focus on an integrated memory assembly with one memory die and one control die, other embodiments may use more dies, such as two memory dies and one control die.

[0036] Similar to the memory die 292 in FIG. 2, the memory structure die 280 in FIG. 3 includes a memory structure 202, which may include multiple independently accessible arrays or "blocks". System control logic 260, column control circuitry 220, and row control circuitry 210 are located in the control die 290. In some embodiments, all or part of the row control circuitry 210 and all or part of the column control circuitry 220 are located on the memory structure die 280. In some embodiments, some circuitry in the system control logic 260 is located on the memory structure die 280.

[0037] Figure 3 illustrates a row control circuitry system 210 on a control die 290, coupled to a memory structure 202 on a memory structure die 280 via an electrical path 293. For example, the electrical path 293 may provide electrical connections between the row decoder 212, the row driver circuitry system 214, and the block select 216, and the bit lines of the memory structure 202. The electrical path may extend from the row control circuitry system 210 in the control die 290 through pads on the control die 290 that bond to corresponding pads on the memory structure die 280, which are connected to the bit lines of the memory structure 202. Each bit line of the memory structure 202 may have a corresponding electrical path connected to the row control circuitry system 210 within the electrical path 293 (including a pair of bonding pads). Similarly, the column control circuitry 220, including column decoder 222, column driver 224, block select 226, and sense amplifier 228, is coupled to memory structure 202 via electrical paths 294. Each of the electrical paths 294 may correspond to, for example, word lines. Additional electrical paths may also be provided between control die 290 and memory structure die 280.

[0038] For the purposes of this document, the phrase "a control circuit" may include one or more of the following: memory controller 102, local memory controller 164, processor 156, system control logic 260, row control circuit system 210, column control circuit system 220, host processor 122, microcontroller, state machine, and / or other control circuit system, or other similar circuitry for controlling non-volatile memory. A control circuit may include hardware only or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. A control circuit may include a processor, FPGA, ASIC, integrated circuit, or other type of circuitry. Such a control circuit system may include a driver that drives to a fixed voltage (such as a power supply), such as via a connection through a node of a fully-on transistor (gate to power supply). Such a control circuit system may include a current source driver.

[0039] For the purposes of this document, the term "apparatus" may include, but is not limited to, one or more of the following: memory system 100, local memory 140, local memory controller 164 and / or a combination of memory controller 102 and local memory 140, storage 104, memory chip 292, integrated memory assembly 270, and / or control chip 290.

[0040] In the following discussion, the memory structure 202 of Figures 2 and 3 will be discussed in the context of a crosspoint architecture. In a crosspoint architecture, a first set of conductive lines or wires (such as word lines) travels in a first direction relative to the underlying substrate; and a second set of conductive lines or wires (such as bit lines) travels in a second direction relative to the underlying substrate. Memory cells are located at the intersections of word lines and bit lines. Memory cells at these crosspoints can be formed according to any of a variety of technologies (including those described above). The following discussion will primarily focus on embodiments based on a crosspoint architecture using MRAM memory cells, each MRAM memory cell being connected in series with a threshold switching selector (such as a bidirectional threshold switch (OTS)) to form an optional memory bit. However, embodiments are not limited to providing current to a crosspoint architecture having MRAM cells (each of which has a magnetic memory element in the series OTS selector). For example, a crosspoint memory array may have memory cells of other technologies such as ReRAM, PCM (phase-change memory), FeRAM, etc.

[0041] FIG4A depicts an embodiment of a portion of a memory array 402 forming an intersection architecture in a perspective view. The memory array 402 of FIG4A is an example of an embodiment of the memory structure 202 in FIG2 or FIG3, wherein the memory die 292 or memory structure die 280 may include a plurality of such memory arrays 402. The memory array 402 may be included in local memory 140 or host memory 124. Bit lines BL1 to BL5 are arranged in a first direction relative to the substrate below the die (not shown) (but indicated as rows entering the drawing), and word lines WL1 to WL5 are arranged in a second direction perpendicular to the first direction, or diagonally to provide an intersection of memory cells interconnected between WL and BL. Figure 4A shows an example of a horizontal crossover structure, where word lines WL 1 to WL 5 and BL 1 to BL 5 both extend horizontally relative to the substrate, while memory cells (two of which are indicated by 401) are oriented so that current flows vertically through the memory cells (e.g., shown as I cells). In memory arrays with additional memory cell layers, as discussed below with respect to Figure 4D, there will be corresponding additional bit line layers and word line layers. A pattern, for example, would originate from the bottom layer: WL, memory cell, BL, memory cell, WL, WL, memory cell, BL, memory cell, WL.

[0042] As depicted in Figure 4A, the memory array 402 includes a plurality of memory cells 401. Memory cells 401 may include rewritable memory elements, such as ReRAM, MRAM, PCM, or other materials with programmable resistors. Memory cells 401 may be referred to herein as programmable resistive memory cells. One type of programmable resistive memory cell is called an MRAM cell, which is a memory cell comprising MRAM memory elements. Memory cells 401 may also include a threshold switching selector as an additional series element within the memory cell 401, such as a bidirectional threshold switch (OTS), a volatile conductive bridge (VCB), a metal-insulator-metal (MIM), or other materials that provide a highly nonlinear dependence of current or resistance on varying selection voltages. The following discussion will focus on memory cells composed of MRAM memory elements combined in series with bidirectional threshold switching elements, but much of the discussion is applicable more generally. The current in the memory cells of the first memory stage is shown to flow upwards, as indicated by the arrow I cell, but the current can flow in either direction to read or write the memory cell bit state, as discussed in more detail below.

[0043] Figures 4B and 4C present a side view and a top view of the intersection structure in Figure 4A, respectively. The side view of Figure 4B shows a bottom conductor (or word line) WL1 and top conductors (or bit lines) BL1 to BLn. The intersections between the top and bottom conductors are MRAM memory cells 401; however, PCM, ReRAM, FeRAM, or other technologies can also be used as memory elements. Figure 4C is a top view illustrating the intersection structure of M bottom conductors WL1 to WLM and N top conductors BL1 to BLN. In a binary embodiment, the MRAM cell at each intersection can be programmed into one of two resistance states: high and low. Further details of embodiments of MRAM memory cell design and read techniques are given below. In some embodiments, such sets of conductors are arranged consecutively into "blocks," and such blocks can be adjacent in the word line (WL) direction and orthogonally paired in the bit line direction to form modules. Such modules can consist of 2 x 2 blocks to form a four-block combination, where the WL driver between these blocks is "center driven" between the blocks, and the WL travels continuously above the transistor driver at approximately the center of the line. Similarly, the BL driver can be located between paired block pairs in the BL direction for center driving, whereby the transistor driver and its area are shared between a pair of blocks. Copper vias or other types of low-resistance vias can decode the transistor driver / selector and connect it to the WL or BL. In addition to memory elements, series select elements, such as OTS, can also be included between the WL and BL in the memory cell.

[0044] Figure 4A illustrates an embodiment with a single layer of word lines and bit lines, wherein the MRAM or other memory technology for the memory cells is located at the intersection of two sets of conductive lines. To increase the storage density of the memory die, multiple layers of such memory cells and conductive lines can be formed. Figure 4D illustrates a two-layer example.

[0045] FIG4D depicts an embodiment of a portion of a second-order memory array forming a cross-point architecture in a perspective view. Similar to FIG4A, FIG4D shows a first layer 418 of memory cells 401 of memory array 403, which connects at the intersection of the first layer word lines WL 1,1 to WL 1,4 and the bit lines BL 1 to BL 5 above. Memory array 403 may be included in memory structure 202 of FIG2 or FIG3. A second layer of memory cells 420 is formed above the bit lines BL 1 to BL 5 and between these bit lines and the second set of word lines WL 2,1 to WL 2,4. In fact, BL is shared. In an alternative, the second layer may include another stack of BL located above the shown BL and below the second stack of WL. Although FIG4D shows two layers 418 and 420 of memory cells, the structure may extend upwards by additional alternating layers of word lines and bit lines in a similar pattern. Depending on the embodiment, the word lines and bit lines of the array in FIG4D can be biased for read or programmed operations, such that current flows from the word line layer to the bit line layer, or vice versa, in each layer. The two layers can be structured to have current flow in the same direction in each layer for a given operation, or to have current flow in opposite directions by driver selection in positive or negative directions. Memory cells can be placed in the same orientation within the first and second layers, thereby enabling the use of current in opposite directions for read or write operations layer by layer. Alternatively, memory cells can be placed in the opposite or flipped orientation when placed between BL and WL in the second layer (thereby enabling the use of current in the same direction as for read or write operations in the memory cells within the first layer). It will be apparent to those skilled in the art that the two layers can be extended to three or more layers.

[0046] The use of a crosspoint architecture allows for arrays with a small footprint, and several such arrays can be formed on a single die. The memory cells formed at each crosspoint can be resistive memory cells, where data values ​​are encoded as different resistance levels, such as two levels in MRAM, or two or more levels for other memory element technologies (such as PCM). Depending on the embodiment, the memory cell can be a binary value having a low-resistance state or a high-resistance state, or it can be a multi-level cell (MLC) with additional resistance between the low-resistance and high-resistance states. The crosspoint array described herein can be used in memory die 292 of FIG. 2, local memory 140 of FIG. 1, and / or host memory 124 of FIG. 1, or any other configuration in which additional memory is applicable. Resistive memory cells can be formed according to many of the technologies mentioned above, such as ReRAM, PCM, FeRAM, or MRAM. The following discussion is presented primarily in the context of memory arrays using crosspoint architecture with binary-valued MRAM memory cells, but most of the discussion can be applied more generally to other memory elements in memory cells within crosspoint arrays or other configurations that are obvious to those of ordinary knowledge in the art.

[0047] FIG5 illustrates the structure of an embodiment of an MRAM cell. The MRAM cell can be used as, for example, the programmable resistive memory cell 401 shown in FIGS. 4A to 4D. The MRAM memory cell includes a bottom electrode 501, a spacer 512, a threshold switching selector 502, a spacer 514, a pair of magnetic layers (reference layer 503 and free layer 507) separated in this example by a separating or tunneling layer of magnesium oxide (MgO) 505, and a top electrode 511 separated from the free layer 507 by a spacer 509. The spacer 509 may be composed of an MgO capping layer in contact with the free layer 507. The spacer 509 may also contain an additional metal layer. In another embodiment, the positions of the reference layer 503 and the free layer 507 are interchanged, wherein the reference layer 503 is on top of the MgO 505, and the free layer 507 is below the MgO 505. In another embodiment, the critical limit switching selector 502 is located between the free layer 507 and the top electrode 511.

[0048] In some embodiments, the bottom electrode 501 is a word line and the top electrode 511 is a bit line. In other embodiments, the bottom electrode 501 is a bit line and the top electrode 511 is a word line. The state of the memory cell is based on the relative orientation of the magnetization of the reference layer 503 and the free layer 507: if the two layers are magnetized in the same direction, the memory cell will be in a parallel (P) low resistance state (LRS); and if they have opposite orientations, the memory cell will be in an anti-parallel (AP) high resistance state (HRS). MLC embodiments will include additional intermediate states. The orientation of the reference layer 503 is fixed, and in the example of FIG5, the orientation is upward. The reference layer 503 is also referred to as a fixed layer or pinned layer. The reference layer 503 may consist of multiple ferromagnetically coupled layers in a structure commonly referred to as a synthetic antiferromagnet or SAF for short.

[0049] Data is written to MRAM memory cells by programming the free layer 507 to have the same or opposite orientation as the reference layer 503. The array of MRAM memory cells can be placed in an initial (or erased) state by setting all MRAM memory cells to a low-resistance state, wherein all their free layers have the same magnetic field orientation as their reference layers. Then, each memory cell is selectively programmed (also called "written") by placing its free layer 507 in a high-resistance state (by reversing the magnetic field to the opposite of the reference layer 503). The reference layer 503 is formed such that it retains its orientation when programming the free layer 507. The reference layer 503 can have a more complex design, including a synthetic antiferromagnetic layer and additional reference layers. For simplicity, these additional layers are omitted in the diagrams and discussion, which focus only on the fixed magnetic layer of the tunneling magnetoresistance in the main responsible cell.

[0050] The threshold switching selector 502 has a high resistance (in an off or non-conductive state) until it is biased to a voltage higher than its threshold voltage or a current higher than its threshold current, and until its voltage bias drops below Vhold (also called "Voffset") or its current drops below Ihold. After crossing Vt and simultaneously exceeding Vhold, the switching selector has a low resistance (in an on or conductive state). The threshold switching selector remains on until its current drops below the holding current Ihold, or its voltage drops below the holding voltage Vhold. When this occurs, the threshold switching selector returns to the off (higher) resistance state. Therefore, to program memory cells at the crossover point, a voltage or current sufficient to turn on the associated threshold switching selector is applied to set or reset the memory cell; and to read the memory cell, the threshold switching selector is activated in a similar manner by turning on the threshold switching selector before determining the resistance state of the memory. One example of a threshold switching selector is a bidirectional threshold switching material for a bidirectional threshold switch (OTS). Examples of threshold switching materials include Ge-Se, Ge-Se-N, Ge-Se-As, Ge-Se-Sb-N, Ge58Se42, GeTe6, Si-Te, Zn-Te, C-Te, B-Te, Ge-As-Te-Si-N, Ge-As-Se-Te-Si, and Ge-Se-As-Te, wherein the atomic percentage of each element ranges from a fractional percentage to more than 90%. In one embodiment, the threshold switching selector is a two-terminal device. The threshold switching selector 502 may also contain an additional conductive layer at the interface with the reference layer 503. For example, a spacer 514 is depicted between the switching selector 502 and the reference layer 503. The spacer layer 514 located at the interface with the reference layer 503 may be a single conductive layer or composed of multiple conductive layers. The threshold switching selector 502 may also contain an additional conductive layer at the interface with the bottom electrode 501. For example, spacer 512 is depicted between switch selector 502 and reference layer 503. The spacer layer 512 at the interface with bottom electrode 501 may consist of a single conductive layer or multiple conductive layers. Examples of conductive layers adjacent to the OTS include carbon, carbon nitride, carbon silicate, tungsten carbide, titanium, titanium nitride, tungsten, tungsten nitride, tantalum, tantalum nitride, and others. The threshold voltage switch has a threshold voltage (Vt) above which the resistance of the device changes substantially from insulating or quasi-insulating to conductive.

[0051] In one embodiment, a current-forced method is used to access MRAM cells. The current-forced method can be used to read or write MRAM cells. In the current-forced method, the access current (e.g., Iread or Iwrite) is driven through the bottom electrode 501 by a current driver. The current is provided by a transistor- or resistor-based current source. In one embodiment, the current driver may be part of an address-selectable column driver circuitry (e.g., array driver 224) for electrode 501. However, alternatively, the current driver may be part of an address-selectable row driver circuitry (e.g., driver circuitry 214) for electrode 501. A voltage (e.g., Vselect) is provided to the top electrode 511. In this document, the terms "read current" (Iread) and "write current" (Iwrite) will be used in conjunction with the access current driven through the MRAM cell (or other programmable resistive cell). The write current can change the state of the MRAM cell. As an example, an MRAM cell with a critical dimension (CD) of approximately 20 nanometers and a RA of 10 Ωµm² can be switched from a P state to an AP state using a write current of approximately 30 µA for approximately 50 ns. If the application time is limited (e.g., < 20 ns), the read current can be approximately half the write current. A write current flowing through the MRAM cell in one direction will change the AP state of the MRAM cell to the P state. A write current flowing through the MRAM cell in another direction (e.g., in the read direction) will change the P state of the MRAM cell from the P state to the AP state. Generally, the read current is preferably set low enough and the read duration short enough before determining the cell state or capturing and storing the voltage level associated with the memory cell state so that the state of the MRAM cell is not changed from the P state to the AP state or from the AP state to the P state during the read operation. Generally, the write current required to switch the MRAM state from P to AP is greater in absolute terms than the write current required to switch the MRAM state from AP to P. Therefore, this may be a better read direction because it provides a margin for state change before correctly sensing the bit state. The current value can be adjusted accordingly by the write direction, or by the current used for P to AP if a single value is used.

[0052] In some embodiments, a read current may be applied in the P2AP direction or alternatively in the AP2P direction. In some embodiments, the MRAM cell is read by performing an SRR (Self-Reference Read). In one embodiment, the SRR has a first read (Read1 in the P2AP direction), a first write (Write1 to the AP state), and a second read (Read2 in the P2AP direction). The cell's original state can then be restored by the second write (a write-back of the bit initially in the P state to the P state). Or in another embodiment, the SRR read current and the destructive write current are reversed; for example, when the memory cell is addressed in the second layer with the same orientation as in the first layer.

[0053] In one embodiment, the voltage level of the memory cell caused by Read1 in the P2AP direction is sensed and stored, for example, on a capacitor; or converted into digital bits by an analog-to-digital converter, and stored in memory (e.g., SRAM) until used in Read2. The state stored on the capacitor can be adjusted, for example, by applying a voltage to one terminal of the capacitor connected to the storage capacitor. Alternatively, the digitally stored level can be adjusted by digitally adding or subtracting 150mV to the stored bit. The 150mV can be adjusted according to the typical bit resistance. For example, if the low resistance state of the bit is 25K ohms and the high resistance is 50K ohms, then the difference is 25K ohms. If the current reading is 15 µA, the voltage difference between states is 25 Kohms x 15 µA = 375 mV. Therefore, 150 mV is acceptable, but 187.5 mV might be better.

[0054] Although the foregoing describes a read in the P2AP direction and a destructive write to the AP state (whereby the write back to the P state is performed after the SRR), in an alternative embodiment, the first SRR has a first read (Read1 in the AP2P direction), a destructive write to the P state (Write 1), and a second read in the AP2P direction (Read2).

[0055] In one embodiment, an MRAM cell is read by applying, for example, approximately 0V to the top electrode 511 by turning on a transistor connected between 511 and a power supply while driving a current, for example, 15 microamperes (µA), through the bottom electrode 501. This read current can flow from the bottom electrode 501 to the top electrode 511. Note that the read can be Read1 or Read2 in the P2AP direction. P2AP means that the current flows in the direction of writing bits from P to AP, or from AP to AP. In some embodiments, bipolar write operations are used to write data to the MRAM cell. In one embodiment, the MRAM cell is written from the AP state to the P state by applying, for example, 3V to the top electrode 511 while driving a write current, for example, -30 µA, through the bottom electrode 501. This write current will flow from the top electrode 511 to the bottom electrode 501. In one embodiment, an MRAM cell is written from a P state to an AP state by simultaneously applying, for example, 0V to the top electrode 511 while driving a current, for example, 30 µA, through the bottom electrode 501. This write current flows from electrode 501 to electrode 511.

[0056] As an alternative to the method in FIG5, a selection voltage may be applied to the bottom electrode 501 as the applied access current passes through the top electrode 511. In one embodiment, an MRAM cell is read by applying, for example, 3V to the bottom electrode 501 while driving, for example, a read current of -15 µA through the top electrode 511. This read current may flow from the bottom electrode 501 to the top electrode 511.

[0057] In one embodiment, an MRAM cell is written from the AP state to the P state by applying, for example, -3V to the bottom electrode 501 while driving a write current, for example, 30 µA, through the top electrode 511. The electron flow will be from the bottom electrode 501 to the top electrode 511. In one embodiment, an MRAM cell is written from the P state to the AP state by applying, for example, 0V to the bottom electrode 501 while driving a current, for example, -30 µA, through the top electrode 511. The electron flow will be from the top electrode 511 to the bottom electrode 501. The direction of the current polarity used to switch the magnetization of a bit to the P state or the AP state can vary based on the reference layer design and the position of the reference layer relative to the free layer.

[0058] Some biasing techniques may cause voltage to be generated in the unselected memory cells of the array, which may induce leakage current in the unselected memory cells. Although this power consumption waste can be mitigated to some extent by designing the memory cells to have relatively high resistance levels in both high-resistance and low-resistance states when the address WL or BL is not selected, this burden leakage will still lead to increased current and power consumption, and will impose additional design constraints on the design of the memory cells and the array due to the lack of read and write margins. One way to solve this unwanted current leakage is to place selector elements in series with each MRAM or other resistive (e.g., ReRAM, PCM) memory cell. For example, the select transistor can be placed in series with each resistive memory cell element in Figures 4A to 4D, so that memory cell 401 is now a composite of select transistor and programmable resistor. Such an architecture may be referred to as 1T1R. However, using a selection transistor requires additional control lines and cell areas to enable the corresponding transistor for the selected memory cell. Furthermore, transistors often cannot scale in the same way as the write current of resistive memory elements, making the use of transistor-based selectors a limiting factor, for example, in cost reduction, as memory arrays shrink in size. An alternative to a selection transistor is to use a threshold switching selector (e.g., threshold switching selector 502) connected in series with a programmable resistive element. A two-terminal threshold switching selector does not require the aforementioned additional control lines and cell area to enable the corresponding selection transistor for the selected memory cell. In some embodiments, the memory system performs a read as described herein, reading a memory cell having a two-terminal threshold switching selector connected in series with a programmable resistive memory element.

[0059] Figures 6A and 6B illustrate an embodiment incorporating an adjacency switching selector into an MRAM memory array with a crosspoint architecture. The examples in Figures 6A and 6B show two MRAM cells (layer 1 cell and layer 2 cell) in a two-layer crosspoint array, as shown in Figure 4D, but presented as a side view. As depicted in Figure 6A, keeping the orientation of the MRAM layers the same as that of layer 1 and layer 2 cells allows for identical manufacturing processes across layers. Figure 6B features inverted memory cells, which allows the drive circuitry system to operate in the same manner; for example, BL is lowered to read the P2AP of each layer. Figures 6A and 6B show the first lower conductive line of word line 1 600, the first upper conductive line of word line 2 620, and the second intermediate conductive line of bit line 610. In these figures, for ease of presentation, all such lines are shown traveling from left to right across the plane. However, in the intersection array, it is more accurately represented in the oblique view of Figure 4D, where word lines (or first conductive lines or wires) travel in a direction parallel to the surface of the underlying substrate, and bit lines (or second conductive lines or wires) travel in a second direction parallel to the surface of the substrate, primarily orthogonal to the first direction. MRAM memory cells are also represented in a simplified form, showing only the reference layer, free layer, and intermediate tunneling barrier. However, in actual implementations, additional structures related to Figure 5 described above are generally included.

[0060] An MRAM element 602, comprising a free layer 601, a tunneling barrier 603, and a reference layer 605, is formed above a threshold switching selector 609, wherein this series combination of the MRAM element 602 and the threshold switching selector 609 forms a layer 1 cell between bit line 610 and word line 1 600. The series combination of the MRAM element 602 and the threshold switching selector 609 operates largely as described above when the threshold switching selector 609 is turned on. However, the threshold switching selector 609 initially requires a voltage higher than its threshold voltage Vth to be turned on, and the bias current or voltage then needs to be maintained higher than the holding current or holding voltage of the threshold switching selector 609 to keep it on during subsequent read or write operations.

[0061] On the second layer, an MRAM element 612, including a free layer 611, a tunneling barrier 613, and a reference layer 615, is formed above a threshold switching selector 619. The series combination of the MRAM element 612 and the threshold switching selector 619 forms a layer 2 cell between bit line 610 and word line 2 620. The layer 2 cell operates as a layer 1 cell, except that the lower conductor now corresponds to bit line 610, and the upper conductor is now a word line (word line 2 620). Other paired layers may similarly share another bit line among them, having the following patterns: WL1, BL1, WL2; WL3, BL2, WL4; or having separate bit lines in the pattern, such as WL1, BL1, WL2, BL2. Or having separate bit lines in the pattern of WL1, BL1, BL2, WL2.

[0062] In the embodiment of FIG. 6A, the threshold switching selector 609 / 619 is located below the MRAM elements 602 / 612, but in an alternative embodiment, the threshold switching selector may be located above one or two layers of MRAM elements. MRAM memory cells are directional. In FIG. 6A, MRAM elements 602 and 612 have the same orientation, with the free layer 601 / 611 above the reference layer 605 / 615 (relative to a substrate not shown). Since each of these two layers, and subsequent layers in embodiments with more layers, can be formed according to the same manufacturing sequence, forming such layers with the same structure between conductive lines can have several advantages, particularly regarding process advantages.

[0063] FIG. 6B illustrates an alternative embodiment configured in a similar manner to the embodiment of FIG. 6A, except that in the layer 2 cell, the positions of the reference layer and the free layer are reversed. More specifically, as in FIG. 6A, between word line 1 650 and bit line 660, the layer 1 cell includes an MRAM element having a free layer 651 formed above a tunneling barrier 653, which in turn is formed above a reference layer 655, wherein an MRAM element 652 is formed above an adjacency switching selector 659. The second layer of the embodiment of FIG. 6B again has an MRAM element 662 formed above an adjacency switching selector 669 between bit line 660 and word line 2 670, but with the MRAM element 662 reversed relative to FIG. 6A, the reference layer 661 is now formed above the tunneling barrier 663 and the free layer 665 is now below the tunneling barrier 663. Alternatively, the configuration of MRAM element 662 can be used in layer 1 cells, and the configuration of MRAM cell 652 can be used in layer 2 cells.

[0064] Although the embodiment of FIG. 6B requires a different processing order to manufacture the various layers, it may have advantages in some embodiments. Specifically, the directionality of the MRAM structure can make the embodiment of FIG. 6B attractive because when writing or reading in the same direction (relative to the reference layer and the free layer), the bit lines are biased to the lower and upper layers in the same way, and the word lines are also biased in the same way. For example, if memory cells of layer 1 and layer 2 are sensed in the P2AP direction (relative to the reference layer and the free layer), bit line layer 660 will be biased to a lower voltage level (e.g., 0V) for both the upper and lower cells, while word lines 1 650 and 2 670 are both biased to a higher voltage level. Regarding writing, the situation is similar when writing to a high-resistance AP state. With both word line 1 650 and word line 2 670 biased to a higher voltage level, bit line 660 is biased to a lower voltage level (e.g., 0V) for both the upper and lower cells.

[0065] Reading data from or writing data to an MRAM memory cell involves passing current through the memory cell. In embodiments where a threshold switching selector is placed in series with an MRAM element, the threshold switching selector can be turned on by applying sufficient voltage and passing sufficient current across the series combination of the threshold switching selector and the MRAM element before current can pass through the MRAM element.

[0066] FIG7 depicts an embodiment of a memory array 700 with a cross-point architecture. The memory array 700 may be included in the memory structure 202 of FIG2 or FIG3. The array 700 has a set of first conductive lines 706a to 706h and a set of second conductive lines 708a to 708d. In one embodiment, the set of first conductive lines 706a to 706h are word lines, and the set of second conductive lines 708a to 708b are bit lines. For ease of discussion, the set of first conductive lines 706a to 706h may be referred to as word lines, and the set of second conductive lines 708a to 708b may be referred to as bit lines. However, the set of first conductive lines 706a to 706h may be bit lines, and the set of second conductive lines 708a to 708b may be word lines.

[0067] The memory array 700 has a plurality of programmable resistive memory cells 401. Each memory cell 401 is connected between one of the first conductive lines 706 and one of the second conductive lines 708 (e.g., at the intersection of one of the first conductive lines 706 and one of the second conductive lines 708). Each memory cell has a programmable resistive memory element 702 connected in series with a threshold switching selector 502. In one embodiment, the programmable resistive memory element includes a magnetoresistive random access memory (MRAM) element. The threshold switching selector 502 is configured to turn on with a lower resistance in response to a voltage level applied exceeding a threshold voltage of the threshold switching selector 502, and to remain on with a lower resistance until the current through the switching selector 502 decreases to the selector holding current (Ihold). The threshold switching selector 502 may be a two-terminal device. In one embodiment, the threshold switching selector 502 includes an OTS.

[0068] A technique for modulating (also referred to as "forming") a threshold switching selector 502 is disclosed. For discussion purposes, a memory cell 401a is selected to modulate the threshold switching selector 502. The selected memory cell 401a is located at the intersection of the selected word line 706g and the selected bit line 708b. The selected memory cell refers to a memory cell selected for performing memory operations (such as modulation, reading, or writing). The selected memory cell is connected between the selected word line and the selected bit line. To modulate the selected memory cell 401a, a selection voltage (such as near-ground potential) is provided to the selected bit line (e.g., bit line 708b) and a modulation voltage (Vs) is applied to the selected word line (e.g., word line 706g). The selected word line refers to a word line connected to at least one selected memory cell. Alternatively, a memory cell can be selected by applying a selection voltage to the selected word line and a modulation voltage (Vs) to the selected bit line simultaneously.

[0069] In one method, word lines not connected to the selected memory cell can be driven by a voltage approximately half the magnitude of the modulation voltage. As depicted in Figure 7, word lines 706a, 706b, 706c, 706d, 706e, 706f, and 706h are each applied a voltage referred to as a half-select voltage (Vs / 2). The half-select voltage (Vs / 2) has approximately half the magnitude of the modulation voltage (Vs).

[0070] In one method, bit lines not connected to the selected memory cell can be driven by a voltage approximately half the magnitude of the modulation voltage. As depicted in Figure 7, bit lines 708a, 708c, and 708d are each applied a voltage referred to as a half-select voltage (Vs / 2). As mentioned above, the half-select voltage (Vs / 2) has approximately half the magnitude of the modulation voltage (Vs).

[0071] Some memory cells connected to the selected word line are referred to herein as half-selected memory cells. The voltage across the half-selected memory cell is approximately half the voltage across the selected memory cell. Each half-selected memory cell 401b connected to the selected word line has a Vs applied to the selected word line and a Vs / 2 applied to its respective bit line. Therefore, each half-selected memory cell 401b has a Vs / 2 applied to the memory cell.

[0072] Some memory cells connected to the selected bit line are referred to herein as half-selected memory cells. The voltage across these half-selected memory cells is approximately half the voltage across the selected memory cell. Each half-selected memory cell 401c connected to the selected bit line has 0V applied to the selected bit line and Vs / 2 applied to its respective word line. Therefore, each half-selected memory cell 401c has Vs / 2 applied to the memory cell.

[0073] The threshold switching selector 502 in such half-selected memory cells 401b, 401c should not be turned on during operations (such as modulation, reading, or writing). However, if the Vth of the threshold switching selector 502 is less than Vs / 2, the threshold switching selector 502 may be turned on during modulation operations. Techniques for preventing the threshold switching selector 502 in half-selected memory cells 401b, 401c from turning on during modulation operations (or at least reducing the probability of it turning on during modulation operations) are disclosed herein. In one embodiment, the Vth of the threshold switching selector 502 is progressively reduced during several modulation cycles, which reduces the likelihood that the threshold switching selector 502 in half-selected memory cells 401b, 401c will turn on during modulation operations.

[0074] No other memory cells are selected, which means that other memory cells have approximately 0V on the memory cell. Figure 7 shows several completely unselected memory cells 401d. In this example, each completely unselected memory cell 401d has a Vs / 2 applied to its word line and a Vs / 2 applied to its bit line. Even if the threshold voltage of the threshold switching selector 502 is slightly lower than the target Vth range, the threshold switching selector 502 of the completely unselected memory cell 401d will still not be turned on.

[0075] In the example of FIG7, there are more word lines than bit lines in the crosspoint array. In another embodiment, there are more bit lines than word lines in the crosspoint array. In another embodiment, the number of bit lines in the crosspoint array is equal to the number of word lines. In the example of FIG7, there are up to twice as many word lines as bit lines in the crosspoint array; however, different ratios can be used. Thus, different block sizes can be implemented. For example, a block may have 1024 BL x 2048 WL, which can be configured into a module of 2048 x 4096 cells by means of WL and BL between four blocks driven by a center. In one embodiment, a set of memory is read by, for example, selecting a memory cell from each of several blocks. In some embodiments, more than one memory cell can be selected from a block for reading.

[0076] In one embodiment, the memory system applies a modulation signal to progressively reduce the threshold voltage of the threshold switching selector 502 over several modulation cycles. The magnitude of the modulation signal decreases in each modulation cycle. In one embodiment, the modulation signal is a modulation voltage. In another embodiment, the modulation signal is a modulation current. The modulation signal has a sufficient magnitude and duration to partially form the threshold switching selector of the cell selected for modulation. Partial formation means slightly reducing Vth, but using multiple modulation cycles to fully form the threshold switching selector 502. Therefore, the threshold switching selector can be partially formed over several modulation cycles until the target operating Vth is reached. For example, multiple modulation cycles can be used to reduce the Vth of the threshold switching selector from Vinit to an operating state with an operating threshold voltage (Vop).

[0077] Figure 8 is a flowchart of one embodiment of a program 800 for a threshold switching selector in a programmable resistive memory cell within a modulated cross switch array. Program 800 can be used to modulate a bidirectional threshold switch (OTS). Other types of threshold switching selectors can be modulated by executing program 800. The programmable resistive memory cell 401 has a programmable resistive memory element 702 connected in series with the threshold switching selector 502. Examples of programmable resistive memory elements include, but are not limited to, MRAM, ReRAM, PCM (phase-change memory), and FeRAM. Program 800 can be executed before operating the cross switch array. Therefore, program 800 can be executed before writing to and reading from the memory cell. When discussing program 800, reference will be made to the cross switch array 700 in Figure 7.

[0078] Step 802 includes setting an initial value for the modulation voltage. A modulation voltage is applied to the memory cell (or unit) selected for partial modulation. In one embodiment, the initial value of the modulation voltage is greater than the maximum expected initial Vth of the threshold switching selector 502. An example of the initial value of the modulation voltage is approximately 4.2V, but this value may vary depending on the characteristics of the threshold switching selector 502.

[0079] Steps 804 to 809 describe partial modulation of the threshold switching selector 502 in the selected memory cell. Optionally, more than one memory cell 401 in the crossbar array can be selected to perform partial modulation in parallel. Program 800 will be described as an example of selecting one memory cell 401 in the crossbar array at a time for partial modulation of the threshold switching selector. For ease of explanation, steps 804 to 808 are described in a certain order. Steps 804 to 808 may occur in different orders and / or some of these steps may be performed simultaneously.

[0080] Step 804 includes applying approximately 0V to the completely unselected memory cell. Step 804 may include applying Vs / 2 to one end of the completely unselected memory cell (e.g., the completely unselected memory cell 401d) and applying Vs / 2 to the other end of the completely unselected memory cell.

[0081] Step 806 includes applying a half-select voltage (Vs / 2) to the half-selected memory cells in the crossbar switch array. Step 806 may include applying Vs to one end of a first group of half-selected memory cells (e.g., half-selected memory cell 401b) and applying Vs / 2 to the other end of the first group of half-selected memory cells. Step 806 may include applying Vs / 2 to one end of a second group of half-selected memory cells (e.g., half-selected memory cell 401c) and applying 0V to the other end of the second group of half-selected memory cells.

[0082] Step 808 includes applying a modulation voltage to the selected memory cell (e.g., selected cell 401a). The duration of the modulation voltage typically ranges from 10 nanoseconds (ns) to 100 ns. However, the duration of the modulation voltage may be longer or shorter than this typical range. In one embodiment, the modulation voltage (Vs) is applied to one end of the selected memory cell, wherein the other end of the selected memory cell is grounded.

[0083] Step 809 includes determining whether to perform additional modulation on the cell at the current value of the modulation voltage. In one embodiment, the memory system applies the modulation voltage to the selected memory cell a predetermined number of times at the current value. The memory system may change the polarity of the modulation signal in the next application. For example, in one iteration of steps 804 to 808, the modulation signal may generate a positive voltage from the word line to the bit line, and in another iteration of steps 804 to 808, the modulation signal may generate a negative voltage from the word line to the bit line.

[0084] Step 810 includes determining whether there is another memory cell 401 in the crossbar switch array that should be selected for partial modulation of the threshold switching selector 502. In one embodiment, the memory system selects each memory cell 401 in the crossbar switch array once in each loop of the modulation procedure. A loop of the modulation procedure refers to partially modulating each memory cell 401 in the crossbar switch array according to a specific value of the modulation voltage. Steps 804 to 808 are repeated with the same value of the modulation voltage until all memory cells 401 in the crossbar switch array have been modulated once.

[0085] After the modulation cycle is completed, in step 812 it is determined whether the threshold switching selector 502 in the crossbar switch array has reached the target threshold voltage range. Note that there may be some differences in the threshold voltage between different threshold switching selectors 502. If the target threshold voltage range has not been reached, the magnitude of the modulation voltage is reduced in step 814. For example, the magnitude of the modulation voltage is reduced by 100mV. The magnitude of the half-select voltage is also reduced accordingly, so that the half-select voltage is maintained at Vs / 2. Then, the memory system executes the next cycle of the modulation procedure by returning to step 804. In one embodiment, the magnitude of the modulation voltage is progressively reduced in each cycle until the magnitude of the modulation voltage reaches the target value. An example range of the target value is between 2V and 3V, but the target value may be lower or higher than this range. After program 800, the memory cell can be read or written.

[0086] In one embodiment, the progressive decrease of the modulation signal (e.g., modulation voltage or modulation current) progressively decreases the threshold voltage of the threshold switching selector 502. Figure 9 is a graph illustrating an example of the progressive decrease of the threshold voltage of the threshold switching selector 502 within each cycle of the modulation procedure. The graph shows the threshold voltage (Vth) of the threshold switching selector 502 for each modulation cycle. Curve 902 is the average Vth of the threshold switching selector 502 in the crossbar switch array. Curve 902 shows the progressive decrease of the Vth of the threshold switching selector 502 within each cycle of the modulation procedure. There may be some differences in the Vth of the threshold switching selector 502. Curve 904 shows the Vth of the threshold switching selector 502 that differs from the average Vth by +3σ. Curve 906 shows the Vth of the threshold switching selector 502 that differs from the average Vth by -3σ.

[0087] During an embodiment of program 800, the modulation voltage during a specific cycle is greater than the threshold voltage of the threshold switching selector 502 during that specific cycle. During an embodiment of program 800, the half-select voltage during a specific cycle is less than the threshold voltage of the threshold switching selector 502 during that specific cycle. Therefore, the threshold switching selector 502 in the half-selected memory cells (e.g., 401b, 401c) is not turned on during the modulation program. Thus, incorrectly selected half-selected memory cells (e.g., 401b, 401c) are avoided.

[0088] For example, in one embodiment, before receiving the modulation voltage in a specific cycle, the Vth of a specific memory cell will be less than Vs but greater than Vs / 2. Therefore, if this specific memory cell is a half-selected memory cell before receiving the modulation voltage, the threshold switching selector 502 in this specific memory cell will not be turned on. Furthermore, the modulation voltage in the specific cycle only gradually reduces (e.g., partially forms) the Vth of the specific memory cell, such that Vth is still greater than Vs / 2. Therefore, if this specific memory cell is a half-selected memory cell, the threshold switching selector 502 in this specific memory cell will not be turned on after receiving the modulation voltage in this specific cycle. Therefore, incorrect selection of half-selected memory cells (e.g., 401b, 401c) is avoided. Therefore, the modulation of the selected memory cell is improved.

[0089] Figure 10A is a flowchart of a procedure 1000 that applies voltage to word lines and bit lines during modulation of the selected memory cell. Procedure 1000 provides further details of an embodiment of steps 804 to 808 of procedure 800. When discussing procedure 1000, reference is made to the crossbar switch array in Figure 7. In Figure 7, memory cell 401a is the selected memory cell. For ease of explanation, the steps of procedure 1000 are described in a certain order. These steps may occur in different orders and / or some of these steps may be performed simultaneously.

[0090] Step 1002 includes grounding the selected bit line. For example, applying 0V to bit line 706b. Step 1004 includes applying a half-select voltage Vs / 2 to the half-selected word line. For example, applying Vs / 2 to word lines 706a, 706b, 706c, 706d, 706e, 706f, and 706h. Step 1006 includes applying a half-select voltage Vs / 2 to the half-selected bit line. For example, applying Vs / 2 to bit lines 708a, 708c, and 708d. Step 1008 includes applying a modulation voltage Vs to the selected word line. For example, applying Vs to word line 706g.

[0091] Figure 10B is a flowchart of procedure 1050, which describes an embodiment of applying voltage to word lines and bit lines during modulation of the selected memory cell. Procedure 1050 provides further details of embodiments of steps 804 to 808 of procedure 800. For ease of explanation, the steps of procedure 1050 are described in a certain order. These steps may occur in different orders and / or some of these steps may be performed simultaneously.

[0092] Step 1052 includes grounding the selected word line. For example, applying 0V to word line 706g. Step 1054 includes applying a half-select voltage Vs / 2 to the half-selected word line. For example, applying Vs / 2 to word lines 706a, 706b, 706c, 706d, 706e, 706f, and 706h. Step 1056 includes applying a half-select voltage Vs / 2 to the half-selected bit line. For example, applying Vs / 2 to bit lines 708a, 708c, and 708d. Step 1058 includes applying a modulation voltage Vs to the selected bit line. For example, applying Vs to bit line 708b.

[0093] Although Procedure 800 describes an embodiment of modulation signal system modulation voltage (Vs), in an alternative embodiment, modulation signal system modulation current is used. For example, a selection voltage (e.g., 0V) can be applied to the selected bit line while driving modulation current to the selected word line. Driving modulation current to the selected word line charges the voltage on the selected word line. Generally, there is a limitation on the maximum voltage that the selected word line can reach (e.g., constant current output voltage, clamping voltage, voltage limit, etc.). A suitable half-select voltage can be applied to the half-selected word line and the half-selected bit line. The half-select voltage can be, for example, half of the voltage limit. The modulation current can be progressively reduced over several modulation cycles, while the half-select voltage is progressively reduced over several modulation cycles.

[0094] Figure 11 is a flowchart of an embodiment of a procedure for modulating a threshold switching selector in a programmable resistive memory cell within a crossbar switch array using modulated current. Procedure 1100 can be used to modulate a bidirectional threshold switch (OTS). Other types of threshold switching selectors can be modulated by executing procedure 1100. Programmable resistive memory cell 401 has a programmable resistive memory element 702 connected in series with threshold switching selector 502. Examples of programmable resistive memory elements include, but are not limited to, MRAM, ReRAM, PCM (phase-change memory), and FeRAM. Procedure 1100 can be executed before operating the crossbar switch array. Therefore, procedure 1100 can be executed before writing to and reading from the memory cell. When discussing procedure 1100, reference will be made to the crossbar switch array 700 in Figure 7.

[0095] Step 1102 includes setting an initial value for how much voltage (e.g., voltage limit) the modulation current can generate on the memory cell. The modulation current is applied to the selected memory cell (or unit) for partial modulation. Applying the modulation current to the selected memory cell can generate a voltage on the selected memory cell, for example, by charging the selected word line. In one embodiment, the initial value of the modulation current will generate a voltage on the selected memory cell greater than the maximum expected initial Vth of the threshold switching selector 502.

[0096] Steps 1104 to 1110 describe the modulation of the threshold switching selector 502 in the selected memory cell. Optionally, more than one memory cell 401 in the crossbar array can be selected for modulation in parallel. Procedure 1100 will be described as an example of selecting one memory cell 401 in the crossbar array at a time for threshold switching selector modulation. For ease of explanation, steps 1104 to 1110 are described in a certain order. Steps 1104 to 1110 may occur in different orders and / or some of these steps may be performed simultaneously.

[0097] Step 1104 includes applying a half-select voltage to the half-selected word line. For example, half of the voltage limit can be applied to word lines 706a, 706b, 706c, 706d, 706e, 706f, and 706h.

[0098] Step 1106 includes applying a half-select voltage Vs / 2 to the half-selected bit line. For example, half of the voltage limit can be applied to bit lines 708a, 708c, and 708d.

[0099] Step 1108 includes grounding the selected bit line. For example, applying 0V to bit line 706b.

[0100] Step 1110 includes applying a modulation current to the selected word line. For example, a modulation current is applied to word line 706g. The modulation current may charge the selected word line until the threshold switching selector 502 in the selected memory cell is turned on. However, there may be a limitation on how high the voltage on the selected word line can be charged (e.g., a voltage limit). In this document, the phrase "modulation current has a voltage limit" is used to refer to the maximum voltage that may appear on memory cell 401 due to the application of the modulation current.

[0101] Step 1111 includes determining whether to perform additional modulation on the cell at the current voltage limit value. In one embodiment, the memory system applies a predetermined number of modulation currents to the selected memory cell at the current voltage limit value. The memory system may change the polarity of the modulation current in the next application (and thus change the voltage on the cell). For example, in one iteration of steps 1104 to 1110, the modulation may produce a positive voltage from the word line to the bit line, and in another iteration of steps 1104 to 1110, the modulation may produce a negative voltage from the word line to the bit line.

[0102] Step 1112 includes determining whether another memory cell 401 exists in the crossbar switch array for partial modulation of the threshold switching selector 502. In one embodiment, the memory system selects each memory cell 401 in the crossbar switch array once in each loop of the modulation procedure. A loop of the modulation procedure refers to modulating each memory cell 401 in the crossbar switch array according to a specific voltage limit of the voltage generated on the cell by the modulation current. Steps 1104 to 1110 are repeated with the same voltage limit of the modulation current until all memory cells 401 in the crossbar switch array have been modulated once.

[0103] After the modulation cycle is completed, in step 1114, it is determined whether the threshold switching selector 502 in the crossbar switch array has reached the target threshold voltage range. Note that there may be some differences in the threshold voltage between different threshold switching selectors 502. If the target threshold voltage range has not been reached, the voltage limit value is reduced in step 1116. The half-select voltage value is also reduced accordingly. Then, the memory system executes the next cycle of the modulation procedure by returning to step 1104. In one embodiment, the voltage limit value is progressively reduced in each cycle until the voltage limit value reaches the target value. After program 1100, memory cells can be read or written.

[0104] As can be seen from the above, according to an embodiment, an apparatus includes an array of cross switches comprising a first set of conductive lines, a second set of conductive lines, and programmable resistor memory cells. Each programmable resistor memory cell has a threshold switching selector connected in series with the programmable resistor memory element. The apparatus has control circuitry communicating with the cross switch array. The control circuitry is configured to apply one or more modulation signals to each programmable resistor memory cell in the cross switch array in each of a plurality of modulation cycles to progressively reduce the threshold voltage of the threshold switching selector in the plurality of modulation cycles. The control circuitry reduces the magnitude of the modulation signal in each modulation cycle to partially form the threshold switching selectors in the plurality of modulation cycles until the target operating threshold voltage range is reached.

[0105] In another embodiment, the modulation signal applied to the selected memory cell generates a voltage on the selected memory cell, the voltage being at least as large as the threshold voltage of the threshold switching selector of the selected memory cell.

[0106] In another embodiment, the control circuit is configured to apply a modulation signal to the selected memory cell while simultaneously applying a half-select voltage to a plurality of half-selected memory cells in the crossbar switch array. The half-select voltage has a value that is approximately half the maximum value of the voltage appearing on the selected memory cell due to the modulation signal being applied to it.

[0107] In another embodiment, the modulation signal gradually reduces the threshold voltage of the threshold switching selector by an amount in each modulation cycle, such that the threshold voltage of the threshold switching selector remains higher than the half-select voltage.

[0108] In another embodiment, in order to apply a modulation signal to a memory cell selected for partial modulation, a control circuit applies a current that generates a voltage on the selected memory cell and limits the voltage on the selected memory cell to a voltage limit, the half-select voltage having an amount of approximately half of the voltage limit.

[0109] In another embodiment, the control circuit reduces the magnitude of the modulation voltage in each modulation cycle to partially form the threshold switching selectors in the plurality of modulation cycles until the target operating threshold voltage range is reached.

[0110] In another embodiment, in order to apply a modulation signal to a memory cell selected for partial modulation, a control circuit applies a current that generates a voltage on the selected memory cell and limits the voltage on the selected memory cell to a voltage limit, the half-select voltage having an amount of approximately half of the voltage limit.

[0111] In another embodiment, the control circuit reduces the voltage limit in each modulation cycle to partially form the threshold switching selectors in the plurality of modulation cycles until the target operating threshold voltage range is reached.

[0112] In another embodiment, for each modulation cycle, the control circuit applies the modulation signal to each memory cell in both positive and negative polarity.

[0113] In another embodiment, each of the limit switching selectors includes a bidirectional limit switch (OTS).

[0114] In another embodiment, the programmable resistive memory element includes a magnetic tunneling interface having a free layer and a reference layer.

[0115] An embodiment includes a method for modulating a threshold switching selector of a programmable resistive memory cell in a cross switch array. The method includes a) applying a modulation voltage to selected memory cells in the cross switch array, and simultaneously applying a half-select voltage to half-selected memory cells in the cross switch array. The modulation voltage has an amount greater than the threshold voltage of the threshold switching selector in the selected memory cell, and the half-select voltage has an amount less than the threshold voltage of the threshold switching selector in the half-selected memory cell. The method includes b) repeating a) for other selected memory cells and other half-selected memory cells in the cross switch array. The method includes c) decreasing the amount of the modulation voltage and repeating a) and b) until the threshold switching selectors of the memory cells in the cross switch array reach a target threshold voltage range.

[0116] An embodiment includes a memory system comprising a crossbar switch array, the crossbar switch array comprising a first set of conductive lines, a second set of conductive lines, and programmable resistive memory cells. Each programmable resistive memory cell has a bidirectional threshold switch (OTS) connected in series with the programmable resistive memory element. The memory system includes control circuitry communicating with the crossbar switch array. The control circuitry is configured to: a) apply a modulation voltage to selected memory cells in the crossbar switch array, and simultaneously apply a half-select voltage to half-selected memory cells in the crossbar switch array. The half-select voltage has an amount approximately half that of the modulation voltage. The control circuitry is configured to: b) repeat a) for other selected memory cells and other half-selected memory cells in the crossbar switch array. The control circuitry is configured to: c) decrease the amount of the modulation voltage and repeat a) and b) until the threshold switching selectors of the memory cells in the crossbar switch array reach a target threshold voltage range.

[0117] For the purposes of this document, references to "an embodiment", "one embodiment", "some embodiments" or "another embodiment" in this specification may be used to describe different or the same embodiments.

[0118] For the purposes of this document, a connection may be a direct connection or an indirect connection (e.g., via one or more other components). In some cases, when an element is referred to as a connection or coupling to another element, the element may be directly connected to the other element or indirectly connected to the other element via an intermediary element. When an element is referred to as being directly connected to another element, there is no intermediary element between the element and the other element. If two devices are directly or indirectly connected such that they can transmit electronic signals between them, the devices are "in communication".

[0119] For the purposes of this document, the term "based on" may be interpreted as "based at least in part on".

[0120] For the purposes of this document, without additional context, the use of numerical terms (such as “first” object, “second” object, and “third” object) may not imply the order of objects, but may be used instead for identification purposes to identify different objects.

[0121] The terms “top” and “bottom”, “upper” and “lower”, and “vertical” and “horizontal” and their forms used herein are for illustrative purposes only, and are not intended to limit the description of the technology, as the items referred to can be interchanged in position and orientation. Furthermore, as used herein, the terms “substantially” and / or “about” mean that the specified dimensions or parameters may vary within acceptable tolerances for a given application.

[0122] The above embodiments have been provided for purposes of illustration and description. They are not intended to be exhaustive or limited to the precise forms disclosed. In view of the above teachings, many modifications and variations are possible. The described embodiments have been selected to best explain the principles and practical application of the proposed technology, thereby enabling those skilled in the art to best utilize it in various embodiments and to contemplate various modifications suitable for that particular purpose. It is intended that this scope be defined by the appended claims. [Simplified Explanation of the Diagram]

[0007] Components with similar numbers refer to common components in different diagrams. [Figure 1] is a block diagram of an embodiment of a non-volatile memory system connected to a host computer. [Figure 2] is a block diagram of an embodiment of a memory die. [Figure 3] is a block diagram of an embodiment of an integrated memory assembly containing control dies and memory structure dies. [Figure 4A] depicts an embodiment of a portion of a memory array forming a crosspoint architecture in an oblique view. [Figure 4B] and [Figure 4C] present the side and top views of the crosspoint structure in Figure 4A, respectively. [Figure 4D] depicts an embodiment of a portion of a second-order memory array forming a crosspoint architecture in an oblique view. [Figure 5] illustrates an embodiment of the structure of an MRAM memory cell, for example, a cell selected here is driven by a current source for reading or writing. [Figure 6A] and [Figure 6B] illustrate an embodiment incorporating a threshold switching selector into an MRAM memory array with a crosspoint architecture. [Figure 7] Depicts an embodiment of a memory array with a crosspoint architecture accessed using a forced current method. [Figure 8] is a flowchart of an embodiment of a procedure for modulating a threshold switching selector in a programmable resistive memory cell within a cross-switch array. [Figure 9] is a graph showing an example of a gradual decrease in the threshold voltage of the threshold switching selector within each cycle of the modulation procedure. [Figures 10A] and [10B] are flowcharts depicting an embodiment of applying voltage to the word line and bit line during partial modulation of the selected memory cell. [Figure 11] is a flowchart of an embodiment of a procedure for modulating a threshold switching selector in a programmable resistive memory cell within a cross-switch array using modulated current.

Claims

1. A memory device comprising: a cross switch array including a first set of conductive lines, a second set of conductive lines, and programmable resistive memory cells, each programmable resistive memory cell having a threshold switching selector connected in series with a programmable resistive memory element; and a control circuit communicating with the cross switch array, wherein the control circuit is configured to: apply one or more modulation signals to each programmable resistive memory cell in the cross switch array in each of a plurality of modulation cycles to progressively reduce a threshold voltage of the threshold switching selectors in the plurality of modulation cycles, wherein the control circuit reduces the magnitude of the modulation signal in each modulation cycle to partially form the threshold switching selectors in the plurality of modulation cycles until a target operating threshold voltage range is reached.

2. The memory device of claim 1, wherein the modulation signal applied to a selected memory cell generates a voltage on the selected memory cell, the voltage being at least as large as the threshold voltage of the threshold switching selector of the selected memory cell.

3. The memory device of claim 2, wherein the control circuit is configured to: apply the modulation signal to the selected memory cell, and simultaneously apply a half-select voltage to a plurality of half-selected memory cells in the crossbar switch array, the half-select voltage having a value that is approximately half the magnitude of a maximum value of the voltage appearing on the selected memory cell due to the application of the modulation signal to the selected memory cell.

4. The memory device of claim 3, wherein the modulation signal gradually reduces the threshold voltage of the threshold switching selector by an amount in each modulation cycle, such that the threshold voltage of the threshold switching selector remains above the half-select voltage.

5. The memory device of claim 3, wherein, in order to apply the modulation signal to a memory cell selected for partial modulation, the control circuit: applies a modulation voltage to the selected memory cell, the half-selection voltage having a value that is approximately half of the modulation voltage.

6. The memory device of claim 5, wherein the control circuit reduces the value of the modulation voltage in each modulation cycle to partially form the threshold switching selectors in the plurality of modulation cycles until the target operating threshold voltage range is reached.

7. The memory device of claim 3, wherein, in order to apply the modulation signal to a memory cell selected for partial modulation, the control circuit: applies a current that forms a voltage on the selected memory cell; and limits the voltage on the selected memory cell to a voltage limit, the half-select voltage having a value that is approximately half of the voltage limit.

8. The memory device of claim 7, wherein the control circuit reduces the value of the voltage limit in each modulation cycle to partially form the threshold switching selectors in the plurality of modulation cycles until the target operating threshold voltage range is reached.

9. The memory device of claim 1, wherein, for each modulation cycle, the control circuit applies the modulation signal to each memory cell in a positive and a negative polarity.

10. The memory device of claim 1, wherein each of the threshold switching selectors includes a bidirectional threshold switch (OTS).

11. The memory device of claim 10, wherein the programmable resistive memory element includes a magnetic tunneling interface having a free layer and a reference layer.

12. A method for modulating a threshold switching selector of a programmable resistive memory cell in a cross-connect array, the method comprising: a) applying a modulation voltage to a selected memory cell in the cross-connect array and simultaneously applying a half-select voltage to half-selected memory cells in the cross-connect array, wherein the modulation voltage has an amount greater than a threshold voltage of a threshold switching selector of the selected memory cell, and the half-select voltage has an amount less than the threshold voltage of the threshold switching selector of the half-selected memory cells; and b) repeating a) for other selected memory cells and other half-selected memory cells in the cross-connect array; and c) decreasing the amount of the modulation voltage and repeating a) and b) until the threshold switching selectors of the memory cells in the cross-connect array reach a target threshold voltage range.

13. The method of claim 12, wherein applying the modulation voltage to the selected memory cell in the cross switch array and simultaneously applying the half-select voltage to the half-selected memory cells in the cross switch array comprises: applying the modulation voltage to one of the selected first conductive lines in the cross switch array and simultaneously applying the half-select voltage to a plurality of half-selected first conductive lines in the cross switch array; and grounding one of the selected second conductive lines in the cross switch array, wherein the selected memory cell resides between the selected first conductive line and the selected second conductive line, and a first group of the half-selected memory cells resides between the plurality of half-selected first conductive lines and the selected second conductive lines.

14. The method of claim 13, wherein applying the half-select voltage to the half-select memory cell in the cross switch array further comprises: applying the half-select voltage to a plurality of second conductive lines of half-selection in the cross switch array, wherein a second group of the half-select memory cells resides between the selected conductive lines of the plurality of half-selection and the selected first conductive lines.

15. The method of claim 12, wherein reducing the amount of the modulation voltage comprises reducing the amount of the modulation voltage in a uniform step for each of a plurality of modulation cycles, so as to partially form the threshold switching selectors within each modulation cycle.

16. A memory system comprising: a crossbar switch array including a first set of conductive lines, a second set of conductive lines, and programmable resistive memory cells, each programmable resistive memory cell having a bidirectional threshold switch (OTS) connected in series with a programmable resistive memory element; and a control circuit communicating with the crossbar switch array, wherein the control circuit is configured to: a) apply a modulation voltage to one selected memory cell in the crossbar switch array, and simultaneously apply a half-select voltage to half-selected memory cells in the crossbar switch array, wherein the half-select voltage has a value approximately half that of the modulation voltage; and b) repeat a) for other selected memory cells and other half-selected memory cells in the crossbar switch array; and c) decrease the value of the modulation voltage and repeat a) and b) until the threshold switching selectors of the memory cells in the crossbar switch array reach a target threshold voltage range.

17. The memory system of claim 16, wherein the modulation voltage has a value greater than the threshold voltage of the selected memory cell.

18. The memory system of claim 17, wherein the half-select voltage has a value less than the threshold voltage of the half-selected memory cells.

19. The memory system of claim 16, wherein the control circuit is configured to: apply the modulation voltage to one of the selected first conductors in the cross switch array, and simultaneously apply the half-select voltage to a plurality of half-selected first conductors in the cross switch array; and ground one of the selected second conductors in the cross switch array, wherein the selected memory cell resides between the selected first conductor and the selected second conductor, and a first group of the half-selected memory cells resides between the plurality of half-selected first conductors and the selected second conductor.

20. The memory system of claim 19, wherein the control circuit is further configured to: apply the half-select voltage to a plurality of half-selected second conductive lines in the cross switch array, wherein a second group of such half-selected memory cells reside between the selected conductive lines of the plurality of half-selected lines and the selected first conductive line.

Images