Circuit for controlling chip frequency, buck power supply, and method for controlling chip frequency

Abstract

This application discloses a chip frequency control circuit, a BUCK power supply, and a chip frequency control method, which are applied in the field of power electronics technology. The input terminal of the frequency reduction control unit is connected to the output voltage feedback signal of the BUCK power supply, and the output terminal of the frequency reduction control unit is connected to the control terminal of a clock oscillator, used to adjust the frequency of the clock signal output by the clock oscillator according to the output voltage feedback signal. The magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal. The clock oscillator outputs the clock signal to the switching transistor control unit, which controls the switching transistor to turn on according to the clock signal drive voltage. Because this circuit directly changes the clock signal frequency of the chip clock oscillator, the FB voltage corresponding to the on and off points of the voltage-controlled switching transistor is relatively fixed, the duty cycle difference between different periods is small, and the final inductor current pulse amplitude is uniformly distributed, thereby achieving linear and smooth frequency adjustment.

Description

Technical Field

[0001] This application relates to the field of power electronics technology, and in particular to a chip frequency control circuit, a BUCK power supply, and a chip frequency control method. Prior Technology

[0002] Figure 1 is a schematic diagram of a traditional chip frequency control circuit. As shown in Figure 1, the current frequency reduction control mode is a passive frequency reduction method, characterized by the constant frequency of the clock signal CLK output by the clock oscillator OSC. When the frequency is the highest constant frequency (i.e., not in frequency reduction mode), the falling edge of the CLK pulse will set the output of the flip-flop DFF to a high level, providing a turn-on signal to the MOS transistor Q0 via the driver circuit. As long as the voltage drop across the resistor RCS reaches the threshold voltage Vlimit, the MOS transistor Q0 will turn off. When the load decreases, the feedback signal FB (i.e., the output voltage feedback signal) generated by the output voltage increases. The output signal of the FB voltage and the first reference voltage VREF1, after being amplified by the operational amplifier EA1, is connected to the non-inverting input of the feedback voltage comparator COMP1. The output signal of EA1 is compared with the second reference voltage VREF2, and the resulting down-frequency signal is set to a high level. This high level resets the D flip-flop DFF and causes the driver output of the drive circuit to start at a low level, thereby forcibly turning off the MOS transistor Q0. The down-frequency signal is usually maintained across cycles until the FB voltage drops to equal VREF1.

[0003] As can be seen, in the traditional solution, the operating frequency exhibits a skip-cycle pattern of reduction, and the sudden frequency changes lead to instability in the inductor current. Furthermore, the FB signal has voltage ripple, causing the width of the down-frequency signal output by the feedback voltage comparator COMP1 to be inconsistent in different cycles, potentially resulting in the MOS transistor Q0 turning off earlier or later. This manifests as an unstable inductor current with varying levels of high and low conduction time for the MOS transistor Q0.

[0004] Therefore, how to achieve smooth linear frequency reduction and avoid instability of inductor current caused by frequency abrupt changes is a problem that those familiar with this technology urgently need to solve. Summary of the Invention

[0005] The purpose of this application is to provide a chip frequency control circuit, a BUCK power supply, and a chip frequency control method to solve the problem of unstable inductor current caused by frequency sudden changes when entering the frequency reduction mode in traditional solutions.

[0006] To address the aforementioned technical problems, this application provides a chip frequency control circuit, comprising: a frequency reduction control unit, a clock oscillator, a switching transistor control unit, and a voltage-controlled switching transistor; The input terminal of the frequency reduction control unit is connected to the output voltage feedback signal of the BUCK power supply, and the output terminal of the frequency reduction control unit is connected to the control terminal of the clock oscillator. It is used to adjust the frequency of the clock signal output by the clock oscillator according to the output voltage feedback signal. The magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal. The output of the clock oscillator is connected to the switching transistor control unit to output the clock signal to the switching transistor control unit. The switching transistor control unit is connected to the switch to drive the voltage control switching transistor to turn on according to the clock signal.

[0007] Preferably, it also includes: a first operational amplifier; The first input terminal of the first operational amplifier is connected to the output voltage feedback signal of the BUCK power supply, and the second input terminal of the first operational amplifier is connected to the first reference voltage; the output terminal of the first operational amplifier is connected to the input terminal of the frequency reduction control unit, and is used to output the amplified output voltage feedback signal to the frequency reduction control unit.

[0008] Preferably, the frequency reduction control unit includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first fixed current source, and a second fixed current source; The sources of both the first PMOS transistor and the second PMOS transistor are connected to a voltage source, and the gates and drains of both transistors are interconnected. The common terminal of the gate and drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the gate of the first NMOS transistor is connected to the output terminal of the first operational amplifier. The common terminal of the gate and drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, and the gate of the second PMOS transistor is connected to a second reference voltage; The source of the first NMOS transistor, the source of the second NMOS transistor, the positive terminal of the first fixed current source, and the gate of the third PMOS transistor are interconnected; the negative terminal of the first fixed current source and the drain of the third PMOS transistor are grounded. The positive terminal of the second fixed current source is connected to the voltage source; the negative terminal of the second fixed current source and the source of the third PMOS transistor are connected to each other, and the common terminal of the connection is connected to the output terminal of the frequency reduction control unit and the control terminal of the clock oscillator.

[0009] Preferably, the clock oscillator includes: a variable current source, a first capacitor, a switch, and an internal comparator; The positive terminal of the variable current source is connected to the voltage source; the negative terminal of the variable current source, the first terminal of the first capacitor, the first terminal of the switch, and the non-inverting input terminal of the internal comparator are interconnected; the second terminal of the first capacitor and the second terminal of the switch are grounded. The inverting input of the internal comparator is connected to the output of the frequency reduction control unit; the output of the internal comparator is connected to the control terminal of the switch; wherein, the output of the internal comparator serves as the output of the clock oscillator to output the clock signal.

[0010] Preferably, the variable current source is a system voltage-controlled current source; The control terminal of the voltage-controlled current source is connected to the output terminal of the frequency reduction control unit.

[0011] Preferably, the switching transistor control unit includes: a D flip-flop and a drive circuit; The clock oscillator is connected to the first input terminal of the D flip-flop, and is used to output the clock signal to the D flip-flop so that the output of the D flip-flop is set to a high level when the falling edge of the clock signal arrives; The output terminal of the D flip-flop is connected to the input terminal of the drive circuit, and the output terminal of the drive circuit is connected to the voltage-controlled switching transistor. After the D flip-flop outputs a high level, the drive circuit drives the voltage-controlled switching transistor to conduct.

[0012] Preferably, it also includes: a current sampling line for acquiring the peak current sampling signal; The current sampling line is connected to the second input terminal of the D flip-flop and is used to reset the D flip-flop based on the peak current sampling signal and the amplified output voltage feedback signal, so as to turn off the voltage control switching transistor.

[0013] Preferably, the current sampling circuit includes: a current sampling resistor, an adder, and an inductor current peak comparator; The current sampling resistor is connected in series with the voltage-controlled switching transistor in the output circuit, and the first terminal of the current sampling resistor is grounded. The first input terminal of the adder is connected to the second terminal of the current sampling resistor; the second input terminal of the adder is connected to the output terminal of the first operational amplifier; the output terminal of the adder is connected to the first input terminal of the inductor current peak comparator. The second input terminal of the inductor current peak comparator is connected to a threshold voltage, and the output terminal of the inductor current peak comparator is connected to the second input terminal of the D flip-flop. The output signal is used to reset the D flip-flop after the output of the adder exceeds the threshold voltage.

[0014] To solve the above-mentioned technical problems, this application also provides a BUCK power supply, which includes the above-mentioned chip frequency control circuit.

[0015] To address the aforementioned technical problems, this application also provides a chip frequency control method, which is applied to the aforementioned frequency reduction control unit; the method includes: Obtain the output voltage feedback signal from the BUCK power supply; The frequency of the clock signal output by the clock oscillator is adjusted according to the output voltage feedback signal, wherein the magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal.

[0016] This application provides a chip frequency control circuit comprising: a down-conversion control unit, a clock oscillator, a switching transistor control unit, and a voltage-controlled switching transistor. The input terminal of the down-conversion control unit is connected to the output voltage feedback signal of the BUCK power supply. The output terminal of the down-conversion control unit is connected to the control terminal of the clock oscillator, used to adjust the frequency of the clock signal output by the clock oscillator according to the output voltage feedback signal. The magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal. Therefore, this scheme is an active down-conversion method, characterized by a variable clock signal frequency in the clock oscillator. The output terminal of the clock oscillator is connected to the switching transistor control unit to output the clock signal to the switching transistor control unit. The switching transistor control unit is connected to a switch to control the switching transistor to conduct according to the clock signal drive voltage. Because this circuit directly changes the clock signal frequency of the chip clock oscillator, the FB voltage corresponding to the on and off points of the voltage-controlled switching transistor is relatively fixed, the duty cycle difference between different periods is small, and the final inductor current pulse amplitude is uniformly distributed, thereby achieving linear and smooth frequency adjustment.

[0017] This application also provides a BUCK power supply and a chip frequency control method, which corresponds to the above-mentioned chip frequency control circuit, and therefore has the same beneficial effects as the above-mentioned chip frequency control circuit. Simple Explanation of the Diagram

[0018] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 is a schematic diagram of a traditional chip frequency control circuit; Figure 2 shows a schematic diagram of the inductor current and frequency curves of a common BUCK power supply; Figure 3 is a schematic diagram of the operation of a traditional chip frequency control circuit in continuous mode; Figure 4 is a schematic diagram of a common high-voltage BUCK power supply application circuit; Figure 5 shows a simulation waveform diagram of the traditional Skip pulse frequency reduction method; Figure 6 is a schematic diagram of a chip frequency control circuit provided in an embodiment of this application; Figure 7 is a schematic diagram of the specific circuit structure of a frequency reduction control unit and a clock oscillator provided in an embodiment of this application; Figure 8 is a schematic diagram of the simulation waveform of the novel chip frequency control circuit provided in the frequency reduction region according to the embodiments of this application. Implementation

[0020] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this application.

[0021] The core of this application is to provide a chip frequency control circuit, a BUCK power supply, and a chip frequency control method to solve the problem of unstable inductor current caused by frequency abrupt changes when entering down-frequency mode in traditional solutions.

[0022] To enable those skilled in this art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] A buck converter, also known as a step-down converter, is a DC-DC converter circuit whose output voltage is lower than the input voltage. In this circuit, the input current is pulsating, while the output current is continuous. The core component of a buck converter is the inductor, which is responsible for converting the input voltage to the output voltage. Voltage-controlled switching transistors control the output voltage by changing their on and off states. Figure 2 shows a schematic diagram of the inductor current and frequency curves of a common buck converter; the output current Iout represents the load change, and the smaller Iout is, the smaller the load. As shown in Figure 2, as the load decreases, the current IPK will decrease to IPK_MIN. If IPK is further reduced, the switching frequency FSW will decrease from its constant maximum frequency, that is, it enters the frequency reduction mode. The frequency reduction mode is one of the important means to reduce switching losses and improve power supply efficiency.

[0024] The chip frequency control circuit in Figure 1 is used as an example for explanation. Figure 3 is a schematic diagram of the continuous mode operation of a traditional chip frequency control circuit. As shown in Figure 3, the built-in clock oscillator OSC provides a clock signal CLK at a fixed frequency. When the falling edge of CLK appears, the output of the flip-flop D sets the driver level of the drive circuit of the switching transistor (i.e., MOS transistor Q0) to high. At this time, Q0 is turned on, and the inductor current IIN_DUCTANCE begins to rise. When the frequency is a constant maximum frequency, Q0 will be turned off as long as the voltage drop across the resistor RCS reaches the voltage VLIMIT (i.e., the inductor current reaches IPK_LIMIT).

[0025] As the load decreases from full load, the switching frequency needs to decrease from its constant maximum frequency to reduce losses in the switching devices. The working mechanism uses the amplified output voltage feedback signal FB and a fixed second reference voltage VREF2 as inputs to the feedback voltage comparator COMP1. The output level of COMP1 serves as the frequency reduction signal. When the frequency reduction signal is at a high level, it forcibly clears the flip-flop DFF. After clearing, the output of the flip-flop DFF is low, and the drive of the MOS transistor Q0 remains off until the output voltage begins to decrease. Once the frequency reduction signal returns to a low level, the flip-flop DFF will output a high level generated by the falling edge of CLK. At this point, the drive of the MOS transistor Q0 reverses back to a high level. As the load continuously decreases, the amplified FB voltage becomes higher than the second reference voltage VREF2, and the time the frequency reduction signal remains at a high level continuously increases, thus achieving a continuous decrease in frequency.

[0026] Figure 4 shows a schematic diagram of a common high-voltage BUCK power supply application circuit. As shown in Figure 4, the FB signal and the output capacitor are not grounded. The FB voltage comes from the voltage divider of the sampling capacitor C5. Because the time constant of capacitor C5 and resistor R1+R2 differs from the time constant of output capacitor C3*load resistor, there is a difference in voltage ripple across the two capacitors. Therefore, the FB signal can only approximately represent the output voltage signal. The circuit shown in Figure 1 uses the Skip pulse method. The clock pulse frequency of the OSC is fixed. When the frequency reduction circuit starts working, it achieves frequency reduction by shielding the drive pulses generated by the clock signal, that is, by reducing the drive pulses. Furthermore, the more frequently the frequency shielding signal appears and the longer each duration, the greater the reduction in switching frequency.

[0027] During the frequency reduction phase, the turn-off signal of the MOS transistor Q0 is determined by the voltage drop across RCS and the frequency reduction signal. The FB signal is generated by the voltage obtained by charging the sampling capacitor C5 through inductor L2 and diode D2 during the turn-off period of the MOS transistor Q0, and then passing it through voltage divider resistors R1 and R2. Since the FB signal and the output voltage signal are not grounded, this signal can only indirectly reflect the output voltage signal. The FB signal has voltage ripple, which causes the width of the frequency reduction signal output by the feedback voltage comparator COMP1 to be inconsistent in different cycles, and the turn-off time of the MOS transistor Q0 may be advanced or delayed. This manifests as an unstable conduction time of the MOS transistor Q0 and an inductor current that fluctuates between high and low values.

[0028] Figure 5 shows a simulation waveform diagram of the traditional Skip pulse frequency reduction method. As shown in Figure 5, it includes the frequency reduction control signal, the MOSFET turn-on signal of the internal MOS transistor Q0, the output voltage Vo on the output capacitor, the inductor current in inductor L2, the internal clock frequency CLK, and the voltage FB (i.e., the output voltage feedback signal) after the voltage on the output sampling capacitor is divided by a resistor. Due to the difference in FB ripple voltage, the width of the frequency reduction signal varies in different cycles, resulting in significant differences in the conduction time of the MOS transistor Q0 in different cycles. The corresponding peak values ​​of the inductor current vary, directly leading to an increase in output voltage ripple.

[0029] The purpose of this application is to solve the problem of duty cycle instability that occurs after the BUCK power supply frequency decreases from its constant maximum frequency. To address this, a chip frequency control circuit is proposed, comprising: a frequency reduction control unit, a clock oscillator, a switching transistor control unit, and a voltage-controlled switching transistor. The input terminal of the frequency reduction control unit is connected to the output voltage feedback signal of the BUCK power supply. The output terminal of the frequency reduction control unit is connected to the control terminal of the clock oscillator, used to adjust the frequency of the clock signal output by the clock oscillator according to the output voltage feedback signal. The magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal. The output terminal of the clock oscillator is connected to the switching transistor control unit to output the clock signal to the switching transistor control unit. The switching transistor control unit is connected to a switch to control the switching transistor to conduct according to the clock signal drive voltage.

[0030] This application does not limit the specific types and structures of the above-mentioned components. A specific implementation scheme is provided here. Figure 6 is a schematic diagram of a chip frequency control circuit provided in an embodiment of this application. As shown in Figure 6, the falling edge of the CLK pulse sets the output of the D flip-flop (DFF) to a high level, providing an on-state signal to the MOS transistor Q0 via the driver circuit. When the load decreases, the output voltage feedback signal FB increases. The FB voltage and the first reference voltage VREF1 are combined with the first operational amplifier EA1 to generate a frequency reduction control signal (i.e., the signal level increases). The clock frequency of the clock oscillator OSC decreases proportionally with the increase in the level. In this mode, the output voltage feedback signal FB and the peak current sampling signal are superimposed and input to the non-inverting input of the inductor current peak comparator COMP2. After comparison with the threshold voltage VLIMIT, the inductor current peak comparator COMP2 generates a high level to reset the D flip-flop (DFF). At this time, the driver circuit output is set to a low level, and the MOS transistor Q0 is turned off. As the output load decreases from full load, the switching frequency begins to decrease, i.e., it enters the frequency reduction mode. The output feedback voltage FB is compared with the first reference voltage VREF1, and the resulting voltage, after error amplification, directly controls the frequency of the internal clock oscillator OSC. In this way, the frequency will not change abruptly, achieving a smooth linear frequency reduction.

[0031] Figure 7 is a schematic diagram of the specific circuit structure of a frequency reduction control unit and a clock oscillator (OSC) provided in an embodiment of this application. As shown in Figure 7, the first PMOS transistor Q1 and the second PMOS transistor Q2 use the "diode connection" method in the analog circuit, with the gate and drain shorted. The transistor always operates in the saturation region, and its function is equivalent to a load resistor, used to regulate the current flowing through the series NMOS transistor. The first NMOS transistor Q3 and the second NMOS transistor Q4 achieve output voltage following, achieving the switching of the input voltage at the inverting input of the internal comparator COMP3 at a constant maximum frequency and frequency reduction.

[0032] When the system load decreases, the output voltage feedback signal FB, after being compared with the reference voltage and amplified by error, triggers the frequency reduction function. The internal CLK clock frequency can be achieved by changing the voltage comparison reference of the sawtooth wave of the internal capacitor's charging and discharging, or by changing the charging and discharging current of the capacitor. The left half of the figure shows the frequency reduction control unit, and the right half shows the clock oscillator OSC.

[0033] Clock frequency: C1 is charged by the variable current source I3, and the capacitor C1 is discharged by the switch S1 to generate a sawtooth wave. Then the sawtooth wave is compared with the input voltage IN1 to generate pulse width modulation CLK.

[0034] Constant operating frequency: controlled by the second reference voltage VREF2. At this time, IN1 voltage = VREF2 - Vth4 + Vth5 ≈ VREF2, where Vth4 and Vth5 are the threshold voltages of the second NMOS transistor Q4 and the third PMOS transistor Q5, respectively.

[0035] The operating frequency during frequency reduction is controlled by Vout1, which is output from the first operational amplifier EA1 after comparing the feedback voltage FB with the first reference voltage VREF1. At this time, the IN1 voltage = Vout1 - Vth3 + Vth5 ≈ Vout1, where Vth3 and Vth5 are the threshold voltages of the first NMOS transistor Q3 and the third PMOS transistor Q5. During frequency reduction, Vout1 > VREF2, the IN1 voltage increases, the sawtooth wave charging period on C1 becomes longer, and the operating frequency of the clock oscillator OSC decreases. I3 has a system voltage-controlled current source, and its current is also controlled by the IN1 voltage. When the IN1 voltage increases, the current of I3 decreases. This design is to make the OSC frequency range wider, which helps to further reduce the switching frequency under light load and improve system efficiency.

[0036] This scheme uses a variable frequency clock signal. When the output load decreases from full load and the frequency enters the down-frequency mode, the voltage obtained by comparing the output voltage feedback signal FB with the first reference voltage VREF1 is amplified and directly reduces the frequency of the internal clock oscillator OSC of the chip. Furthermore, the frequency can be reduced smoothly and linearly as the load decreases. Figure 8 is a schematic diagram of the simulation waveform of the novel chip frequency control circuit provided in this application in the down-frequency region. As shown in Figure 8, the simulation results show that the duty cycle of the power supply is relatively fixed for different cycles, the amplitude of the inductor current is relatively stable, and the resulting output ripple is also uniform.

[0037] In traditional frequency reduction methods, the clock frequency CLK of the OSC (Optical Clock Oscillator) is fixed, and frequency reduction is achieved by shielding the Q0 drive pulses of part of the MOS transistor. Due to the voltage ripple of the FB signal, the voltage at the turn-off point FB varies, causing inconsistent amplitude of the inductor current in the frequency reduction region. The new frequency reduction method in this application, however, does not clear the D flip-flop after the frequency reduction circuit starts working, and does not forcibly pull down the CLK signal emitted by the OSC. The FB voltage signal is compared with a reference and then directly controls the frequency of the OSC; that is, by reducing the frequency of the OSC, the switching frequency is reduced, achieving linear frequency reduction.

[0038] The chip frequency control circuit provided in this application includes: a down-frequency control unit, a clock oscillator, a switching transistor control unit, and a voltage-controlled switching transistor. The input terminal of the down-frequency control unit is connected to the output voltage feedback signal of the BUCK power supply. The output terminal of the down-frequency control unit is connected to the control terminal of the clock oscillator, used to adjust the frequency of the clock signal output by the clock oscillator according to the output voltage feedback signal. The magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal. Therefore, this scheme is an active down-frequency reduction method, characterized by a variable clock signal frequency in the clock oscillator. The output terminal of the clock oscillator is connected to the switching transistor control unit to output the clock signal to the switching transistor control unit. The switching transistor control unit is connected to a switch to control the switching transistor to conduct according to the clock signal drive voltage. Since this circuit directly changes the clock signal frequency of the chip clock oscillator, the FB voltage corresponding to the on and off points of the voltage-controlled switching transistor is relatively fixed, the duty cycle difference between different periods is small, and the final inductor current pulse amplitude is uniformly distributed, thereby achieving linear and smooth frequency adjustment.

[0039] As mentioned in the above embodiments, this application does not limit the specific structure of the chip frequency control circuit. The circuit provided in this embodiment also includes a first operational amplifier EA1; the first input terminal of the first operational amplifier is connected to the output voltage feedback signal FB of the BUCK power supply, and the second input terminal of the first operational amplifier is connected to the first reference voltage VREF1; the output terminal of the first operational amplifier is connected to the input terminal of the down-conversion control unit, and is used to output the amplified output voltage feedback signal to the down-conversion control unit. By amplifying the output voltage feedback signal with the first operational amplifier, the subsequent control becomes more precise.

[0040] Based on the above implementation, this embodiment provides a specific frequency reduction control unit to control the clock frequency of a clock oscillator. Specifically, the frequency reduction control unit of this embodiment consists of a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first fixed current source, and a second fixed current source. The sources of both the first and second PMOS transistors are connected to a voltage source, and their gates and drains are interconnected. The common terminal of the gate and drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the gate of the first NMOS transistor is connected to the output terminal of a first operational amplifier. The common terminal of the gate and drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, and the gate of the second PMOS transistor is connected to a second reference voltage. The sources of the first NMOS transistor, the second NMOS transistor, the positive terminal of the first fixed current source, and the gate of the third PMOS transistor are interconnected; the negative terminal of the first fixed current source and the drain of the third PMOS transistor are grounded. The positive terminal of the second fixed current source is connected to a voltage source; the negative terminal of the second fixed current source and the source of the third PMOS transistor are interconnected, and their common terminal serves as the output terminal of the down-conversion control unit and is connected to the control terminal of the clock oscillator. Correspondingly, the clock oscillator specifically consists of a variable current source, a first capacitor, a switch, and an internal comparator. The positive terminal of the variable current source is connected to a voltage source; the negative terminal of the variable current source, the first terminal of the first capacitor, the first terminal of the switch, and the non-inverting input terminal of the internal comparator are interconnected; the second terminal of the first capacitor and the second terminal of the switch are grounded; the inverting input terminal of the internal comparator is connected to the output terminal of the down-conversion control unit; the output terminal of the internal comparator is connected to the control terminal of the switch; wherein, the output terminal of the internal comparator serves as the output terminal of the clock oscillator to output a clock signal. Specifically, the variable current source is a voltage-controlled current source; the control terminal of the voltage-controlled current source is connected to the output terminal of the frequency reduction control unit. By controlling the voltage-controlled switching transistor Q0 through the specific structure provided in this embodiment, a smooth linear frequency reduction can be achieved since the frequency of the clock oscillator will not change abruptly.

[0041] In practical applications, the switching transistor control unit can be specifically composed of a D flip-flop and a driving circuit. A clock oscillator is connected to the first input terminal of the D flip-flop to output a clock signal to the D flip-flop so that the output of the D flip-flop is set to a high level when the falling edge of the clock signal arrives. The output terminal of the D flip-flop is connected to the input terminal of the driving circuit, and the output terminal of the driving circuit is connected to the voltage-controlled switching transistor. After the D flip-flop outputs a high level, the driving circuit drives the voltage-controlled switching transistor to conduct.

[0042] The above structure can drive the voltage-controlled switching transistor to conduct, and after the voltage-controlled switching transistor is turned on, it also needs to be turned off to achieve complete control of the voltage-controlled switching transistor. This embodiment provides a specific implementation scheme, in which the chip frequency control circuit also includes a current sampling circuit, which is used to acquire the peak current sampling signal. The current sampling circuit is connected to the second input terminal of the D flip-flop, and is used to reset the D flip-flop based on the peak current sampling signal and the amplified output voltage feedback signal, so as to turn off the voltage-controlled switching transistor. This document provides a specific structure for a current sampling circuit, comprising: a current sampling resistor, an adder, and an inductor current peak comparator; the current sampling resistor and a voltage-controlled switching transistor are connected in series in the output circuit, and the first terminal of the current sampling resistor is grounded; the first input terminal of the adder is connected to the second terminal of the current sampling resistor; the second input terminal of the adder is connected to the output terminal of a first operational amplifier; the output terminal of the adder is connected to the first input terminal (non-inverting input terminal) of the inductor current peak comparator; a threshold voltage is connected to the second input terminal (inverting input terminal) of the inductor current peak comparator, and the output terminal of the inductor current peak comparator is connected to the second input terminal of a D flip-flop, used to output a signal to reset the D flip-flop when the output of the adder exceeds the threshold voltage. The output voltage feedback signal FB and the peak current sampling signal are superimposed and input to the non-inverting input of the inductor current peak comparator. They are compared with the threshold voltage V LIMIT at the inverting input and then the inductor current peak comparator generates a high-level reset D flip-flop. At this time, the output of the drive circuit is set to the low level, and the voltage control switching transistor Q0 is turned off.

[0043] To address the aforementioned technical problems, this application provides a BUCK power supply, which includes the chip frequency control circuit described in the above embodiments.

[0044] Since the embodiments of the BUCK power supply section correspond to the embodiments of the chip frequency control circuit section, please refer to the description of the embodiments of the chip frequency control circuit section for the embodiments of the BUCK power supply section, and will not be repeated here.

[0045] The BUCK power supply provided in this embodiment corresponds to the above-mentioned chip frequency control circuit, and therefore has the same beneficial effects as the above-mentioned chip frequency control circuit.

[0046] To address the aforementioned technical problems, this application also provides a chip frequency control method, applied to the frequency reduction control unit in the above embodiments. The method includes the following steps: S1: Obtaining the output voltage feedback signal of the BUCK power supply. S2: Adjusting the frequency of the clock signal output by the clock oscillator according to the output voltage feedback signal. Wherein, the magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal.

[0047] Since the embodiments of the method section correspond to the embodiments of the wafer frequency control circuit section, please refer to the description of the embodiments of the wafer frequency control circuit section for the embodiments of the method section, and they will not be repeated here.

[0048] The method provided in this embodiment corresponds to the above-described wafer frequency control circuit, and therefore has the same beneficial effects as the above-described wafer frequency control circuit.

[0049] The foregoing has provided a detailed description of a chip frequency control circuit, a BUCK power supply, and a chip frequency control method provided in this application. The various embodiments in the specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from the principles of this application, and such improvements and modifications also fall within the protection scope of this application.

[0050] It should also be noted that, in this specification, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between such entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a program, method, object, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such program, method, object, or apparatus. Without further limitations, an element defined by the phrase "comprising a..." does not exclude the presence of other identical elements in a program, method, object, or apparatus that includes the aforementioned element.

[0051] C1: Capacitor C5: Sampling capacitor CLK: Clock signal / clock frequency / signal COMP1: Feedback Voltage Comparator COMP2: Inductor current peak comparator COMP3: Internal Comparator D2: Dipolar DFF:D flip-flop Driver: via driver circuit / driver circuit EA1: Operational Amplifier / First Operational Amplifier FB: Feedback signal / output voltage Feedback signal / voltage / output feedback voltage / feedback voltage Frequency reduction: Frequency reduction control signal Fsw: Switching frequency I3: Variable Current Source / Voltage-Controlled Current Source I IN_D UC TANC E: Inductor current IN1: Input voltage Inductor current: Current Iout: Output current I pk: Current I PK_LIMIT: Inductor current I PK_MIN: Current L2: Inductor MOSFET turn-on: On-start signal OSC: Clock Oscillator / Built-in Clock Oscillator / Internal Clock Oscillator Q0: MOS transistor / Internal MOS transistor on the chip / Voltage-controlled switching transistor Q1: First PMOS transistor Q2: Second PMOS transistor Q3: First NMOS transistor Q4: Second NMOS transistor Q5: Third PMOS transistor R1: Resistance / Voltage via voltage divider resistor R2: Resistance / Voltage via voltage divider resistor RCS: Resistance S1: Switch V LIMIT: Voltage / Preliminary Voltage VO: Output voltage V REF1: First reference voltage V REF2: Second reference voltage

Claims

1. A chip frequency control circuit, characterized in that it comprises: The system comprises a frequency reduction control unit, a clock oscillator, a switching transistor control unit, and a voltage-controlled switching transistor. The input of the frequency reduction control unit is connected to the output voltage feedback signal of the BUCK power supply. The output of the frequency reduction control unit is connected to the control terminal of the clock oscillator, used to adjust the frequency of the clock signal output by the clock oscillator according to the output voltage feedback signal. The magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal. The output of the clock oscillator is connected to the switching transistor control unit to output the clock signal to the switching transistor control unit. The switching transistor control unit is connected to the voltage-controlled switching transistor to drive the voltage-controlled switching transistor to conduct according to the clock signal.

2. As in request item 1, the chip frequency control circuit, wherein, It also includes: a first operational amplifier; the first input terminal of the first operational amplifier is connected to the output voltage feedback signal of the BUCK power supply, the second input terminal of the first operational amplifier is connected to the first reference voltage; the output terminal of the first operational amplifier is connected to the input terminal of the down-conversion control unit, and is used to output the amplified output voltage feedback signal to the down-conversion control unit.

3. As in request item 2, the chip frequency control circuit, wherein, The frequency reduction control unit includes: a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first fixed current source, and a second fixed current source; the sources of the first PMOS transistor and the second PMOS transistor are both connected to a voltage source, and the gates and drains of the first PMOS transistor and the second PMOS transistor are interconnected; the common terminal of the gate and drain of the first PMOS transistor is connected to the drain of the first NMOS transistor, and the gate of the first NMOS transistor is connected to the output terminal of the first operational amplifier; the common terminal of the gate and drain of the second PMOS transistor is connected to the drain of the second NMOS transistor, and the gate of the second PMOS transistor is connected to a second reference voltage; the sources of the first NMOS transistor, the second NMOS transistor, the positive terminal of the first fixed current source, and the gate of the third PMOS transistor are interconnected; the negative terminal of the first fixed current source and the drain of the third PMOS transistor are grounded; The positive terminal of the second fixed current source is connected to the voltage source; the negative terminal of the second fixed current source and the source of the third PMOS transistor are connected to each other, and the common terminal of the connection is connected to the output terminal of the frequency reduction control unit and the control terminal of the clock oscillator.

4. The chip frequency control circuit as described in request item 3, wherein, The clock oscillator includes: a variable current source, a first capacitor, a switch, and an internal comparator; the positive terminal of the variable current source is connected to the voltage source; the negative terminal of the variable current source, the first terminal of the first capacitor, the first terminal of the switch, and the non-inverting input terminal of the internal comparator are interconnected; the second terminal of the first capacitor and the second terminal of the switch are grounded; the inverting input terminal of the internal comparator is connected to the output terminal of the frequency reduction control unit; the output terminal of the internal comparator is connected to the control terminal of the switch; wherein, the output terminal of the internal comparator serves as the output terminal of the clock oscillator to output the clock signal.

5. The chip frequency control circuit as described in request item 4, wherein, The variable current source is a voltage-controlled current source; the control terminal of the voltage-controlled current source is connected to the output terminal of the frequency reduction control unit.

6. The chip frequency control circuit as described in any of requests 2 to 5, wherein, The switching transistor control unit includes: a D flip-flop and a driving circuit; a clock oscillator is connected to the first input terminal of the D flip-flop and is used to output the clock signal to the D flip-flop so that the output of the D flip-flop is set to a high level when the falling edge of the clock signal arrives; the output terminal of the D flip-flop is connected to the input terminal of the driving circuit, and the output terminal of the driving circuit is connected to the voltage-controlled switching transistor. After the D flip-flop outputs a high level, the driving circuit drives the voltage-controlled switching transistor to turn on.

7. The chip frequency control circuit as described in request item 6, wherein, It also includes: a current sampling line for acquiring a peak current sampling signal; the current sampling line is connected to the second input terminal of the D flip-flop, and is used to reset the D flip-flop based on the peak current sampling signal and the amplified output voltage feedback signal, so as to turn off the voltage-controlled switching transistor.

8. The chip frequency control circuit as described in request item 7, wherein, The current sampling circuit includes: a current sampling resistor, an adder, and an inductor current peak comparator; the current sampling resistor is connected in series with the voltage-controlled switching transistor in the output circuit, and the first terminal of the current sampling resistor is grounded; the first input terminal of the adder is connected to the second terminal of the current sampling resistor; the second input terminal of the adder is connected to the output terminal of the first operational amplifier; the output terminal of the adder is connected to the first input terminal of the inductor current peak comparator; a threshold voltage is connected to the second input terminal of the inductor current peak comparator, and the output terminal of the inductor current peak comparator is connected to the second input terminal of the D flip-flop, used to output a signal to reset the D flip-flop when the output of the adder exceeds the threshold voltage.

9. A BUCK power supply, characterized in that it includes a chip frequency control circuit as claimed in any one of claims 1 to 8.

10. A chip frequency control method, characterized in that it is applied to a frequency reduction control unit as described in any one of claims 1 to 5; the method includes: Obtain the output voltage feedback signal of the BUCK power supply; The frequency of the clock signal output by the clock oscillator is adjusted according to the output voltage feedback signal, wherein the magnitude of the output voltage feedback signal is negatively correlated with the frequency of the clock signal.

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