Electronic package and substrate structure thereof

Abstract

This invention discloses an electronic package and its substrate structure. The substrate structure includes a substrate body and surface circuitry. The substrate body has a first side and a second side. The first side defines a die-placement area and a peripheral area adjacent to the die-placement area. Conversely, the second side defines a projected die-placement area and a projected peripheral area adjacent to the projected die-placement area. A stress concentration area is defined at the corner of the projected die-placement area in the projected peripheral area, and a stress extension line is further defined in the stress concentration area. This ensures that the layout direction of the surface circuitry formed on the second side of the substrate body does not overlap with the stress extension line, thereby preventing damage to the surface circuitry.

Description

Technical Field

[0001] This invention relates to a semiconductor structure, and more particularly to an electronic package and its substrate structure. Prior Technology

[0002] With the evolution of semiconductor packaging technology, different packaging types have been developed for semiconductor devices. Among them, ball grid array (BGA), such as PBGA, EBGA, and FCBGA, is an advanced semiconductor packaging technology. Its feature is that a packaging substrate is used to place the semiconductor chip, and a number of solder balls arranged in a grid array are placed on the back of the packaging substrate. This allows more input / output connections to be accommodated on the same unit area of ​​the carrier to meet the needs of highly integrated semiconductor chips.

[0003] Figure 1 shows a cross-sectional schematic diagram of a prior art ball grid array packaging structure. This packaging structure has a semiconductor wafer 110 disposed on one surface of a packaging substrate 100, and a plurality of solder balls 120 disposed in an array on the other surface of the packaging substrate 100 for subsequent connection to a circuit board.

[0004] Furthermore, with the rapid development of the semiconductor industry, in order to meet the demand for multi-functional integration and high capacity of electronic products, larger-sized chips are often placed in the packaging structure. This not only tests the circuit design capabilities of the packaging substrate and the packaging process capabilities, but also causes excessive stress on the overall structure, and even leads to abnormal reliability. Common problems include cracking of the green paint on the packaging substrate surface or breakage of the surface circuit on the side with solder balls.

[0005] To solve the problems of cracked green paint or broken surface circuits on the packaging substrate, it is often necessary to change the material of the packaging substrate or change the appearance and size of the semiconductor wafer (such as changing the thickness and size of the semiconductor wafer). However, such changes are major process changes and are usually unacceptable to customers.

[0006] Therefore, how to overcome the various problems of the aforementioned conventional technologies without changing the materials and dimensions has become an urgent issue to be addressed. Summary of the Invention

[0007] In view of the various deficiencies of the prior art, the present invention provides a substrate structure comprising: a substrate body having a first side and a second side opposite to each other, the first side defining a crystal placement area and a peripheral area adjacent to the crystal placement area, the second side defining a projected crystal placement area and a projected peripheral area adjacent to the projected crystal placement area, wherein the projected crystal placement area corresponds to the vertical projection position of the crystal placement area, the projected peripheral area corresponds to the vertical projection position of the peripheral area, a stress concentration area is further defined in the corner of the projected peripheral area corresponding to the projected crystal placement area, and a stress extension line is further defined in the stress concentration area; and a surface circuit formed on the second side of the substrate body and including conductive traces, wherein the arrangement direction of the conductive traces does not overlap with the stress extension line.

[0008] The present invention further provides an electronic package comprising: a substrate structure including: a substrate body having a first side and a second side opposite to each other, the first side defining a die placement area and a peripheral area adjacent to the die placement area, the second side defining a projected die placement area and a projected peripheral area adjacent to the projected die placement area, wherein the projected die placement area corresponds to a vertical projection position of the die placement area, the projected peripheral area corresponds to a vertical projection position of the peripheral area, a stress concentration area is further defined in the projected peripheral area corresponding to a corner of the projected die placement area, and a stress extension line is further defined in the stress concentration area; and a surface circuit formed on the second side of the substrate body and including conductive traces, wherein the arrangement direction of the conductive traces does not overlap with the stress extension line; and an electronic component disposed in the die placement area of ​​the substrate structure.

[0009] In the aforementioned electronic package and its substrate structure, the first side of the substrate body is a crystal-mounted side for carrying electronic components, and the second side of the substrate body is a ball-mounted side for mounting multiple conductive components.

[0010] In the aforementioned electronic package and its substrate structure, the length and width of the stress concentration area are the widths of the three conductive elements, respectively.

[0011] In the aforementioned electronic package and its substrate structure, the angle between the stress extension line and one side of the adjacent projected crystal placement area is 135 degrees.

[0012] In the aforementioned electronic package and its substrate structure, the width of the conductive traces in the stress concentration area of ​​the surface circuit is greater than the width of the conductive traces in other areas.

[0013] In the aforementioned electronic package and its substrate structure, the width of the conductive trace in the stress concentration area of ​​the surface circuit is twice the width of the conductive trace in other areas.

[0014] In the aforementioned electronic package and its substrate structure, the substrate body includes a dielectric layer and a circuit layer bonded to the dielectric layer, and the surface circuit is electrically connected to the circuit layer.

[0015] In the aforementioned electronic package and its substrate structure, the surface circuitry includes an electrical connection pad connected to the conductive trace.

[0016] As can be seen from the above, the electronic package and its substrate structure of the present invention mainly ensure that the conductive traces of the surface circuit formed on the second side of the substrate body do not overlap with the stress extension lines in the stress concentration area on the second side of the substrate body, and can further widen the width of the surface circuit located in the stress concentration area to avoid surface circuit damage. Simple Explanation of the Diagram

[0017] Figure 1 is a cross-sectional schematic diagram of a conventional ball grid array packaging structure.

[0018] Figure 2 is a cross-sectional schematic diagram of the electronic package and its substrate structure of the present invention.

[0019] Figure 3 is a partial bottom view of the first embodiment of the substrate structure of the present invention.

[0020] Figure 4 is a partial bottom view of the second embodiment of the substrate structure of the present invention. Implementation

[0021] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification.

[0022] It should be understood that the structures, proportions, sizes, etc., illustrated in the accompanying drawings of this specification are only for the purpose of assisting those skilled in the art in understanding and reading the content disclosed herein, and are not intended to limit the conditions under which the present invention can be implemented. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in the proportional relationships, or adjustments to the size, without affecting the effects and objectives that the present invention can produce, should still fall within the scope of the technical content disclosed herein. Furthermore, the terms such as "above," "first," "second," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of the present invention. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of the present invention.

[0023] Please refer to Figures 2 and 3 simultaneously. Figure 2 is a cross-sectional view of the electronic package and its substrate structure of the present invention, and Figure 3 is a partial bottom view of the substrate structure of the present invention.

[0024] The electronic package 3 includes a substrate structure 2a and electronic components 30 disposed on the substrate structure 2a.

[0025] The substrate structure 2a includes a substrate body 20 and surface circuitry 21 formed on the substrate body 20.

[0026] The substrate body 20 has a first side 20a and a second side 20b opposite to each other. The first side 20a of the substrate body 20 can serve as a crystal placement side for carrying electronic components 30, and the second side 20b of the substrate body 20 can serve as a ball placement side for connecting conductive components 33.

[0027] The substrate body 20 is, for example, a packaged substrate with a core layer or a coreless packaged substrate, which includes a dielectric layer 202 and a circuit layer 203 bonded to the dielectric layer 202.

[0028] The surface layer circuit 21 is formed on the first side 20a and the second side 20b of the substrate body 20 and is electrically connected to the circuit layer 203. In this embodiment, the surface layer circuit 21 includes a plurality of interconnected electrical connection pads 211 and conductive traces 212. One end of the conductive trace 212 is connected to the electrical connection pad 211, and the other end can be connected to a conductive blind via, thereby electrically connecting to the circuit layer 203 through the conductive blind via.

[0029] The circuit layer 203 and the surface circuit 21 can be formed, for example, by a redistribution layer (RDL) fabrication method. The material forming the circuit layer 203 and the surface circuit 21 is copper, and the material forming the dielectric layer 202 is a dielectric material such as polybenzoxazole (PBO), polyimide (PI), or prepreg (PP).

[0030] The first side 20a of the substrate body 20 defines a die placement area A and a peripheral area B adjacent to the die placement area A, wherein the surface layer circuit 21 formed on the first side 20a of the substrate body 20 can span the die placement area A and the peripheral area B. The die placement area A is used to place electronic components, and the peripheral area B is disposed around the die placement area A and can be used to place passive components or heat sinks.

[0031] The second side 20b of the substrate body 20 defines a projection crystal placement area A' and a projection peripheral area B' adjacent to the projection crystal placement area A'. The projection crystal placement area A' corresponds to the vertical projection position of the crystal placement area A, and the projection peripheral area B' corresponds to the vertical projection position of the peripheral area B. The surface layer circuit 21 formed on the second side 20b of the substrate body 20 can span the projection crystal placement area A' and the projection peripheral area B'.

[0032] The electronic component 30 is an active component such as a semiconductor wafer. In this embodiment, the electronic component 30 has an active surface 30a and a non-active surface 30b, and the active surface 30a has a plurality of electrode pads, so that the electronic component 30 is electrically connected to the electrical connection pads 211 of the surface layer circuit 21 of the first side 20a of the substrate body 20 by a plurality of conductive bumps 31 containing solder material in a flip-chip manner, and then the conductive bumps 31 are covered with a primer 32.

[0033] In addition, the electronic package 3 further includes a plurality of conductive elements 33 disposed on the substrate structure 2a (the second side 20b of the substrate body 20).

[0034] In this embodiment, the conductive element 33 is, for example, a solder ball, which is disposed on the electrical connection pad 211 of the surface line 21 on the second side 20b of the substrate body 20, so that the electronic package 3 can be electrically connected to an external device (e.g., a circuit board) through the plurality of conductive elements 33.

[0035] In addition, a stress concentration area C is redefined in the corner of the projection periphery area B' of the second side 20b of the substrate body 20, corresponding to the projection crystal placement area A'. The stress concentration area C is the area where the substrate body 20 is subjected to stress during the packaging process, and its length and width are approximately the width of three conductive elements 33 (solder balls).

[0036] Furthermore, a stress extension line L is further defined in the stress concentration area C. The stress extension line L is the extension direction of the stress concentration area C with greater stress. The surface circuit 21 (conductive trace 212) formed on the second side 20b of the substrate body 20 does not overlap with the stress extension line L to avoid the surface circuit 21 on the second side 20b of the substrate body 20 from cracking.

[0037] In one embodiment, as shown in FIG3, the angle X between the stress extension line L and one side of the adjacent projection crystal placement area A' is approximately 135 degrees, and the arrangement direction of the conductive trace 212 of the surface circuit 21 formed on the second side 20b of the substrate body 20 is approximately 90 degrees with one side of the adjacent projection crystal placement area A'. The two angles are different to avoid overlap.

[0038] In another embodiment, as shown in FIG4, the width of the conductive trace 212a of the surface circuit 21 formed on the second side 20b of the substrate body 20 in the stress concentration region C is greater than the width of the conductive trace 212b in other regions. For example, the width of the conductive trace 212a of the surface circuit 21 in the stress concentration region C is about twice the width of the conductive trace 212b in other regions, so as to avoid the surface circuit 21 from cracking.

[0039] In summary, the electronic package and its substrate structure of the present invention mainly ensure that the conductive traces of the surface circuits formed on the second side of the substrate body do not overlap with the stress extension lines in the stress concentration area on the second side of the substrate body, and can further widen the width of the surface circuits located in the stress concentration area to avoid surface circuit damage.

[0040] The above embodiments are illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as set forth in the following patent claims.

[0041] 100: Packaging substrate 110: Semiconductor wafers 120: Welding ball 2a: Substrate structure 20:Substrate body 20a: First side 20b: Second side 202: Dielectric layer 203: Line Layer 21: Surface circuit 211: Electrical connection pad 212, 212a, 212b: Conductive traces 3: Electronic packaging components 30: Electronic components 30a: Surface of Action 30b: Non-functional surface 31: Conductive bump 32: Base rubber 33: Conductive elements A: Crystal placement area B: Outer Zone A': Projection crystal placement area B': Projection perimeter area C: Stress concentration area L: Stress extension line X, Y: included angle

Claims

1. A substrate structure comprising: The substrate body has a first side and a second side opposite to each other. The first side defines a die-placement area and a peripheral area adjacent to the die-placement area. The second side is a ball-mounting side for placing a plurality of conductive elements and defines a projected die-placement area and a projected peripheral area adjacent to the projected die-placement area. The projected die-placement area corresponds to the vertical projection position of the die-placement area, and the projected peripheral area corresponds to the vertical projection position of the peripheral area. A stress concentration area is further defined in the projected peripheral area at a corner corresponding to the projected die-placement area. The length and width of the stress concentration area are the widths of three conductive elements, and a stress extension line is further defined in the stress concentration area. The angle between the stress extension line and one side of the adjacent projected die-placement area is 135 degrees. A surface layer circuit is formed on the second side of the substrate body and includes conductive traces, wherein the arrangement direction of the conductive traces does not overlap with the stress extension line.

2. The substrate structure as described in claim 1, wherein, The first side of the substrate body is the crystal placement side for carrying electronic components.

3. The substrate structure as described in claim 1, wherein, The width of the conductive traces in the stress concentration area of ​​the surface circuit is greater than the width of the conductive traces in other areas.

4. The substrate structure as described in claim 1, wherein, The width of the conductive trace in the stress concentration area of ​​the surface circuit is twice the width of the conductive trace in other areas.

5. The substrate structure as described in claim 1, wherein, The substrate body includes a dielectric layer and a circuit layer bonded to the dielectric layer, and the surface circuit is electrically connected to the circuit layer.

6. The substrate structure as described in claim 1, wherein, The surface circuitry includes an electrical connection pad that is connected to the conductive trace.

7. An electronic package, comprising: A substrate structure comprising: a substrate body having a first side and a second side opposite to each other, wherein the first side defines a die-placement area and a peripheral area adjacent to the die-placement area, the second side is a ball-mounting side for placing a plurality of conductive elements, and defines a projected die-placement area and a projected peripheral area adjacent to the projected die-placement area, the projected die-placement area corresponding to the vertical projection position of the die-placement area, the projected peripheral area corresponding to the vertical projection position of the peripheral area, a stress concentration area is further defined in the projected peripheral area at a corner corresponding to the projected die-placement area, the length and width of the stress concentration area are respectively the width of three conductive elements, and a stress extension line is further defined in the stress concentration area, the angle between the stress extension line and one side of the adjacent projected die-placement area is 135 degrees; and a surface circuit formed on the second side of the substrate body and including conductive traces, wherein the arrangement direction of the conductive traces does not overlap with the stress extension line; and electronic components disposed in the die-placement area of ​​the substrate structure.

8. The electronic package as described in claim 7, wherein, The first side of the substrate body is the crystal placement side for carrying the electronic component.

9. The electronic package as described in claim 7, wherein, The width of the conductive traces in the stress concentration area of ​​the surface circuit is greater than the width of the conductive traces in other areas.

10. The electronic package as described in claim 7, wherein, The width of the conductive trace in the stress concentration area of ​​the surface circuit is twice the width of the conductive trace in other areas.

11. The electronic package as described in claim 7, wherein, The substrate body includes a dielectric layer and a circuit layer bonded to the dielectric layer, and the surface circuit is electrically connected to the circuit layer.

12. The electronic package as described in claim 7, wherein, The surface circuitry includes an electrical connection pad that is connected to the conductive trace.

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