memory devices

Abstract

A memory device capable of storing data with high precision is provided, comprising: a first memory cell including a first magnetoresistive element and a first switching element connected to the first magnetoresistive element; a first wiring connected to a first end of the first memory cell; a second wiring connected to a second end of the first memory cell; a first switch having a third end and a fourth end connected to the second wiring; a third wiring connected to the fourth end; a second switch having a fifth end and a sixth end connected to the third wiring; a fourth wiring connected to the sixth end; a first transistor having a gate connected to the third wiring and a seventh end connected to the fourth wiring; a third switch connected between the seventh end and a first node receiving a first voltage; and a sensing amplifier circuit connected to the fourth wiring.

Description

[Technical Field]

[0001] The implementation method is generally related to a memory device. [Previous Technology]

[0002] A memory device using a magnetoresistive element is known. [Summary of the Invention]

[0003] The problem to be solved by the present invention is to provide a memory device that can store data with high precision.

[0004] A memory device according to one embodiment includes a first memory cell, a first wiring, a second wiring, a first switch, a third wiring, a second switch, a fourth wiring, a first transistor, a third switch, and a sense amplifier circuit. The first memory cell includes a first magnetoresistive element and a first switch element connected to the first magnetoresistive element. The first wiring is connected to a first terminal of the first memory cell. The second wiring is connected to a second terminal of the first memory cell. The first switch has a third terminal and a fourth terminal connected to the second wiring. The third wiring is connected to the fourth terminal. The second switch has a fifth terminal and a sixth terminal connected to the third wiring. The fourth wiring is connected to the sixth terminal. The first transistor has a gate connected to the third wiring and a seventh terminal connected to the fourth wiring. The third switch is connected between the seventh terminal and a first node receiving a first voltage. The sense amplifier circuit is connected to the fourth wiring.

Implementation Method

[0006] Hereinafter, embodiments will be described with reference to the figures. For multiple constituent elements having substantially the same function and structure in a certain embodiment or different embodiments, additional numbers or characters are sometimes appended to the end of the reference symbols to distinguish them from each other.

[0007] In subsequent embodiments of a previously described embodiment, the differences from the previously described embodiment are primarily described. Unless expressly or implicitly excluded, all descriptions relating to a particular embodiment also apply to the description of other embodiments.

[0008] In this specification and the claims, the term "connected" to another second element includes the first element being directly or always or selectively connected to the second element via a conductive element.

[0009] Hereinafter, a three-dimensional orthogonal coordinate system will be used to describe the implementation method. The direction of the x-axis is called the X-direction. The direction opposite to the X-direction is called the -X-direction. The direction of the y-axis is called the Y-direction. The direction opposite to the Y-direction is called the -Y-direction. The direction of the z-axis is called the Z-direction, with "up" referring to the Z-direction. The direction opposite to the Z-direction is called the -Z-direction, with "down" referring to the -Z-direction.

[0010] 1. First Embodiment 1.1. Configuration (Structure) Figure 1 shows the functional blocks of the memory device according to the first embodiment. The memory device 1 includes a core circuit 111, an input / output circuit 12, a control circuit 13, a decoding circuit 14, a page buffer 15, and a voltage generation circuit 16.

[0011] The core circuit 11 is a circuit that includes multiple memory cells MC and wiring and circuits for accessing the memory cells MC.

[0012] Input / output circuit 12 is a circuit for inputting and outputting data and signals. Input / output circuit 12 receives control signals CNT, commands CMD, address information ADD, and data DAT from an external source of memory device 1, such as a memory controller. Input / output circuit 12 outputs data DAT.

[0013] Control circuit 13 receives command CMD and control signal CNT from input / output circuit 12. Control circuit 13 controls core circuit 11 based on the control indicated by command CMD and control signal CNT to control data reading from memory cell MC and data writing to memory cell MC. Control circuit 13 also controls voltage generation circuit 16 based on the control indicated by command CMD and control signal CNT.

[0014] Decoding circuit 14 is a circuit that decodes address information ADD. Decoding circuit 14 receives address information ADD from input / output circuit 12. Decoding circuit 14 decodes address information ADD and generates a signal based on the decoding result for selecting memory cell MC as the object of data reading or data writing. The generated signal is sent to core circuit 11.

[0015] Page buffer 15 is a circuit that temporarily stores data of a certain size. Page buffer 15 receives data DAT to be written to memory cell MC from input / output circuit 12, temporarily stores the data, and transmits the data to core circuit 11. Page buffer 15 receives data read from memory cell MC, temporarily stores the read data, and transmits the data DAT to input / output circuit 12.

[0016] During the data writing process of the memory cell MC, the voltage generation circuit 16 supplies the voltage used for data writing to the core circuit 11. During the data reading process from the memory cell MC, the voltage generation circuit 16 supplies the voltage used for data reading to the core circuit 11.

[0017] Figure 2 shows the functional blocks of the core circuit of the memory device according to the first embodiment. As shown in Figure 2, the core circuit 11 includes multiple sub-core circuits SCC, multiple global character lines GWL, multiple global bit lines GBL, GWL selector GWS, GBL selector GBS, conversion circuit group CCS, wiring FWL, wiring FBL, write circuit 18 and read circuit 19.

[0018] Each sub-core circuit SCC is a group of multiple constituent elements, including multiple memory cells MC, multiple selectors, and multiple wiring. Each sub-core circuit SCC is connected to a global word line GWL and a global bit line GBL.

[0019] Each global character line (GWL) is connected to multiple sub-core circuits (SCC). Each global bit line (GBL) is connected to multiple sub-core circuits (SCC).

[0020] The GWL selector GWS is a circuit that selects one of a plurality of global character lines GWL. Each GWL selector GWS receives address information ADD or a signal based on address information ADD, and connects the global character line GWL determined by the received address information ADD or the signal based on address information to the wiring FWL.

[0021] A GBL selector GBS is a circuit that selects one of a plurality of global bit lines GBL. Each GBL selector GBS receives address information ADD or a signal based on address information ADD, and connects one of the plurality of global bit lines GBL, determined by the received address information ADD or the signal based on address information, to wiring FBL.

[0022] The conversion circuit group CCS is a group of circuits that convert current into voltage. The conversion circuit group CCS is connected between the wiring FBL and the global bit line GBL. The conversion circuit group CCS applies a voltage to the wiring FBL based on the magnitude of the current flowing through the global bit line GBL.

[0023] The write circuit 18 is a circuit that controls the writing of data to the memory cell MC. The write circuit 18 receives the write data DAT from the input / output circuit 12 and receives the voltage for data writing from the voltage generation circuit 16. Based on the control of the control circuit 13 and the write data DAT, the write circuit 18 supplies the voltage and current used for data writing to wiring FWL and wiring FBL.

[0024] The readout circuit 19 is a circuit that controls the readout of data from the memory cell MC. The readout circuit 19 receives a voltage from the voltage generation circuit 16 for data readout. Based on the control of the control circuit 13, the readout circuit 19 uses the voltage used for data readout to determine the data stored in the memory cell MC. The determined data is supplied to the input / output circuit 12 as readout data DAT. The readout circuit 19 includes multiple sense amplifier circuits SAC. The sense amplifier circuit SAC is a circuit that outputs data determined to be stored in the memory cell MC as the data readout target, using a voltage based on the data stored in the memory cell MC as the data readout target. Details of the sense amplifier circuit SAC will be described below.

[0025] Figure 3 shows the constituent elements and connections of the GWL selector and GBL selector of the memory device according to the first embodiment. As shown in Figure 3, the GWL selector GWS includes a number of switches GWSW equal to the number of sub-core circuits SCC connected to each global word line GBL. Each switch GWSW is connected to a wiring FWL at one end and to a global word line GWL at the other end. Each switch GWSW is a p-type or n-type metal-oxide-semiconductor field-effect transistor (MOSFET), or p-type and n-type MOSFETs connected in parallel and receiving complementary signals at their respective gates. The description relating to the switch GWSW also applies to the switches GWSW, WSW, BSW, SW1, SW2, SW3, SW4, SW5, SW6, SW11, and SW12 described later. Each switch GWSW is turned on or off by control of the read circuit 19 or write circuit 18 based on address information ADD or a signal based on address information.

[0026] The GBL selector GBS includes the same number of switches GBSW as the number of sub-core circuits SCC connected to each global bit line GWL. Each switch GBSW is connected to a wiring FBL at one end and to a global bit line GBL at the other end. Each switch GBSW is turned on or off by control of a read circuit 19 or a write circuit 18 based on address information ADD or a signal based on address information.

[0027] The conversion circuit group CCS contains the same number of conversion circuits CC as the number of sub-core circuits SCC connected to each global bit line GWL. Each conversion circuit CC is connected between the wiring FBL and a global bit line GBL. Each conversion circuit CC applies a voltage to the global bit line GBL connected to it, based on the magnitude of the current flowing through the wiring FBL to which it is connected.

[0028] Figure 4 shows the functional blocks of the sub-core circuit of the memory device according to the first embodiment. As shown in Figure 4, each sub-core circuit SCC includes a memory cell array MCA, multiple word lines WL, multiple bit lines BL, WL selector WS, BL selector BS, global word line GWL, and global bit line GBL.

[0029] A memory cell array (MCA) is a collection of arranged memory cells (MCs). Memory cells (MCs) can non-volatilely store data. Word lines (WL) and bit lines (BL) are also located within the memory cell array (MCA). The following description is based on an example where word lines (WL) are associated with rows and bit lines (BL) are associated with columns. Word lines (WL) and bit lines (BL) are simple names used to distinguish between the two types of wiring, and they can also have opposite names. Each memory cell (MC) is connected to one word line (WL) and one bit line (BL). A memory cell (MC) is determined by selecting a column and selecting a row.

[0030] Each word line WL is connected to multiple memory cells MC. Each bit line BL is connected to multiple memory cells MC. Each memory cell MC contains one MTJ element MTJ and one switching element SE. In each memory cell MC, the MTJ element MTJ and the switching element SE are connected in series. The switching element SE of each memory cell MC is connected to one word line WL. The MTJ element MTJ of each memory cell MC is connected to one bit line BL.

[0031] An MTJ element is a device that exhibits a tunneling magnetoresistive effect, such as a device containing a magnetic tunnel junction (MTJ). MTJ elements are also called magnetoresistive effect devices. MTJ elements are variable resistance devices that can switch between low-resistance and high-resistance states. MTJ elements can use the difference between the two resistance states to store one bit of data. In one example, an MTJ element stores data "0" in a low-resistance state and data "1" in a high-resistance state.

[0032] The switching element SE is a component having two terminals for electrically connecting or disconnecting the two terminals. When the voltage applied between the two terminals along a first direction is less than a certain threshold voltage, the switching element SE is in a high-resistance state, for example, an electrically non-conducting state (off state). When the voltage applied between the two terminals rises to above the threshold voltage, the switching element SE becomes a low-resistance state, for example, an electrically conducting state (on state). When the voltage applied between the two terminals of the low-resistance switching element SE becomes less than the threshold voltage, the switching element SE becomes a high-resistance state. The switching element SE also has the same function as this switching between high-resistance and low-resistance states based on the magnitude of the voltage applied along the first direction in a second direction opposite to the first direction. That is, the switching element SE is a bidirectional switching element. By turning the switching element SE on or off, the presence or absence of current supply to the MTJ element MTJ connected to the switching element SE can be controlled, i.e., the selection or non-selection of the MTJ element MTJ.

[0033] Each WL selector WS is a circuit that selects one of a plurality of character lines WL. Each WL selector WS receives address information ADD or a signal based on address information ADD, and connects one of the plurality of character lines WL, determined by the received address information ADD or the signal based on address information ADD, to a global character line GWL.

[0034] Each BL selector BS is a circuit that selects one of a plurality of bit lines BL. Each BL selector BS receives address information ADD or a signal based on address information ADD, and connects one of the plurality of bit lines BL, determined by the received address information ADD or the signal based on address information ADD, to a global bit line GBL.

[0035] Figure 5 shows the constituent elements and connections of the WL selector and BL selector of the memory device according to the first embodiment. As shown in Figure 5, the WL selector WS includes the same number of switches WSW as the number of memory cells MC connected to each bit line BL. Each switch WSW is connected to a global word line GWL at one end and to a word line WL at the other end. Each switch WSW is turned on or off by the control of the readout circuit 19 based on address information ADD or a signal based on address information ADD.

[0036] The BL selector BS includes the same number of switches BSW as the number of memory cells MC connected to each word line WL. Each switch BSW is connected to the global bit line GBL at one end and to a bit line BL at the other end. Each switch BSW is turned on or off by the control of the readout circuit 19 based on the address information ADD or the signal based on the address information ADD.

[0037] In the examples of Figures 2, 3, 4, and 5, the core circuit 11 has two levels. The lowest level is the configuration shown in Figure 4, which includes a group of memory cells MC, word lines WL, bit lines BL, WL selectors WS, and BL selectors BS. The second level is the configuration shown in Figure 2, which includes a group of sub-core circuits SCC, global word lines GWL, global bit lines GBL, GWL selectors GWS, and GBL selectors GBS.

[0038] The core circuit 11 may also have three or more levels. By turning on the selector switch in each level, a word line WL is connected to the write circuit 18 and the read circuit 19. Similarly, by turning on the selector switch in each level, a bit line BL is connected to the write circuit 18 and the read circuit 19.

[0039] FIG6 is a perspective view of a portion of the memory cell array of the memory device according to the first embodiment. As shown in FIG6, a plurality of conductors 21 and a plurality of conductors 22 are provided.

[0040] The conductor 21 has a straight shape, extends along the X direction and is arranged along the Y direction. Each conductor 21 functions as at least a part of a character line WL.

[0041] Conductor 22 is located in the Z direction relative to conductor 21. Conductor 22 has a straight shape, extends in the Y direction and is arranged in the X direction. Each conductor 22 functions as at least part of a bit line BL.

[0042] A memory cell MC is provided at the intersection of conductor 21 and conductor 22. The memory cells MC are arranged in a matrix along the xy plane including the X and Y directions. Each memory cell MC includes a structure that functions as a switching element SE and a structure that functions as an MTJ element MTJ. The structure that functions as a switching element SE and the structure that functions as an MTJ element MTJ each include one or more layers. For example, the structure that functions as an MTJ element MTJ is located on the upper surface of the structure that functions as a switching element SE. The lower surface of the memory cell MC is connected to the upper surface of a conductor 21. The upper surface of the memory cell MC is connected to the lower surface of a conductor 22.

[0043] Figure 7 shows a cross-sectional view of a structural example of a memory cell in the memory device of the first embodiment. The switching element SE includes a variable resistance material 32. The variable resistance material 32 is a material that dynamically exhibits variable resistance, for example, having a layered shape. The variable resistance material 32 is a two-terminal switching element, with the first terminal of the two terminals being one of the upper and lower surfaces of the variable resistance material 32, and the second terminal of the two terminals being the other of the upper and lower surfaces of the variable resistance material 32. When the voltage applied between the two terminals is less than a certain threshold voltage, the variable resistance material is in a "high resistance" state, for example, an electrically non-conductive state. When the voltage applied between the two terminals reaches or exceeds the threshold voltage, the variable resistance material becomes a "low resistance" state, for example, an electrically conductive state. When the voltage applied between the two terminals of the variable resistance material 32 in the low resistance state decreases and becomes less than the threshold voltage, the variable resistance material becomes a high resistance state.

[0044] In one example, the variable resistor material 32 comprises an insulator and a dopant introduced into the insulator by ion implantation. The insulator may comprise, for example, an oxide, SiO2, or a material substantially formed from SiO2. In one example, the dopant comprises arsenic (As) or germanium (Ge). The description of "substantially formed (or constituted)" and similar descriptions indicate that a "substantially formed" constituent element may contain unintended impurities.

[0045] The switching element SE may further include a lower electrode 31 and an upper electrode 33. Figure 7 illustrates this example. A variable resistive material 32 is located on the upper surface of the lower electrode 31, and the upper electrode 33 is located on the upper surface of the variable resistive material 32.

[0046] The MTJ component includes a strong magnetic layer 35, an insulating layer 36, and a strong magnetic layer 37. As an example, as shown in FIG7, the insulating layer 36 is located on the upper surface of the strong magnetic layer 35, and the strong magnetic layer 37 is located on the upper surface of the insulating layer 36.

[0047] The strong magnetic layer 35 is a layer of material exhibiting strong magnetism. The strong magnetic layer 35 has an easy magnetization axis along the interface penetrating the strong magnetic layer 35, the insulating layer 36, and the strong magnetic layer 37. In one example, it has an easy magnetization axis at an angle of 45° or more and 90° or less relative to the interface. In another example, it has an easy magnetization axis along a direction orthogonal to the interface. The magnetization direction of the strong magnetic layer 35 remains unchanged whether data is read from or written to the memory cell MC. The strong magnetic layer 35 can function as a so-called reference layer RL. The strong magnetic layer 35 may also comprise multiple layers. Hereinafter, the strong magnetic layer 35 is sometimes referred to as the reference layer RL.

[0048] The insulating layer 36 is an insulating layer. The insulating layer 36 contains, for example, magnesium oxide (MgO) or is substantially composed of MgO, and functions as a so-called tunneling barrier (TB).

[0049] The strong magnetic layer 37 is a layer of material exhibiting strong magnetism. The strong magnetic layer 37 may contain, for example, cobalt iron boron (CoFeB) or iron boride (FeB), or be substantially composed of CoFeB or FeB. The strong magnetic layer 37 has an easy magnetization axis along the interface penetrating the strong magnetic layer 35, the insulating layer 36, and the strong magnetic layer 37. In one example, it has an easy magnetization axis at an angle of 45° or more and 90° or less relative to the interface; in another example, it has an easy magnetization axis along a direction orthogonal to the interface. The magnetization direction of the strong magnetic layer 37 can vary depending on the data written to the memory cell MC, and the strong magnetic layer 37 can function as a so-called memory layer (SL). Hereinafter, the strong magnetic layer 37 is sometimes referred to as the memory layer SL.

[0050] If the magnetization direction of the memory layer SL is parallel to the magnetization direction of the reference layer RL, then the MTJ element MTJ has a low resistance. If the magnetization direction of the memory layer SL is antiparallel to the magnetization direction of the reference layer RL, then the MTJ element MTJ has a higher resistance than when the magnetization direction of the memory layer SL is antiparallel to the magnetization direction of the reference layer RL.

[0051] When a current of magnitude Icp or greater flows from the memory layer SL toward the reference layer RL, the magnetization direction of the memory layer SL becomes parallel to the magnetization direction of the reference layer RL. When a current of magnitude Icap or greater flows from the reference layer RL toward the memory layer SL, the magnetization direction of the memory layer SL becomes antiparallel to the magnetization direction of the reference layer RL.

[0052] MTJ Components MTJ may also contain further layers.

[0053] Figure 8 shows an example of the voltage and current characteristics of the memory cell in the memory device of the first embodiment. The horizontal axis of the graph represents the magnitude of the terminal voltage (i.e., the potential difference between the two ends) of the memory cell MC. The vertical axis of the graph represents the magnitude of the current flowing through the memory cell MC on a logarithmic scale. Figure 8 uses dashed lines to represent hypothetical characteristics that do not actually occur. Figure 8 shows the cases where the memory cell MC is in a low resistance state and a high resistance state.

[0054] As the voltage increases from 0, the current continues to increase until it reaches the threshold voltage Vth. Until the voltage reaches the threshold voltage Vth, the switching element SE of the memory cell MC is open, i.e., non-conductive.

[0055] When the voltage increases further and reaches the critical voltage Vth, that is, when point A is reached, the relationship between voltage and current exhibits a discontinuous change, displaying the characteristics shown at points B1 and B2. The magnitude of the current at points B1 and B2 is significantly greater than the magnitude of the current at point A. This rapid change in current is based on the switching element SE of the memory cell MC being turned on. The magnitude of the current at points B1 and B2 depends on the resistance state of the MTJ element MTJ of the memory cell MC.

[0056] When the self-switching element SE is turned on, for example, when the voltage and current show the relationship shown at point B1 or point B2 and points with higher voltages, the voltage decreases and the current continues to decrease.

[0057] When the voltage decreases further and reaches a certain value, the voltage-current relationship becomes discontinuous. The voltage at which the voltage-current relationship begins to become discontinuous depends on the terminal voltage of the MTJ element MTJ in the memory cell MC, that is, on whether the MTJ element MTJ is in a high-resistance state or a low-resistance state. When the MTJ element MTJ is in a low-resistance state, the voltage-current relationship becomes discontinuous from point C1. When the MTJ element MTJ is in a high-resistance state, the voltage-current relationship becomes discontinuous from point C2. The voltage-current relationship exhibits the characteristics shown at points D1 and D2 when reaching points C1 and C2, respectively. The current magnitudes at points D1 and D2 are significantly smaller than the current magnitudes at points C1 and C2, respectively. This rapid change in current is due to the switching element SE of the memory cell MC being turned off.

[0058] The terminal voltage at point D1 of the memory cell MC of an MTJ element that includes a low resistance state is called the low holding voltage VhdL. The terminal voltage at point D2 of the memory cell MC of an MTJ element that includes a high resistance state is called the high holding voltage VhdH.

[0059] Figure 9 shows the constituent elements of the conversion circuit of the memory device according to the first embodiment, the connections of the constituent elements, and related constituent elements. Figure 9 shows an example of Q+1 global bit lines GBL_0 to GBL_Q.

[0060] Each switching circuit CC includes an n-type MOSFET Tr1 and a switch SW1. The transistor Tr1 and switch SW1 are connected in series between the wiring FBL and the node receiving the ground voltage VSS. The transistor Tr1 is connected at its gate to a global bit line GBL. Switch SW1_0 receives signal S1_0. Switch SW1_0 is turned on or off by signal S1_0. Similarly, for all cases where α is an integer greater than or equal to 1 and less than Q, switch SW1_α receives signal S1_α. Switch SW1_α is turned on or off by signal S1_α. Signals S1_0 to S1_Q are supplied by the readout control circuit RCC. The readout control circuit RCC is included in the readout circuit 19.

[0061] During the period when the switch SW1 receives a high-level or "H" level signal S1, it becomes in the ON state, maintaining the electrical connection between one end of the switch SW1 and the other end. During the period when the switch SW1 receives a low-level or "L" level signal S1, it becomes in the OFF state, maintaining the electrical disconnection between one end of the switch SW1 and the other end.

[0062] Let n be an integer greater than or equal to 2. The same applies to the switch SWn and signal Sn described later. That is, for switch SWn, the description related to switch SW1 is replaced with the description of switch SWn, and for signal Sn, the description related to signal S1 is replaced with the description of signal Sn.

[0063] For all cases where α is an integer greater than or equal to 0 and less than or equal to Q, the readout control circuit RCC maintains the signal S1_α at a high level during the data readout period when the address information ADD specifies the global bit line GBL_α.

[0064] FIG10 shows the constituent elements of the readout circuit of the memory device according to the first embodiment and an example of the connection of the constituent elements. Furthermore, as an example, FIG10 also shows a memory cell MC that is the object of data readout and the constituent elements associated with the memory cell MC. Hereinafter, the memory cell MC that is the object of data readout or data writeout is sometimes referred to as the selected memory cell MC_s.

[0065] The switch GBSW used to connect the selected memory cell MC_s to the wiring FBL is called switch GBSW_s. The signal received by switch GBSW at the control terminal is sometimes called signal SGB, and the signal received by switch GBSW_s at the control terminal is sometimes called signal SGB_s.

[0066] The readout circuit 19 further includes switches SW2, SW3, SW4, SW5 and SW6, an n-type MOSFET Tr2 and a sense amplifier circuit SAC.

[0067] Switch SW2 is connected between the node receiving the pre-charge voltage VPRCH and the wiring FBL. In one example, the pre-charge voltage VPRCH is supplied by the self-voltage generation circuit 16. The pre-charge voltage VPRCH is higher than the ground voltage VSS.

[0068] Switch SW3 is connected between wiring FBL and the node receiving a fixed-size non-selective voltage VUSEL. In one example, the non-selective voltage VUSEL is supplied by the self-voltage generation circuit 16. The non-selective voltage VUSEL has a height between the ground voltage VSS and the pre-charge voltage VPRCH. In one example, the non-selective voltage VUSEL has a height of half the pre-charge voltage VPRCH.

[0069] Transistor Tr2 is connected at one end to a node that receives a fixed positive voltage Vhh. Voltage Vhh is the internal power supply voltage of memory device 1, and in one example, it is lower than the power supply voltage VDD. In one example, voltage Vhh is supplied by the voltage generation circuit 16. Transistor Tr2 receives a fixed positive voltage Vload at its gate, and voltage Vload is higher than the ground voltage VSS. In one example, voltage Vload is supplied by the voltage generation circuit 16. Transistor Tr2 receives a constant current at the other end based on the magnitude of voltage Vhh and voltage Vload.

[0070] Switch SW4 is connected between the other end of transistor Tr2 and wiring FBL.

[0071] The sense amplifier circuit SAC outputs data OUT, determined to be stored in the selected memory cell MC_s, which is the target of data readout, based on the supplied voltage. In one example, the sense amplifier circuit SAC includes an operational amplifier OP. The non-inverting input of the operational amplifier OP is connected to wiring FBL. The inverting input of the operational amplifier OP receives a fixed-value voltage VREF. In one example, the voltage VREF has a height between the high holding voltage VhdH and the low holding voltage VhdL.

[0072] Switch SW5 is connected between wiring FWL and the node receiving the non-selective voltage VUSEL. Switch SW6 is connected between wiring FWL and the node receiving the ground voltage VSS.

[0073] Read out the RCC output signals S2, S3, S4, S5 and S6 of the control circuit.

[0074] FIG11 shows the layout of a portion of the memory device according to the first embodiment. As shown in FIG11, the memory device 1 includes a substrate 41. The substrate 41 is unfolded along the xy plane. The memory device 1 includes region 42_1 and region 42_2.

[0075] Region 42_1 includes multiple source / drain regions 43_1 and multiple conductors 45_1. The source / drain regions 43_1 have various sizes and shapes. The conductors 45_1 have various sizes and shapes. The source / drain regions 43_1 are irregularly arranged. The portions of each source / drain region 43_1 and conductor 45_1 that overlap with that source / drain region 43_1 function as transistors TR_1. In one example, the transistor TR_1 is a transistor in a sense amplifier circuit SAC.

[0076] Region 42_2 includes multiple source / drain regions 43_2 and multiple conductors 45_2. The source / drain regions 43_2 and conductors 45_2 are arranged in a regular manner. In the example of Figure 11, the source / drain regions 43_2 have the same size or an equal multiple of a certain reference size and are arranged in a matrix. The conductors 45_2 are also arranged in a regular manner. In the example of Figure 11, the conductors 45_2 have the same size in the Y direction and are arranged along the X direction.

[0077] The portions of each source / drain region 43_2 and conductor 45_2 that overlap with the source / drain region 43_2 function as transistors TR_2. In one example, transistor TR_2 is switch GWSW, switch GBSW, switch WSW, and switch BSW. Moreover, in one example, transistor TR_2 is transistor Tr1 and switch SW1. That is, the switching circuit CC is located in region 42_2.

[0078] Region 42_2 does not contain source / drain regions and conductors with irregular shapes, sizes and / or configurations as in region 42_1.

[0079] 1.2. Operation Figure 12 shows the potentials of several signals and wirings during the data readout period of the memory device of the first embodiment along the timeline. Figure 12 shows the state in which a selected memory cell MC_s is selected as the data readout target. That is, the switches BSW, WSW, and GWSW connected to the selected memory cell MC_s are turned on during the period shown in Figure 12. When data readout begins in the state in which the selected memory cell MC_s is selected as the data readout target, the operation during the period shown in Figure 12 begins.

[0080] During the period shown in FIG12, the selected memory cell MC_s, which is the data read-out target, is selected. For this purpose, the signal SB_s has a high level during the period shown in FIG12. The signal SB_s is a signal that turns the switch BSW, which is connected to the selection bit line BL_s, on or off. The selection bit line BL_s is a bit line BL connected to the selected memory cell MC_s. With the high-level signal SB_s, during the period shown in FIG12, the selection bit line BL_s is connected to a global bit line GBL via the on switch BSW. Hereinafter, the global bit line GBL connected to the selection bit line BL_s via the on switch BSW is sometimes referred to as the selected global bit line GBL_s.

[0081] Throughout the period shown in FIG12, the signal SGB_ns has a low level. The signal SGB_ns is a signal that turns the switch GBSW_ns, which is connected to the global bit line GBL other than the selected global bit line GBL_s, on or off. Hereinafter, the global bit line GBL other than the selected global bit line GBL_s is sometimes referred to as the non-selected global bit line GBL_ns. With the low level signal SGB_ns, the switch GBSW_ns is turned off, and therefore, throughout the period shown in FIG12, the self-connection line FBL of the non-selected global bit line GBL_ns is cut off.

[0082] Throughout the period shown in Figure 12, the signal S1_ns has a low level. The signal S1_ns is the signal S1 supplied to the switch SW1 in the conversion circuit CC connected to the non-selected global bit line GBL_ns.

[0083] At time t1, signal S1_s has a low level. Signal S1_s is the signal S1 supplied to switch SW1 in the conversion circuit CC connected to the global selection bit line GBL_s. By means of the low level signal S1_s, switch SW1 in the conversion circuit CC connected to the global selection bit line GBL_s is disconnected.

[0084] At time t1, signals S2, S4, and S6 are at a low level, and signals S3 and S5 are at a high level. Therefore, switches SW2, SW4, and SW6 are open, and switches SW3 and SW5 are closed.

[0085] At time t1, signal SGB_s has a low level. Signal SGB_s is a signal that turns switch GBSW_s on or off, which is connected to the global bit line GBL connected to the on switch BSW. Switch GBSW_s is turned off by the low level signal SGB_s.

[0086] Based on the fact that switch SW2 is open and switch SW3 is closed, wiring FBL receives the non-selection voltage VUSEL. Therefore, the potential of the selected bit line BL_s (selection bit line potential) VBL has the non-selection potential VUSEL. The non-selection potential VUSEL is a potential of magnitude that the wiring has by receiving the non-selection voltage VUSEL. In one example, it has a height that is substantially the same as the non-selection voltage VUSEL.

[0087] Based on the fact that switch SW6 is open and switch SW5 is closed, wiring FWL receives non-selection voltage VUSEL. Therefore, the potential (selection word line potential) VWL of the word line (selection word line) WL connected to the selected memory cell MC_s has non-selection potential VUSEL.

[0088] At time t2, signal SGB_s is set to high level. This selects the global bit line GBL_s to be connected to wiring FBL.

[0089] At time t2, signal S2 is set to a high level and signal S3 is set to a low level. Hereby, switch SW2 is turned on and switch SW3 is turned off. Therefore, starting from time t2, the select bit line potential VBL rises to the precharge potential VPRCH. The precharge potential VPRCH is a potential of magnitude obtained by applying a precharge voltage VPRCH through the wiring, and in one example, has a height substantially the same as the precharge voltage VPRCH.

[0090] At time t3, signal S2 is set to a low level. Consequently, switch SW2 is opened, and wiring FBL, the global selection bit line GBL_s, and the selection bit line BL_s are electrically floating. After time t3, the selection bit line potential VBL also stops at the pre-charge potential VPRCH.

[0091] At time t3, signal SGB_s is set to low level. This causes switch GBSW_s to open, and the global bit line GBL_s self-matching line FBL to be cut off.

[0092] At time t4, signal S5 is set to a low level and signal S6 is set to a high level. This causes switch SW5 to open and switch SW6 to close. Consequently, the select word line potential VWL decreases towards the ground potential VSS. The ground potential VSS is a potential that the wiring receives by accepting the ground voltage VSS, and in one example, it has a height substantially the same as the ground voltage VSS.

[0093] At time t5, the difference between the select word line potential VWL and the select bit line potential VBL reaches the threshold voltage Vth. At this point, the switching element SE of the select memory cell MC_s is turned on. Consequently, the select word line WL is electrically connected to the select bit line BL_s via the turned-on switching element SE in the select memory cell MC_s. Thus, cell current flows from the select bit line BL_s towards the select word line WL.

[0094] Because the select bit line BL_s is electrically floating, the select bit line potential VBL decreases due to the cell current flow. At this time, the decrease in the select bit line potential VBL depends on the state of the MTJ element MTJ of the select memory cell MC_s. The select bit line potential VBL decreases more slowly when the MTJ element MTJ of the select memory cell MC_s is in a high-resistance state than when the MTJ element MTJ of the select memory cell MC_s is in a low-resistance state.

[0095] At time t6, the selection bit line potential VBL becomes the height of the resistance state of the MTJ element MTJ based on the selection memory cell MC_s. That is, due to the decrease in the selection bit line potential VBL, the difference between the selection bit line potential VBL and the selection bit line potential VBL decreases. Consequently, when the terminal voltage of the selection memory cell MC_s reaches a certain height, the switching element SE of the selection memory cell MC_s is turned off. As a result, the decrease in the selection bit line potential VBL stops, and the selection bit line potential VBL will have a certain height.

[0096] Through the actions from time t4 to time t6, the selected bit line potential VBL, and even the selected global bit line GBL_s, will have a potential based on the state of the selected memory cell MC_s. Hereinafter, the actions from time t4 to time t6 are sometimes referred to as signal output actions.

[0097] At time t7, signals S4 and S1_s are set to a high level. This turns on switches SW1 and SW4, applying a constant current to wiring FBL. At time t7, the global selection bit line GBL_s has a potential corresponding to the state of the selection memory cell MC_s; therefore, a voltage based on the state of the selection memory cell MC_s is applied to the gate of transistor Tr1. Thus, the potential of wiring FBL will have a potential based on the state of the selection memory cell MC_s. In this way, the cell current based on the magnitude of the state of the selection memory cell MC_s is converted into a potential (voltage).

[0098] Subsequently, the self-sensing amplifier circuit SAC outputs data determined by the potential of the wiring FBL and identified as the data stored in the selected memory cell MC_s.

[0099] At time t8, signals S4 and S1_s are set to low level. The actions during the period from time t7 to time t8 are sometimes referred to as sensing actions.

[0100] Signal S1_s may also be a high level only during the signal output action and sensing action, that is, after time t4 and a low level until time t4.

[0101] 1.3. Advantages (Effects) According to the first embodiment, as described below, a memory device with high operational margin and high accuracy in storing data can be provided.

[0102] As an example for reference, consider the following configuration: the input of the switching circuit CC, i.e., the gate of transistor Tr1, is connected to the wiring FBL, and the output of the switching circuit CC, i.e., the drain of transistor Tr1, is connected to the sense amplifier circuit SAC. During the signal output operation and the sensing operation, the switch GBSW remains on. As explained above with reference to FIG3, wiring FBL is connected to multiple components via multiple global bit lines GBL, therefore wiring FBL has a large parasitic capacitance. Due to the large parasitic capacitance, the cell current flowing through the switching element SE of the select memory cell MC_s is large. This can cause readout interference. Readout interference can cause unintended data to be written to the select memory cell MC_s, potentially damaging the select memory cell MC_s.

[0103] To suppress readout interference, the selection bit line BL_s can perform signal output operation while either the self-select global bit line GBL_s or the wiring FBL is disconnected. Furthermore, after a potential Vout based on the state of the selected memory cell MC_s appears on the selection bit line BL_s due to the signal output operation, the selection bit line BL_s is connected to the self-select global bit line GBL_s and the wiring FBL. This allows the charge accumulated in the selection bit line BL_s to be transferred to the wiring FBL through charge sharing. Sensing operation is performed in this state. At this time, because the capacity of the selection bit line BL_s is small, the charge accumulated in the selection bit line BL_s with potential Vout is small. Therefore, cell current is suppressed, and readout interference is suppressed. On the other hand, the small amount of charge accumulated in the selection bit line BL_s is shared by the charge, so after charge sharing, the potential of the wiring FBL is less than the potential Vout. Therefore, the current input to the conversion circuit CC is small, resulting in a small margin for sensing operation.

[0104] According to the first embodiment, the input of the conversion circuit CC is connected to the global bit line GBL, and the output of the conversion circuit CC is connected to the wiring FBL. Furthermore, signal output and sensing operations are performed during the period when the global bit line GBL_s is switched off by the wiring FBL. Since the global bit line GBL_s is switched off by the wiring FBL, during the signal output operation, the selection bit line BL_s and the global bit line GBL_s have a potential Vout based on the state of the selection memory cell MC_s. On the other hand, the charge accumulated in the selection bit line BL_s and the global bit line GBL_s is small. Therefore, the cell current is small when the switching element SE of the selection memory cell MC_s is turned on. On the other hand, since the selection bit line BL_s and the global bit line GBL_s have a potential Vout based on the state of the selection memory cell MC_s, the output of the conversion circuit CC is large. Therefore, high-precision data memory and high operational margin can be achieved.

[0105] 1.4. The modified sense amplifier circuit SAC may also have the constituent elements and connections shown in FIG13. FIG13 shows the constituent elements and connections of the sense amplifier circuit of the memory device in the modified example of the first embodiment.

[0106] As shown in Figure 13, the sensing amplifier circuit SAC includes switches SW11 and SW12, capacitors CP1 and CP2, and operational amplifier OP.

[0107] Switch SW11 is connected between wiring FBL and node SAMP. In one example, signal S11 is supplied by the self-readout control circuit RCC.

[0108] Capacitor CP1 is connected between node SAMP and the node receiving ground voltage VSS.

[0109] Switch SW12 is connected between wiring FBL and node EVAL. In one example, signal S12 is supplied by the self-readout control circuit RCC.

[0110] Capacitor CP2 is connected between node EVAL and the node that receives the ground voltage VSS.

[0111] Operational amplifier OP is connected to node SAMP at the inverting input and to node EVAL at the non-inverting input.

[0112] The data readout process is as follows. First, with switch SW11 on, the operation described above (refer to Figure 12) is performed. This causes a potential to appear at node SAMP based on the state of the selected memory cell MC_s. Then, switch SW11 is turned off, thereby storing the potential based on the state of the selected memory cell MC_s at node SAMP. The data judgment by the sense amplifier circuit SAC after time t7, as described above (refer to Figure 12), is not performed.

[0113] Write predetermined fixed reference data to the selected memory cell MC_s. The reference data can be either data "0" or data "1". The following description is based on an example of data "0".

[0114] With switch SW12 on, the operation described above with reference to Figure 12 is performed. This causes a potential in node EVAL based on the state of the selected memory cell MC_s. This potential in the selected memory cell MC_s is based on reference data. Subsequently, switch SW12 is turned off, thereby storing the potential based on the state of the selected memory cell MC_s in node EVAL. The data judgment by the sense amplifier circuit SAC after time t7, as described above with reference to Figure 12, is not performed.

[0115] Operational amplifier OP is enabled, thereby outputting data OUT with values ​​based on the potentials of node SAMP and node EVAL. Data OUT has a value based on the data stored in memory cell MC_s at the start time of data readout. In the case where memory cell MC_s stores data "0" at the start time of data readout, the data stored in memory cell MC_s at the start time of data readout is the same as the written reference data. Data OUT is output with a value reflecting this situation.

[0116] On the other hand, if the memory cell MC_s at the start time of data readout has data "1", the data stored in the memory cell MC_s at the start time of data readout is different from the written reference data. Output data OUT with a value reflecting this situation.

[0117] After outputting the data OUT, the data stored in the selected memory cell MC_s at the start time of data reading will be written to the selected memory cell MC_s.

[0118] According to a modified example, the data of the selected memory cell MC_s is determined by comparing the potential (potential of node SAMP) based on the state of the selected memory cell MC_s with the potential (potential of node EVAL) based on the known data written to the selected memory cell MC_s. Even if the characteristics of the memory cell MC inevitably deviate, the effect of the deviation is suppressed compared to the case where the potential based on the state of the selected memory cell MC_s is compared with a common potential.

[0119] Furthermore, constituent elements with the same function but different locations (e.g., switches GBSW connected to different global bit lines GBL) may inevitably have different characteristics. Even when reading data from multiple memory cells that store the same data, the results of the data readout may differ due to deviations in the characteristics of the constituent elements involved in reading data from memory cell MC. According to a modified example, the data of the selected memory cell MC_s is determined by comparing the potential read from the selected memory cell MC_s with the potential based on known reference data written to the selected memory cell MC_s. Therefore, the constituent elements involved in reading data from the selected memory cell MC_s are the same as the constituent elements involved in reading the written reference data. Thus, the situation where deviations in the readout results of reading the same data from different memory cells MC due to deviations in the characteristics of multiple constituent elements is suppressed.

[0120] 2. Second Embodiment The second embodiment differs from the first embodiment in terms of the data reading operation.

[0121] FIG14 shows the potentials of several signals and wirings during the data readout period of the memory device of the second embodiment along time. FIG14 similarly shows the state of selecting a memory cell MC as the data readout target, just like FIG12 of the first embodiment. When data readout begins in the state of selecting the memory cell MC as the data readout target, the operation during the period shown in FIG14 begins.

[0122] As shown in Figure 14, at time t4, signal SB_s is set to the low level. Therefore, at time t4, the selection bit line BL_s is cut off from the global selection bit line GBL_s. Thus, the signal output operation is performed while both the selection bit line BL_s and the global selection bit line GBL_s are cut off.

[0123] At time t7, signal SB_s is set to a high level. Hereby, the selection bit line BL_s is connected to the selection global bit line GBL_s. Therefore, the sensing operation is performed while the selection bit line BL_s and the selection global bit line GBL_s are connected.

[0124] According to the second embodiment, during the signal output operation, the selection bit line BL_s is disconnected from the global selection bit line GBL_s. Therefore, the parasitic capacitance of the wiring connected to the selection memory cell MC_s (i.e., the selection bit line BL_s) during the signal output operation is smaller than that in the first embodiment. Therefore, the cell current is smaller.

[0125] 3. Third Embodiment The third embodiment is implemented in addition to the first embodiment.

[0126] Figure 15 shows the potentials of several signals and wirings during the data readout period of the memory device of the third embodiment, along the timeline. Figure 15 similarly shows the state of selecting a memory cell MC_s as the target of data readout, just like Figure 12 of the first embodiment. When data readout begins in the state of selecting the memory cell MC_s as the target of data readout, the operation during the period shown in Figure 15 begins.

[0127] As shown in Figure 15, at time t7, signal SB_s is set to low level. This causes the selection bit line BL_s to be cut off from the global selection bit line GBL_s. The cutting off of the selection bit line BL_s from the global selection bit line GBL_s continues until the end of the period shown in Figure 15.

[0128] According to the third embodiment, as described below, data can be read with high accuracy. Even if the switching element SE is off, a small leakage current may still flow through the switching element SE. Therefore, during data readout, after the switching element SE of the selected memory cell MC_s is off (time t5 in FIG. 15), the potential VBL of the selected bit line may drop. This may cause a decrease in data readout accuracy and / or a decrease in data readout margin. According to the third embodiment, after the signal output operation, the selected bit line BL_s is cut off from the selected global bit line GBL_s. Therefore, after the signal output operation, the phenomenon that the charge of the wiring FBL used for data determination is reduced due to leakage through the switching element SE is suppressed. This helps to suppress the decrease in data readout accuracy and / or readout margin. Even if the amount of charge accumulated in the wiring connected to the selected memory cell MC_s due to the signal output operation is small, the decrease in data readout accuracy and / or readout margin can be suppressed.

[0129] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are also included in the scope of the invention described in the claims and their equivalents. [Simplified Explanation of the Diagram]

[0005] Figure 1 shows a functional block of the memory device according to the first embodiment. Figure 2 shows a functional block of the core circuit of the memory device according to the first embodiment. Figure 3 shows the constituent elements and connections of the GWL selector and GBL selector of the memory device according to the first embodiment. Figure 4 shows a functional block of the sub-core circuit of the memory device according to the first embodiment. Figure 5 shows the constituent elements and connections of the WL selector and BL selector of the memory device according to the first embodiment. Figure 6 is a perspective view of a portion of the memory cell array of the memory device according to the first embodiment. Figure 7 shows a cross-sectional view of a structural example of the memory cell of the memory device according to the first embodiment. Figure 8 shows an example of the voltage and current characteristics of the memory cell of the memory device according to the first embodiment. Figure 9 shows the constituent elements and connections of the switching circuit of the memory device according to the first embodiment, as well as related constituent elements. Figure 10 shows the constituent elements and connections of the readout circuit of the memory device according to the first embodiment. Figure 11 shows a layout of a portion of the memory device according to the first embodiment. Figure 12 shows several signals and the potentials of the wiring during the data readout period of the memory device according to the first embodiment. Figure 13 shows the constituent elements and connections of the sensing amplifier circuit of the memory device in a variation of the first embodiment. Figure 14 shows, along time, several signals and wiring potentials during the data readout period of the memory device in the second embodiment. Figure 15 shows, along time, several signals and wiring potentials during the data readout period of the memory device in the third embodiment.

Claims

1. A memory device, comprising: The first memory cell includes a first magnetoresistive element and a first switching element connected to the first magnetoresistive element; A first wiring is connected to a first end of the first memory cell; a second wiring is connected to a second end of the first memory cell; a first switch has a third end and a fourth end connected to the second wiring; a third wiring is connected to the fourth end; a second switch has a fifth end and a sixth end connected to the third wiring; a fourth wiring is connected to the sixth end; a first transistor has a gate connected to the third wiring and a seventh end connected to the fourth wiring; a third switch is connected between the seventh end and a first node receiving a first voltage; and a sensing amplifier circuit is connected to the fourth wiring.

2. The memory device as claimed in claim 1, comprising: The first region includes multiple first source / drain regions of different shapes and sizes and multiple first gate electrodes of different shapes and sizes; The second region is provided with a group of a plurality of second source / drain regions arranged in a first direction in a second direction, and a second gate electrode extending in the second direction is provided in a first direction in a second direction. The sense amplifier circuit includes at least a portion of one of the plurality of first source / drain regions and one of the plurality of first gate electrodes. The first transistor includes at least a portion of one of the plurality of second source / drain regions and the second gate electrode.

3. The memory device as claimed in claim 1, wherein the readout period of reading data from the first memory cell includes a first period during which the first switch and the third switch are maintained on, and the second switch is maintained off.

4. The memory device as claimed in claim 3, comprising: The second memory cell includes a second magnetoresistive element and a second switching element connected to the second magnetoresistive element; The fifth wiring is connected to the eighth terminal of the second memory cell; the sixth wiring is connected to the ninth terminal of the second memory cell; the fourth switch has a tenth terminal and an eleventh terminal connected to the sixth wiring; and the seventh wiring is connected to the eleventh terminal. The fifth switch has a twelfth terminal connected to the seventh wiring and a thirteenth terminal connected to the fourth wiring; the second transistor has a gate connected to the seventh wiring and a fourteenth terminal connected to the fourth wiring. And a sixth switch, connected between the fourteenth terminal and the second node receiving the first voltage, wherein the fourth, fifth and sixth switches are kept off during the readout.

5. The memory device as claimed in claim 4, wherein during a second period prior to the first period, the fourth wiring is electrically floating after a second voltage is applied, during the period during which the fourth wiring is electrically floating, a third voltage lower than the second voltage is applied to the first wiring, and during the first period, a fourth voltage lower than the third voltage is applied to the first wiring.

6. The memory device as claimed in claim 3, wherein the read-out period further includes a third period following the first period, during which the third switch is maintained on and the first switch and the second switch are maintained off.

7. The memory device of claim 6, wherein during a second period prior to the first period, the fourth wiring is electrically floating after a second voltage is applied, during the period during which the fourth wiring is electrically floating, a third voltage lower than the second voltage is applied to the first wiring, and during the first period, a fourth voltage lower than the third voltage is applied to the first wiring.

8. The memory device of claim 1, wherein the readout period of data from the first memory cell includes a first period and a third period following the first period, wherein during the first period, the third switch is maintained on, the first switch and the second switch are maintained off, and during the third period, the first switch is maintained on and the second switch is maintained off.

9. The memory device of claim 8, wherein during a second period prior to the first period, the fourth wiring is electrically floating after a second voltage is applied, during the period during which the fourth wiring is electrically floating, a third voltage lower than the second voltage is applied to the first wiring, and during the first period, a fourth voltage lower than the third voltage is applied to the first wiring.

10. The memory device according to any one of claims 1 to 9, wherein the sense amplifier circuit comprises: a seventh switch connected between the fourth wiring and the eighth wiring; a first capacitor having one end connected to the eighth wiring; an eighth switch connected between the fourth wiring and the ninth wiring; a second capacitor having one end connected to the ninth wiring; and an operational amplifier having a first input connected to the eighth wiring and a second input connected to the ninth wiring.

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