Memory devices and memory systems

Abstract

This invention provides a memory device and a memory system that are highly reliable and capable of high-speed operation. The memory device of one embodiment includes: a plurality of memory cells; word lines; and a controller; the plurality of memory cells are configured to: memorize a plurality of bit data depending on which of a plurality of states containing different threshold voltages, and read out the plurality of bit data with a readout voltage corresponding to each state; the word lines are commonly connected to the plurality of memory cells; the controller can read out the plurality of memory cells and distinguish them into a plurality of first memory cells corresponding to a threshold voltage on the high state side, and at least one second memory cell corresponding to a threshold voltage on the low state side; the controller is configured to: count the number of first memory cells instead of the number of second memory cells, and perform a readout operation targeting the plurality of memory cells using a readout voltage shifted from the readout voltage based on the counting result.

Description

Technical Field

[0001] The embodiments relate to a memory device and a memory system. Prior Technology

[0002] There is a known type of NAND flash memory that can non-volatilely store data. Summary of the Invention

[0003] A memory device and memory system are provided, which are highly reliable and capable of high-speed operation.

[0004] The memory device of the embodiment includes: a plurality of memory cells; word lines; and a controller; the plurality of memory cells are configured to: memorize a plurality of bit data according to which of a plurality of states included in a plurality of states with different threshold voltages, and read out the plurality of bit data with a readout voltage corresponding to each state; the word lines are commonly connected to the plurality of memory cells; the controller can read out the plurality of memory cells and distinguish them into a plurality of first memory cells corresponding to the threshold voltage of the high state side, and at least one second memory cell corresponding to the threshold voltage of the low state side; the controller is configured to: count the number of the first memory cells instead of the number of the second memory cells, and perform a readout operation targeting the plurality of memory cells using a readout voltage shifted from the readout voltage based on the counting result. Simple Explanation of the Diagram

[0005] Figure 1 is a block diagram showing an example of the configuration of the memory system according to the first embodiment. Figure 2 is a block diagram showing an example of the hardware configuration of the memory controller provided in the memory system of the first embodiment. Figure 3 is a block diagram showing an example of the hardware configuration of the memory device in the memory system of the first embodiment. Figure 4 is a diagram showing an example of the circuit configuration of the memory cell array provided in the memory device of the first embodiment. Figure 5 is a diagram showing an example of the circuit configuration of the column decoder module provided in the memory device of the first embodiment. Figure 6 is a diagram showing an example of the circuit configuration of the sense amplifier module and data register included in the memory device of the first embodiment. Figure 7 is a schematic diagram illustrating an example of the threshold voltage distribution and data allocation of the memory cell transistor in the memory device of the first embodiment. Figure 8 is a block diagram showing an example of the configuration of the voltage adjustment unit provided in the memory device of the first embodiment. Figure 9 is a schematic diagram illustrating the general overview of Vth tracing. Figure 10 (A) and (B) are schematic diagrams showing specific examples of settings in Vth tracing. Figure 11 is a flowchart illustrating one example of the on-chip tracking process of the memory device according to the first embodiment. Figure 12 is a schematic diagram illustrating an example of an instruction sequence tracked on a chip in a memory device according to the first embodiment. Figure 13 is a schematic diagram showing an example of the motion waveform tracked on the chip of the memory device according to the first embodiment. Figure 14 is a schematic diagram showing an overview of the counting objects being tracked on the chip of the memory device according to the first embodiment. Figure 15 is a diagram showing an example of the correspondence between count values ​​and shift values ​​in the memory device of the first embodiment. Figure 16 is a specific example of a shift value table used for on-chip tracking in the memory device of the first embodiment. Figure 17 is a specific example of a lookup table used for on-chip tracking in the memory device of the first embodiment. Figure 18 is a schematic diagram showing an example of the motion waveform tracked on the chip of the memory device in the first variation of the first embodiment. Figure 19 is a schematic diagram showing an example of the motion waveform tracked on the chip of the memory device in the second variation of the first embodiment. Figure 20 is a block diagram showing an example of the configuration of the voltage adjustment unit provided in the memory device of the second embodiment. Figure 21 is a flowchart illustrating one example of the on-chip tracking processing flow of the memory device according to the second embodiment. Figure 22 is a schematic diagram showing an example of the motion waveform tracked on the chip of the memory device according to the second embodiment. Figure 23 is a schematic diagram showing an overview of the counting objects being tracked on the chip of the memory device according to the second embodiment. Figure 24 is a flowchart illustrating one example of the on-chip tracking process of the memory device in the third embodiment. Figure 25 is a schematic diagram illustrating an example of an instruction sequence for a read-out operation using the results of on-chip tracking in a memory device according to the third embodiment. Figure 26 is a schematic diagram showing an example of the action waveform in the readout operation of the memory device according to the third embodiment, which utilizes the results of tracking on the chip. Implementation

[0006] Hereinafter, each embodiment will be described with reference to the drawings.

[0007] Each embodiment illustrates an apparatus or method for embodying the technical concept of the invention. The drawings are schematic or conceptual. Descriptive details are appropriately omitted. Components with substantially the same function and structure are labeled with the same symbols. Numbers and other symbols on the reference symbols are used for reference and to distinguish similar elements from each other.

[0008] <1> The first embodiment relates to a memory system (MS) configured to determine an optimal shift value for the readout voltage on a chip based on a predetermined number of memory cells. Details of the memory system MS according to the first embodiment will be described below.

[0009] <1-1> Structure First, the structure of the memory system MS in the first embodiment will be explained.

[0010] <1-1-1> Configuration of Memory System MS Figure 1 is a block diagram showing an example of the configuration of the memory system MS according to the first embodiment. As shown in Figure 1, the memory system MS can be connected to an external host device HD (also called a host). The host device HD is an electronic machine such as a personal computer, a portable information terminal, or a server. The memory system MS is a storage device such as a memory card or an SSD (solid state drive). The memory system MS includes, for example, a memory controller 1 and at least one memory device 2.

[0011] The memory controller 1 is configured as a semiconductor integrated circuit, such as a SoC (System on a Chip), ASIC (Application Specific Integrated Circuit), or FPGA (Field-Programmable Gate Array). The memory controller 1 has the function of managing and controlling the memory device 2. The memory controller 1 is connected to the host device HD via the host bus HB. The memory controller 1 is connected to the memory device 2 via the memory bus MB. The memory controller 1 can control the memory device 2 based on commands received from the host device HD. For example, the memory controller 1 can control the memory device 2 to perform read, write, and erase operations.

[0012] Memory device 2 is, for example, a semiconductor memory device configured to store non-volatile data. Memory device 2 is, for example, a NAND flash memory. In NAND flash memory, the unit of data read and write operations is called a page. Memory device 2 includes a plurality of memory cell transistors MT, a plurality of bit lines BL, and a plurality of word lines WL. For example, each memory cell transistor MT is associated with one bit line BL and one word line WL. Row addresses are allocated to each bit line BL. Page addresses are allocated to each word line WL.

[0013] <1-1-2> Hardware Configuration of Memory Controller 1 Figure 2 is a block diagram showing an example of the hardware configuration of the memory controller 1 provided in the memory system MS of the first embodiment. As shown in Figure 2, the memory controller 1 includes, for example, a host interface circuit (host I / F) 10, a memory interface circuit (memory I / F) 11, a CPU (Central Processing Unit) 12, an ECC (Error Correction Code) circuit 13, a ROM (Read Only Memory) 14, a RAM (Random Access Memory) 15, and a buffer memory 16. The host I / F 10, memory I / F 11, CPU 12, ECC circuit 13, ROM 14, RAM 15, and buffer memory 16 can be connected to an internal bus.

[0014] The host I / F10 controls communication between the host device HD and the memory controller 1 according to the interface specifications. The host I / F10 is connected to the host device HD via the host bus HB. The host I / F10 supports interface specifications such as SATA (Serial Advanced Technology Attachment), SAS (Serial Attached SCSI), PCIe™ (PCI Express), and NVMe™ (Non-Volatile Memory Express™).

[0015] The memory I / F11 controls communication between the memory controller 1 and the memory device 2 according to the interface specifications. The memory I / F11 is connected to the memory device 2 via the memory bus MB. The memory I / F11 supports interface specifications such as Toggle DDR and ONFI (Open NAND Flash Interface).

[0016] CPU 12 is a processor that controls the overall operation of memory controller 1. According to the write request received via host I / F 10, CPU 12 instructs memory device 2 to perform data write operation via memory I / F 11. According to the read request received via host I / F 10, CPU 12 instructs memory device 2 to perform data read operation via memory I / F 11.

[0017] ECC circuit 13 is a circuit that performs ECC processing. ECC processing includes data encoding and decoding. ECC circuit 13 encodes the data to be written to memory device 2 and decodes the data read from memory device 2.

[0018] ROM14 is non-volatile memory. ROM14 stores programs such as firmware. ROM14 is, for example, EEPROM™ (Electrically Erasable Programmable Read-Only Memory). CPU12 performs various processes by executing the firmware stored in ROM14, etc.

[0019] RAM15 is volatile memory. RAM15 is used as the operating area of ​​CPU12. RAM15 is, for example, SRAM (Static Random Access Memory) or DRAM (Dynamic Random Access Memory).

[0020] The buffer memory 16 is, for example, volatile memory. The buffer memory 16 temporarily stores data received via host I / F 10 or data received via memory I / F 11. The buffer memory 16 is, for example, DRAM or SRAM. The buffer memory 16 may also be installed externally to the memory controller 1.

[0021] <1-1-3> Hardware Configuration of Memory Device 2 Figure 3 is a block diagram showing an example of the configuration of the memory device 2 provided in the memory system MS of the first embodiment. As shown in Figure 3, the memory device 2 includes, for example, a memory cell array 20, an input / output circuit 21, a logic controller 22, a temporary register circuit 23, a sequencer 24, a standby / busy controller 25, a driver circuit 26, a column decoder module 27, a data temporary register 28, a sense amplifier module 29, and a voltage adjustment unit 30. Signals transmitted and received via the memory bus MB include, for example, input / output signals I / O0~I / O7, control signals CEn, CLE, ALE, WEn, REn and WPn, and a standby / busy signal RBn.

[0022] The memory cell array 20 is a collection of multiple memory cell transistors (MTs). The memory cell array 20 contains multiple blocks BLK0~BLKn ("n" is an integer greater than or equal to 1). Blocks BLK are used, for example, as units for data erasure operations. Block addresses are assigned to each block BLK. The memory cell array 20 is configured with multiple bit lines BL0~BLm ("m" is an integer greater than or equal to 1) and multiple word lines WL (not shown).

[0023] Input / output circuit 21 controls the transmission and reception of input / output signals I / O0~I / O7. Input / output signals I / O may include, for example, data DAT, status information, address, and instruction. Input / output circuit 21 can input and output data DAT between data register 28 and memory controller 1. Input / output circuit 21 can output status information transmitted from register circuit 23 to memory controller 1. Input / output circuit 21 can output address and instruction transmitted from memory controller 1 to register circuit 23 respectively.

[0024] The logic controller 22 controls the input / output circuit 21 and the sequencer 24 based on various control signals input from the memory controller 1. The logic controller 22 enables the memory device 2 based on the control signal CEn. Based on the control signals CLE and ALE, the logic controller 22 notifies the input / output circuit 21 that the received input / output signals (I / O) of the memory device 2 are instructions and addresses, respectively. Based on the control signal WEn, the logic controller 22 commands the input / output circuit 21 to receive input / output signals (I / O), and based on the control signal REn, commands the input / output circuit 21 to send input / output signals (I / O). Based on the control signal WPn, the logic controller 22 puts the memory device 2 into a protection state.

[0025] The temporary register circuit 23 temporarily stores states, addresses, and instructions. The state represents information about the operational status of the memory device 2. The state is updated based on the control of the sequencer 24 and transmitted to the memory controller 1 via the input / output circuit 21. Addresses may include block addresses, page addresses, row addresses, etc. Instructions include commands related to various operations of the memory device 2.

[0026] The sequencer 24 is a controller that controls the overall operation of the memory device 2. Based on the instructions and addresses stored in the temporary register circuit 23, the sequencer 24 performs read, write, and erase operations. Furthermore, the sequencer 24 can read from a plurality of memory transistors MT and distinguish them into a plurality of memory transistors MT corresponding to a threshold voltage on the high state side and at least one memory transistor MT corresponding to a threshold voltage on the low state side. The sequencer 24 can also perform on-chip tracking, which includes deriving a better shift value for the read voltage and performing a read operation using the derived shift value. Details of on-chip tracking will be described below.

[0027] The standby / busy controller 25 generates a standby / busy signal RBn based on the control of the sequencer 24. The standby / busy signal RBn is a signal that informs the memory controller 1 whether the memory device 2 is in a standby state or a busy state. The standby state is the state in which the memory device 2 can accept commands from the memory controller 1, and is notified by the high-level standby / busy signal RBn. The busy state is the state in which the memory device 2 cannot accept commands from the memory controller 1, and is notified by the low-level standby / busy signal RBn.

[0028] The driver circuit 26 generates voltages that will be used in read, write, and erase operations. The driver circuit 26 supplies the generated voltages to the column decoder module 27 or the sense amplifier module 29.

[0029] The column decoder module 27 is a circuit used to select block BLK or supply voltage to wiring such as word lines WL. The column decoder module 27 includes a plurality of column decoders RD0~RDn. Column decoders RD0~RDn are associated with blocks BLK0~BLKn respectively. Each column decoder RD can set the associated block BLK to be selected or not selected based on the block address.

[0030] Data register 28 is a circuit that temporarily stores data DAT. Data register 28 is used when inputting and outputting data DAT, for example, between input / output circuit 21 and sense amplifier module 29. Furthermore, during on-chip tracking, data register 28 outputs data read from memory cell array 20 to voltage adjustment unit 30. Data register 28 can also be called a data latch, page register, or cache memory.

[0031] The sense amplifier module 29 is a circuit used to supply voltage to each bit line BL or to read data. The sense amplifier module 29 includes a plurality of sense amplifier units SAU0~SAUm. The sense amplifier units SAU0~SAUm are associated with a plurality of bit lines BL0~BLm respectively. Each sense amplifier unit SAU can determine the data to be read from the selected memory cell transistor MT based on the voltage of the bit line BL with which it is associated.

[0032] The voltage adjustment unit 30 has the following function: during on-chip tracking, it determines the optimal shift value of the read voltage based on the instruction of the sequencer 24 and the data DAT transmitted from the data buffer 28. The detailed configuration of the voltage adjustment unit 30 will be described below.

[0033] Furthermore, in memory device 2, the group of memory cell array 20, column decoder module 27, and sense amplifier module 29 can also be referred to as a plane. A plane includes at least memory cell array 20. Memory device 2 may include a plurality of planes. Sequencer 24 may be configured to control each of the plurality of planes.

[0034] The following describes an example of the detailed circuit configuration of the memory cell array 20, the column decoder module 27, the data buffer 28, and the sense amplifier module 29.

[0035] (1: Circuit Configuration of Memory Cell Array 20) Figure 4 shows an example of the circuit configuration of the memory cell array 20 according to the first embodiment. Figure 4 shows one of the plurality of blocks BLK included in the memory cell array 20. As shown in Figure 4, a plurality of bit lines BL0~BLm, a plurality of word lines WL0~WL7, select gate lines SGD0~SGD4, select gate line SGS, and source line SL are provided in the block BLK. The select gate lines SGD0~SGD4 and SGS, and the word lines WL0~WL7 are provided for each block BLK. The bit lines BL0~BLm are shared by the plurality of blocks BLK. The source line SL can be shared by the plurality of blocks BLK, or it can be provided for each block BLK.

[0036] For example, a block BLK contains 5 string units SU0~SU4. Each string unit SU contains multiple NAND strings NS. The multiple NAND strings NS are associated with bit lines BL0~BLm respectively. That is, each bit line BL is shared by the NAND strings NS that are assigned the same row address among the multiple blocks BLK. Each NAND string NS is connected between the bit line BL it is associated with and the source line SL.

[0037] Each NAND string (NS) includes, for example, memory cell transistors MT0 to MT7 and select transistors STD and STS. Each memory cell transistor MT is a memory cell with a control gate and a charge accumulation layer, non-volatilely storing (memorizing) data. The threshold voltage of the memory cell transistor MT can be varied based on the amount of charge injected into the charge accumulation layer, etc. The memory cell transistor MT stores data corresponding to the threshold voltage. The select transistors STD and STS are used to select the string cell (SU).

[0038] In each NAND string NS, the select transistor STD, memory cell transistors MT7~MT0, and select transistor STS are connected in series sequentially. Specifically, the drain of the select transistor STD is connected to the bit line BL with which it is associated. The source of the select transistor STD is connected to the drain of the memory cell transistor MT7. The drain of the select transistor STS is connected to the source of the memory cell transistor MT0. The source of the select transistor STS is connected to the source line SL. The memory cell transistors MT0~MT7 are connected in series between the select transistor STD and STS.

[0039] Select gate lines SGD0~SGD4 are associated with serial units SU0~SU4 respectively. Each select gate line SGD is connected to the gate of each of the multiple select transistors STD contained in the serial unit SU with which it is associated. Select gate line SGS is connected to the gate of each of the multiple select transistors STS contained in the block BLK with which it is associated. Character lines WL0~WL7 are connected to the control gate of each of the multiple memory cell transistors MT0~MT7 contained in the block BLK with which they are associated.

[0040] In this specification, a collection of multiple memory cell transistors (MTs) commonly connected to the word line WL within a single serial unit (SU) is called a cell (CU). In this specification, the collection of 1-bit data stored by each of the multiple memory cell transistors (MTs) within a cell (CU) is called page data. A cell (CU) can store more than two pages of data depending on the number of bits of data stored by each memory cell transistor (MT).

[0041] Furthermore, the memory cell array 20 may also have circuit configurations other than those described above. For example, the number of string cells SU contained in each block BLK, or the number of memory cell transistors MT, select transistors STD, and STS contained in each NAND string NS, can be designed to be arbitrary.

[0042] (2: Circuit Configuration of Column Decoder Module 27) Figure 5 shows an example of the circuit configuration of the column decoder module 27 according to the first embodiment. Figure 5 shows the connection relationship between the driver circuit 26 and the memory cell array 20 and the column decoder module 27, as well as the detailed circuit configuration of one column decoder RD0. Furthermore, the circuit configuration of the column decoders RD other than column decoder RD0 is similar to that of column decoder RD0. As shown in Figure 5, each column decoder RD is connected to the signal lines CG0~CG7, SGDD0~SGDD4, SGSD, USGD, and USGS connected to the driver circuit 26. In addition, each column decoder RD is connected to the word lines WL0~WL7 of the block BLK associated with it, and the select gate lines SGD0~SGD4 and SGS.

[0043] The column decoder RD0 includes, for example, transistors TR0-TR19, transmit gate lines TG and bTG, and block decoder BD. Transistors TR0-TR19 are each N-type high-voltage transistors. The transmit gate line TG is connected to the gate of each of transistors TR0-TR13. The transmit gate line bTG is connected to the gate of each of transistors TR14-TR19. The drains of transistors TR0-TR13 are connected to signal lines SGSD, CG0-CG7, and SGDD0-SGDD4, respectively. The sources of transistors TR0-TR13 are connected to the select gate line SGS, word lines WL0-WL7, and select gate lines SGD0-SGD4 of block BLK0, respectively. The drain and source of transistor TR14 are connected to the signal line USGS and the select gate line SGS of block BLK0, respectively. The drains of transistors TR15-TR19 are connected to the signal line USGD. The sources of transistors TR15 to TR19 are respectively connected to the select gate lines SGD0 to SGD4 of block BLK0.

[0044] The block decoder (BD) is a circuit that decodes block addresses. Based on the decoding result of the block address, the block decoder (BD) applies a voltage of one of the high and low levels to the transmit gate line (TG), and a voltage of the other of the high and low levels to the transmit gate line (bTG). Specifically, for the selected block (BLK), the block decoder (BD) applies a high level voltage to the transmit gate line (TG) and a low level voltage to the transmit gate line (bTG). For the unselected block (BLK), the block decoder (BD) applies a low level voltage to the transmit gate line (TG) and a high level voltage to the transmit gate line (bTG). Therefore, the voltages of signal lines CG0~CG7 are applied to the word lines WL0~WL7 of the selected block BLK, the voltages of signal lines SGDD0~SGDD4 and SGSD are applied to the select gate lines SGD0~SGD4 and SGS of the selected block BLK, and the voltages of signal lines USGD and USGS are applied to the select gate lines SGD and SGS of the unselected block BLK.

[0045] Furthermore, the column decoder module 27 may also have circuit configurations other than those described above. For example, the number of transistors TR included in the column decoder module 27 can be appropriately changed according to the number of wirings in each block BLK. The signal line CG is shared by multiple blocks BLK, and is therefore also called the global character line. The character line WL is set for each block, and is therefore also called the local character line. The signal lines SGDD and SGSD are shared by multiple blocks BLK, and are therefore also called the global transmission gate lines. The select gate lines SGD and SGS are set for each block, and are therefore also called the local transmission gate lines.

[0046] (3: Circuit Configuration of Sensing Amplifier Module 29 and Data Buffer 28) Figure 6 shows an example of the circuit configuration of the sensing amplifier module 29 and data buffer 28 according to the first embodiment. As shown in Figure 6, each sensing amplifier unit SAU includes, for example, a bit line connection section BLHU, a sensing amplifier section SA, buses DBUS and LBUS, latch circuits SDL, ADL, BDL, CDL and DDL, an arithmetic unit OP, and a transistor T0. The data buffer 28 includes a plurality of latch circuits XDL0 to XDLm. The latch circuits XDL0 to XDLm are respectively associated with the sensing amplifier units SAU0 to SAUm. The latch circuits XDL0 to XDLm are respectively connected to the sensing amplifier unit SAU with which they are associated via the bus DBUS.

[0047] The bit line connection section BLHU is, for example, a protection circuit that prevents the high voltage applied to the channel of the NAND string NS during an erase operation from being applied to the sense amplifier section SA. The bit line connection section BLHU can also be configured to apply a specified voltage to an unselected bit line BL.

[0048] The sensing amplifier section SA is a circuit used to determine data based on the voltage of the bit line BL, or to apply voltage to the bit line BL. Each sensing amplifier section SA is connected to the bit line BL with which it is associated via the bit line connection section BLHU. When the control signal STB is activated during readout, the sensing amplifier section SA determines whether the data read from the selected memory cell transistor MT is "0" bit data or "1" bit data based on the voltage of the bit line BL with which it is associated. The control signal STB is generated, for example, by the sequencer 24.

[0049] The latch circuits SDL, ADL, BDL, CDL, and DDL can temporarily hold data. The latch circuits SDL, ADL, BDL, CDL, and DDL, along with the sense amplifier section SA, are configured to transmit and receive data via the bus LBUS.

[0050] The arithmetic logic unit (OP) uses the data stored in the latch circuits SDL, ADL, BDL, CDL, and DDL to perform various logic operations. Furthermore, the sense amplifier unit (SAU) can also contain additional arithmetic circuitry for performing various logic operations, replacing the OP.

[0051] The transistor T0 of each sense amplifier unit (SAU) controls the signal transmission between it and the associated bus DBUS and LBUS. One end of the transistor T0 of each sense amplifier unit (SAU) is connected to the associated bus DBUS. The other end of the transistor T0 of each sense amplifier unit (SAU) is connected to the associated bus LBUS. A control signal DSW is input to the gate of the transistor T0 of each sense amplifier unit. The control signal DSW is generated, for example, by the sequencer 24.

[0052] Each latch circuit XDL can temporarily hold data. Each latch circuit XDL is configured to transmit and receive data with the associated sense amplifier unit SAU via the bus DBUS. Each latch circuit XDL is used for the input and output of data DAT between the sense amplifier module 29 and the input / output circuit 21. Each latch circuit XDL can also be shared by multiple sense amplifier units SAU.

[0053] Furthermore, the sense amplifier module 29 may also have circuit configurations other than those described above. For example, the number of latching circuits in each sense amplifier unit SAU can be appropriately changed. The arithmetic unit OP can also be omitted from the sense amplifier unit SAU.

[0054] <1-1-4> Threshold Voltage Distribution of Memory Cell Crystals (MTs) Figure 7 is a diagram illustrating an example of the threshold voltage distribution and data allocation of memory cell crystals (MTs) in the memory system MS of the first embodiment. The vertical axis "NMTs" represents the number of memory cell crystals (MTs). The horizontal axis "Vth" represents the threshold voltage of the memory cell crystals (MTs). As shown in Figure 7, when each memory cell crystal (MT) stores 4 bits of data (4 bits / cell), for example, the threshold voltage distribution of multiple memory cell crystals (MTs) forms 16 states. Since the data written to each cell (CU) is randomized, the memory cell crystals (MTs) are distributed approximately equally among the 16 states. That is, the multiple memory cell crystals (MTs) can be read out by the sequencer 24 and distinguished into multiple memory cell crystals (MTs) corresponding to the threshold voltage of the high state side and at least one memory cell crystal (MT) corresponding to the threshold voltage of the low state side.

[0055] In this specification, the 16 states are designated as S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, and S15, in ascending order of threshold voltage. Each memory cell transistor (MT) belonging to states S0 through S15 is assigned a distinct 4-bit data. Furthermore, each memory cell MT can also store 2, 3, or more bits of data, and may be assigned data different from what is described below. The operations described below can also be applied to the case where the memory cell MT stores multiple bits of data.

[0056] The following is an example of data allocation for memory cell transistors (MTs) belonging to 16 states. Furthermore, the 4-bit data stored by each memory cell transistor MT is also referred to as the topmost bit data, the uppermost bit data, the middlemost bit data, and the bottommost bit data. Additionally, a page of data composed of the topmost bit data, uppermost bit data, middlemost bit data, and bottommost bit data stored by each of the plurality of memory cell transistors MTs contained in each cell unit (CU) is also referred to as the topmost page data, uppermost page data, middlemost page data, and bottommost page data, respectively.

[0057] S0 State: "1111 (Topmost bit data / Top bit data / Median bit data / Bottom bit data)" S1 State: "0111" S2 State: "0011" S3 State: "1011" S4 State: "1001" S5 State: "1000" S6 State: "1010" S7 State: "0010" S8 State: "0110" S9 State: "0100" S10 State: "0000" S11 State: "0001" S12 State: "0101" S13 State: "1101" S14 State: "1100" S15 State: "1110"

[0058] A readout voltage is set between adjacent states. Specifically, a readout voltage R1 is set between states S0 and S1. A readout voltage R2 is set between states S1 and S2. Similarly, readout voltages R3 to R15 are set between adjacent states. That is, a readout voltage Rj (where "j" is an integer between 1 and 15) is set between states S(j-1) and Sj. Furthermore, the readout voltage VREAD is set to a voltage higher than that of the state with the highest threshold voltage (e.g., state S15).

[0059] A read voltage is applied to the character line WL selected for read operation. The memory cell transistor MT within the cell CU of the selected character line WL, if it has a threshold voltage lower than the applied read voltage, becomes ON. A read pass voltage VREAD is applied to the unselected character line WL. The memory cell transistor MT connected to the character line WL to which the read pass voltage VREAD is applied remains ON regardless of the data stored.

[0060] When applying the data allocation shown in Figure 7, the lower page data is determined by reading out using readout voltages R5, R11, and R14. The middle page data is determined by reading out using readout voltages R4, R6, R9, and R15. The upper page data is determined by reading out using readout voltages R2, R8, R10, and R12. The topmost page data is determined by reading out using readout voltages R1, R3, R7, and R13. During the reading out of page data using multiple readout voltages, appropriate computational processing is performed within the sense amplifier unit (SAU).

[0061] Furthermore, the data allocation shown in Figure 7 is also called 3-4-4-4 encoding because the lower, middle, upper, and topmost page data are determined by reading 3, 4, 4, and 4 times respectively. The topmost bit data and the topmost page can also be referred to as the highest bit and the highest page, respectively.

[0062] <1-1-5> Configuration of Voltage Adjustment Unit 30 Figure 8 is a block diagram showing an example of the configuration of the voltage adjustment unit 30 provided in the memory device 2 of the first embodiment. As shown in Figure 8, the voltage adjustment unit 30 includes, for example, an arithmetic circuit 31, a counter 32, a table selection unit 33, a table holding register 34, and a table number holding register 35.

[0063] The arithmetic circuit 31 is a circuit capable of performing an exclusive OR (XOR) operation on the data received from the data register 28. Specifically, the arithmetic circuit 31 receives the results of the first read operation and the second read operation from the data register 28. Then, the arithmetic circuit 31 performs an XOR operation on the results of the first read operation and the second read operation. At this time, the arithmetic circuit 31 performs an XOR operation on the data determined by the same sense amplifier unit (SAU). Furthermore, the arithmetic circuit 31 has a reduction mechanism capable of performing a reduction process on the data received from the data register 28. The reduction mechanism reduces the amount of data received from the data register 28 by the reduction process. The amount of data reduction performed by the reduction process is designed based on the performance of the counter 32. For example, the reduction mechanism is configured such that, when the counter 32 is an 8-bit counter, the data received from the data register 28 is reduced to 1 / 16 by the reduction process.

[0064] Counter 32 receives the result of the XOR operation from the arithmetic circuit 31. Then, counter 32 counts the number of "1" bits contained in the received XOR result. Afterward, counter 32 outputs the count result to the table selection unit 33.

[0065] The table selection unit 33 uses information from the lookup table 342 to select the index number of the shift value table 341 corresponding to the optimal shift value of the read voltage based on the counting result (count value) received from the counter 32. Then, the table selection unit 33 writes the selected index number to the table number holding register 35. Furthermore, the table selection unit 33 outputs the information in the shift value table 341 corresponding to the selected index number to the sequencer 24. The sequencer 24 can perform a read operation based on the information from the shift value table 341 received from the table selection unit 33.

[0066] The table retainer 34 stores the shift value table 341 and the lookup table 342. The shift value table 341 stores information related to the shift value of the read voltage for each of the plurality of index numbers. The lookup table 342 stores information that associates the index numbers of the shift value table 341 with the counting results of the counter 32. The values ​​for the shift value table 341 and the lookup table 342 are, for example, values ​​read from a specified ROM region of the memory device 2.

[0067] The table number holding register 35 stores the index number of the shift value table 341 selected by the table selection unit 33. The table number holding register 35 can manage the index number for each specified group. For example, the table number holding register 35 can be configured to share the same index number for each block BLK, or it can be configured to share the same index number for each character line WL. The operation when sharing the index number will be explained in the third embodiment.

[0068] Furthermore, the shift value table 341 or lookup table 342 is created, for example, based on data obtained from a pre-performed pressure test, etc. Moreover, the created shift value table 341 and lookup table 342 are set in a designated memory area (ROM area) of the memory cell array 20 before the memory device 2 is shipped. In the voltage adjustment unit 30, the reduction processing performed by the reduction mechanism of the arithmetic circuit 31 can also be performed after the XOR operation. Alternatively, the reduction mechanism can be omitted from the arithmetic circuit 31 of the voltage adjustment unit 30. In this case, the reduction processing is performed by reducing the data transferred from the data register 28 to the arithmetic circuit 31 without using the arithmetic circuit 31. Furthermore, the reduction processing can also be performed during readout. When the reduction processing is performed during readout, the readout time can be shortened as the number of readout data decreases. This is not a limitation; the memory device 2 of the first embodiment only needs to be configured to perform the reduction processing.

[0069] <1-2> Next, the operation of the memory system MS in the first embodiment will be explained.

[0070] <1-2-1> Overview of Vth Tracking First, an overview of Vth tracking is provided. Vth tracking is an operation that searches for the valley position between two adjacent states (hereinafter referred to as adjacent states) and estimates the optimal readout voltage. The optimal readout voltage is the readout voltage value that minimizes the number of faulty bits (failed bits) when performing the readout operation. Vth tracking is also called tracking operation. Figure 9 is a schematic diagram showing the overview of Vth tracking. The vertical axis "NMTs" represents the number of memory cell transistors (MTs). The horizontal axis "Vth" represents the threshold voltage of the memory cell transistors (MTs). Furthermore, Figure 9 shows the area near the valley position of adjacent states and elements related to Vth tracking.

[0071] As shown in Figure 9, in Vth tracking, multiple shift reads are first performed according to a preset readout voltage setting. Each shift read specifies the shift amount of the voltage from the starting read level. The number of shift reads corresponds to the number of samples. In this example, the number of samples is 7. Furthermore, the location where sampling (shift reads) is performed is represented as a sampling point. The shift amount is specified, for example, by a DAC (Digital Analog Converter) value. In the multiple shift reads in Vth tracking, multiple read levels set at equal intervals are used. The interval between adjacent read levels corresponds to the sampling step size, which is equivalent to the voltage width between samples.

[0072] Next, the number of memory cell transistors (MTs) in the ON state at each read level (hereinafter referred to as the ON cell count) is counted, and the difference between the ON cell counts at two adjacent read levels is calculated. Then, a histogram of the ON cell counts is generated, and the point where the curve of the ON cell count difference bulges downwards is extracted, i.e., the point where the difference in the ON cell count becomes minimal (minimum detection). Then, the ratio of the two differences adjacent to the minimum point is calculated, and the voltage difference (potential difference) between the two read levels adjacent to the minimum point is internally divided using the calculated ratio (internal division ratio processing). The voltage obtained thereby is estimated as the optimal readout voltage. This series of Vth tracking processes can, for example, be executed on the chip using the memory device 2 without going through the memory controller 1.

[0073] Furthermore, to enable memory device 2 to perform Vth tracking at high speed, the number of samples is preferably fewer. In Vth tracking, the sampling start point, sampling step size, and number of samples can be adjusted using register settings. The register settings in Vth tracking are determined, for example, using a representative memory device 2, based on the evaluation results obtained from prior pressure application. Figure 10 is a schematic diagram showing a specific example of the settings in Vth tracking. Figures 10 (A) and (B) illustrate the following cases: in the Vth tracking settings, the number of samples is 7, and the sampling step size is different.

[0074] When ensuring a large sampling range with fewer sampling attempts, consider setting a larger sampling step size, as shown in Figure 10(A) (the sampling step size in Figure 10 is large). In this case, the sampling range is more likely to include the valley positions of adjacent states, which can cope with changes in the threshold voltage distribution under various pressures. On the other hand, the accuracy of the internal ratio processing may decrease, resulting in a worse estimation accuracy of the optimal readout voltage.

[0075] In contrast, to maintain better estimation accuracy of the readout voltage, consider setting a smaller sampling step size, as shown in Figure 10(B) (the sampling step size in Figure 10 is small). However, if the sampling step size is smaller, the sampling range will be smaller, thus increasing the likelihood that the sampling range will not include the valley positions of adjacent states. That is, with fewer sampling times and a smaller sampling step size, it may not be able to cope with changes in the threshold voltage distribution under various pressures. In other words, it may not be able to maintain tolerance to various pressures.

[0076] Therefore, in Vth tracking, a certain number of sampling operations are required to balance the estimation accuracy of the readout voltage and the maintenance of pressure tolerance. However, considering the time required to read from the memory cell array 20 to the data buffer 28, there may be upper limits or combinational constraints when setting the sampling step size and the number of sampling operations. For example, it is difficult to make the following adjustment: without changing the sampling range, to correspondingly increase the degree to which the number of sampling operations and the sampling step size become narrower.

[0077] Therefore, it is ideal to balance the estimation accuracy of the optimal readout voltage with the maintenance of pressure tolerance, and to achieve high-speed Vth tracking. Thus, the memory device 2 of the first embodiment performs on-chip tracking that can estimate the optimal readout voltage with fewer samplings.

[0078] <1-2-2> On-chip tracking: In on-chip tracking, the memory device 2 of the first embodiment counts the number of memory cells having a state (e.g., state S15) corresponding to a high state side among a plurality of states, and performs a read operation targeting the plurality of memory cells based on the counting result using a shifted readout voltage. The details of on-chip tracking in the memory device 2 of the first embodiment will be described below.

[0079] (1: On-chip tracing processing flow) Figure 11 is a flowchart illustrating an example of the on-chip tracing processing flow of the memory device 2 in the first embodiment. For example, when the memory device 2 in the first embodiment receives the address of the page to be read and the execution instruction for on-chip tracing from the memory controller 1, it begins a series of processes as shown in Figure 11.

[0080] First, memory device 2 performs an RL1 read (step ST11). The RL1 read is a read operation using a read voltage RL1. The RL1 read corresponds to a single state read of the first read point. The read voltage RL1 is, for example, set to overlap with the highest state (e.g., state S15).

[0081] Subsequently, memory device 2 performs RL2 readout (step ST12). RL2 readout is a readout operation using readout voltage RL2. RL2 readout corresponds to a single state readout of a second readout point, which is different from the first readout point. The readout voltage RL2 is, for example, set to overlap with the highest state (e.g., state S15) and be higher than the readout voltage RL1.

[0082] Subsequently, memory device 2 performs an XOR operation on the results read from RL1 and RL2 (step ST13). In the processing of step ST13, the XOR operation on the results read from RL1 and RL2 is performed for each corresponding sense amplifier unit (SAU).

[0083] Next, memory device 2 uses a reduction mechanism to count the number of "1" bits (the number of "1" bits of data) in the XOR operation result (step ST14). The reduction mechanism adjusts the reduction amount, for example, so that a maximum estimated 255 bits are reached. Then, counter 32 counts the number of "1" bits contained in the reduced XOR operation result. Furthermore, in the processing of step ST14, counter 32 is controlled to prevent overflow. For example, if counter 32 is an 8-bit counter, the count value stops at 255 counts.

[0084] Subsequently, the memory device 2 selects a table number based on the count value and the lookup table 342 (step ST15). That is, the table selection unit 33 uses the lookup table 342 to select the table number (index number) of the shift value table 341 corresponding to the count value in step ST14.

[0085] Subsequently, memory device 2 saves the selected table number in table number holding register 35 (step ST16). Furthermore, in step ST16, if, for example, a table number associated with the same address is already saved in table number holding register 35, the newly selected table number is overwritten.

[0086] Subsequently, memory device 2 performs a read operation using a shift value corresponding to the selected table number (step ST17). That is, sequencer 24 derives a better read voltage to be used based on the shift value corresponding to the selected table number, and performs a read operation using the better read voltage.

[0087] Furthermore, the above description explains the use of shift value table 341 and lookup table 342 to determine the optimal shift value of the readout voltage, but it is not limited to this. The memory device 2 of the first embodiment can also be configured to determine the shift value of the readout voltage by performing calculations using a linear equation with the count value of step ST14 as a variable. Also, the XOR operation can be performed using the operation unit OP of each sense amplifier unit SAU. In this case, the data obtained by applying the XOR operation is transmitted to the data buffer 28, and after reduction processing, it is output to the counter 32.

[0088] (2: Instruction Sequence) Figure 12 is a schematic diagram showing an example of an on-chip trace instruction sequence in the memory device 2 of the first embodiment. In Figure 12, the input / output signals I / O and the standby / busy signal RBn are shown when on-chip trace is executed. Furthermore, before the operation begins, the standby / busy signal RBn is "H" (high level: standby state).

[0089] As shown in Figure 12, firstly, the memory controller 1 sends the instructions "xxh", "yyh", "00h", address "ADD", and "30h" sequentially to the memory device 2. Instruction "xxh" is an instruction that uses on-chip tracking. Instruction "yyh" is an instruction that indicates an action corresponding to a specific page. Instruction "yyh" changes depending on the page being read. Instruction "00h" is an instruction that indicates a read operation. Address "ADD" may contain information such as the block BLK, serial unit SU, and word line WL of the read target. Address "ADD" can be sent in multiple loops. Instruction "30h" is an instruction that instructs the memory device 2 to begin a read operation based on the instructions and addresses held in the temporary register circuit 23.

[0090] If the instruction "30h" is held in the register circuit 23, the sequencer 24 causes the memory device 2 to change from the standby state (RBn="H") to the busy state (RBn="L" (low level: busy state)) and begins on-chip tracing. In Figure 12, the period of on-chip tracing is represented by tR.

[0091] When on-chip tracking is complete, sequencer 24 causes memory device 2 to switch from busy state to standby state. When the read operation is detected to be finished based on the change of standby / busy signal RBn, memory controller 1 causes the read result (data DAT) to be output sequentially to memory device 2, for example by switching control signal REn.

[0092] (3: On-chip tracking waveform) Figure 13 is a schematic diagram showing an example of the on-chip tracking waveform in the memory device 2 of the first embodiment. In Figure 13, the voltage of the selected word line WLsel and the control signal STB are shown. Furthermore, in the initial state before the start of operation, the voltage of the selected word line WLsel is VSS, and the control signal STB is at the low level ("L"). Hereinafter, the case of performing on-chip tracking targeting the following bit pages will be described.

[0093] As shown in Figure 13, the on-chip tracking period in the first embodiment includes three periods, P1, P2, and P3. Period P1 corresponds to the period for performing a readout operation (sampling), which collects information for selecting a better shift value for the readout voltage. Period P2 corresponds to the period for selecting a better shift value for the readout voltage based on the information collected in period P1. Period P3 corresponds to the period for performing a readout operation that utilizes a better readout voltage based on the better shift value of the readout voltage selected in period P2.

[0094] Specifically, during period P1, sequencer 24 applies a readout voltage VREAD (not shown) to the unselected character line WL. Sequencer 24 also applies a readout voltage RL1 to the selected character line WLsel, activating the control signal STB. The readout result is then stored in any latch circuit of each sense amplifier unit SAU (step ST11 in Figure 11). Next, sequencer 24 applies a readout voltage RL2 to the selected character line WLsel, activating the control signal STB. The readout result is then stored in any latch circuit of each sense amplifier unit SAU (step ST12 in Figure 11).

[0095] During period P2, the sequencer 24 controls the voltage adjustment unit 30 to select a better shift value of the read voltage based on the result of the read operation during period P1 (steps ST13~ST16 in Figure 11).

[0096] During period P3, sequencer 24 applies a read pass voltage VREAD (not shown) to the unselected character line WL. Sequentially, sequencer 24 applies preferred read voltages R5sft, R11sft, and R14sft to the selected character line WLsel. During each of the periods when preferred read voltages R5sft, R11sft, and R14sft are applied, the control signal STB is activated. The preferred read voltage R5sft is the read voltage R5 obtained by applying a preferred shift value to the reference value of read voltage R5. The preferred read voltage R11sft is the read voltage R11 obtained by applying a preferred shift value to the reference value of read voltage R11. The preferred read voltage R14sft is the read voltage R14 obtained by applying a preferred shift value to the reference value of read voltage R14. The sequencer 24 determines the next page data based on the read results using the optimal read voltages R5sft, R11sft, and R14sft. The sequencer 24 then stores the determined data in the data buffer 28.

[0097] The actions described above can also be performed when tracing is performed on a chip with other pages selected.

[0098] (4: Summary of Counting Objects) Figure 14 is a schematic diagram showing the summary of the counting objects being tracked on the chip of the memory device 2 in the first embodiment. Figure 14 shows the correspondence between the S14 and S15 states, the readout results of RL1, the readout results of RL2, and the XOR operation results in the threshold voltage distribution of the memory cell transistor MT. As shown in Figure 14, in this example, the readout voltages RL1 and RL2 are set to overlap with the S15 state, which is the highest state.

[0099] During RL1 readout, "1" bits of data are read from memory cell transistors (MTs) whose threshold voltage is below the readout voltage RL1, and "0" bits of data are read from memory cell transistors (MTs) whose threshold voltage is above the readout voltage RL1. During RL2 readout, "1" bits of data are read from memory cell transistors (MTs) whose threshold voltage is below the readout voltage RL2, and "0" bits of data are read from memory cell transistors (MTs) whose threshold voltage is above the readout voltage RL2.

[0100] As a result, the XOR operation result of the readout from RL1 and the readout from RL2 becomes "0" bits in memory transistors MT with a threshold voltage below the readout voltage RL1, "1" bits in memory transistors MT with a threshold voltage above the readout voltage RL1 and below the readout voltage RL2, and "0" bits in memory transistors MT with a threshold voltage above the readout voltage RL2. Therefore, the counting objects in step ST14 of Figure 11 correspond to the number of memory transistors MT with a threshold voltage above the readout voltage RL1 and below the readout voltage RL2 (the number of "1" bits).

[0101] Furthermore, in the first embodiment, the number of memory cell transistors (MTs) used for counting is less than the number corresponding to one page of data. Also, for example, the width of state S15 falls within a range slightly larger than 40DAC. When the reduction mechanism reduces the 16 kilobytes of read data, including parity, to 1 / 16 for output, state S15 contains approximately 500 bits. In contrast, for example, by setting the read voltage RL2 to the voltage value of read voltage RL2 + 8DAC, it is expected that the count value will not exceed 255 bits. By appropriately setting the range of read voltages RL1 and RL2 in this way, better read voltage accuracy and high-speed on-chip tracking can be achieved.

[0102] (5: Correspondence between Count Result and Shift Value) Figure 15 is a graph showing an example of the correspondence between count value and shift value in the memory device 2 of the first embodiment. The vertical axis represents the preferred shift value of the read voltage. The horizontal axis represents the count value in the processing of step ST14 in Figure 11. Figure 15 shows the relationship between count value and shift value under each of the read voltages R4, R6, R9 and R15 used in the read operation of the median page data. The graph shown in Figure 15 is generated by applying pressure to a median page and repeatedly performing the acquisition of the count value of the median page and the search for the preferred shift value.

[0103] In this example, an approximate straight line is obtained between the count value and the shift value for each of the read voltages R4, R6, R9, and R15. The first-order function corresponding to this approximate straight line is not limited to the middle page; it can be obtained similarly for other pages. Thus, the relationship between the count value and the optimal shift value of the read voltage obtained through step S14 is obtained by approximating each read voltage with a first-order function. Therefore, the memory device 2 can derive the optimal shift value for each read voltage based on the count value.

[0104] Furthermore, to simplify the process of deriving the optimal shift value of the readout voltage based on the count value, the memory device 2 of the first embodiment uses a shift value table 341 and a lookup table 342. Specific examples of the shift value table 341 and the lookup table 342 will be described below.

[0105] (6: Specific Example of Shift Value Table 341) Figure 16 is a diagram showing a specific example of the shift value table 341 used for on-chip tracking in the memory device 2 of the first embodiment. Figure 16 shows the correspondence between the table number NTBL corresponding to the index value of the shift value table 341 and the shift value (DAC value) of the read voltage of each page. In this example, the common table number NTBL is shown in the case of using the lower page data, middle page data, upper page data, and topmost page data.

[0106] The shift amounts of the read voltages R5, R11, and R14, which are associated with the read operation of the next page data, are shown below. Table No. NTBL: Shift Amount of Read Voltages R5, R11, R14 1: 0, -4, -7 2: -2, -6, -10 3: -3, -8, -12 4: -4, -10, -15 5: -5, -12, -17 6: -6, -14, -20

[0107] The shift amounts of readout voltages R4, R6, R9, and R15, which are associated with the readout action of the median page data, are shown below. Table No. NTBL: Shift Amount of Readout Voltages R4, R6, R9, and R15 1: -1, -2, -4, -9 2: -2, -3, -5, -12 3: -3, -5, -7, -15 4: -4, -6, -9, -18 5: -5, -7, -11, -21 6: -6, -9, -12, -24

[0108] The shift amount of the read voltages R2, R8, R10, and R12, which are associated with the read operation of the data from the parent page, is shown below. Table No. NTBL: Shift Amount of Read Voltages R2, R8, R10, and R12 1: 0, -3, -5, -6 2: 0, -4, -7, -8 3: 0, -6, -9, -10 4: -1, -8, -11, -13 5: -1, -9, -13, -15 6: -2, -11, -14, -17

[0109] The shift amount of the read voltages R1, R3, R7, and R13, which are associated with the read operation of the top-level page data, is shown below. Table No. NTBL: Shift amount of read voltages R1, R3, R7, and R13 1: -5, 0, -3, -4 2: -5, -1, -4, -7 3: -5, -2, -5, -9 4: -6, -3, -7, -11 5: -6, -4, -8, -14 6: -6, -5, -9, -16

[0110] By using the shift value table 341 as described above, the table selection unit 33 can obtain a better shift value for the read voltage corresponding to the table number NTBL. Furthermore, the shift value table 341 may also represent the shift value of the read voltage as a voltage value instead of a DAC value.

[0111] (7: Specific Example of Lookup Table 342) Figure 17 is a diagram showing a specific example of the lookup table 342 used in on-chip tracking of the memory device 2 in the first embodiment. Figure 17 shows the correspondence between the count value NC of the counter 32 and the table number NTBL of the shift value table 341.

[0112] One of the table numbers NTBL is associated with the size of the count value NC, as shown below. Count value NC size: Table number NTBL NC<28: 0 28≦NC<66: 1 66≦NC<104: 2 104≦NC<142: 3 142≦NC<180: 4 180≦NC<218: 5 218≦NC: 6

[0113] By using the lookup table 342 as described above, the table selection unit 33 can select the table number NTBL corresponding to the count value NC. Furthermore, the range of the count value NC assigned to the table number NTBL can be divided into fewer segments than in the example shown in Figure 17, or it can be divided into more segments than in the example shown in Figure 17. The count value NC used as a reference is appropriately set based on the evaluation results as described using Figure 15.

[0114] <1-3> Effects of the First Embodiment According to the first embodiment, a memory device 2 and a memory system MS with high reliability and high-speed operation can be provided. Hereinafter, the effects of the first embodiment will be explained in detail.

[0115] When reading data from NAND flash memory, the optimal read voltage is set based on prior test results, relative to the conditions at the time of product shipment, for all block BLKs and all word lines WLs. However, using only this read voltage for normal reading is insufficient to handle the stresses of write / erase cycles, data retention, cross temperature, and IR reflow. When these stresses are applied to the NAND flash memory, the number of error bits increases, making error correction difficult using the ECC circuit 13 of the memory controller 1.

[0116] In response, Vth tracking can derive the optimal readout voltage to cope with the aforementioned pressure. Furthermore, the effect of pressure on the readout voltage tends to be greater at higher pressure levels. Moreover, memory device 2 can determine the readout voltage for other states by determining the optimal readout voltage for the high pressure state.

[0117] However, Vth tracking acquires sample data from multiple readout operations and estimates a better shift value for the readout voltage based on the acquired sample data before performing the final data readout operation. Therefore, there are concerns about the impact on sequential or random readout performance when performing Vth tracking. In other words, high-speed operation requires balancing the estimation accuracy of the readout voltage shift value and the maintenance of pressure tolerance with fewer sampling operations.

[0118] Therefore, the memory system MS of the first embodiment can perform on-chip tracking to derive a better readout voltage with fewer sampling times. Specifically, in order to extract the memory cell to be counted, the memory device 2 performs two single-level reads (RL1 readout and RL2 readout). Then, the memory device 2 performs an XOR operation on the result of the two single-level reads, and appropriately reduces the number of "1" bits from the result of the XOR operation to perform counting. Afterwards, the memory device 2 selects a better shift value for the readout voltage corresponding to the counting result from the shift value table 341.

[0119] In this way, the memory device 2 can derive a better read voltage with two sampling times and perform a read operation using the better read voltage. Therefore, the first embodiment can provide a memory device 2 and a memory system MS with high reliability and high-speed operation. Furthermore, the memory device 2 can estimate the read voltage of the low-state side based on the results of on-chip tracking on the high-state side. As a result, the memory device 2 of the first embodiment can shorten the time required to estimate the better read voltage, thereby saving power consumption.

[0120] Furthermore, in the memory device 2 of the first embodiment, the number of bits of the installed counter 32 may be limited in order to suppress hardware costs. Moreover, if the number of bits counted by the counter 32 at one time increases, the tracking speed on the chip may slow down. In contrast, in the memory device 2 of the first embodiment, by performing an XOR operation between the result read from RL1 and the result read from RL2, the number of bits counted by the counter 32 can be reduced.

[0121] Furthermore, by utilizing a reduction mechanism, the memory device 2 of the first embodiment can reduce the number of counting objects, thereby eliminating the limitation on the number of bits of the counter 32. Therefore, the memory device 2 of the first embodiment has high reliability and can operate at high speed, thereby reducing the manufacturing cost of the memory device 2.

[0122] <1-4> Variations of the First Embodiment The memory system MS of the first embodiment can be varied in various ways.

[0123] For example, the RL1 readout in step ST11 and the RL2 readout in step ST12 are performed in the highest state (S15 state in 4 bits / cell) where the voltage transition is greatest under data holding pressure. However, writing to the highest state does not require worrying about writing to a higher state, so there is a possibility of setting ΔVPGM to be larger than other states to perform high-speed writing. ΔVPGM corresponds to the difference in voltage setting value of the write pulse in each program-verify loop during the write operation. Therefore, the threshold voltage width after writing in the highest state is larger than in other states, which may make it unsuitable as the target for RL1 and RL2 readouts. In this case, states lower than the highest state (such as S14 or S13 states) can also be set as the target for RL1 and RL2 readouts.

[0124] Furthermore, steps ST11 and ST12 can also be performed using a readout operation with a readout voltage. Figure 18 is a schematic diagram showing an example of the on-chip tracking operation waveform of the memory device 2 in the first variation of the first embodiment. In Figure 18, the voltage of the selected word line WLsel and the control signal STB are shown. Moreover, in the initial state before the start of operation, the voltage of the selected word line WLsel is VSS, and the control signal STB is at the low level ("L"). Hereinafter, the case of performing on-chip tracking targeting the following bit pages will be described.

[0125] As shown in Figure 18, the on-chip tracking period in the first variation of the first embodiment includes three periods, P1, P2, and P3, just like in the first embodiment. The operation of periods P2 and P3 in the first variation of the first embodiment is the same as in the first embodiment.

[0126] During the first variation of the first embodiment, at period P1, the sequencer 24 applies a readout voltage VREAD (not shown) to the unselected character line WL. Also, the sequencer 24 applies a readout voltage RL3 to the selected character line WLsel. The readout voltage RL3 is, for example, the same voltage as the readout voltage RL2. Furthermore, during the period when the readout voltage RL3 is applied to the selected character line WLsel, the sequencer 24 activates the control signal STB twice at different times. The two readout results are then stored in any latch circuit of each sense amplifier unit SAU. This operation achieves the same result as performing the RL1 readout in step ST11 of FIG11 and the RL2 readout in step ST12.

[0127] For example, when the readout voltage RL3 is applied to the selected word line WLsel, the CR charges, causing the voltage of the selected word line WLsel to rise. Then, the difference in the timing of data acquisition in the sense amplifier unit SAU is converted into the voltage difference between the readout voltages RL1 and RL2. In this way, the memory device 2 in the first variation of the first embodiment can obtain the same readout result as the readout operation during period P1 in the first embodiment by using a readout operation with a readout voltage RL3. Furthermore, this readout operation can also be achieved by activating the control signal STB twice at different times when the discharge time of the sense nodes included in the sense amplifier unit SA is different after the charging of the selected word line WLsel is completed.

[0128] The operations described above can also be performed when on-chip tracking of other pages is selected. Therefore, similar to the first embodiment, the memory device 2 of the first variation of the first embodiment can perform a read operation using a better shift value of the read voltage obtained from on-chip tracking, thereby improving the reliability of the memory device 2. Furthermore, the memory device 2 of the first variation of the first embodiment can shorten the sampling time compared to the first embodiment.

[0129] Furthermore, similar to the first embodiment, the memory device 2 of the first variation of the first embodiment can also use a linear function with count values ​​as variables instead of the lookup table 342 to calculate the shift value of the read voltage. Also, when the memory device 2 of the first embodiment is equipped with the same soft-bit read operation as described above, the read operation described above can be directly implemented using the circuitry used in the soft-bit read operation.

[0130] Furthermore, during the on-chip tracking periods P1 and P3, the order in which the read voltages are applied can start from the higher voltage. Also, the sequencer 24 can maintain the last read voltage applied during period P1 during period P2, and directly switch from that read voltage to a better read voltage during period P3. Figure 19 is a schematic diagram showing an example of the on-chip tracking operation waveform of the memory device 2 in the second variation of the first embodiment. In Figure 19, the voltage of the selected word line WLsel and the control signal STB are shown. Furthermore, in the initial state before the start of operation, the voltage of the selected word line WLsel is VSS, and the control signal STB is at a low level ("L"). Hereinafter, the case of performing on-chip tracking targeting the following bit pages will be described.

[0131] As shown in Figure 19, the on-chip tracking period in the second variation of the first embodiment is the same as that in the first embodiment, including three periods P1, P2, and P3. During period P1, the sequencer 24 sequentially applies readout voltages RL2 and RL1 to the selected character line WLsel. During period P2, the voltage of the selected character line WLsel is maintained at the readout voltage RL1. Then, during period P3, the sequencer 24 changes the voltage of the selected character line WLsel from the readout voltage RL1 to a preferred readout voltage R14sft, and then sequentially applies preferred readout voltages R11sft and R5sft to the selected character line WLsel. In the second variation of the first embodiment, the control signal STB is activated during each period where the readout voltage is applied, just as in the first embodiment, to read out the data.

[0132] The operations described above can also be performed when on-chip tracing of other pages is selected. Therefore, the on-chip tracing of the memory device 2 in the second variation of the first embodiment can achieve the same effect as in the first embodiment. Furthermore, the memory device 2 in the second variation of the first embodiment can shorten the time required for voltage control of the selected word line WLsel compared to the first embodiment, thereby shortening the on-chip tracing time. Moreover, the second variation of the first embodiment can also be combined with the first variation of the first embodiment. That is, during on-chip tracing P1 in the second variation of the first embodiment, a read operation using a read voltage can be performed in the same way as in the first variation of the first embodiment.

[0133] <2> The second embodiment relates to a memory system MS configured to determine an optimal shift value for the readout voltage based on a count of the number of memory cell transistors (MTs) in a threshold region different from that of the first embodiment. The following details the differences between the memory system MS of the second embodiment and the first embodiment.

[0134] <2-1> Figure 20 is a block diagram showing an example of the configuration of the voltage adjustment unit 30A provided in the memory device 2 of the second embodiment. As shown in Figure 20, the voltage adjustment unit 30A includes, for example, a counter 32A, a table selection unit 33, a table holding register 34, and a table number holding register 35. That is, the voltage adjustment unit 30A has the following configuration: compared with the voltage adjustment unit 30 of the first embodiment, the arithmetic circuit 31 is omitted, and the counter 32 is replaced by the counter 32A.

[0135] Counter 32A receives data corresponding to the read result from data register 28. Then, counter 32A counts the number of "0" bits contained in the received data. Afterwards, counter 32A outputs the count result to table selection unit 33. Counter 32A is configured, for example, to count a larger quantity than counter 32 in the first embodiment. Counter 32 is, for example, a 9-bit counter. Furthermore, counter 32A has a reduction mechanism capable of performing a reduction process on the data received from data register 28. The configuration of the reduction mechanism is the same as in the first embodiment.

[0136] Furthermore, in the second embodiment, the shift value table 341 and lookup table 342 stored in the table-holding register 34 respectively store information that establishes a correlation between the count value of the "0" bit data obtained by the counter 32A and the optimal shift value of the read voltage. In the voltage adjustment unit 30A, the reduction mechanism can also be omitted from the counter 32A of the voltage adjustment unit 30A. In this case, the reduction process is performed by reducing the data transferred from the data register 28 to the counter 32A without using the counter 32A. Also, the reduction process can be performed during reading. When the reduction process is performed during reading, the read time can be shortened as the number of read data decreases. It is not limited to this; the memory device 2 of the second embodiment can be configured to perform the reduction process as long as it is capable of doing so. The other configurations of the memory system MS of the second embodiment are the same as those of the memory system MS of the first embodiment.

[0137] <2-2> The following describes the operation of the memory system MS in the second embodiment.

[0138] (1: On-chip tracing processing flow) Figure 21 is a flowchart illustrating an example of the on-chip tracing processing flow of the memory device according to the second embodiment. For example, when the memory device 2 of the second embodiment receives the address of the page to be read and the execution instruction for on-chip tracing from the memory controller 1, it begins a series of processes as shown in Figure 21.

[0139] First, memory device 2 performs RL4 readout (step ST21). RL4 readout is a readout operation using readout voltage RL4. The readout voltage RL4 is set, for example, to overlap with the highest state (e.g., state S15).

[0140] Next, memory device 2 uses a reduction mechanism to count the number of "0" bits (the number of "0" bits) in the result read from RL4 (step ST22). The reduction mechanism adjusts the reduction amount, for example, to a maximum estimated 511 bits. Then, counter 32A is used to count the number of "0" bits contained in the reduced result read from RL4. Furthermore, in the process of step ST22, counter 32A is controlled to prevent overflow. For example, if counter 32A is a 9-bit counter, the count value stops at 511 counts.

[0141] Then, similarly to the first embodiment, the memory device 2 selects a table number based on the count value and the lookup table 342 (step ST15).

[0142] Subsequently, similar to the first embodiment, the memory device 2 saves the selected table number in the table number holding register 35 (step ST16).

[0143] Subsequently, similar to the first embodiment, the memory device 2 performs a read operation using a shift value corresponding to the selected table number (step ST17).

[0144] Furthermore, the above description explains the use of shift value table 341 and lookup table 342 to determine the optimal shift value of the readout voltage, but it is not limited to this. The memory device 2 of the second embodiment may also be configured to determine the shift value of the readout voltage by performing calculations using linear equations with the count value of step ST22 as a variable.

[0145] (2: On-chip tracking waveform) Figure 22 is a schematic diagram showing an example of the on-chip tracking waveform of the memory device 2 according to the second embodiment. In Figure 22, the voltage of the selected word line WLsel and the control signal STB are shown. Furthermore, in the initial state before the start of operation, the voltage of the selected word line WLsel is VSS, and the control signal STB is at the low level ("L"). Hereinafter, the case of performing on-chip tracking targeting the following bit pages will be described.

[0146] As shown in Figure 22, the on-chip tracking period in the second embodiment includes three periods, P1, P2 and P3, just like in the first embodiment.

[0147] During P1 in the second embodiment, the sequencer 24 applies a readout voltage VREAD (not shown) to the unselected character line WL. Also, the sequencer 24 applies a readout voltage RL4 to the selected character line WLsel. The readout voltage RL4 is set, for example, to overlap with the highest-order state (e.g., state S15). Then, during the period when the readout voltage RL4 is applied, the sequencer 24 activates the control signal STB. The readout result is then stored in any of the latch circuits of each sense amplifier unit SAU (step ST21 in FIG. 21).

[0148] During period P2 in the second embodiment, the sequencer 24 controls the voltage adjustment unit 30A to select a better shift value of the readout voltage based on the result of the readout operation during period P1 (steps ST22, ST15, and ST16 in FIG21).

[0149] During P3 of the second embodiment, the sequencer 24 applies a read pass voltage VREAD (not shown) to the unselected character line WL. Furthermore, the sequencer 24 sequentially applies preferred read voltages R5sft, R11sft, and R14sft to the selected character line WLsel, and activates the control signal STB during each of the periods when preferred read voltages R5sft, R11sft, and R14sft are applied. Subsequently, the sequencer 24 determines the next page data based on the read results using each of the preferred read voltages R5sft, R11sft, and R14sft. Afterward, the sequencer 24 stores the determined data in the data buffer 28.

[0150] The operations described above can also be performed when on-chip tracking of other pages is selected. Furthermore, the memory device 2 of the second embodiment can use a linear function with count values ​​as variables instead of the lookup table 342 to calculate the shift value of the read voltage. Furthermore, during the on-chip tracking periods P1 and P3 of the second embodiment, the order in which the read voltage is applied can start from the higher voltage, as described in the second variation of the first embodiment. Also, the sequencer 24 can maintain the read voltage last applied during period P1 during period P2 and directly switch from that read voltage to a better read voltage during period P3. Therefore, the memory device 2 of the second embodiment, like the second variation of the first embodiment, can shorten the on-chip tracking time.

[0151] (3: Summary of Counting Process) Figure 23 is a schematic diagram showing the summary of the counting process during on-chip tracking of the memory device 2 in the second embodiment. Figure 23 shows the correspondence between the S14 and S15 states in the threshold voltage distribution of the memory cell transistor MT and the result of RL4 readout. As shown in Figure 23, in this example, the readout voltage RL4 is set to overlap with the S15 state, which is the highest state.

[0152] During RL4 readout, "1" bits of data are read from memory cell transistors (MTs) whose threshold voltage is below the readout voltage RL4, and "0" bits of data are read from memory cell transistors (MTs) whose threshold voltage is above the readout voltage RL4. Therefore, the number of counting objects in step ST22 of Figure 21 corresponds to the number of memory cell transistors (MTs) whose threshold voltage is above the readout voltage RL4 (the number of "0" bits).

[0153] Furthermore, in the second embodiment, the number of memory cell transistors (MTs) used for counting is less than the number corresponding to one page of data. The threshold voltage width after writing in the highest state is larger than in other states, which may make it unsuitable as an object for RL4 readout. In this case, states lower than the highest state (e.g., S14 or S13 states) can also be set as objects for RL4 readout. Other operations of the memory system MS in the second embodiment are the same as those in the memory system MS in the first embodiment.

[0154] <2-3> As explained above, the memory device 2 of the second embodiment counts the "0" bit data based on the sampling result and derives a better read voltage based on the shift value table 341 and the lookup table 342. Therefore, the memory device 2 of the second embodiment can perform a read operation using the better read voltage. Thus, like the first embodiment, the second embodiment can provide a memory device 2 and a memory system MS that are highly reliable and capable of high-speed operation.

[0155] <3> The third embodiment relates to a memory system MS capable of performing a read operation using the results of on-chip tracking described in the first or second embodiment. Hereinafter, details of the memory system MS in the third embodiment will primarily describe the differences from the first and second embodiments.

[0156] <3-1> The configuration of the memory system MS in the third embodiment is the same as that in the first or second embodiment.

[0157] <3-2> The following describes the operation of the memory system MS in the third embodiment.

[0158] (1: On-chip tracing processing flow) Figure 24 is a flowchart illustrating an example of the on-chip tracing processing flow of the memory device 2 in the third embodiment. For example, when the memory device 2 in the third embodiment receives the address of the page to be read from the memory controller 1 and an execution instruction for a read operation using the result of on-chip tracing, it begins a series of processes as shown in Figure 24.

[0159] First, memory device 2 reads the corresponding table number established for the page to be read from table number holding register 35 (step ST31). The table number read in step ST31 is a table number obtained from other pages in the same character line WL, or a table number obtained from the same block BLK, etc.

[0160] Subsequently, memory device 2 reads the shift value corresponding to the table number read from table number holding register 35 from shift value table 341 (step ST32).

[0161] Subsequently, memory device 2 uses the read shift value to perform a read operation (step ST33). That is, sequencer 24 derives a better read voltage to be used based on the shift value corresponding to the selected table number, and performs the read operation using the better read voltage.

[0162] Furthermore, the above description explains the use of shift value table 341 and lookup table 342 to determine the optimal shift value of the read voltage, but it is not limited to this. The memory device 2 of the third embodiment can also be configured such that, when the table number holding register 35 stores a count value instead of a table number, the shift value of the read voltage is determined by calculation using a linear equation with the count value as a variable. In this case, the table number holding register 35 can also be configured to hold the count value obtained in step ST14 or ST22.

[0163] (2: Instruction Sequence) Figure 25 is a schematic diagram illustrating an example of an instruction sequence for a read operation using the results of on-chip tracking in the memory device 2 of the third embodiment. Figure 25 shows the input / output signals I / O and the standby / busy signal RBn when the read operation using the results of on-chip tracking is executed. Furthermore, before the operation begins, the standby / busy signal RBn is "H" (high level: standby state).

[0164] As shown in Figure 25, firstly, the memory controller 1 sends the instructions "zzh", "yyh", "00h", address "ADD", and "30h" to the memory device 2 in sequence. The instruction "zzh" is an instruction that indicates the results of tracing on the chip.

[0165] If the instruction "30h" is held in the register circuit 23, the sequencer 24 causes the memory device 2 to change from the standby state (RBn="H") to the busy state (RBn="L" (low level: busy state)) and begins the read operation using the results traced on the chip. In Figure 25, the period for performing the read operation using the results traced on the chip is represented by tR.

[0166] When the read operation using the results tracked on the chip is completed, the sequencer 24 causes the memory device 2 to change from a busy state to a standby state. When the read operation is detected to be finished based on the change of the standby / busy signal RBn, the memory controller 1 causes the read results (data DAT) to be output sequentially to the memory device 2, for example by switching the control signal REn.

[0167] (3: Waveform of Readout Operation) Figure 26 is a schematic diagram showing an example of the waveform of the readout operation of the memory device according to the third embodiment, which utilizes the result of on-chip tracing. In Figure 26, the voltage of the selected word line WLsel and the control signal STB are shown. Furthermore, in the initial state before the start of the operation, the voltage of the selected word line WLsel is VSS, and the control signal STB is at the low level ("L"). Hereinafter, the case of performing on-chip tracing targeting the following bit pages will be described.

[0168] As shown in Figure 26, the readout operation using the results traced on the chip only includes period P3. Specifically, during period P3 in the second embodiment, the sequencer 24 obtains the shift value of the readout voltage obtained from the shift value table 341 based on the index number of the shift value table 341 held in the table number holding register 35 (steps ST31 and ST32 in Figure 24). Then, the sequencer 24 sets the preferred readout voltages R5sft, R11sft, and R14sft obtained by applying the shift value of the obtained readout voltage, and performs the readout operation in the same way as during period P3 shown in Figure 13 in the first embodiment (step ST33 in Figure 24).

[0169] The operations described above can also be performed when tracing is performed on a chip with other pages selected. Other operations of the memory system MS in the third embodiment are the same as those in the memory system MS of the first or second embodiment.

[0170] <3-3> Effects of the Third Embodiment The memory device 2 of the third embodiment, based on instructions from the memory controller 1, uses table numbers obtained from associated pages, etc., to derive an optimal read voltage for the page to be read. Therefore, the memory device 2 of the third embodiment can perform a read operation using the optimal read voltage without performing, for example, the processing during periods P1 and P2 shown in FIG13. Thus, the third embodiment, like the first or second embodiment, can provide a memory device 2 and memory system MS with high reliability and high-speed operation.

[0171] <4> In other embodiments of the memory controller 1 described above, an MPU (Micro Processing Unit) may be used instead of the CPU 12. Furthermore, the processes described in the above embodiments may each be executed by dedicated hardware circuitry, a processor executing a program (firmware), or a combination thereof.

[0172] The instruction sequence illustrated in the above embodiments is only one example. The page of the read object can also be represented by the address ADD. Any number can be applied to "xxh", "yyh", and "zzh". The flowchart used for illustration in the above embodiments is only one example. Other processes can also be added to the processes shown in the flowchart. In this specification, "connection" means electrical connection and does not exclude, for example, the presence of other components. "Electrical connection" can also contain insulators, as long as it can operate in the same way as an electrical connection. Character lines WL, select gate lines SGD and SGS, etc., can also be simply referred to as "wiring".

[0173] A high-level voltage is the voltage that turns on an N-type transistor whose gate is at that level. A low-level voltage is the voltage that turns off an N-type transistor whose gate is at that level. In this specification, the application of voltage to the character line WL corresponds to the following situation: the driver circuit 26 applies voltage to the character line WL via the column decoder module 27. The application of voltage to other wirings also corresponds to the situation where the driver circuit 26 applies voltage to the character line WL via the column decoder module 27. The voltage of each wiring can be estimated based on the voltage of the signal lines connecting the driver circuit 26 and the column decoder module 27.

[0174] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments may be implemented in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. These embodiments or variations thereof are included within the scope or spirit of the invention, and are included within the scope of the invention described in the claims and their equivalents.

[0175] 00h,30h,xxh,yyh,zzh: Instructions 1: Memory controller 2: Memory device 10: Host Interface Circuit 11: Memory Interface Circuit 12: CPU 13: ECC circuit 14:ROM 15: RAM 16: Buffer memory 20: Memory Cell Array 21: Input / output circuit 22: Logic Controller 23: Temporary Register Circuit 24: Sequencer 25: Standby / Busy Controller 26: Driver circuit 27: Column Decoder Module 28: Data Temporary Memory 29: Sensing Amplifier Module 30, 30A: Voltage Regulation Section 31: Operational Circuit 32,32A: Counter 33: Table Selection Section 34: Table hold register 35: Table Number Retention Register 341: Shift Value Table 342: Lookup Table ADD: address ADL, BDL, CDL, DDL, SDL, XDL, XDL0~XDLm: Latch circuit ALE, CEn, CLE, DSW, REn, STB, WEn, WPn: Control signals BD: Block Decoder BL, BL0~BLm: Bit lines BLHU: Bit line connector BLK, BLK0~BLKn: Blocks bTG,TG: Transmission gate line CG,CG0~CG7,SGDD,SGDD0~SGDD4,SGSD,USGD,USGS: Signal lines CU: Cell unit DAT: Data DBUS, LBUS: Bus H: High level HB: Host Bus HD: Main unit I / O, I / O0~I / O7: Input / output signals L: Low level MB: Memory Bus MS: Memory System MT, MT0~MT7: Memory Cell Electron NMTs: Number of memory cell transistors NS: NAND string OP: Arithmetic Department P1, P2, P3, tR: Period R1~R15, RL1, RL2, RL3, RL4: Readout voltage R5sft, R11sft, R14sft: Optimal readout voltage RBn: Standby / Busy signal RD, RD0~RDn: Column decoder S0~S15: Status SA: Sensing Amplifier Section SAU, SAU0~SAUm: Sensing amplifier unit SGD, SGD0~SGD4, SGS: Select gate wire SL: Source Line ST11~ST17, ST21, ST22, ST31~ST33: Steps STD, STS: Select Transistor SU, SU0~SU4: Serial units T0, TR, TR0~TR19: Transistors VREAD: Reads the voltage passing through. VSS: Voltage Vth: Threshold voltage of memory cellular transistor WL, WL0~WL7, WLsel: Character lines

Claims

1. A memory device comprising: a plurality of memory cells; word lines; and a controller; wherein the plurality of memory cells are configured to: memorize a plurality of bit data depending on which of a plurality of states containing different threshold voltages, and read out the plurality of bit data with a readout voltage corresponding to each state; the word lines are commonly connected to the plurality of memory cells; the controller is configured to: read out the plurality of memory cells and classify them into a plurality of first memory cells corresponding to a threshold voltage on a high state side, and at least one second memory cell corresponding to a threshold voltage on a low state side; the controller is configured to: count the number of the first memory cells instead of the number of the second memory cells, and perform a readout operation targeting the plurality of memory cells using a readout voltage shifted from the readout voltage based on the counting result.

2. The memory device of claim 1, wherein the plurality of memory cells store a plurality of pages of data, and the number of the first memory cells is less than or equal to the number of one page of data in the plurality of pages of data.

3. The memory device of claim 1, wherein when the controller counts the number of the first memory cells, it excludes a portion of the first memory cells having a first bit value based on a plurality of sampling results.

4. The memory device of claim 3 further includes: a counter for the aforementioned counting; and the controller is further configured to control the counter to not overflow during the aforementioned counting.

5. The memory device of claim 2, wherein the controller is further configured to perform a read operation on the second memory cell using a read voltage shifted from the read voltage based on the counting result.

6. The memory device as requested in item 1, wherein the number of the first memory cells is the result of a mutually exclusive OR operation of the two sampling results.

7. The memory device of claim 6, wherein the first memory cell is included in the highest state among the plurality of states, and the two sampling results are obtained by a readout operation using a readout voltage set to overlap with the highest state.

8. The memory device as claimed in claim 6, wherein the above two sampling results are obtained by reading out using two different readout voltages.

9. The memory device as claimed in claim 6, wherein the above two sampling results are obtained by reading data twice at different times using a readout voltage.

10. The memory device as requested in claim 1, wherein the number of the first memory cells is based on a single sampling result.

11. The memory device of claim 10, wherein the first memory cell is included in the highest state among the plurality of states, and the first sampling result is obtained by a readout operation using a readout voltage set to overlap with the highest state.

12. The memory device of claim 1 further comprises: a first memory circuit configured to store a table that associates the magnitude of the counting result with the shift amount of the readout voltage; and the controller further configured to: determine the shifted readout voltage based on the table.

13. The memory device of claim 1, wherein the controller is further configured to determine the shifted read voltage using the relationship between the magnitude of the counting result and the shift amount of the read voltage.

14. The memory device of claim 1, wherein the controller is further configured to perform: counting the number of the first memory cells based on receiving the first instruction and address; and performing a read operation on the plurality of memory cells using the shifted read voltage based on the count result.

15. The memory device of claim 12 further includes: a second memory circuit configured to store the index number of the table corresponding to the above counting result.

16. The memory device of claim 15, wherein the controller is further configured to: when the second memory circuit stores the index number, use the shifted readout voltage based on the shift value corresponding to the index number to perform a readout operation of a second page of data that is different from the first page of data used to obtain the index number.

17. The memory device of claim 16, wherein the group memory of the plurality of memory cells connected to the aforementioned character lines comprises a plurality of pages of data including the aforementioned page 1 data and the aforementioned page 2 data.

18. The memory device of claim 16, wherein the controller is further configured to: obtain the index number from the second memory circuit based on receiving the second instruction and address, and perform the read operation of the second page of data.

19. A memory system comprising: a memory device as claimed in claim 14; and a memory controller configured to issue the first instruction and send it to the memory device.

20. A memory system comprising: a memory device as claimed in claim 18; and a memory controller configured to issue the second instruction and send it to the memory device.

21. A memory device comprising: a plurality of memory cells; word lines; and a controller; wherein the plurality of memory cells are configured to: memorize a plurality of bit data depending on which of a plurality of states containing different threshold voltages, and read out the plurality of bit data with a readout voltage corresponding to each state; the word lines are commonly connected to the plurality of memory cells; the controller is configured to: read out the plurality of memory cells and classify them into a plurality of first memory cells corresponding to a threshold voltage on a high state side, and at least one second memory cell corresponding to a threshold voltage on a low state side; the controller is configured to: when counting the number of the first memory cells, after counting except for a portion of the first memory cells having a first bit value based on a plurality of sampling results, perform a readout operation targeting the plurality of memory cells using a readout voltage shifted from the readout voltage based on the counting result.

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