Inrush current suppression circuit

Abstract

This invention provides a surge current suppression circuit. The surge current suppression circuit includes a switching element, a charging circuit, a switching control circuit, and a compensation circuit. A first terminal of the switching element is coupled to an input voltage. The control terminal of the switching element is connected to a control node. The charging circuit outputs a charging current to the control node. The switching control circuit sets the control current value based on the output voltage of the second terminal of the switching element and the ramp voltage, and draws the control current from the control node. The compensation circuit sets the compensation current value based on the control voltage and output voltage of the control node, and draws or supplies compensation current to the control node from the ramp voltage.

Description

Technical Field

[0001] This invention relates to surge current, and more particularly to a surge current suppression circuit. Prior Technology

[0002] When a switching element switches slowly, it needs to wait until the voltage at the control terminal of the switching element gradually increases to a level higher than the critical voltage of the switching element before the second terminal of the switching element supplies an output voltage to the load. However, during the gradual increase of the voltage at the control terminal of the switching element, the difference between the divided voltage and the ramp voltage at the output terminal of the switching element becomes too large. At this time, in order to make the divided voltage of the output voltage at the second terminal of the switching element reach the ramp voltage more quickly, the amplifier will regulate the operation of the switching element, causing the switching element to supply a larger current. As a result, the output voltage at the second terminal of the switching element will suddenly jump to ground instead of rising smoothly, and a surge will appear in the output current at the second terminal of the switching element, causing the switching element and the load connected to the second terminal to burn out. Summary of the Invention

[0003] To address the shortcomings of existing technologies, this invention provides a surge current suppression circuit, comprising a switching element, a charging circuit, a switching control circuit, and a compensation circuit. A first terminal of the switching element is coupled to an input voltage. A control terminal of the switching element is connected to a control node. The charging circuit is connected to the control node. The charging circuit is configured to output a charging current to the control node. The switching control circuit connects a second terminal of the switching element and the control terminal, and is coupled to a ramp voltage. The switching control circuit is configured to set a control current value based on the output voltage of the second terminal of the switching element and the ramp voltage, and to draw the control current from the control node. The compensation circuit is connected to the control node, the second terminal of the switching element, and a ramp node between the switching control circuit and the ramp voltage. The compensation circuit is configured to set a compensation current value based on the control voltage of the control node and the output voltage, and to draw the compensation current from the ramp node.

[0004] Furthermore, to address the shortcomings of existing technologies, this invention provides a surge current suppression circuit, comprising a switching element, a charging circuit, a switching control circuit, and a compensation circuit. A first terminal of the switching element is coupled to an input voltage. A control terminal of the switching element is connected to a control node. The charging circuit is connected to the control node. The charging circuit is configured to output a charging current to the control node. The switching control circuit connects a second terminal of the switching element and the control terminal and is coupled to a ramp voltage. The switching control circuit is configured to set a control current value based on the output voltage of the second terminal of the switching element and the ramp voltage, and to draw the control current from the control node. The compensation circuit is connected to the control node and the second terminal of the switching element. The compensation circuit is configured to set a compensation current value based on the control voltage of the control node and the output voltage of the second terminal of the switching element, and to output the compensation current to the control node.

[0005] As described above, the present invention provides a surge current suppression circuit. The surge current suppression circuit of the present invention appropriately draws or supplies compensation current to stably control the operation of the switching circuit, so that the output voltage at the second terminal of the switching element does not suddenly jump to ground but rises smoothly, and no surge occurs in the output current at the second terminal of the switching element, thereby preventing the switching element and the load connected to its second terminal from burning out.

[0006] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Simple Explanation of the Diagram

[0007] Figure 1 is a circuit diagram of the surge current suppression circuit of the first embodiment of the present invention.

[0008] Figure 2 is a circuit diagram of the surge current suppression circuit of the second embodiment of the present invention.

[0009] Figure 3 is a circuit diagram of the surge current suppression circuit of the third embodiment of the present invention.

[0010] Figure 4 is a circuit diagram of the compensation circuit included in the surge current suppression circuit of the fourth embodiment of the present invention.

[0011] Figure 5 is a flowchart of the surge current suppression circuit of the first to sixth embodiments of the present invention.

[0012] Figure 6 shows the signal waveforms of the surge current suppression circuits in the first to fourth embodiments of the present invention.

[0013] Figure 7 shows the waveforms of the surge current suppression circuits of the first to fourth embodiments of the present invention and the conventional surge current suppression circuits.

[0014] Figure 8 is a circuit diagram of the surge current suppression circuit according to the fifth embodiment of the present invention.

[0015] Figure 9 is a circuit diagram of the compensation circuit included in the surge current suppression circuit of the sixth embodiment of the present invention.

[0016] Figure 10 shows the waveforms of the surge current suppression circuits of the fifth and sixth embodiments of the present invention and the conventional surge current suppression circuit. Implementation

[0017] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. Furthermore, the accompanying drawings of the present invention are for simple illustrative purposes only and are not depictions of actual dimensions, as stated in advance. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the scope of protection of the present invention. In addition, the term "or" used herein should be interpreted to include, depending on the actual situation, any combination of any one or more of the associated listed items.

[0018] Please refer to Figures 1, 5 and 6, where Figure 1 is a circuit diagram of the surge current suppression circuit of the first embodiment of the present invention; Figure 5 is a flowchart of the steps of the surge current suppression circuit of the first to sixth embodiments of the present invention; and Figure 6 is a waveform diagram of the signal of the surge current suppression circuit of the first to fourth embodiments of the present invention.

[0019] As shown in Figure 1, in the first embodiment, the surge current suppression circuit of the present invention includes a switching element SW, a charging circuit 100, a switching control circuit 200, and a compensation circuit 300.

[0020] The first terminal (e.g., drain) of the switching element SW is coupled to an input voltage VIN. The second terminal (e.g., source) of the switching element SW serves as an output terminal of the surge current suppression circuit of the present invention and can be connected to a load. The voltage at the second terminal of the switching element SW serves as an output voltage VOUT. The control terminal (e.g., gate) of the switching element SW and the charging circuit 100 are both connected to a control node NT.

[0021] The first terminal U1 (e.g., the inverting input) of the switch control circuit 200 is coupled to a ramp voltage Vramp. The second terminal U2 (e.g., the non-inverting input) of the switch control circuit 200 is connected to the second terminal of the switching element SW. The third terminal of the switch control circuit 200 is connected to a control node NT.

[0022] The charging circuit 100 outputs a charging current Ichg to a control node NT (as shown in step S11 of Figure 5), causing the control terminal of the switching element SW to receive a control current Iswg from the control node NT. At this time, the control current Iswg received by the control terminal of the switching element SW is all or part of the charging current Ichg output by the charging circuit 100.

[0023] As the control current Iswg received by the control terminal of the switching element SW increases, the voltage at the control terminal of the switching element SW increases, which in turn increases the output current ILS at the second terminal of the switching element SW, causing the output voltage VOUT at the second terminal of the switching element SW to increase.

[0024] The switch control circuit 200 obtains an output voltage VOUT from the second terminal of the switch element SW, and determines whether to draw a control current Iamp from a control node NT that is connected to the control terminal of the switch element SW, the charging circuit 100 and the third terminal U3 of the switch control circuit 200, and sets the amount of the control current Iamp drawn from this control node NT.

[0025] For example, the switch control circuit 200 includes an amplifier configured to multiply the voltage difference between an output voltage VOUT at the second terminal of the switch element SW and a ramp voltage Vramp by a gain to generate an amplified voltage difference, based on which the amount of a control current Iamp drawn (or practically supplied) from a control node NT connected to the control terminal of the switch element SW, the charging circuit 100, and the third terminal U3 of the switch control circuit 200 is set.

[0026] It is worth noting that during the slow start-up of the switching element SW, the voltage at the control terminal of SW increases slowly, and the time required for the voltage at the control terminal of SW to increase to the critical voltage of SW for SW to turn on is relatively long. Therefore, the voltage difference between the output voltage VOUT at the second terminal of SW and the ramp voltage Vramp is initially too high. When the voltage difference between the output voltage VOUT at the second terminal of SW and the ramp voltage Vramp is too high, the control terminal of SW will receive a control current Iswg with a large current value from a control node NT to accelerate the turn-on of SW, causing the second terminal of SW to generate an output voltage VOUT with the voltage value required by the load. At this time, the output voltage VOUT at the second terminal of SW will suddenly jump rather than rise smoothly, and even the control current Iswg received by the control terminal of SW and the output current ILS at the second terminal of SW may generate a surge, causing the switching element SW and the load connected to its output terminal to burn out.

[0027] In order to prevent the burning out of the switching element SW and the load connected thereto, as described above, the surge current suppression circuit of the present invention includes, in addition to the switching element SW, the charging circuit 100, and the switching control circuit 200, a compensation circuit 300.

[0028] The first terminal P1 of the compensation circuit 300 is connected to a control node NT. The second terminal P2 of the compensation circuit 300 is connected to the second terminal of the switching element SW. The third terminal P3 of the compensation circuit 300 is connected to a ramp node NR between the first terminal U1 of the switch control circuit 200 and the ramp voltage Vramp.

[0029] The compensation circuit 300 determines whether to extract a compensation current Icmp from a ramp node NR between the control terminal of the switching element SW, the charging circuit 100, and the third terminal U3 of the switching control circuit 200, based on the control voltage VNT of a control node NT connected to the control terminal of the switching element SW, the charging circuit 100, and the third terminal U3 of the switching control circuit 200, and the output voltage VOUT of the second terminal of the switching element SW, and sets the amount of the compensation current Icmp extracted from the ramp node NR.

[0030] For example, when the compensation circuit 300 determines that the voltage difference obtained by subtracting the output voltage VOUT of the second terminal of the switching element SW from the control voltage VNT of the control node NT (which is connected to the control terminal of the switching element SW, the charging circuit 100, and the third terminal U3 of the switching control circuit 200) is not higher than the critical voltage VT of the switching element SW, the compensation circuit 300 activates the protection mechanism (as shown in step S13 of Figure 5). When the compensation circuit 300 activates the protection mechanism, it draws a compensation current Icmp from a ramp node NR between the first terminal U1 of the switching control circuit 200 and the ramp voltage Vramp (as shown in step S14 of Figure 5) to reduce the ramp voltage Vramp at the ramp node NR. As a result, the voltage difference between the ramp voltage Vramp and the output voltage VOUT of the second terminal of the switching element SW decreases, as shown in Figure 6. After the ramp voltage Vramp decreases, it will approach the output voltage VOUT of the second terminal of the switching element SW.

[0031] Furthermore, when the ramp voltage Vramp decreases and approaches the output voltage VOUT of the second terminal of the switching element SW, the switch control circuit 200 will increase the control current Iamp drawn from the control node NT, which is shared by the control terminal of the switching element SW, the charging circuit 100, and the third terminal U3 of the switch control circuit 200, earlier to reduce the voltage at the control terminal of the switching element SW. This effectively prevents surges in the output current ILS and output voltage VOUT of the second terminal of the switching element SW, thus preventing the switching element SW and the load connected to its output terminal from burning out.

[0032] When the compensation circuit 300 determines that the voltage difference obtained by subtracting the output voltage VOUT of the second terminal of the switching element SW from the control voltage VNT of the control terminal of the switching element SW is higher than the critical voltage VT of the compensation transistor TM (as shown in step S13 of Figure 5), the surge current suppression circuit of the present invention stops starting the protection mechanism, that is, the compensation circuit 300 stops drawing a compensation current Icmp from a ramp node NR between the first terminal U1 of the switch control circuit 200 and the ramp voltage Vramp (as shown in step S15 of Figure 5).

[0033] Please refer to Figures 2 and 5, where Figure 2 is a circuit diagram of the surge current suppression circuit of the second embodiment of the present invention; and Figure 5 is a flowchart of the steps of the surge current suppression circuit of the first to sixth embodiments of the present invention.

[0034] The similarities between the second embodiment and the first embodiment of the present invention will not be repeated herein. The difference between the second embodiment and the first embodiment of the present invention is that, as shown in FIG2, the surge current suppression circuit of the second embodiment of the present invention, in addition to including the switching element SW, the charging circuit 100, the switching control circuit 200, and the compensation circuit 300, also includes a ramp voltage generating circuit 400.

[0035] The ramp voltage generating circuit 400 is connected to the first terminal U1 of the switch control circuit 200 to output a ramp voltage Vramp to a ramp node NR. The first terminal U1 of the switch control circuit 200 obtains the ramp voltage Vramp from the ramp node NR.

[0036] For example, as shown in Figure 2, the ramp voltage generating circuit 400 includes a ramp capacitor Css and a ramp current source Ess. The ramp current source Ess is connected to the first terminal of the ramp capacitor Css. The first terminal of the ramp capacitor Css is connected to the first terminal U1 of the switch control circuit 200. The second terminal of the ramp capacitor Css is grounded.

[0037] The ramp current source Ess outputs a ramp current to the ramp capacitor Css to charge the ramp capacitor Css, causing the ramp voltage Vramp at the first terminal of the ramp capacitor Css to gradually increase to a target ramp voltage value (as shown in step S12 of Figure 5). The voltage at the first terminal of the ramp capacitor Css serves as the ramp voltage Vramp input to the first terminal U1 of the switch control circuit 200.

[0038] Please refer to Figure 3, which is a circuit diagram of the surge current suppression circuit of the third embodiment of the present invention.

[0039] The similarities between the third embodiment and the first and second embodiments of the present invention will not be repeated herein. The difference between the third embodiment and the second embodiment is that, in addition to including the switching element SW, the charging circuit 100, the switching control circuit 200, the compensation circuit 300, and the ramp voltage generating circuit 400, the surge current suppression circuit of the third embodiment further includes a voltage divider circuit 500 and an output capacitor Cout.

[0040] The first terminal of the output capacitor Cout is connected to the second terminal of the switching element SW. The second terminal of the output capacitor Cout is grounded.

[0041] The load can be connected to the first terminal of the output capacitor Cout or the second terminal of the switching element SW.

[0042] Voltage divider circuit 500 is connected to the second terminal of switching element SW or the first terminal of output capacitor Cout, and to the second terminal U2 of switch control circuit 200. Voltage divider circuit 500 divides the output voltage VOUT to output a feedback voltage Vdv. In the third embodiment, this feedback voltage Vdv is a divided voltage of the output voltage VOUT. In practice, as in the second embodiment, the feedback voltage Vdv can be the output voltage VOUT.

[0043] The switch control circuit 200 determines whether to extract a compensation current Icmp from a ramp node NR between the control terminal of the switch element SW, the control node NT shared by the charging circuit 100 and the third terminal U3 of the switch control circuit 200, and the feedback voltage Vdv (the voltage difference between them or an amplified voltage difference formed by multiplying it by a gain) and sets the current amount of this compensation current Icmp based on the control voltage VNT of the control node NT shared by the control terminal of the switch element SW, the charging circuit 100 and the third terminal U3 of the switch control circuit 200.

[0044] For example, the voltage divider circuit 500 includes a first voltage divider resistor R1 and a second voltage divider resistor R2. The first terminal of the first voltage divider resistor R1 (serving as an input terminal of the voltage divider circuit 500) is connected to the second terminal of the switching element SW or the first terminal of the output capacitor Cout. The first terminal of the second voltage divider resistor R2 is connected to the second terminal of the first voltage divider resistor R1. A voltage divider node ND between the first terminal of the second voltage divider resistor R2 and the second terminal of the first voltage divider resistor R1 (serving as an output terminal of the voltage divider circuit 500) is connected to the second terminal U2 of the switch control circuit 200. The voltage at the voltage divider node ND between the first terminal of the second voltage divider resistor R2 and the second terminal of the first voltage divider resistor R1 is a divided voltage of the output voltage VOUT of the second terminal of the switching element SW, and is input as a feedback voltage Vdv to the second terminal U2 of the switch control circuit 200.

[0045] Please refer to Figures 4 to 6, where Figure 4 is a circuit diagram of the compensation circuit included in the surge current suppression circuit of the fourth embodiment of the present invention, Figure 5 is a flowchart of the steps of the surge current suppression circuit of the first to sixth embodiments of the present invention, and Figure 6 is a waveform diagram of the signal of the surge current suppression circuit of the first to fourth embodiments of the present invention.

[0046] The compensation circuit 300 shown in Figures 1 to 3 can be the same as the compensation circuit 300 shown in Figure 4. As shown in Figure 4, the compensation circuit 300 includes a compensation transistor TM, a bias current source CSM, a compensation control circuit CTM, and a compensation switch MW.

[0047] The first terminal of the compensation transistor TM is connected to the bias current source CSM. The bias current source CSM supplies a bias current Ibias to the first terminal of the compensation transistor TM.

[0048] The second terminal of the compensation transistor TM is connected to the second terminal of the switching element SW or the first terminal of the output capacitor Cout, so as to receive an output voltage VOUT from the second terminal of the switching element SW or the first terminal of the output capacitor Cout.

[0049] The control terminal of the compensation transistor TM is connected to a control node NT that is shared by the control terminal of the switching element SW, the third terminal U3 of the charging circuit 100 and the switching control circuit 200, so as to receive a control voltage VNT from the control node NT.

[0050] The compensation control circuit CTM outputs a compensation control voltage Vcon based on the voltage at the first terminal of the compensation transistor TM.

[0051] For example, the compensation control circuit CTM may include an inverter NOT1 and a flip-flop FF1 or other logic circuit elements, with the input of the inverter NOT1 (serving as the input of the compensation control circuit CTM) connected to the first terminal of the compensation transistor TM.

[0052] For example, the flip-flop FF1 is an SR flip-flop, or in practice, it can be replaced with other types of flip-flops or other logic circuits. The first input S of the flip-flop FF1 is connected to the output of the inverter NOT1. The second input R of the flip-flop FF1 is coupled to the logic level ENB. The inverted output QB of the flip-flop FF1 is connected to the control terminal of the compensation switch MW.

[0053] As shown in Figure 4, the first terminal of the compensation switch MW serves as the third terminal P3 of the compensation circuit 300, connected to a ramp node NR between the first terminal U1 of the switch control circuit 200 (as shown in Figures 1 to 3) and the ramp voltage Vramp (or the ramp voltage generation circuit 400). The second terminal of the compensation switch MW is grounded. The control terminal of the compensation switch MW receives a compensation control voltage Vcon from the inverting output terminal QB of the flip-flop FF1 (which serves as the output terminal of the compensation control circuit CTM).

[0054] As shown in Figure 6, when the output voltage VOUT at the second terminal of the switching element SW or the first terminal of the output capacitor Cout is still zero or low, the voltage difference between the feedback voltage Vdv (which is the voltage divider of the output voltage VOUT) and the ramp voltage Vramp is relatively large.

[0055] When the voltage difference between the control voltage VNT received at the control terminal of the compensation transistor TM and the output voltage VOUT received at the second terminal of the compensation transistor TM is not higher than a critical voltage VT of the compensation transistor TM (as shown in step S13 of Figure 5), the control terminal of the compensation switch MW receives a high-level compensation control voltage Vcon from the inverting output terminal QB of the flip-flop FF1 and is turned on. At this time, the surge current suppression circuit of the present invention activates the protection mechanism, that is, the compensation circuit 300 draws a compensation current Icmp from a ramp node NR between the first terminal U1 of the switch control circuit 200 and the ramp voltage Vramp (or the ramp voltage generating circuit 400) (as shown in step S14 of Figure 5). In other words, a compensation current Icmp flows from the first terminal U1 of the switch control circuit 200 and the ramp voltage Vramp (or the ramp voltage generating circuit 400) through the compensation circuit 300 to ground, thereby reducing the ramp voltage Vramp of the ramp node NR. As shown in Figure 6, after the high-level compensation control voltage Vcon is output at the inverting output terminal QB of the flip-flop FF1, the voltage value of the ramp voltage Vramp decreases, which reduces the voltage difference between the output voltage VOUT at the second terminal of the switching element SW and the ramp voltage Vramp.

[0056] For example, the compensation current Icmp is equal to the current value obtained by multiplying the output voltage VOUT of the second terminal of the switching element SW or the first terminal of the output capacitor Cout by a preset value, and the voltage difference between the control terminal of the switching element SW, the control voltage VNT of the control node NT connected to the third terminal U3 of the charging circuit 100 and the switching control circuit 200, by a preset value.

[0057] The compensation transistor TM will turn off when the voltage difference between the control voltage VNT received at the control terminal of the compensation transistor TM and the output voltage VOUT received at the second terminal of the compensation transistor TM exceeds a critical voltage VT of the compensation transistor TM. At this time, the surge current suppression circuit of the present invention stops activating the protection mechanism, that is, the compensation circuit 300 stops drawing a compensation current Icmp from a ramp node NR between the first terminal U1 of the switch control circuit 200 and the ramp voltage Vramp (or with the ramp voltage generation circuit 400) (as shown in step S15 of Figure 5).

[0058] Furthermore, when the compensation circuit 300 stops drawing a compensation current Icmp from the ramp node NR, the ramp voltage Vramp of the ramp node NR stops decreasing. At the same time, the ramp current source Ess continuously supplies a ramp current Icss to the ramp capacitor Css, causing the ramp voltage Vramp of the ramp capacitor Css to continuously increase (as shown in step S16 of Figure 5).

[0059] Please refer to Figures 1 to 7, where Figure 7 is a waveform diagram of the surge current suppression circuit of the first to fourth embodiments of the present invention and the conventional surge current suppression circuit.

[0060] As shown in Figure 7, compared to the traditional surge current suppression circuit where the output voltage VOUT jumps to ground, the surge current suppression circuit of the present invention, as shown in Figures 1 to 4, has a smooth output voltage VOUT.

[0061] In a conventional surge current suppression circuit, the feedback voltage Vdv0 of the output voltage VOUT0 takes a period of time to reach the ramp voltage Vramp0. However, in the surge current suppression circuit of the present invention shown in Figures 1 to 4, the ramp voltage Vramp is pulled down, so that the output voltage VOUT reaches the ramp voltage Vramp more quickly.

[0062] Compared to the ramp current Icss0 of the traditional surge current suppression circuit, the surge current suppression circuit of the present invention, as shown in Figures 2 to 4, draws a compensation current Icmp from the ramp node NR to reduce the ramp current Icss received by the ramp capacitor Css from the ramp current source Ess, thereby pulling down the ramp voltage Vramp of the ramp node NR.

[0063] In a traditional surge current suppression circuit, the voltage difference between the feedback voltage Vdv0 of the output voltage VOUT0 and the ramp voltage Vramp0 is relatively high. To ensure that the feedback voltage Vdv0 reaches the ramp voltage Vramp0 quickly, a higher control voltage VNT0 is supplied to the control terminal of the switching element. As a result, a surge is generated in the output current ILS0 at the second terminal of the switching element in the traditional surge current suppression circuit; that is, a large current is instantaneously generated, causing the second terminal of the switching element and its connected load to burn out.

[0064] In contrast, the surge current suppression circuit of this invention pulls down the ramp voltage Vramp, resulting in a lower voltage difference between the output voltage VOUT of the surge current suppression circuit and the ramp voltage Vramp, thus preventing surges in the output current ILS of the switching element SW. Therefore, the surge current suppression circuit of this invention and its connected load will not burn out and can operate normally.

[0065] Please refer to Figures 8 and 10, where Figure 8 is a circuit diagram of the surge current suppression circuit of the fifth embodiment of the present invention, and Figure 10 is a waveform diagram of the surge current suppression circuit of the fifth and sixth embodiments of the present invention and a conventional surge current suppression circuit.

[0066] The similarities between the fifth embodiment and the first to third embodiments of the present invention will not be repeated herein. The differences between the fifth embodiment and the third embodiment of the present invention are explained below.

[0067] As shown in Figure 3, the third terminal U3 of the compensation circuit 300 in the third embodiment of the present invention is connected to a ramp node NR between the first terminal U1 of the switch control circuit 200 and the ramp voltage Vramp or the ramp voltage generating circuit 400, and a compensation current Icmp is drawn from this ramp node NR.

[0068] In contrast, as shown in Figure 8, the third terminal U3 of the compensation circuit 300 in the fifth embodiment of the present invention is connected to a control node NT shared by the control terminal of the switching element SW, the charging circuit 100, and the third terminal U3 of the switch control circuit 200. The compensation circuit 300 determines whether to supply a compensation current Icmp and sets the current value of the compensation current Icmp based on a control voltage VNT of the control node NT shared by the control terminal of the switching element SW, the charging circuit 100, and the third terminal U3 of the switch control circuit 200, and the output voltage VOUT of the second terminal of the switching element SW or the first terminal of the output capacitor Cout. Accordingly, it outputs a compensation current Icmp, as shown in Figures 8 and 10, to the control node NT shared by the control terminal of the switching element SW, the charging circuit 100, and the switch control circuit 200.

[0069] Thus, compared to the control voltage VNT0 and control current Iswg0 of the control terminal of the switching element in the traditional switching current method, the control voltage VNT and control current Iswg obtained from the control node NT by the control terminal of the switching element SW in the fifth embodiment of the present invention are larger. As a result, the feedback voltage Vdv of the output voltage VOUT at the second terminal of the switching element SW rises to the ramp voltage Vramp earlier, causing the switching control circuit 200 to draw a control current Iamp from the control node NT earlier, thereby preventing a surge in the output current ILS at the second terminal of the switching control circuit 200.

[0070] Please refer to Figure 9, which is a circuit diagram of the compensation circuit included in the surge current suppression circuit of the sixth embodiment of the present invention.

[0071] The sixth embodiment of the present invention has a configuration that is largely the same as that of the fourth embodiment, and the similarities will not be repeated herein. The differences between the sixth embodiment and the fourth embodiment of the present invention are explained below.

[0072] As shown in Figure 4, the first terminal of the compensation switch MW of the compensation circuit 300 of the fourth embodiment of the present invention serves as the third terminal P3 of the compensation circuit 300 and is connected to a ramp node NR between the first terminal U1 of the switch control circuit 200 shown in Figure 3 and the ramp voltage Vramp (or the ramp voltage generating circuit 400). The second terminal of the compensation switch MW is grounded. A portion of the current supplied by the ramp current source Ess shown in Figure 3 flows into the compensation circuit 300 as the compensation current Icmp from the ramp node NR, and then flows through the compensation switch MW inside the compensation circuit 300 as shown in Figure 4 to ground. As a result, as shown in Figure 3, only another portion of the current supplied by the ramp current source Ess flows to the ramp capacitor Css as the ramp current Icss. In this way, the voltage of the ramp capacitor Css is reduced, thereby reducing the ramp voltage Vramp of the ramp node NR.

[0073] In contrast, the compensation circuit 300 of the sixth embodiment of the present invention, as shown in FIG. 9, further includes a compensation current source CSW. The compensation current source CSW is connected to the first terminal of the compensation switch MW. The second terminal of the compensation switch MW serves as the third terminal P3 of the compensation circuit 300, and is connected to a control node NT shared by the control terminal of the switching element SW, the charging circuit 100, and the third terminal U3 of the switch control circuit 200, as shown in FIG. 8. A compensation current Icmp supplied by the compensation current source CSW flows through the turned-on compensation switch MW to the control node NT. Thus, the control current Iswg obtained by the control terminal of the switching element SW from the control node NT is larger. As a result, the feedback voltage Vdv of the output voltage VOUT of the second terminal of the switching element SW rises earlier to reach the ramp voltage Vramp, causing the switch control circuit 200 to draw a control current Iamp from the control node NT earlier, thereby preventing a surge in the output current ILS of the second terminal of the switch control circuit 200.

[0074] In summary, this invention provides a surge current suppression circuit. The surge current suppression circuit of this invention appropriately draws or supplies compensation current to stably control the operation of the switching circuit, ensuring that the output voltage at the second terminal of the switching element does not suddenly jump to ground but rises smoothly, and that no surge occurs in the output current at the second terminal of the switching element, thereby preventing the switching element and the load connected to its second terminal from burning out.

[0075] The content disclosed above is only a preferred and feasible embodiment of the present invention, and is not intended to limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the contents of the present invention specification and drawings are included in the scope of the patent application of the present invention.

[0076] 100: Charging circuit NT: Control Node VNT, VNT0: Control voltage Ichg: Charging current Iswg, Iswg0: Control current Iamp: Control current 200: Switch control circuit U1, P1: First end U2, P2: Second end U3, P3: Third end NR: Slope Wave Node Vramp, Vramp0: ramp voltage 300: Compensation Circuit Icmp: Compensation current SW: Switching element ILS, ILS0: Output current VIN: Input voltage VOUT, VOUT0: Output voltage 400: Slope Voltage Generation Circuit Css: Slope capacitor Ess: Oblique current source Icss, Icss0: Slope current Vdv, Vdv0: Feedback voltage 500: Voltage divider circuit R1: First voltage divider resistor R2: Second voltage divider resistor ND: Voltage divider node CSM: Bias Current Source TM: Compensating Transistor CTM: Compensation Control Circuit NOT1: Inverter FF1: Shifter S: First input terminal R: Second input terminal QB: Inverting output terminal ENB: Enable logic level Vcon: Compensation control voltage MW: Compensation switch S11~S16: Steps

Claims

1. A surge current suppression circuit, comprising: a switching element, a first terminal of the switching element coupled to an input voltage, and a control terminal of the switching element connected to a control node; a charging circuit connected to the control node and configured to output a charging current to the control node; a switching control circuit connected to a second terminal of the switching element and the control terminal and coupled to a ramp voltage, configured to set a current value of a control current based on an output voltage of the second terminal of the switching element and the ramp voltage, and to draw the control current from the control node; and a compensation circuit connected to the control node, the second terminal of the switching element, and connected to a ramp node between the switching control circuit and the ramp voltage, configured to set a current value of a compensation current based on a control voltage of the control node and the output voltage, and to draw the compensation current from the ramp node.

2. The surge current suppression circuit as claimed in claim 1 further comprises: a voltage divider circuit connected to a second terminal of the switching element and the switching control circuit, configured to divide the output voltage to output a divided voltage; wherein the switching control circuit is configured to set the current value of the control current based on the control voltage and the divided voltage.

3. The surge current suppression circuit as claimed in claim 2, wherein the voltage divider circuit comprises: a first voltage divider resistor, a first end of which is connected to a second end of the switching element; a second voltage divider resistor, a first end of which is connected to a second end of the first voltage divider resistor, and a voltage divider node between the first end of the second voltage divider resistor and the second end of the first voltage divider resistor is connected to the switching control circuit.

4. The surge current suppression circuit as claimed in claim 1 further comprises: a ramp voltage generating circuit connected to the switch control circuit and configured to output the ramp voltage to the switch control circuit.

5. The surge current suppression circuit as claimed in claim 4, wherein the ramp voltage generating circuit comprises: a ramp capacitor, a first terminal of which is connected to the switch control circuit, and a second terminal of which is grounded; and a ramp current source connected to the first terminal of the ramp capacitor and configured to output a ramp current to the ramp capacitor; and wherein the switch control circuit is configured to receive the voltage at the first terminal of the ramp capacitor as the ramp voltage.

6. The surge current suppression circuit as claimed in claim 1 further comprises: an output capacitor, a first terminal of which is connected to a second terminal of the switching element, and the second terminal of which is grounded.

7. The surge current suppression circuit as claimed in claim 1, wherein the compensation circuit comprises: a bias current source configured to output a bias current; a compensation transistor, a first terminal of which is connected to the bias current source, a control terminal of which is connected to the control node, and a second terminal of which is connected to a second terminal of the switching element; a compensation control circuit connected to the first terminal of the compensation transistor and configured to output a compensation control voltage based on the voltage at the first terminal of the compensation transistor; and a compensation switch, a first terminal of which is connected to the ramp node, a second terminal of which is grounded, and a control terminal of which is connected to the compensation control circuit.

8. The surge current suppression circuit as claimed in claim 7, wherein the compensation control circuit comprises: an inverter, the input of which is connected to a first terminal of the compensation transistor; and a flip-flop, a first input of which is connected to the output of the inverter, a second input of which is coupled to a power logic level, and an inverted output of which is connected to the control terminal of the compensation switch.

9. A surge current suppression circuit, comprising: a switching element, a first terminal of the switching element coupled to an input voltage, and a control terminal of the switching element connected to a control node; a charging circuit connected to the control node and configured to output a charging current to the control node; a switching control circuit connected to a second terminal of the switching element and the control terminal and coupled to a ramp voltage, configured to set a control current value based on an output voltage of the second terminal of the switching element and the ramp voltage, and to draw the control current from the control node; and a compensation circuit connected to the control node and the second terminal of the switching element, configured to set a compensation current value based on a control voltage of the control node and the output voltage of the second terminal of the switching element, and to output the compensation current to the control node.

10. The surge current suppression circuit of claim 9 further comprises: a voltage divider circuit connected to a second terminal of the switching element and the switching control circuit, configured to divide the output voltage to output a divided voltage; wherein the switching control circuit is configured to set the current value of the control current based on the control voltage and the divided voltage.

11. The surge current suppression circuit of claim 10, wherein the voltage divider circuit comprises: a first voltage divider resistor, a first end of the first voltage divider resistor being connected to a second end of the switching element; a second voltage divider resistor, a first end of the second voltage divider resistor being connected to a second end of the first voltage divider resistor, and a voltage divider node between the first end of the second voltage divider resistor and the second end of the first voltage divider resistor being connected to the switching control circuit.

12. The surge current suppression circuit as claimed in claim 9 further comprises: a ramp voltage generating circuit connected to the switch control circuit and configured to output the ramp voltage to the switch control circuit.

13. The surge current suppression circuit of claim 12, wherein the ramp voltage generating circuit comprises: a ramp capacitor, a first terminal of which is connected to the switch control circuit, and a second terminal of which is grounded; and a ramp current source connected to the first terminal of the ramp capacitor and configured to output a ramp current to the ramp capacitor; and wherein the switch control circuit is configured to receive the voltage at the first terminal of the ramp capacitor as the ramp voltage.

14. The surge current suppression circuit as claimed in claim 9 further comprises: an output capacitor, a first terminal of which is connected to a second terminal of the switching element, and the second terminal of which is grounded.

15. The surge current suppression circuit of claim 9, wherein the compensation circuit comprises: a compensation transistor, a control terminal of which is connected to the control node, and a second terminal of which is connected to a second terminal of the switching element; a bias current source connected to a first terminal of the compensation transistor and configured to output a bias current to the first terminal of the compensation transistor; a compensation control circuit connected to the first terminal of the compensation transistor and configured to output a compensation control voltage based on the voltage at the first terminal of the compensation transistor; a compensation current source configured to output the compensation current; and a compensation switch, a first terminal of which is connected to the compensation current source, a second terminal of which is connected to the control node, and a control terminal of which is connected to the compensation control circuit.

16. The surge current suppression circuit of claim 15, wherein the compensation control circuit comprises: an inverter, the input of which is connected to a first terminal of the compensation transistor; and a flip-flop, a first input of which is connected to the output of the inverter, a second input of which is coupled to a power logic level, and an inverted output of which is connected to a control terminal of the compensation switch.

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