Semiconductor device structure and methods of forming the same

Abstract

The embodiments disclosed herein provide a semiconductor device structure and a method for forming the same. The structure includes: a gate electrode layer disposed above a substrate; a source / drain region disposed above the substrate; conductive contacts disposed above the source / drain regions; and a first etch-stop layer disposed on the conductive contacts and the gate electrode layer, wherein the first etch-stop layer comprises SiCN or SiOCN. The structure further includes: a first dielectric layer disposed on the first etch-stop layer; and a first conductive feature disposed in the first dielectric layer and the first etch-stop layer, wherein the first conductive feature is electrically connected to the conductive contacts. The structure further includes: a second conductive feature disposed in the first dielectric layer and the first etch-stop layer, wherein the second conductive feature is electrically connected to the gate electrode layer.

Description

[Technical Field]

[0001] None [Previous Technology]

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in generations of ICs, each generation featuring smaller and more complex circuits than the previous one. In IC development, functional density (i.e., the number of interconnects per wafer area) typically increases, while geometry (i.e., the smallest component (or line) that can be produced using the manufacturing process) decreases. This scaling down process typically yields benefits by increasing production efficiency and reducing associated costs. This scaling down also increases the complexity of handling and manufacturing ICs.

[0003] Therefore, it is necessary to improve the processing and manufacturing of ICs. [Summary of the Invention]

[0004] None

Implementation Method

[0006] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided object. Specific examples of elements and arrangements described below are used to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0007] Furthermore, for ease of description, spatial relative terms such as "below," "under," "below," "above," and "above" may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of elements in use or operation. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0008] While embodiments of this disclosure discuss nanostructured channel FETs, such as gate all-around (GAA) FETs, such as horizontal gate all-around (HGAA) FETs or vertical gate all-around (VGAA) FETs, certain implementations of this disclosure can be used with other processes and / or other devices, such as planar FETs, fin FETs, and other suitable devices. Other modifications that may be considered within the scope of this disclosure will be readily apparent to those skilled in the art. In the case of a gate all-around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, one or more lithography processes can be used to pattern these structures, including dual-patterning processes or multi-patterning processes. Typically, dual-patterning or multi-patterning processes combine lithography and self-alignment processes to allow the creation of patterns, for example, patterns with a pitch smaller than that obtained using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a lithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can be used to pattern a GAA structure.

[0009] Figures 1 through 13D illustrate exemplary processes for manufacturing a semiconductor device structure 100 according to embodiments of the present disclosure. It will be understood that additional operations may be provided before, during, and after the processes shown in Figures 1 through 13D, and some operations described below may be substituted or eliminated for additional embodiments of the method. The order of operations / processes is not limited and is interchangeable.

[0010] Figures 1 through 6 are perspective views of various stages of manufacturing a semiconductor device structure 100 according to some embodiments. As shown in Figure 1, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed on the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), aluminum indium arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate, wherein an insulating layer (not shown) is disposed between two silicon layers for reinforcement. In one aspect, the insulating layer is an oxygen-containing layer.

[0011] The substrate 101 may include various regions that are doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopants may be, for example, phosphorus for an n-type field effect transistor (NFET) and boron for a p-type field effect transistor (PFET).

[0012] The semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructure channels, such as nanostructure channel FETs, in multi-gate devices. In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layer 106 and second semiconductor layer 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, and the second semiconductor layer 108 may be made of SiGe. In some instances, the first semiconductor layer 106 may be made of SiGe, and the second semiconductor layer 108 may be made of Si. Alternatively, in some embodiments, either of the first and second semiconductor layers 106, 108 may be or include other materials such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0013] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process (such as epitaxy). For example, the epitaxial growth of the semiconductor layer stack 104 can be performed by a molecular beam epitaxy (MBE) process, a metal-organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0014] The first semiconductor layer 106 or a portion thereof may form nanostructure channels of the semiconductor device structure 100 in subsequent manufacturing stages. The term nanostructure is used herein to designate any material portion having nanometer- or even micrometer-scale dimensions and an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term refers to elongated material portions with circular and substantially circular cross-sections, and beam-shaped or strip-shaped material portions, including, for example, cylindrical or substantially rectangular cross-sections. The nanostructure channels of the semiconductor device structure 100 may be surrounded by gate electrodes. The semiconductor device structure 100 may include nanostructure transistors. Nanostructure transistors may be referred to as nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having gate electrodes around the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0015] Each first semiconductor layer 106 may have a thickness ranging from about 5 nm to about 30 nm. The thickness of each second semiconductor layer 108 may be equal to, less than or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 may have a thickness ranging from about 2 nm to about 50 nm. As illustrated in Figure 1, three first semiconductor layers 106 and three second semiconductor layers 108 are arranged alternately, which is for illustrative purposes only and is not intended to limit the specific content described in the claims. It is understood that any number of first semiconductor layers 106 and any number of second semiconductor layers 108 may be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels of the semiconductor device structure 100.

[0016] In Figure 2, the fin structure 112 is formed from a semiconductor layer stack 104. Each fin structure 112 has an upper portion including first and second semiconductor layers 106, 108 and a substrate portion 116 formed from a substrate 101. The fin structure 112 can be formed by patterning a hard mask layer (not shown) formed on the semiconductor layer stack 104 using multiple patterning operations including lithography and etching processes. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The lithography process may include the following steps: forming a photoresist layer (not shown) on the hard mask layer; exposing the photoresist layer to the pattern; performing a post-exposure baking process; and developing the photoresist layer to form a mask element including the photoresist layer. In some embodiments, an electron beam lithography process may be used to pattern the photoresist layer to form a mask element. The etching process forms trenches 114 in unprotected areas, through a hard mask layer, through the semiconductor layer stack 104, and into the substrate 101, thereby leaving a plurality of extended fin structures 112. The trenches 114 extend in the X direction. Dry etching (e.g., RIE), wet etching, and / or combinations thereof can be used to etch the trenches 114.

[0017] In Figure 3, after the fin structure 112 is formed, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Then, a planarization operation, such as chemical mechanical polishing (CMP) and / or etching back, is performed to expose the top of the fin structure 112. The insulating material 118 may be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), low-k dielectric material, or any suitable dielectric material. The insulating material 118 may be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD).

[0018] In Figure 4, insulating material 118 is recessed to form isolation region 120. The recessed insulating material 118 exposes a portion of the fin structure 112, such as the semiconductor layer stack 104. The recessed insulating material 118 exposes trenches 114 between adjacent fin structures 112. Isolation region 120 can be formed using a suitable process, such as a dry etching process, a wet etching process, or a combination thereof. The top surface of insulating material 118 may be flush with or below the surface of the second semiconductor layer 108, which contacts the substrate portion 116 formed by substrate 101.

[0019] In Figure 5, one or more sacrificial gate structures 130 (only one is shown) are formed on the semiconductor device structure 100. The sacrificial gate structure 130 is formed on a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a masking layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the masking layer 136 may be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the masking layer 136, and then patterning these layers into the sacrificial gate structure 130. Then, spacers 138 are formed on the sidewalls of the sacrificial gate structure 130. For example, the spacers 138 may be formed by conformally depositing one or more layers of spacers 138 and anisotropically etching the one or more layers. In some embodiments, the spacers 138 are also formed on the sidewalls of the exposed portion of the fin structure 112. In some embodiments, while one sacrificial gate structure 130 is presented, two or more sacrificial gate structures 130 may be arranged along the X direction. In some embodiments, the contact polyp (CPP), i.e., the minimum center-to-center distance between adjacent sacrificial gate electrode layers 134, ranges from about 35 nm to about 100 nm.

[0020] The sacrificial gate dielectric layer 132 may include one or more dielectric material layers, such as silicon oxide-based materials. The sacrificial gate electrode layer 134 may include silicon, such as polycrystalline silicon or amorphous silicon. The masking layer 136 may include multiple layers, such as oxide layers and nitride layers. The spacer 138 may be made of dielectric materials, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon carbide, SiOCN and / or combinations thereof.

[0021] A portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 is used as a channel region of the semiconductor element structure 100.

[0022] In Figure 6, the portion of the fin structure 112 not covered by the sacrificial gate structure 130 and spacer 138 is recessed above, below, or on the top surface of the isolation region 120. The partial recess of the fin structure 112 can be achieved by an etching process, an isotropic or anisotropic etching process, and the etching process can be selective relative to one or more crystalline planes of the substrate 101. The etching process can be dry etching, such as RIE, NBE, etc., or wet etching, such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant.

[0023] Figures 7A, 7B and 7C are cross-sectional side views of the semiconductor device structure 100 taken along lines AA, BB and CC of Figure 6, respectively.

[0024] Figures 8A, 8B, and 8C are cross-sectional side views taken along lines AA, BB, and CC of Figure 6, respectively, according to some embodiments, of one of the various manufacturing stages of the semiconductor device structure 100. As shown in Figure 8A, the edge portions of each second semiconductor layer 108 of the semiconductor layer stack 104 are removed horizontally in the X direction. The removal of the edge portions of the second semiconductor layer 108 forms cavities. In some embodiments, portions of the second semiconductor layer 108 are removed by a selective wet etching process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 can be selectively etched using a wet etchant, such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution.

[0025] After removing the edge portions of each of the second semiconductor layers 108, a dielectric layer is deposited in the cavity to form a dielectric spacer 144. The dielectric spacer 144 may be made of a low-k dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. The dielectric spacer 144 may be formed by first forming a conformal dielectric layer, such as ALD, using a conformal deposition process, and then anisotropically etching to remove portions of the conformal dielectric layer other than the dielectric spacer 144. During the anisotropic etching process, the dielectric spacer 144 is protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 covers the spacers 144 along the X direction.

[0026] Figures 9A, 9B, and 9C are cross-sectional side views taken along lines AA, BB, and CC of Figure 6, respectively, according to some embodiments, of one of the various manufacturing stages of a semiconductor device structure 100. As shown in Figures 9A and 9C, a source / drain (S / D) region 146 is formed from a substrate portion 116. The S / D region 146 may be grown vertically and horizontally to form facets that may correspond to crystal planes of the material used for the substrate portion 116. In this disclosure, the source region and drain region are used interchangeably and have substantially the same structure. Furthermore, the source / drain region may refer to the source / drain individually or collectively, depending on the context. The S / D region 146 may consist of one or more layers of Si, SiP, SiC, and SiCP for an n-channel FET or one or more layers of Si, SiGe, and Ge for a p-channel FET. For a p-channel FET, a p-type dopant, such as boron (B), may also be included in the S / D region 146. The S / D region 146 can be formed by epitaxial growth methods using CVD, ALD, or MBE.

[0027] Figures 10A, 10B, and 10C are cross-sectional side views taken along lines AA, BB, and CC of Figure 6, respectively, according to some embodiments, of one of the various stages of manufacturing the semiconductor device structure 100. In Figures 10A, 10B, and 10C, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. The CESL 162 covers the sidewalls of the sacrificial gate structure 130, the insulating material 118, and the S / D region 146. The CESL 162 may include a nitrogen-containing material, such as silicon nitride, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Subsequently, an interlayer dielectric (ILD) layer 164 is formed on the CESL 162 above the semiconductor device structure 100. The material of the interlayer dielectric layer 164 may include compounds (including Si, O, C and / or H), such as silicon oxide, SiCOH, or SiOC. Organic materials (such as polymers) may also be used for the interlayer dielectric layer 164. The interlayer dielectric layer 164 may be deposited by a PECVD process or other suitable deposition techniques. In some embodiments, the k-value of the interlayer dielectric layer 164 is less than 4, such as about 2.5 to about 3.5. In some embodiments, after forming the interlayer dielectric layer 164, the semiconductor device structure 100 may undergo a heat treatment to anneal the interlayer dielectric layer 164.

[0028] After forming the interlayer dielectric layer 164, a planarization operation, such as CMP, is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed, as shown in Figures 10A and 10B.

[0029] Figures 11A, 11B, and 11C are cross-sectional side views taken along lines AA, BB, and CC of Figure 6, respectively, according to some embodiments, of one of the various manufacturing stages of the semiconductor device structure 100. As shown in Figures 11A and 11B, the sacrificial gate structure 130 and the second semiconductor layer 108 are removed. Removing the sacrificial gate structure 130 and the second semiconductor layer 108 forms openings between spacers 138 and between the first semiconductor layer 106. An interlayer dielectric layer 164 protects the S / D region 146 during the removal process. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. The sacrificial gate layer 134 can be removed first by any suitable method, such as dry etching, wet etching, or a combination thereof, and then the sacrificial gate dielectric layer 132 can be removed by any suitable method, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant, such as a tetramethylammonium hydroxide (TMAH) solution, may be used to selectively remove the sacrificial gate electrode layer 134, but without removing the spacer 138, the interlayer dielectric layer 164, and the contact etch termination layer 162.

[0030] A selective wet etching process can be used to remove the second semiconductor layer 108. When the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of Si, the chemical composition used in the selective wet etching process removes SiGe without substantially affecting the Si, the dielectric material of the spacer 138, and the dielectric spacer 144. In one embodiment, the second semiconductor layer 108 can be etched using a wet etchant, such as, but not limited to, hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), phosphoric acid (H3PO4), a dry etchant, such as a fluorine-based (e.g., F2) or chlorine-based gas (e.g., Cl2), or any suitable isotropic etchant.

[0031] After the nanostructure channel (i.e., the exposed portion of the first semiconductor layer 106) is formed, a gate dielectric layer 170 is formed to surround the exposed portion of the first semiconductor layer 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 may be collectively referred to as the gate structure 174. In some embodiments, an interfacial layer (IL) (not shown) is formed between the gate dielectric layer 170 and the exposed surface of the first semiconductor layer 106. In some embodiments, the gate dielectric layer 170 includes one or more layers of dielectric material, such as silicon oxide, silicon nitride, high-k dielectric material, other suitable dielectric material, and / or combinations thereof. Examples of high-k dielectric materials include HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 170 can be formed by CVD, ALD, or any suitable deposition technique. The gate electrode layer 172 may comprise one or more layers of conductive materials, such as polycrystalline silicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicon, cobalt silicon, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or any combination thereof. The gate electrode layer 172 can be formed by CVD, ALD, electroplating, or other suitable deposition techniques. The gate electrode layer 172 may also be deposited on the upper surface of the interlayer dielectric layer 164. Then, the gate dielectric layer 170 and gate electrode layer 172 formed on the interlayer dielectric layer 164 are removed by means of, for example, CMP, until the top surface of the interlayer dielectric layer 164 is exposed.

[0032] Figures 12A, 12B, and 12C are cross-sectional side views taken along lines AA, BB, and CC of Figure 6, respectively, according to some embodiments, of one of the various stages of manufacturing the semiconductor device structure 100. As shown in Figures 12B and 12C, conductive contacts 180 are formed in the interlayer dielectric layer 164 and the contact etch-stop layer 162. The conductive contacts 180 are electrically connected to the corresponding S / D region 146 via the silicon layer 182. The conductive contacts 180 may be conductive and may include a material having one or more of Ru, Mo, Co, Ir, W, Ti, Ta, Cu, TiN, or TaN. The conductive contacts 180 may be formed by any suitable method, such as electrochemical plating (ECP) or PVD. The silicon layer 182 may be formed by any suitable process. In some embodiments, a metal layer (not shown) is first formed on the semiconductor device structure 100. The metal layer may include Ti, Ni, Ru, Co, W, or other suitable metals. The metal layer may be deposited using any suitable process, such as ALD, CVD, or PVD. After metal layer deposition, an annealing process is performed to react the S / D region 146 with the metal layer, thereby forming a silicon layer 182. The silicon layer 182 may include any suitable material, such as NiSi, TiSi, CoSi, RuSi, or WSi. A planarization process, such as CMP, may be performed such that the top surface of the gate electrode layer 172 and the top surface of the conductive contact 180 are substantially coplanar, as shown in Figure 12A. In some embodiments, the conductive contact 180 has a critical dimension of about 5 nm to about 50 nm.

[0033] Figures 13A to 13D are cross-sectional side views taken along line AA of Figure 6, according to some embodiments, of various stages of manufacturing a semiconductor device structure 100. For clarity, various components on the substrate 101 are omitted in Figures 13A to 13D. As shown in Figure 13A, in some embodiments, conductive contacts 180 are formed between pads 202. Pads 202 may include any suitable dielectric material, such as SiN. In some embodiments, pads 202 are absent, and conductive contacts 180 contact the interlayer dielectric layer 164. Next, as shown in Figure 13B, an etch stop layer 204 is formed on the interlayer dielectric layer 164, the gate structure 174, and the conductive contacts 180. The etch stop layer 204 may be referred to as a middle contact etch stop layer (MCESL). In some embodiments, the etch stop layer 204 may include a material different from the contact etch stop layer 162. For example, the contact etch stop layer 162 is made of SiN, while the etch stop layer 204 is made of a dielectric material with a k-value lower than that of the contact etch stop layer 162. In some embodiments, the etch stop layer 204 comprises SiCN. For example, the etch stop layer 204 comprises a material having about 35 to 45 weight percent silicon, 20 to 30 weight percent carbon, and 30 to 40 weight percent nitrogen. With the above composition, the etch stop layer 204 has a k-value of about 4 to about 5, which is significantly lower than that of SiN, and the density of the etch stop layer 204 is greater than about 1.9 g / cm³, such as about 1.9 g / cm³ to about 2 g / cm³. The reduced k-value of the etch stop layer 204 can lead to a reduction in capacitance (Ceff), thereby improving RO_AC and wafer acceptance test (WAT) by 1%. In some embodiments, the etch stop layer 204 comprises SiOCN. For example, the etch stop layer 204 comprises a material having about 35 to 45 weight percent silicon, 20 to 30 weight percent oxygen, 10 to 20 weight percent carbon, and 20 to 30 weight percent nitrogen. With the above composition, the k-value of the etch stop layer 204 is less than about 4.5, such as about 4 to about 4.5, which is significantly lower than the k-value of SiN, and the density of the etch stop layer 204 is greater than about 2 g / cm³, such as about 2 g / cm³ to about 2.5 g / cm³. With the increase in density, the etch stop layer 204 prevents oxygen from diffusing from the subsequently formed interlayer dielectric layer 206 into the gate structure 174 and the conductive contact 180.

[0034] In some embodiments, the etch stop layer 204 is a SiCN layer and is formed by PECVD using tetramethylsilane (TMS) as a precursor. NH3 plasma can be used to better separate TMS. In some embodiments, the etch stop layer 204 is a SiOCN layer and is formed by PECVD using dimethyldimethoxysilane (DMDMOS) as a precursor. NH3 plasma can also be used to better separate DMDMOS. In some embodiments, the process for forming the etch stop layer 204 and the interlayer dielectric layer 206 (Figure 13C) is a PECVD process, and the etch stop layer 204 and the interlayer dielectric layer 206 are formed in the same processing chamber without breaking the vacuum to move the substrate to another chamber.

[0035] In some embodiments, the thickness of the etch stop layer 204 ranges from about 2.5 nm to about 3.5 nm. If the thickness of the etch stop layer 204 is less than about 2.5 nm, the etch stop layer 204 may not be able to effectively reduce Ceff and block oxygen. On the other hand, if the thickness of the etch stop layer 204 is greater than about 3.5 nm, the process of forming an opening in the interlayer dielectric layer 206 (Figure 13C) and forming the conductive feature 208 in the etch stop layer 204 (Figure 13D) may take longer. Furthermore, due to the larger CD of the conductive feature 208, the etch stop layer 204 may result in a smaller gate resistance. For example, in the process of forming an opening in the interlayer dielectric layer 206, the SiCN or SiCON material of the etch stop layer 204 has a faster etching rate. Therefore, due to the faster etching rate of the etch stop layer 204, the bottom critical dimension of the opening in the interlayer dielectric layer 206 is larger, which results in a larger conductive feature 208 (Figure 13D).

[0036] As shown in Figure 13C, another interlayer dielectric layer 206 is deposited on the etch stop layer 204. The interlayer dielectric layer 206 may comprise the same material as the interlayer dielectric layer 164. Next, as shown in Figure 13D, conductive features 208 are deposited in the interlayer dielectric layer 206 and the etch stop layer 204. The conductive features 208 may comprise conductive materials such as Ru, Mo, Co, Ir, W, Ti, Ta, Cu, TiN, TaN, or combinations thereof, or other suitable materials. The conductive features 208 may be formed by any suitable process (such as PVD or ECP). In some embodiments, the conductive features 208 are electrically connected to the gate electrode layer 172 and / or the conductive contact 180.

[0037] Figures 14A to 14D are cross-sectional side views taken along line AA of Figure 6 according to an alternative embodiment, showing various stages of manufacturing the semiconductor device structure 100. As shown in Figure 14A, after the conductive contact 180 is formed, a barrier layer 210 is selectively formed on a dielectric material but not on a metal surface. For example, the barrier layer 210 is selectively formed on the pad 202, the interlayer dielectric layer 164, the contact etch stop layer 162, the gate dielectric layer 170, and the spacer 138, but not on the conductive contact 180 and the gate electrode layer 172. The barrier layer 210 may comprise a polymer comprising silicon, carbon, nitrogen, oxygen, or combinations thereof. In some embodiments, the barrier layer 210 is a silyl self-assembled monolayer (SAM). In some embodiments, silyl SAM may include octadecyltrichlorosilane (ODTS), octadecyltrimethoxysilane (OTMS), (3-aminopropyl)triethoxysilane (APTES), butyltriethoxysilane, cyclohexyltrimethoxysilane, cyclopentyltrimethoxysilane, dodecyltriethoxysilane, dodecyltrimethoxysilane, decyltriethoxysilane, dimethoxy(methyl)-n-octylsilane, triethoxyethylsilane, ethyltriethoxysilane, etc. Methoxysilane, hexyltrimethoxysilane, hexyltriethoxysilane, hexadecyltrimethoxysilane, hexadecyltriethoxysilane, triethoxymethylsilane, trimethoxy(methyl)silane, methoxy(dimethyl)octadecylsilane, methoxy(dimethyl)-n-octylsilane, octadecyltriethoxysilane, triethoxy-n-octylsilane, trimethoxy(propyl)silane, trimethoxy-n-octylsilane, triethoxy(propyl)silane, or other suitable compounds. In some embodiments, the barrier layer 210 may be formed by CVD, molecular layer deposition (MLD), or other suitable processes.

[0038] As shown in Figure 14B, after the barrier layer 210 is formed, an etch stop layer 212 is selectively formed on the metal surfaces of the conductive contact 180 and the gate electrode layer 172. In some embodiments, the etch stop layer 212 comprises the same material as the etch stop layer 204. Due to the hydrophilic / hydrophobic properties of the barrier layer 210, the etch stop layer 212 is prevented from forming on the barrier layer 210, and therefore the etch stop layer 212 is formed on the area not covered by the barrier layer 210. Therefore, in some embodiments, the etch stop layer 212 is selectively formed on the conductive contact 180 and the gate electrode layer 172 to provide a termination point for subsequent etching processes, thereby forming an opening in the conductive feature 208 to prevent oxygen from diffusing from the subsequently formed interlayer dielectric layer 206 to the conductive contact 180 and the gate electrode layer 172, thereby reducing Ceff. No etch stop layer is formed on spacer 138, interlayer dielectric layer 164, contact etch stop layer 162, gate dielectric layer 170 and pad 202 because no stop point needs to be set at those locations in subsequent etching processes, and there is no risk of metal oxidation. Furthermore, the k value of interlayer dielectric layer 206 is significantly lower than the k value of etch stop layer 212, thereby further reducing Ceff.

[0039] As shown in Figure 14C, after forming the etch stop layer 212, the barrier layer 210 is removed. In some embodiments, the barrier layer 210 may be removed by a dry etching process, a wet etching process, or other suitable processes. After removing the barrier layer 210, the etch stop layer 212 remains on the gate electrode layer 172 and the conductive contact 180. An interlayer dielectric layer 206 is formed on the spacer 138, the gate dielectric layer 170, the contact etch stop layer 162, the interlayer dielectric layer 164, the pad 202, and the etch stop layer 212, as shown in Figure 14C. Next, as shown in Figure 14D, conductive features 208 are formed in the interlayer dielectric layer 206 and the etch stop layer 212.

[0040] Figures 15A to 15G are cross-sectional side views taken along line AA of Figure 6 according to an alternative embodiment, showing various stages of manufacturing the semiconductor device structure 100. As shown in Figure 15A, a contact etch-stop layer 162 and an interlayer dielectric layer 164 are formed over the S / D region 146. Next, as shown in Figure 15B, conductive contacts 180 and a silicon layer 182 are formed. A planarization process (such as a CMP process) may be performed to remove portions of the conductive contacts 180 formed on the sacrificial gate electrode layer 134. As shown in Figure 15C, an etch-stop layer 222 and an interlayer dielectric layer 206 are formed on the conductive contacts 180 and the sacrificial gate electrode layer 134. In some embodiments, the etch-stop layer 222 comprises the same material as the contact etch-stop layer 162. In some embodiments, the etch-stop layer 222 comprises the same material as the etch-stop layer 204, which may result in a reduction in Ceff. As shown in Figure 15D, an opening 220 is formed in the interlayer dielectric layer 206 and the etch stop layer 222, extending between the spacer 138 and the first semiconductor layer 106. In other words, a portion of the interlayer dielectric layer 206 and the etch stop layer 222, along with the sacrificial gate electrode layer 134, the sacrificial gate dielectric layer 132, and the second semiconductor layer 108, is removed to form the opening 220. Next, as shown in Figure 15E, a gate dielectric layer 170 and a gate electrode layer 172 are formed in the opening 220. Another etch stop layer 224 and another interlayer dielectric layer 226 are formed on the interlayer dielectric layer 206, the gate dielectric layer 170, and the gate electrode layer 172, as shown in Figure 15F. In some embodiments, the etch stop layer 224 comprises the same material as the etch stop layer 204. As a result, Ceff is reduced, and oxygen is prevented from diffusing from the interlayer dielectric layer 226 into the gate electrode layer 172. Next, as shown in Figure 15G, conductive features 228 are formed in the interlayer dielectric layer 226, the etch stop layer 224, the interlayer dielectric layer 206, and the etch stop layer 222. Conductive features 228 may include the same material as conductive features 208. In some embodiments, one conductive feature 228 is electrically connected to the gate electrode layer 172, and another conductive feature 228 is electrically connected to the conductive contact 180, as shown in Figure 15G.

[0041] Figures 16A and 16B are cross-sectional side views taken along line AA of Figure 6 according to an alternative embodiment, showing various stages of manufacturing a semiconductor device structure 100. In some embodiments, an etch stop layer 224 is selectively formed on the gate electrode layer 172, as shown in Figure 16A. The etch stop layer 224 may be selectively formed on the gate electrode layer 172 using a barrier layer (not shown), such as the barrier layer 210 shown in Figure 14A. The barrier layer may be formed first on the dielectric material of the interlayer dielectric layer 206 and the gate dielectric layer 170, and then removed after the etch stop layer 224 is selectively formed on the gate electrode layer 172. The etch stop layer 224 prevents oxygen from diffusing from the interlayer dielectric layer 226 into the gate electrode layer 172. In some embodiments, the interlayer dielectric layer 226 is in direct contact with the interlayer dielectric layer 206, as shown in Figure 16A. In some embodiments, when forming the opening of the conductive feature 208, the etch stop layers 224, 222 provide an end point for the etching process. Therefore, even if the opening of the conductive feature 208 above the conductive contact 180 is deeper than the opening of the conductive feature 208 above the gate electrode layer 172, over-etching is prevented due to the etch stop layers 224, 222. In some embodiments, the etch stop layers 222, 224 comprise the same material, such as SiCN or SiOCN, and portions of the etch stop layers 222, 224 are removed simultaneously. In other words, a single etching process can be performed to remove portions of the etch stop layers 222, 224 to expose the conductive contact 180 and the gate electrode layer 172. Then, as shown in Figure 16B, the conductive feature 228 is formed in the opening above the conductive contact 180 and the gate electrode layer 172.

[0042] Figures 17A to 17E are cross-sectional side views taken along line AA of Figure 6 according to an alternative embodiment, showing various stages of manufacturing the semiconductor device structure 100. As shown in Figure 17A, after the gate structure 174 is formed, a CMP process is performed to remove a portion of the gate electrode layer 172 formed on the interlayer dielectric layer 164. Next, as shown in Figure 17B, an etch stop layer 222 and an interlayer dielectric layer 206 are formed on the interlayer dielectric layer 164 and the gate structure 174. In some embodiments, the etch stop layer 222 comprises the same material as the etch stop layer 204. Therefore, the etch stop layer 222 provides a termination point for subsequent etching processes, reduces Ceff, and prevents oxygen from diffusing from the interlayer dielectric layer 206 into the gate electrode layer 172. As shown in Figure 17C, conductive contacts 180 are formed in the interlayer dielectric layer 206 and the etch stop layer 222, and a silicon layer 182 is formed between the conductive contacts 180 and the S / D region 146. Next, an etch stop layer 224 and an interlayer dielectric layer 226 are formed on the conductive contacts 180 and the interlayer dielectric layer 206, as shown in Figure 17D. In some embodiments, the etch stop layer 224 comprises the same material as the etch stop layer 204. Therefore, the etch stop layer 224 provides a termination point for subsequent etching processes, reduces Ceff, and prevents oxygen from diffusing from the interlayer dielectric layer 226 into the conductive contacts 180. Next, as shown in Figure 17E, conductive features 228 are formed in the interlayer dielectric layer 226, the etch stop layer 224, the interlayer dielectric layer 206, and the etch stop layer 222. The conductive features 228 are electrically connected to the gate electrode layer 172 and the conductive contacts 180.

[0043] Figure 18 is a cross-sectional side view of one of the stages of manufacturing a semiconductor device structure 100, taken along line AA of Figure 6 according to an alternative embodiment. In some embodiments, an etch stop layer 222 is selectively formed on the gate electrode layer 172, and an etch stop layer 224 is selectively formed on the conductive contact 180, as shown in Figure 18. Therefore, the etch stop layers 222, 224 provide termination points for subsequent etching processes to form openings in the conductive feature 208, preventing oxygen from diffusing from the interlayer dielectric layers 206, 226 into the gate electrode layer 172 and the conductive contact 180, and reducing Ceff. No etch stop layers are formed on the dielectric material because termination points are not required at those locations in subsequent etching processes, there is no risk of metal oxidation, and the k-values ​​of the interlayer dielectric layers 206, 226 are significantly lower than the k-values ​​of the etch stop layers 222, 224, thereby further reducing Ceff.

[0044] Figures 19A to 19D are cross-sectional side views taken along line AA of Figure 6 according to an alternative embodiment, showing various stages of manufacturing a semiconductor device structure 100. In some embodiments, a conductive feature 304 is formed in a dielectric layer 302. The conductive feature 304 may be a gate electrode layer 172 or a conductive contact 180, and the dielectric layer 302 may be an interlayer dielectric layer 164, an interlayer dielectric layer 206, or an interlayer dielectric layer 226. An etch stop layer 306 is deposited on the dielectric layer 302 and the conductive feature 304. In some embodiments, the etch stop layer 306 is made of SiN and has a k value of approximately 7. Next, as shown in Figure 19B, a mask layer 308 is formed on a portion of the etch stop layer 306 disposed on the conductive feature 304. The portion of the etch stop layer 306 located on the dielectric layer 302 is exposed.

[0045] As shown in Figure 19C, a placement process 310 is performed to place dopant into the exposed portion of the etch stop layer 306 to reduce the k-value. In some embodiments, the dopant includes carbon. In some embodiments, the dopant includes carbon and oxygen. After the placement process 310, the mask layer 308 is removed, and the etch stop layer 306 includes a first portion 306a disposed on the conductive feature 304 and a second portion 306b disposed on the dielectric layer 302, as shown in Figure 19D. The first portion 306a and the second portion 306b have different compositions. For example, the first portion 306a includes undoped SiN, while the second portion 306b includes carbon-doped SiN or carbon and oxygen-doped SiN. In some embodiments, the first portion 306a includes SiN having a first k-value and a first density, while the second portion 306b includes SiCN or SiOCN having a second k-value and a second density. The second k-value may be significantly smaller than the first k-value, and the second density may be significantly smaller than the first density. The second k value can lead to a decrease in Ceff. Although the oxygen barrier performance of the second portion 306b is not as good as that of the first portion 306a, there is no metal beneath the second portion 306b. Therefore, there is no risk of metal oxidation. The etch stop layer 306, including the first portion 306a and the second portion 306b, can replace the etch stop layer 204 shown in Figure 13D, the etch stop layer 222 shown in Figures 15G, 16B and 17E, and the etch stop layer 224 shown in Figures 15G, 16B and 17E. When used as etch stop layers 204, 222 or 224, the first portion 306a of the etch stop layer 306 is disposed on a conductive material, such as the conductive contact 180 and / or the gate electrode layer 172, and the second portion 306b of the etch stop layer 306 is disposed on a dielectric material, such as the interlayer dielectric layer 164, the interlayer dielectric layer 206 and / or the interlayer dielectric layer 226.

[0046] Embodiments of this disclosure provide a semiconductor device structure 100 including an etch stop layer 204 made of SiCN or SiOCN. Some embodiments offer advantages. For example, the k-value of the etch stop layer 204 is lower than that of a conventional etch stop layer, while the density of the etch stop layer 204 is sufficiently high to prevent oxygen from diffusing from the dielectric material disposed on the etch stop layer 204 into conductive features disposed below the etch stop layer 204. The reduced k-value may result in a decrease in Ceff.

[0047] The embodiment is a semiconductor device structure. The structure includes: a gate electrode layer disposed above a substrate; a source / drain region disposed above the substrate; a conductive contact disposed above the source / drain region; and a first etch-stop layer disposed on the conductive contact and the gate electrode layer, wherein the first etch-stop layer includes SiCN or SiOCN. The structure further includes: a first dielectric layer disposed on the first etch-stop layer; and a first conductive feature disposed in the first dielectric layer and the first etch-stop layer, wherein the first conductive feature is electrically connected to the conductive contact. The structure further includes: a second conductive feature disposed in the first dielectric layer and the first etch-stop layer, wherein the second conductive feature is electrically connected to the gate electrode layer.

[0048] Another embodiment is a semiconductor device structure. The structure includes: a source / drain region disposed above a substrate; a conductive contact disposed above the source / drain region; a first etch-stop layer disposed on the conductive contact, and the first etch-stop layer includes SiCN or SiOCN. The structure further includes: a first dielectric layer disposed on the first etch-stop layer; a gate electrode layer disposed through the first dielectric layer and the first etch-stop layer; a second etch-stop layer disposed on the gate electrode layer; a second dielectric layer disposed on the second etch-stop layer; and a first conductive feature disposed in the first dielectric layer, the first etch-stop layer, and the second dielectric layer, and the first conductive feature is electrically connected to the conductive contact. The structure further includes: a second conductive feature disposed in the second dielectric layer and the second etch-stop layer, and the second conductive feature is electrically connected to the gate electrode layer.

[0049] Another embodiment is a method. The method includes the following steps: performing a planarization process to expose a gate electrode layer, conductive contacts, and spacers; selectively depositing a first etch-stop layer on the gate electrode layer and conductive contacts. The first etch-stop layer comprises SiCN or SiOCN. The method further includes the following steps: depositing a first dielectric layer on the first etch-stop layer and spacers; forming first and second conductive features in the first dielectric layer and the first etch-stop layer. The first conductive feature is electrically connected to the gate electrode layer, and the second conductive feature is electrically connected to the conductive contacts.

[0050] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0005] The various aspects of this disclosure can be best understood from the following detailed description in conjunction with the accompanying drawings. Note that, according to standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Figures 1, 2, 3, 4, 5, and 6 are perspective views of various stages of manufacturing a semiconductor device structure according to some embodiments. Figures 7A, 8A, 9A, 10A, 11A, and 12A are cross-sectional side views of various stages of manufacturing a semiconductor device structure taken along line AA of Figure 6 according to some embodiments. Figures 7B, 8B, 9B, 10B, 11B, and 12B are cross-sectional side views of various stages of manufacturing a semiconductor device structure taken along line BB of Figure 6 according to some embodiments. Figures 7C, 8C, 9C, 10C, 11C, and 12C are cross-sectional side views taken along line CC of Figure 6, according to some embodiments, of various stages of manufacturing a semiconductor device structure. Figures 13A, 13B, 13C, and 13D are cross-sectional side views taken along line AA of Figure 6, according to some embodiments, of various stages of manufacturing a semiconductor device structure. Figures 14A, 14B, 14C, and 14D are cross-sectional side views taken along line AA of Figure 6, according to alternative embodiments, of various stages of manufacturing a semiconductor device structure. Figures 15A, 15B, 15C, 15D, 15E, 15F, and 15G are cross-sectional side views taken along line AA of Figure 6, according to alternative embodiments, of various stages of manufacturing a semiconductor device structure. Figures 16A and 16B are cross-sectional side views taken along line AA of Figure 6, according to an alternative embodiment, of various stages of manufacturing a semiconductor device structure. Figures 17A, 17B, 17C, 17D, and 17E are cross-sectional side views taken along line AA of Figure 6, according to an alternative embodiment, of various stages of manufacturing a semiconductor device structure. Figure 18 is a cross-sectional side view taken along line AA of Figure 6, according to an alternative embodiment, of one of the stages of manufacturing a semiconductor device structure. Figures 19A, 19B, 19C, and 19D are cross-sectional side views taken along line AA of Figure 6, according to an alternative embodiment, of various stages of manufacturing a semiconductor device structure. [Biomaterial Storage]

[0052] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A semiconductor device structure, comprising: a gate electrode layer disposed above a substrate; a source / drain region disposed above the substrate; a conductive contact disposed above the source / drain region; a first etch-stop layer disposed on the conductive contact and the gate electrode layer, wherein the first etch-stop layer comprises SiCN or SiOCN; a first dielectric layer disposed on the first etch-stop layer; a first conductive feature disposed in the first dielectric layer and the first etch-stop layer, wherein the first conductive feature is electrically connected to the conductive contact; a second conductive feature disposed in the first dielectric layer and the first etch-stop layer, wherein the second conductive feature is electrically connected to the gate electrode layer; and a second dielectric layer, wherein the conductive contact is disposed in the second dielectric layer, and the first dielectric layer is in contact with the second dielectric layer.

2. The semiconductor device structure as claimed in claim 1, further comprising a second etch-stop layer disposed above the source / drain region, wherein the conductive contact is disposed in the second etch-stop layer.

3. The semiconductor device structure as claimed in claim 2, wherein the first and second etch-stop layers comprise different materials.

4. The semiconductor device structure as claimed in claim 1, wherein the first etch stop layer further comprises 35 to 45 weight percent silicon, 20 to 30 weight percent carbon and 30 to 40 weight percent nitrogen.

5. A semiconductor device structure, comprising: a source / drain region disposed on a substrate; a conductive contact disposed above the source / drain region; a first etch-stop layer disposed on the conductive contact, wherein the first etch-stop layer comprises SiCN or SiOCN; a first dielectric layer disposed on the first etch-stop layer; a gate electrode layer disposed through the first dielectric layer and the first etch-stop layer; a second etch-stop layer disposed on the gate electrode layer; a second dielectric layer disposed on the second etch-stop layer, wherein the first dielectric layer is in contact with the second dielectric layer; a first conductive feature disposed in the first dielectric layer, the first etch-stop layer and the second dielectric layer, wherein the first conductive feature is electrically connected to the conductive contact; and a second conductive feature disposed in the second dielectric layer and the second etch-stop layer, wherein the second conductive feature is electrically connected to the gate electrode layer.

6. The semiconductor device structure as claimed in claim 5, wherein the second etch stop layer comprises SiCN or SiOCN.

7. The semiconductor device structure as claimed in claim 5, wherein the second etch stop layer comprises: a first portion disposed on and in contact with the gate electrode layer; and a second portion disposed on and in contact with the first dielectric layer, wherein the first portion and the second portion have different compositions.

8. A method for forming a semiconductor device structure, comprising the following steps: performing a planarization process to expose a gate electrode layer, a conductive contact, a spacer, and a first dielectric layer; selectively depositing a first etch stop layer on the gate electrode layer and the conductive contact, wherein the first etch stop layer comprises SiCN or SiOCN; depositing a second dielectric layer on the first etch stop layer and the spacer; and forming first and second conductive features in the second dielectric layer and the first etch stop layer, wherein the first conductive feature is electrically connected to the gate electrode layer, and the second conductive feature is electrically connected to the conductive contact, wherein the first dielectric layer is in contact with the second dielectric layer.

9. The method of claim 8, wherein the first etch stop layer and the second dielectric layer are deposited in the same processing chamber.

10. The method of claim 9, wherein the planarization process further exposes a second etch stop layer, the second etch stop layer having a k value greater than the first etch stop layer.

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