Semiconductor memory devices

Abstract

A highly integrated semiconductor memory device is provided. The semiconductor memory device includes: a substrate; a first via wiring extending in a first direction; a plurality of first semiconductor layers arranged side-by-side in the first direction and electrically connected to the first via wiring; a memory portion arranged side-by-side in the first direction and electrically connected to the plurality of first semiconductor layers; a plurality of first gate electrodes arranged side-by-side in the first direction and facing the plurality of first semiconductor layers; and a plurality of first wirings arranged side-by-side in the first direction and extending in a second direction, and electrically connected to the plurality of first semiconductor layers. The first gate electrode is electrically connected; and the plurality of second semiconductor layers are arranged side by side in the first direction and are electrically connected to the plurality of first wirings; and the plurality of second gate electrodes are arranged side by side in the first direction and face the plurality of second semiconductor layers; and the second via wiring extends in the first direction and is electrically connected to the plurality of second gate electrodes; and the second wiring extends in the first direction and is electrically connected to the plurality of second semiconductor layers, and is arranged side by side with the plurality of second semiconductor layers in the third direction.

Description

[Technical Field]

[0001] This embodiment relates to a semiconductor memory device. [Previous Technology]

[0002] With the increasing integration of semiconductor memory devices, there has been progress in the review of the 3D transformation of semiconductor memory devices. [Summary of the Invention]

[0003] A semiconductor memory device capable of high integration is provided.

[0004] One embodiment of the semiconductor memory device includes: a substrate; a first via wiring extending in a first direction intersecting the surface of the substrate; a plurality of first semiconductor layers arranged side-by-side in the first direction and electrically connected to the first via wiring; a memory portion arranged side-by-side in the first direction and electrically connected to the plurality of first semiconductor layers; a plurality of first gate electrodes arranged side-by-side in the first direction and facing the plurality of first semiconductor layers; and a plurality of first wirings arranged side-by-side in the first direction and extending in a second direction intersecting the first direction. Extending and electrically connected to a plurality of first gate electrodes; and a plurality of second semiconductor layers, arranged side-by-side in a first direction and electrically connected to a plurality of first wirings; and a plurality of second gate electrodes, arranged side-by-side in a first direction and facing the plurality of second semiconductor layers; and a second via wiring, extending in a first direction and electrically connected to a plurality of second gate electrodes; and a second wiring, extending in a first direction and electrically connected to a plurality of second semiconductor layers, and arranged side-by-side with the plurality of second semiconductor layers in a third direction intersecting the first and second directions.

Implementation Method

[0006] Next, with reference to the drawings, the semiconductor memory device of the embodiment will be described in detail. Furthermore, the following embodiments are merely examples and are not intended to limit the scope of the present invention. Also, the following drawings are illustrative, and for ease of explanation, some components may be omitted. Furthermore, for multiple embodiments, common parts may be marked with the same element symbols and their descriptions may be omitted.

[0007] Furthermore, in this specification, when referring to "semiconductor memory device," it may refer to a memory chip, or it may refer to a memory system that includes a controller chip, such as a memory chip, memory card, or SSD (Solid State Drive). It may also refer to a device that includes a host computer, such as a smartphone, tablet, or personal computer.

[0008] Furthermore, in this specification, when it is mentioned that the first component is "electrically connected" to the second component, it may mean that the first component is directly connected to the second component, or it may mean that the first component is connected to the second component via wiring, semiconductor components, or transistors. For example, when three transistors are connected in series, even if the second transistor is in the OFF state, the first transistor and the third transistor system are still "electrically connected".

[0009] Furthermore, in this specification, when it is mentioned that the first configuration is "electrically connected between" the second and third configurations, it may mean that the first configuration, the second configuration, and the third configuration are connected in series and the second configuration is electrically connected to the third configuration via the first configuration.

[0010] Furthermore, in this specification, when it is mentioned that the circuit or the like "conducts" the wiring of the two, for example, there may be a situation that means "this circuit or the like includes a transistor or the like, this transistor or the like is placed in the current path between the two wirings, and this transistor or the like is in the ON state".

[0011] Furthermore, in this specification, a specific direction that is parallel to the top surface of the substrate is referred to as the X direction, a direction that is parallel to the top surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and a direction that is perpendicular to the top surface of the substrate is referred to as the Z direction.

[0012] Furthermore, in this specification, there may be cases where the direction along a specific surface is referred to as the first direction, the direction intersecting the first direction along the specific surface is referred to as the second direction, and the direction intersecting the specific surface is referred to as the third direction. These first, second, and third directions may correspond to any one of the X, Y, and Z directions, or they may not correspond to each other.

[0013] Furthermore, in this specification, the terms "upper" or "lower" are used with the substrate as a reference. For example, if the direction away from the substrate along the Z direction is called "upper," then the direction approaching the substrate along the Z direction is called "lower." Also, when referring to a particular configuration as "below" or "lower end," it refers to the substrate-side surface or end of that configuration; when referring to "upper" or "upper end," it refers to the surface or end of that configuration opposite to the substrate. Furthermore, the surface intersecting the X or Y direction is called a "side surface," etc.

[0014] Furthermore, in this specification, when referring to the “center position” of a certain component, it may refer to, for example, the position of the center of the circumscribed circle of the component, or the center of gravity of the image of the component on a specific surface.

[0015] [First Embodiment] [Circuit Configuration] FIG1 is a schematic circuit diagram showing a portion of the configuration of the semiconductor memory device according to the first embodiment. As shown in FIG1, the semiconductor memory device of this embodiment includes a memory cell array (MCA). The memory cell array (MCA) includes a plurality of memory layers ML0 to ML3 (hereinafter referred to as "memory layers ML"), a plurality of bit lines BL connected to the plurality of memory layers ML0 to ML3, a plurality of global bit lines (GBL) electrically connected to the plurality of bit lines BL, and plate lines (PL) connected to the plurality of memory layers ML0 to ML3.

[0016] Memory layers ML0 to ML3 each have a plurality of word lines WL0 to WL2 (hereinafter referred to as "word lines WL") and a plurality of memory cells MC connected to these word lines WL0 to WL2. Each memory cell MC has a transistor TrC and a capacitor CpC. One electrode of the transistor TrC is connected to a bit line BL. The other electrode of the transistor TrC is connected to the capacitor CpC. Furthermore, one and the other electrodes of the transistor TrC function as source electrodes or drain electrodes depending on the voltage supplied to the transistor TrC. The gate electrode of the transistor TrC is connected to one of the word lines WL0 to WL2. One electrode of the capacitor CpC is connected to the other electrode of the transistor TrC. The other electrode of capacitor CpC is connected to the plate line PL.

[0017] In addition, each bit line BL is connected to a plurality of memory cells MC corresponding to a plurality of memory layers ML0 to ML3. Also, each bit line BL is connected to a global bit line GBL.

[0018] Furthermore, memory layers ML0 to ML3 are each equipped with a plurality of transistors TrR0a, TrR1a, TrR2a, and TrR3a (hereinafter referred to as "transistor TrRa") and a plurality of transistors TrR0b, TrR1b, TrR2b, and TrR3b (hereinafter referred to as "transistor TrRb"), which are configured corresponding to a plurality of word lines WL0 to WL2. One electrode of transistors TrRa and TrRb is connected to one of the word lines WL0 to WL2. The other electrode of transistors TrRa, TrR1a, TrR2a, and TrR3a is connected to layer select lines LL0a, LL1a, LL2a, and LL3a (hereinafter referred to as "layer select line LL"), respectively. The other electrode of transistors TrR0b, TrR1b, TrR2b, and TrR3b is connected to wiring NLL. Additionally, one and the other electrodes of transistors TrRa and TrRb function as source or drain electrodes depending on the voltage supplied to them. The gate electrodes of transistors TrRa and TrRb are connected to word line select lines LW0a, LW1a, LW2a, LW0b, LW1b, and LW2b (hereinafter referred to as "word line select line LW"), respectively.

[0019] Furthermore, the character line select line LW is connected to the plurality of transistors TrRa and TrRb corresponding to the plurality of memory layers ML0 to ML3. Also, the layer select lines LL0a, LL1a, LL2a, and LL3a are respectively connected to all transistors TrR0a, TrR1a, TrR2a, and TrR3a corresponding to memory layers ML0 to ML3. The wiring NLL is connected to all transistors TrR0b, TrR1b, TrR2b, and TrR3b corresponding to all character lines WL0, WL1, and WL2.

[0020] [Readout Operation] Figure 2 is a schematic circuit diagram used to explain the readout operation of the semiconductor memory device in the first embodiment.

[0021] During the read operation, one of the multiple memory layers ML0 to ML3 is selected. In the illustrated example, memory layer ML0 is selected. When selecting memory layers ML0 to ML3, for example, a voltage VON is supplied to the layer selection line LL0a corresponding to the memory layer ML0 that is the target of the read operation, and a voltage VOFF is supplied to the other layer selection lines LL1a, LL2a, and LL3a. Alternatively, for example, a voltage VOFF is supplied to the wiring NLL.

[0022] Voltage VON, for example, has a magnitude that enables the transistor TrC to be in the ON state. Voltage VOFF, for example, has a magnitude that enables the transistor TrC to be in the OFF state. For example, when the transistor TrC is an NMOS transistor, voltage VON is larger than voltage VOFF. Also, for example, when the transistor TrC is a PMOS transistor, voltage VON is smaller than voltage VOFF.

[0023] Furthermore, during the readout operation, one of the plurality of character lines WL0 to WL2 is selected. In the illustrated example, character line WL0 is selected. When selecting character lines WL0 to WL2, for example, voltage VON' is supplied to the character line selection line LW0a corresponding to the character line WL0 to be read out among the plurality of character line selection lines LW0a, LW1a, and LW2a, and voltage VOFF' is supplied to the other character line selection lines LW1a and LW2a. Furthermore, voltage VOFF' is supplied to the character line selection line LW0b corresponding to the character line WL0 to be read out among the plurality of character line selection lines LW0b, LW1b, and LW2b, and voltage VON' is supplied to the other character line selection lines LW1b and LW2b.

[0024] Voltage VON', for example, has a magnitude that enables transistors TrRa and TrRb to be in the ON state. Voltage VOFF', for example, has a magnitude that enables transistors TrRa and TrRb to be in the OFF state. For example, when transistors TrRa and TrRb are NMOS transistors, voltage VON' is larger than voltage VOFF'. Also, for example, when transistors TrRa and TrRb are PMOS transistors, voltage VON' is smaller than voltage VOFF'.

[0025] Here, at the word line WL0 (hereinafter referred to as the "selection word line WL0") connected to the memory cell MC (hereinafter referred to as the "selection memory cell MC") which is the object of the read operation, a voltage VON is supplied via transistor TrR0a. This causes transistor TrC in the selection memory cell MC to be in the ON state. Accompanying this, the voltage of the global bit line GBL changes, or a current flows at the global bit line GBL. By detecting this voltage change or current, the data stored in the selection memory cell MC can be read out.

[0026] Furthermore, at the non-selection word line WL0 corresponding to the memory layers ML1, ML2, ML3 that are different from the selected memory cell MC, a voltage VOFF is supplied via transistors TrR1a, TrR2a, and TrR3a. As a result, the transistor TrC in the memory cell MC is in the OFF state.

[0027] Furthermore, at the non-select word lines WL1 and WL2 corresponding to memory layers ML0, ML1, ML2, and ML3, a voltage VOFF is supplied via transistor TrRb, which is connected to the word line select lines LW1b and LW2b. As a result, the transistor TrC in the memory cell MC is in the OFF state.

[0028] In addition, the following description is based on examples where the transistors TrC, TrRa, and TrRb are all NMOS transistors.

[0029] [Structure] FIG3 is a schematic perspective view showing the configuration of a portion of the semiconductor memory device according to the first embodiment. FIG4 is a schematic perspective view showing the configuration of a portion of the semiconductor memory device, with an enlarged view of a portion of FIG3. FIG5 and FIG6 are schematic XY cross-sectional views showing the configuration of a portion of the semiconductor memory device. FIG7, FIG9 and FIG11 are schematic XY cross-sectional views showing the configuration of a portion of the semiconductor memory device, with an enlarged view of a portion of FIG5 respectively. FIG8 is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device, showing the configuration shown in FIG7 cut along line A-A' and observed in the direction of the arrow. FIG10 is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device, showing the configuration shown in FIG9 cut along line B-B' and observed in the direction of the arrow. Figure 12 is a schematic cross-sectional view showing the structure of a portion of the semiconductor memory device, illustrating the configuration shown in Figure 11 when cut along line C-C' and viewed in the direction of the arrow. Figure 13 is a schematic XY cross-sectional view showing the configuration of a portion of the semiconductor memory device, with an enlarged view of a portion of Figure 6. Figure 14 is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device, illustrating the configuration shown in Figure 13 when cut along line D-D' and viewed in the direction of the arrow. Figure 15 is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device, illustrating the configuration shown in Figure 6 when cut along line E-E' and viewed in the direction of the arrow.

[0030] Figure 3 shows a portion of a semiconductor substrate Sub and a memory cell array MCA disposed above the semiconductor substrate Sub.

[0031] The semiconductor substrate Sub is, for example, a silicon (Si) semiconductor substrate containing p-type impurities such as boron (B). An insulating layer (not shown) and an electrode layer are disposed on the top of the semiconductor substrate Sub. The insulating layer (not shown) and the electrode layer on the top of the semiconductor substrate Sub constitute peripheral circuitry for controlling the semiconductor memory device of the first embodiment. For example, a sense amplifier circuit is disposed in the region directly below the memory cell array MCA. The sense amplifier circuit is electrically connected to the global bit line GBL. During readout, the sense amplifier circuit can read out the data stored in the selected memory cell MC by detecting changes in voltage or current in the bit line GBL. Furthermore, the peripheral circuitry includes a sequencer that supplies specific voltages to each wiring within the memory cell array MCA and each component within the sense amplifier circuit in a specific timing sequence, thereby performing readout operations.

[0032] The memory cell array MCA has a plurality of memory layers ML arranged side by side in the Z direction. Furthermore, an insulating layer 103, such as silicon oxide (SiO2), is disposed between the plurality of memory layers ML.

[0033] As shown in Figures 5 and 6, a memory cell region RMC is provided at the memory cell array MCA.

[0034] Furthermore, as shown in Figure 5, at the memory cell array MCA, a "transistor region RTrRa disposed on one side of the Y direction relative to the memory cell region RMC" and a "wiring region RLL disposed on one side of the Y direction relative to the transistor region RTrRa" are provided. Also, at the memory cell array MCA, a "connection wiring region RCL1 disposed between the memory cell region RMC and the transistor region RTrRa" and a "connection wiring region RCL2 disposed between the transistor region RTrRa and the wiring region RLL" are provided.

[0035] Furthermore, as shown in Figure 6, at the memory cell array MCA, a transistor region RTrRb is provided on the other side of the memory cell region RMC in the Y direction. Also, at the memory cell array MCA, a connection wiring region RCL1 is provided between the memory cell region RMC and the transistor region RTrRb.

[0036] [Structure of Memory Cell Region RMC] As shown in Figure 5, a plurality of insulating layers 101 arranged side by side in the X direction and a conductive layer 102 disposed between two adjacent insulating layers 101 in the X direction are provided in the memory cell region RMC. The insulating layers 101 and the conductive layer 102 extend in the Y and Z directions, and the plurality of memory layers ML are interrupted in the X direction.

[0037] The insulating layer 101 may contain, for example, silicon oxide (SiO2). The conductive layer 102 may contain, for example, a laminated structure of titanium nitride (TiN) and silicon germanium (SiGe). The conductive layer 102 may function as a plate line PL (FIG. 1).

[0038] Furthermore, in the region between the insulating layer 101 and the conductive layer 102 in the memory cell region RMC, a plurality of via wirings 104 arranged side by side in the Y direction are provided. These plurality of via wirings 104, for example, as shown in FIG3, penetrate a plurality of memory layers ML and extend in the Z direction.

[0039] The through-hole wiring 104, as shown in Figure 4, includes, for example, a conductive oxide film 104a containing a conductive oxide, a barrier conductive film 104b such as titanium nitride (TiN), and a conductive component 104c such as tungsten (W). Alternatively, the through-hole wiring 104 may replace the conductive oxide film 104a with ruthenium (Ru), iridium (Ir), or other metals. Furthermore, the through-hole wiring 104 may also contain only a conductive oxide, or only ruthenium (Ru), iridium (Ir), or other metals.

[0040] In this specification, "conductive oxide" is, for example, defined as containing indium tin oxide (ITO), indium zinc oxide (IZO), ruthenium oxide (RuO2), iridium oxide (IrO2), or other oxygen-containing conductive materials.

[0041] The conductive member 104c has a slightly cylindrical shape extending in the Z direction. The barrier conductive film 104b has a slightly cylindrical shape extending in the Z direction along the outer peripheral surface of the conductive member 104c. The conductive oxide film 104a has a slightly cylindrical shape extending in the Z direction along the outer peripheral surface of the barrier conductive film 104b. The via wiring 104, for example, functions as a bit line BL (FIG. 1).

[0042] The memory layer ML includes a conductive layer 120 that is disposed between an insulating layer 101 and a plurality of via wirings 104 and extends in the Y direction, a plurality of transistor structures 110 that are arranged side by side in the Y direction corresponding to the plurality of via wirings 104, and a plurality of capacitor structures 130 that are disposed between a conductive layer 102 and a plurality of transistor structures 110 and arranged side by side in the Y direction corresponding to the plurality of via wirings 104.

[0043] The transistor structure 110, for example, as shown in FIG4, includes a semiconductor layer 111 that is connected to the outer peripheral surface of the via wiring 104 and extends in the X direction, an insulating layer 112 disposed on the upper and lower surfaces, both sides in the Y direction and one side (conductive layer 120 side) of the semiconductor layer 111, and a conductive layer 113 disposed on the upper and lower surfaces, both sides in the Y direction and one side (conductive layer 120 side) of the insulating layer 112.

[0044] In the XY cross-section as illustrated in Figure 7, the two sides of the semiconductor layer 111 in the X direction can also be formed along circles centered on the center position of the via wiring 104. Similarly, the side of one side (the conductive layer 120 side) of the insulating layer 112 and the conductive layer 113 in the X direction can also be formed along circles centered on the center position of the via wiring 104. Furthermore, the two sides of the semiconductor layer 111, the insulating layer 112, and the conductive layer 113 in the Y direction can also be formed in a straight line along the side of the insulating layer 115.

[0045] Furthermore, the two sides of the semiconductor layer 111 in the X direction may not be formed along a circle. In this case, similarly, for example, the two sides of the semiconductor layer 111 in the X direction may also be curved when viewed from the Z direction. For example, the length of the semiconductor layer 111 in the X direction may also vary depending on its position in the Y direction. For example, the length of the semiconductor layer 111 in the X direction near the insulating layer 115 may be shorter than the length of the semiconductor layer 111 in the X direction away from the insulating layer 115.

[0046] Semiconductor layer 111, for example, functions as a channel region of transistor TrC (FIG. 1). Semiconductor layer 111, for example, may be a semiconductor containing at least one of gallium (Ga) and aluminum (Al), and indium (In), zinc (Zn), and oxygen (O), or may be other oxide semiconductors. A plurality of semiconductor layers 111 arranged side by side in the Z direction are commonly connected to via wiring 104 extending in the Z direction.

[0047] The insulating layer 112, for example, functions as a gate insulating film of the transistor TrC (FIG. 1). The insulating layer 112, for example, contains silicon oxide (SiO2) or the like.

[0048] The conductive layer 113, for example, functions as the gate electrode of a transistor TrC (FIG. 1). The conductive layer 113, for example, comprises a conductive oxide such as titanium nitride (TiN) or indium tin oxide (ITO). As shown in FIG. 5, a plurality of conductive layers 113 arranged side by side in the Y direction are commonly connected to the conductive layer 120 extending in the Y direction. As shown in FIG. 7 and FIG. 8, the conductive layer 113 faces the top, bottom, two sides in the Y direction, and one side (the conductive layer 120 side) of the semiconductor layer 111, separated by an insulating layer 112.

[0049] Furthermore, as shown in FIG5, an insulating layer 115, such as silicon oxide (SiO2), is disposed between two adjacent semiconductor layers 111 in the Y direction. The insulating layer 115 extends in the Z direction through a plurality of memory layers ML.

[0050] The conductive layer 120, for example, functions as a character line WL (FIG. 1). The conductive layer 120 extends in the Y direction as described above. One side of the conductive layer 120 in the X direction is connected to a plurality of conductive layers 113 arranged side-by-side in the Y direction. As shown in FIG. 7 and FIG. 8, the conductive layer 120, for example, includes a barrier conductive film 121 of titanium nitride (TiN) and a conductive film 122 of tungsten (W).

[0051] The capacitor structure 130, for example, as shown in FIG7 and FIG8, includes a "conductive layer 131", an "insulating layer 132 disposed on the upper and lower surfaces, both sides in the Y direction and one side (transistor structure 110 side) of the conductive layer 131", a "conductive layer 133 disposed on the upper and lower surfaces, both sides in the Y direction and one side (transistor structure 110 side) of the insulating layer 132", and an "insulating layer 134 disposed on the upper and lower surfaces and both sides in the Y direction of the conductive layer 133".

[0052] The conductive layer 131 functions as one of the electrodes in the capacitor CpC (FIG. 1). The conductive layer 131 may, for example, be a laminated structure comprising titanium nitride (TiN) and silicon germanium (SiGe). The conductive layer 131 is connected to the conductive layer 102.

[0053] The insulating layer 132 functions as an insulating layer for the capacitor CpC (FIG. 1). The insulating layer 132 may, for example, be zirconium dioxide (ZrO2), aluminum oxide (Al2O3), or other insulating metal oxides. Furthermore, the insulating layer 132 may, for example, be a laminated film of multiple insulating metal oxides (e.g., a laminated film of zirconium dioxide and aluminum oxide).

[0054] The conductive layer 133, for example, functions as the other electrode of a capacitor CpC (FIG. 1). The conductive layer 133, for example, is a conductive oxide containing indium tin oxide (ITO). The conductive layer 133 is insulated from the conductive layer 131 by the insulating layer 132. The conductive layer 133 is connected to one side of the semiconductor layer 111 in the X direction (the side of the conductive layer 102).

[0055] The insulating layer 134 may contain, for example, silicon oxide (SiO2). In the illustrated example, the insulating layer 134 is continuous with the insulating layer 112.

[0056] [Structure of Transistor Region RTrRa] As shown in FIG5, in the transistor region RTrRa, a plurality of insulating layers 201 are arranged side by side in the X direction corresponding to the plurality of insulating layers 101, and an insulating layer 202 is disposed between two adjacent insulating layers 201 in the X direction. The insulating layers 201 and 202 extend in the Y and Z directions and divide the plurality of memory layers ML in the X direction. The insulating layers 201 and 202 may contain, for example, silicon oxide (SiO2).

[0057] Furthermore, in the region between the insulating layer 201 and the insulating layer 202 in the transistor region RTrRa, a plurality of via wirings 204 are provided. The plurality of via wirings 204 are arranged side by side in the Y direction and extend in the Z direction, for example, as shown in FIG12, through a plurality of memory layers ML.

[0058] The through-hole wiring 204, for example, has a laminated structure comprising titanium nitride (TiN) and tungsten (W). The through-hole wiring 204 has a slightly cylindrical shape extending in the Z direction.

[0059] A plurality of via wirings 204 arranged side by side in the Y direction, for example, function as a single character line selection line LW (FIG. 1). The character line selection line LW, for example, is configured in multiple ways corresponding to a plurality of character lines WL contained in the memory layer ML, as shown in FIG. 1.

[0060] The memory layer ML includes "a portion of a plurality of transistor structures 210 disposed corresponding to a plurality of conductive layers 120", "a conductive layer 221 disposed between the transistor structure 210 and the insulating layer 201", and "a conductive layer 222 disposed between the transistor structure 210 and the insulating layer 202".

[0061] The transistor structure 210, as shown in FIG. 12, includes a portion disposed in the memory layer ML and a portion disposed at a height position corresponding to the insulating layer 103. The portion disposed in the memory layer ML, as shown in FIG. 11, includes "a plurality of insulating layers 211 disposed on the outer peripheral surface of a plurality of via wirings 204" and "a semiconductor layer 213 disposed on the outer peripheral surface of these plurality of insulating layers 211 and extending in the Y direction". The portion disposed at a height position corresponding to the insulating layer 103, as shown in FIG. 12, includes "an insulating layer 214 disposed above and below the semiconductor layer 213" and "a conductive layer 215 disposed above and below the insulating layer 214".

[0062] In the XY cross section as illustrated in Figure 11, the two sides of the semiconductor layer 213 in the X direction can also be formed along a plurality of circles that overlap each other and are centered on a plurality of the center positions of a plurality of via wirings 204.

[0063] The insulating layer 211 may contain, for example, silicon oxide (SiO2). The insulating layer 211 has a slightly cylindrical shape that extends in the Z direction along a portion of the outer peripheral surface of the through-hole wiring 204. The insulating layer 211 is continuous with the insulating layer 214 (FIG. 12).

[0064] Semiconductor layer 213, for example, functions as a channel region of transistor TrRa (FIG. 1). Semiconductor layer 213, for example, may be a semiconductor containing at least one of gallium (Ga) and aluminum (Al), and indium (In), zinc (Zn), and oxygen (O), or may be other oxide semiconductors.

[0065] The insulating layer 214, for example, functions as a gate insulating film of the transistor TrRa (FIG. 1). The insulating layer 214, for example, contains silicon oxide (SiO2) or the like.

[0066] The conductive layer 215, for example, functions as the gate electrode of a transistor TrRa (FIG. 1). The conductive layer 215, for example, comprises a laminated structure of titanium nitride (TiN) and tungsten (W). The conductive layer 215 is connected to a plurality of via wirings 204 arranged side by side in the Y direction. When considering two adjacent semiconductor layers 213 in the Z direction, the conductive layer 215 disposed between them faces the lower surface of the upper semiconductor layer 213 and the upper surface of the lower semiconductor layer 213, separated by an insulating layer 214. The plurality of conductive layers 215 arranged side by side in the Z direction are commonly connected to via wirings 204 extending in the Z direction.

[0067] Furthermore, when focusing on two adjacent conductive layers 215 in the Z direction, these conductive layers 215 are connected only through via wiring 204. That is, the two ends of these two conductive layers 215 in the Y direction are separated in the Z direction. Similarly, the two ends of these two conductive layers 215 in the X direction are also separated in the Z direction.

[0068] The conductive layer 221 is connected to one side (the insulating layer 201 side) of the semiconductor layer 213 in the X direction. As shown in FIG. 5, the conductive layer 221 extends in the Y direction from the transistor region RTrRa to the connection wiring region RCL2, and has the function of electrically connecting the electrode of the other side of the transistor TrRa (FIG. 1) to the layer select line LL (FIG. 1). The conductive layer 221, for example, contains a conductive oxide. Alternatively, the conductive layer 221 may contain ruthenium (Ru), iridium (Ir), or other metals instead of a conductive oxide. Furthermore, the conductive layer 221 may also contain only a conductive oxide, or only ruthenium (Ru), iridium (Ir), or other metals.

[0069] The conductive layer 221 may, for example, be as shown in FIG. 12, having a portion formed below the insulating layer 103, a portion formed above the insulating layer 103, and a portion formed on one side (the insulating layer 201 side) of the semiconductor layer 213 in the X direction. Furthermore, insulating layers 223 and 224 such as silicon oxide (SiO2) may also be provided in the area surrounded by the conductive layer 221.

[0070] The conductive layer 222 is connected to the semiconductor layer 213. As shown in FIG. 5, the conductive layer 222 extends in the Y direction from the transistor region RTrRa to the connection wiring region RCL1, and functions to electrically connect one of the electrodes of the transistor TrRa (FIG. 1) to the word line WL (FIG. 1). The conductive layer 222 may, for example, contain a conductive oxide. Alternatively, the conductive layer 222 may contain ruthenium (Ru), iridium (Ir), or other metals instead of a conductive oxide. Furthermore, the conductive layer 222 may also contain only a conductive oxide, or only ruthenium (Ru), iridium (Ir), or other metals.

[0071] The conductive layer 222 may, for example, be as shown in FIG. 12, having a portion formed below the insulating layers 103 and 214, a portion formed above the insulating layers 103 and 214, and a portion formed on the side of the semiconductor layer 213 in the X direction (the insulating layer 202 side). Furthermore, in the area surrounded by the conductive layer 222, insulating layers 223 and 224 such as silicon oxide (SiO2) may also be provided.

[0072] [Structure of Connection Wiring Area RCL1] As shown in FIG. 5, insulating layers 301 and 302 arranged side by side in the Y direction are provided in the connection wiring area RCL1. Insulating layer 301 is connected to the Y-direction end of insulating layer 101. Insulating layer 302 is provided on the memory cell region RMC side relative to insulating layer 301. Insulating layer 302 is connected to the Y-direction end of insulating layer 202. Insulating layers 301 and 302 extend in the X and Z directions and divide the plurality of memory layers ML in the Y direction. Insulating layers 301 and 302 may contain, for example, silicon oxide (SiO2).

[0073] Furthermore, in the region between the insulating layer 301 and the insulating layer 302 in the wiring area RCL1, an insulating layer 304 of silicon oxide (SiO2) or the like is provided. The insulating layer 304, for example, extends in the Z direction through a plurality of memory layers ML, as shown in FIG10.

[0074] The memory layer ML has a plurality of connection wiring portions 310 disposed corresponding to the plurality of conductive layers 120. The connection wiring portion 310, for example, as shown in FIG9, has a semiconductor layer 311 such as silicon (Si) disposed on the outer peripheral surface of the insulating layer 304, and conductive layers 312 disposed on the upper, lower and outer peripheral surfaces of the semiconductor layer 311.

[0075] In the XY cross-section as illustrated in FIG9, the side surfaces of the semiconductor layer 311 and the conductive layer 312 in the X direction can also be formed along a circle centered on the center position of the insulating layer 304. Furthermore, the side surfaces of the semiconductor layer 311 and the conductive layer 312 in the Y direction can also be formed in a straight line along the side surfaces of the insulating layers 301 and 302 in the Y direction.

[0076] One side of the conductive layer 312 in the X direction is connected to the conductive layer 120. The other side of the conductive layer 312 in the X direction is connected to the conductive layer 222. The conductive layer 312 has the function of electrically connecting one of the electrodes of the transistor TrRa (FIG. 1) to the word line WL (FIG. 1).

[0077] [Structure of Connection Wiring Area RCL2] As shown in Figure 5, insulating layers 401 and 402 are provided side-by-side in the Y direction at the connection wiring area RCL2. Insulating layer 402 is provided on the memory cell region RMC side relative to insulating layer 401. Insulating layer 402 is connected to the Y-direction end of insulating layer 202. Insulating layers 401 and 402 extend in the X and Z directions, and divide the plurality of memory layers ML in the Y direction. Insulating layers 401 and 402 may contain, for example, silicon oxide (SiO2).

[0078] Furthermore, in the area between the insulating layer 401 and the insulating layer 402 in the wiring connection area RCL2, an insulating layer 404 of silicon oxide (SiO2) or the like is provided. The insulating layer 404 extends in the Z direction through a plurality of memory layers ML.

[0079] The memory layer ML has a plurality of connection wiring portions 410 disposed corresponding to the plurality of conductive layers 120. The connection wiring portion 410 has a semiconductor layer 411 of silicon (Si) or the like disposed on the outer peripheral surface of the insulating layer 404, and conductive layers 412 disposed on the upper surface, lower surface and outer peripheral surface of the semiconductor layer 411.

[0080] In the XY cross-section as illustrated in Figure 5, the side surfaces of the semiconductor layer 411 and the conductive layer 412 in the X direction can also be formed along a circle centered on the center of the insulating layer 404. Furthermore, the side surfaces of the semiconductor layer 411 and the conductive layer 412 in the Y direction can also be formed in a straight line along the side surfaces of the insulating layers 401 and 402 in the Y direction.

[0081] One side of the conductive layer 412 in the X direction is connected to the conductive layer 221. The other side of the conductive layer 412 in the X direction is connected to the conductive layer 501 in the wiring region RLL. The conductive layer 412 has the function of electrically connecting the other electrode of the transistor TrRa (FIG. 1) to the layer select line LL (FIG. 1).

[0082] [Structure of Wiring Area RLL] The memory layer ML has a conductive layer 501 extending in the X direction. The conductive layer 501, for example, functions as a layer select line LL (FIG. 1). The conductive layer 501 is connected to a plurality of conductive layers 412 arranged side by side in the X direction. The conductive layer 501, for example, has a laminated structure comprising titanium nitride (TiN) and tungsten (W).

[0083] [Structure of transistor region RTrRb] As shown in FIG6, at transistor region RTrRb, there are a plurality of conductive layers 601 arranged side by side in the X direction corresponding to the plurality of insulating layers 101, conductive layers 602 disposed on the X and Y side surfaces of conductive layers 601, and insulating layers 202 disposed between two adjacent conductive layers 601 in the X direction (between two adjacent conductive layers 602 in the X direction).

[0084] Conductive layers 601 and 602, as shown in Figures 6 and 15, extend in the Y and Z directions, and divide the plurality of memory layers ML in the X direction. Conductive layer 601, for example, comprises a laminated structure of titanium nitride (TiN) and tungsten (W). Conductive layer 602, for example, comprises a conductive oxide. Alternatively, conductive layer 602 may replace the conductive oxide with ruthenium (Ru), iridium (Ir), or other metals. Furthermore, conductive layer 602 may also comprise only a conductive oxide, or only ruthenium (Ru), iridium (Ir), or other metals. Conductive layers 601 and 602, for example, function as wiring NLL (Figure 1).

[0085] Furthermore, in the region between the conductive layers 601 and 602 and the insulating layer 202 in the transistor region RTrRb, a plurality of via wirings 204 are provided. That is, in the transistor region RTrRb, the conductive layers 601 and 602 and the insulating layer 202 are arranged side by side with the plurality of via wirings 204 in the X direction.

[0086] The memory layer ML includes "a portion of a plurality of transistor structures 610 disposed corresponding to a plurality of conductive layers 120", "a conductive layer 621 disposed between the transistor structure 610 and the conductive layer 601", and "a conductive layer 622 disposed between the transistor structure 610 and the insulating layer 202".

[0087] The transistor structure 610, as shown in FIG. 14, includes a portion disposed in the memory layer ML and a portion disposed at a height position corresponding to the insulating layer 103. The portion disposed in the memory layer ML, as shown in FIG. 13, includes "a plurality of insulating layers 211 disposed on the outer peripheral surface of a plurality of via wirings 204" and "a semiconductor layer 613 disposed on the outer peripheral surface of these plurality of insulating layers 211 and extending in the Y direction". The portion disposed at a height position corresponding to the insulating layer 103, as shown in FIG. 14, includes "an insulating layer 614 disposed above and below the semiconductor layer 613" and "a conductive layer 615 disposed above and below the insulating layer 614".

[0088] The semiconductor layer 613, insulating layer 614, and conductive layer 615 are basically constructed in the same manner as the semiconductor layer 213, insulating layer 214, and conductive layer 215 (Figs. 11 and 12). However, the semiconductor layer 613, insulating layer 614, and conductive layer 615 function as the channel region, gate insulating film, and gate electrode of the transistor TrRb (Fig. 1), respectively. Furthermore, in the transistor region RTrRb, conductive layers 601, 602, and insulating layer 202 are arranged side by side with the semiconductor layer 613, insulating layer 614, and conductive layer 615 in the X direction.

[0089] The conductive layer 621 is connected to one side of the semiconductor layer 613 in the X direction (the conductive layer 601 side). The conductive layer 621 is embedded in the region between two adjacent insulating layers 103 in the Z direction. As shown in Figures 6 and 15, the conductive layer 621 is connected to the conductive layer 602 and has the function of electrically connecting the other electrode of the transistor TrRb (Figure 1) to the wiring NLL (Figure 1). The conductive layer 621 may, for example, contain a conductive oxide. Alternatively, the conductive layer 621 may contain ruthenium (Ru), iridium (Ir), or other metals instead of a conductive oxide. Furthermore, the conductive layer 621 may also contain only a conductive oxide, or only ruthenium (Ru), iridium (Ir), or other metals.

[0090] The conductive layer 622 is basically constructed in the same manner as the conductive layer 222. However, the conductive layer 622 is connected to the semiconductor layer 613. Furthermore, the conductive layer 622, as shown in FIG. 6, extends in the Y direction from the transistor region RTrRb to the connection wiring region RCL1, and has the function of electrically connecting one of the electrodes of the transistor TrRb (FIG. 1) to the word line WL (FIG. 1).

[0091] [Manufacturing Method] Figures 16 to 118 are schematic cross-sectional views used to explain the manufacturing method of the semiconductor memory device of the first embodiment. Figures 16, 25, 27, 30, 32, 34, 37, 39, 42, 44, 46, 49, 51, 53, 55, 57, 59, 61, 103, 105, 107, 109, 111, 113, 115 and 117 show cross-sections corresponding to those in Figure 7. Figures 17, 26, 28, 29, 31, 33, 35, 36, 38, 40, 43, 45, 47, 50, 52, 54, 56, 58, 60, 62, 104, 106, 108, 110, 112, 114, 116, and 118 show cross-sections corresponding to Figure 8. Figures 18, 41, 48, and 69 show cross-sections corresponding to Figure 6. Figures 19, 21, 23, 70, 74, 82, 86, 90, 94, 96, and 98 show cross-sections corresponding to Figure 9. Figures 20, 22, 24, 71, 75, 83, 87, 91, 95, 97, 99, and 100 show cross-sections corresponding to Figure 10. Figures 63, 67, 72, 76, 78, 80, 84, 88, 92, and 101 show cross-sections corresponding to Figure 13. Figures 64, 65, 66, 68, 73, 77, 79, 81, 85, 89, 93, and 102 show cross-sections corresponding to Figure 14.

[0092] In this manufacturing method, for example as shown in FIG17, a plurality of insulating layers 103 and a plurality of sacrificial layers MLA are alternately formed. The sacrificial layers MLA may contain, for example, silicon nitride (Si3N4). This process is performed, for example, by CVD (Chemical Vapor Deposition).

[0093] Next, insulating layers 115, 301, 302, and 402 are formed, for example, as shown in Figures 16 and 18. Also, although not shown in the figures, insulating layer 401 is formed (Figure 5). In this process, for example, openings are formed at positions corresponding to insulating layers 115, 301, 302, 401, and 402. These openings extend in the X and Z directions, and the plurality of insulating layers 103 and the plurality of sacrificial layers MLA arranged side-by-side in the Z direction are interrupted in the Y direction. This process is performed, for example, by means of RIE (Radio Interchange Equipment). After the openings are formed, insulating layers 115, 301, 302, 401, and 402 are formed. This process is performed, for example, by CVD (Continuous Chemical Deposition).

[0094] Next, as shown in Figures 19 and 20, an opening 304A is formed at a position corresponding to the insulating layer 304. The opening 304A, as shown in Figure 20, extends in the Z direction and penetrates the plurality of insulating layers 103 and the plurality of sacrificial layers MLA arranged side-by-side in the Z direction. This process is performed, for example, by means of a RIE (Relative Insulation Layer).

[0095] Furthermore, although the illustration is omitted, the connecting wiring portion 410 (Fig. 5) is formed in the same manner as the connecting wiring portion 310. For example, in this process, an opening identical to the opening 304A is formed at the position corresponding to the insulating layer 404 (Fig. 5). Similarly, in the following processes, the work performed at the position corresponding to the connecting wiring portion 310 is also performed at the position corresponding to the connecting wiring portion 410.

[0096] Next, as shown in Figures 21 and 22, an opening 310A is formed at a position corresponding to the connection wiring portion 310. Inside the opening 310A, a portion of the upper and lower parts of the insulating layer 103, a portion of the X-direction side of the sacrificial layer MLA, and a portion of the Y-direction side of the insulating layers 301 and 302 are exposed. In this process, for example, a portion of the sacrificial layer MLA is selectively removed through the opening 304A. This process is performed, for example, by wet etching.

[0097] Next, for example as shown in Figures 23 and 24, a sacrificial layer 304B of silicon (Si) or the like is formed inside the openings 310A and 304A. This process is performed, for example, by CVD or the like.

[0098] Next, as shown in Figures 25 and 26, an opening 104A is formed at a position corresponding to the through-hole wiring 104. The opening 104A, as shown in Figure 26, extends in the Z-direction and penetrates a plurality of insulating layers 103 and a plurality of sacrificial layers MLA arranged side-by-side in the Z-direction. This process is performed, for example, by means of a RIE (Relative Insulation Layer).

[0099] Next, as shown in Figures 27 and 28, an opening 111A is formed at a position corresponding to the semiconductor layer 111. Inside the opening 111A, a portion of the upper and lower parts of the insulating layer 103, a portion of the X-direction side of the sacrificial layer MLA, and a portion of the Y-direction side of the insulating layer 115 are exposed. In this process, for example, a portion of the sacrificial layer MLA is selectively removed via the opening 104A. This process is performed, for example, by wet etching.

[0100] Next, for example as shown in FIG29, a portion of the insulating layer 103 is removed. In this process, the width of the opening 111A in the Z direction is widened. This process is performed, for example, by wet etching.

[0101] Next, as shown in Figures 30 and 31, for example, an insulating layer 114A is formed on the inner peripheral surface of opening 104A, the inner peripheral surface of opening 111A, and the upper and lower surfaces of insulating layer 103. Insulating layer 114A contains silicon oxide (SiO2) containing boron (B). This process is performed, for example, by CVD or the like.

[0102] Next, as shown in Figures 32 and 33, a conductive layer 113A and a sacrificial layer 111B of silicon (Si) or the like are formed inside openings 111A and 104A. The conductive layer 113A is formed on the top and bottom surfaces of the insulating layer 114A, on the exposed surface of opening 104A, on the exposed surface of opening 111A, and on both sides in the Y direction. Opening 111A is filled by the sacrificial layer 111B, while opening 104A is not filled by the sacrificial layer 111B. This process is performed, for example, by CVD.

[0103] Next, for example as shown in Figures 34 and 35, a portion of the sacrificial layer 111B is removed, exposing the portion of the conductive layer 113A that is positioned at a height corresponding to the insulating layer 103. This process is performed, for example, by wet etching.

[0104] Next, for example as shown in FIG36, the portion of conductive layer 113A that is disposed at a height position corresponding to insulating layer 103 is removed. This process is performed, for example, by wet etching.

[0105] Next, for example as shown in Figures 37 and 38, the sacrificial layer 111B is removed. This process is performed, for example, by wet etching.

[0106] Next, for example as shown in Figures 39 and 40, a sacrificial layer 104B of silicon (Si) or the like is formed inside the openings 111A and 104A. This process is performed, for example, by CVD or the like.

[0107] Next, for example as shown in FIG41, an opening 101A is formed at a position corresponding to the insulating layer 101. The opening 101A extends in the Y and Z directions and penetrates the plurality of insulating layers 103 and the plurality of sacrificial layers MLA arranged side by side in the Z direction, thus dividing these structures in the X direction. This process is performed, for example, by means of a RIE (Relative Insulation Layer).

[0108] Furthermore, although the illustration is omitted, the conductive layer 501 (Fig. 5) is formed in the same manner as the conductive layer 120. For example, in this process, an opening is also formed near the conductive layer 501 (Fig. 5). This opening extends in both the X and Z directions and penetrates the plurality of insulating layers 103 and the plurality of sacrificial layers MLA arranged side by side in the Z direction, thus interrupting these structures in the Y direction. Similarly, in the following process, the process performed at the position corresponding to the conductive layer 120 is also performed at the position corresponding to the conductive layer 501.

[0109] Next, as shown in Figures 42 and 43, an opening 120A is formed at a position corresponding to the conductive layer 120. Inside the opening 120A, a portion of the upper and lower parts of the insulating layer 103, the X-direction side surface of the insulating layer 114A, and the X-direction side surface of the insulating layer 115 are exposed. In this process, for example, the sacrificial layer MLA is removed through the opening 101A. This process is performed, for example, by wet etching.

[0110] Next, for example as shown in Figures 44 and 45, a portion of the insulating layer 114A exposed at the openings 120A and 101A in the X direction of the conductive layer 113A is removed via the openings 120A and 101A. This process is performed, for example, by wet etching.

[0111] Next, as shown in Figures 46 and 47, a conductive layer 120 is formed. In this process, for example, a barrier conductive film 121 and a conductive film 122 are formed inside the openings 120A and 101A by a method such as CVD. In this process, the opening 120A is filled by the barrier conductive film 121 and the conductive film 122, while the opening 101A is not filled. Next, for example, a portion of the barrier conductive film 121 and the conductive film 122 formed inside the opening 101A is removed by a method such as wet etching. In addition, although the illustration is omitted, after this process, an insulating layer 101 is formed inside the opening 101A.

[0112] Next, as shown in Figures 48-50, an opening 102A is formed at a position corresponding to the conductive layer 102. The opening 102A extends in the Y and Z directions and penetrates the plurality of insulating layers 103 and the plurality of sacrificial layers MLA and insulating layers 115 arranged side by side in the Z direction, thus interrupting the configuration in the X direction. This process is performed, for example, by means of a RIE (Radio Interchange Equipment).

[0113] Next, for example as shown in Figures 51 and 52, an opening 130A is formed at a position corresponding to the capacitor structure 130. In this process, the sacrificial layer MLA is removed through the opening 102A. This process is performed, for example, by wet etching.

[0114] Next, as shown in Figures 53 and 54, an insulating layer 114 is formed. In this process, for example, a portion of the insulating layer 114A located on the side of the conductive layer 113A in the X direction of the opening 102A is removed via openings 102A and 130A. This process is performed, for example, by wet etching.

[0115] Next, as shown in Figures 55 and 56, a conductive layer 113 is formed. In this process, for example, a portion of the conductive layer 113A located on the side of the sacrificial layer 104B in the X direction of the opening 102A is removed via openings 102A and 130A. This process is performed, for example, by wet etching.

[0116] Next, for example as shown in Figures 57 and 58, the sacrificial layer 104B is removed. This process is performed, for example, by wet etching.

[0117] Next, as shown in Figures 59 and 60, insulating layers 112 and 134 and a semiconductor layer 111C are formed inside openings 111A, 104A, 130A, and 102A. Insulating layers 112 and 134 are formed at the following locations: the exposed surface of conductive layer 113 opposite to opening 111A; the upper portion, the lower portion, and the exposed surface of insulating layer 103 opposite to opening 102A; the exposed surface of insulating layer 114 opposite to opening 104A; and a portion of the Y-direction side surface of insulating layer 115. Opening 111A is filled by the semiconductor layer 111C, while openings 104A, 130A, and 102A are not filled by the semiconductor layer 111C. This process is performed, for example, by CVD.

[0118] Next, as shown in Figures 61 and 62, a sacrificial layer 104C of silicon (Si) or the like is formed inside the opening 104A. Also, a sacrificial layer 102B of silicon (Si) or the like is formed inside the openings 102A and 130A. This process is performed, for example, by CVD or the like.

[0119] Next, as shown in Figures 63 and 64, an opening 204A is formed at a position corresponding to the through-hole wiring 204. The opening 204A, as shown in Figure 64, extends in the Z-direction and penetrates a plurality of insulating layers 103 and a plurality of sacrificial layers MLA arranged side-by-side in the Z-direction. This process is performed, for example, by means of a RIE (Relative Insulation Layer).

[0120] Next, for example as shown in FIG. 65, an opening 615A is formed at a position corresponding to the conductive layer 615. Inside the opening 615A, a portion of the upper and lower parts of the sacrificial layer MLA are exposed. In this process, for example, a portion of the insulating layer 103 is selectively removed through the opening 204A. This process is performed, for example, by wet etching.

[0121] Furthermore, although the illustrations are omitted, the conductive layer 215, insulating layer 214, and semiconductor layer 213 (FIG. 12) are formed in the same manner as the conductive layer 615, insulating layer 614, and semiconductor layer 613, respectively. For example, in this process, an opening is also formed at a position corresponding to the conductive layer 215 (FIG. 12). In this process, for example, a portion of the insulating layer 103 is selectively removed via the opening 204A. Similarly, in the following processes, the processes performed at the positions corresponding to the conductive layer 615, insulating layer 614, and semiconductor layer 613 are also performed at the positions corresponding to the conductive layer 215, insulating layer 214, and semiconductor layer 213.

[0122] Next, for example as shown in FIG. 66, a portion of the sacrificial layer MLA is removed. In this process, the width of the opening 615A in the Z direction is widened. This process is performed, for example, by wet etching.

[0123] Next, for example as shown in Figures 67 and 68, insulating layers 211 and 614, conductive layer 615, and through-hole wiring 204 are formed inside the openings 615A and 204A. This process is performed, for example, by CVD or the like.

[0124] Furthermore, as shown in Figures 69-73, openings 601A and 202A are formed at positions corresponding to the conductive layer 601 and the insulating layer 202. Also, although not shown in the figures, the same opening as opening 601A is formed at a position corresponding to the insulating layer 201 (Figure 5). Openings 601A and 202A, and the opening corresponding to the insulating layer 201 (Figure 5), extend in the Y and Z directions and penetrate the plurality of insulating layers 103 and the plurality of sacrificial layers MLA arranged side-by-side in the Z direction, thus dividing this configuration in the X direction. This process is performed, for example, by means of a RIE (Radio Interchange Equipment).

[0125] Next, as shown in Figures 74-77, openings 222A, 621A, 622A, and 613A are formed at positions corresponding to conductive layers 222, 621, 622 and semiconductor layer 613. Inside openings 222A and 622A, a portion of the upper and lower parts of insulating layer 103, as well as a portion of one side of insulating layers 302 and 402 in the Y direction, are exposed. Inside opening 621A, a portion of the upper and lower parts of insulating layer 103, as well as a portion of one side of insulating layer 301 in the Y direction, are exposed. Inside opening 613A, a portion of the upper and lower parts of insulating layer 614, the outer peripheral surface of insulating layer 211, and a portion of one side of insulating layers 301 and 402 in the Y direction are exposed. In this process, for example, a portion of the sacrificial layer MLA is selectively removed via openings 222A, 621A, and 622A. This process is performed, for example, by wet etching.

[0126] Next, as shown in Figures 78 and 79, a semiconductor layer 613B is formed inside the openings 613A, 622A, 202A, 621A, and 601A. The opening 613A is filled by the semiconductor layer 613B, while the openings 622A, 202A, 621A, and 601A are not filled by the semiconductor layer 613B. This process is performed, for example, by CVD.

[0127] Next, a semiconductor layer 613 is formed, for example as shown in Figures 80 and 81. In this process, a portion of the semiconductor layer 613B is removed, for example, by a method such as wet etching. Specifically, the portion of the semiconductor layer 613B formed inside the opening 613A is left, and the rest is removed. Then, the upper part of the opening 601A is closed by an insulating layer or the like (not shown).

[0128] Next, as shown in Figures 82 and 83, a conductive layer 222B, an insulating layer 223A, and a sacrificial layer 224A are formed inside the openings 222A and 202A. Also, as shown in Figures 84 and 85, a conductive layer 622B, an insulating layer 223A, and a sacrificial layer 224A are formed inside the openings 622A and 202A. The conductive layers 222B and 622B are formed at: "the upper portion, the lower portion, and the exposed surface of the insulating layer 103 facing the opening 202A", "the upper portion and the lower portion of the insulating layers 214 and 614", "the outer peripheral surface of the semiconductor layers 213 and 613", "one side of the insulating layer 301 in the X direction", and "one side of the insulating layers 302 and 402 in the Y direction". Openings 222A and 622A are filled using insulating layer 223A and sacrificial layer 224A, while opening 202A is not filled using insulating layer 223A and sacrificial layer 224A. This work is carried out, for example, by ALD, CVD, etc.

[0129] Furthermore, in this process, a conductive layer, an insulating layer 223A, and a sacrificial layer 224A corresponding to the conductive layer 221 are formed inside an opening (not shown) corresponding to the conductive layer 221 (Figs. 11 and 12) and the insulating layer 201 (Fig. 5). The conductive layer (not shown) corresponding to the conductive layer 221 is formed at "the upper part, the lower part, and the exposed surface of the opening (not shown) corresponding to the insulating layer 201 of the insulating layer 103", "the upper part and the lower part of the insulating layer 214", "the outer peripheral surface of the semiconductor layer 213", "one side of the insulating layer 402 in the X direction", and "one side of the insulating layers 301 and 401 in the Y direction". The opening (not shown) corresponding to the conductive layer 221 is filled by the insulating layer 223A and the sacrificial layer 224A, while the opening (not shown) corresponding to the insulating layer 201 is not filled by the insulating layer 223A and the sacrificial layer 224A.

[0130] Next, as shown in Figures 86-89, conductive layers 222 and 622 and insulating layer 223 are formed. Also, conductive layer 221 (Figures 11 and 12) is formed. In this process, portions of conductive layers 222B and 622B, the conductive layer (not shown) corresponding to conductive layer 221, insulating layer 223A, and sacrificial layer 224A that are exposed at the opening 202A of insulating layer 103 and the opening (not shown) corresponding to insulating layer 201 (Figure 5) are removed, exposing insulating layer 103 at opening 202A. Thus, conductive layers 222B and 622B, the conductive layer (not shown) corresponding to conductive layer 221, and insulating layer 223A are separated in the Z direction, and conductive layers 222, 622, 221, and insulating layer 223 are formed. This process is performed, for example, by wet etching.

[0131] Next, as shown in Figures 90-93, the sacrificial layer 224A is removed. This process is performed, for example, by wet etching.

[0132] Next, as shown in Figures 94 and 95, the sacrificial layer 304B is removed. This process is performed, for example, by wet etching.

[0133] Next, as shown in Figures 96 and 97, a conductive layer 312B and a semiconductor layer 311B are formed inside openings 311A ​​and 304A. The conductive layer 312B is formed on "the upper portion, the lower portion, and the exposed surface of the insulating layer 103 facing opening 304A", "one side of the conductive layer 222 in the X direction", and "one side of the conductive layer 120 in the X direction". Opening 311A ​​is filled by the semiconductor layer 311B, while opening 304A is not filled by the semiconductor layer 311B. This process is performed, for example, by CVD.

[0134] Next, as shown in Figures 98 and 99, a semiconductor layer 311 is formed. In this process, a portion of the semiconductor layer 311B formed at the inner peripheral surface of the insulating layer 103 opposite the opening 304A is removed, exposing a portion of the conductive layer 312B at the opening 304A. Thus, the semiconductor layer 311B is segmented in the Z direction, and a plurality of semiconductor layers 311 arranged side-by-side in the Z direction are formed. This process is performed, for example, by wet etching.

[0135] Next, as shown in FIG. 100, a conductive layer 312 is formed. In this process, the portion of the conductive layer 312B formed at the inner peripheral surface of the insulating layer 103 opposite the opening 304A is removed, exposing the insulating layer 103 at the opening 304A. Thus, the conductive layer 312B is segmented in the Z direction, and a plurality of conductive layers 312 arranged side-by-side in the Z direction are formed. This process is performed, for example, by wet etching.

[0136] Next, as shown in Figures 9-12, 101, and 102, an insulating layer 224 is formed inside openings 222A, 622A, and an opening (not shown) corresponding to conductive layer 221, and an insulating layer 202 is formed inside opening 202A. Furthermore, an insulating layer 304 is formed inside opening 304A. This process is performed, for example, by CVD or the like.

[0137] Next, as shown in FIG15, conductive layers 621, 602, and 601 are formed inside the openings 621A and 601A. This process is performed, for example, by ALD and CVD.

[0138] Next, for example as shown in Figures 103 and 104, the sacrificial layer 102B is removed. This process is performed, for example, by wet etching.

[0139] Next, as shown in Figures 105 and 106, a semiconductor layer 111 is formed. In this process, a portion of the semiconductor layer 111C formed at the exposed surfaces of the insulating layer 134 opposite to the openings 130A and 102A is removed, and the semiconductor layer 111C is divided in the Y and Z directions. This process is performed, for example, by wet etching.

[0140] Next, as shown in Figures 107 and 108, a conductive layer 133A, an insulating layer 130B, and a sacrificial layer 130C are formed on one side of the semiconductor layer 111 in the X direction (the side of the opening 102A) and at the exposed surface of the insulating layer 134 opposite to the openings 130A and 102A. This process is performed, for example, by ALD, CVD, etc.

[0141] Next, for example as shown in Figures 109 and 110, a portion of the sacrificial layer 130C is removed through the opening 102A. In this process, for example, the portion of the insulating layer 130B corresponding to the "side surface of the insulating layer 115 and the insulating layer 103 in the X direction" is exposed. This process is performed, for example, by wet etching.

[0142] Next, for example as shown in Figures 111 and 112, a portion of the insulating layer 130B is removed through the opening 102A. In this process, for example, the portion of the conductive layer 133A corresponding to the "side surface of the insulating layer 115 and the insulating layer 103 in the X direction" is exposed. This process is performed, for example, by wet etching.

[0143] Next, as shown in Figures 113 and 114, a conductive layer 113 is formed. In this process, for example, the portion of the conductive layer 133A that is disposed on the "side surface of the insulating layer 115 and the insulating layer 103 in the X direction" is removed, and the conductive layer 133A is divided in the Y and Z directions. This process is performed, for example, by wet etching.

[0144] Next, for example as shown in Figures 115 and 116, the sacrificial layer 130C and the insulating layer 130B are removed through the opening 102A. This process is performed, for example, by wet etching.

[0145] Next, as shown in Figures 117 and 118, a capacitor structure 130 and a conductive layer 102 are formed. In this process, for example, an insulating layer 132 and conductive layers 131 and 102 are formed on the top and bottom surfaces of the conductive layer 133, on one side in the X direction (the side of the opening 102A), and on both sides in the Y direction, as well as on the X-direction side of the insulating layer 134. This process is performed, for example, by CVD or the like.

[0146] Subsequently, by removing the sacrificial layer 104C and forming via wiring 104 (Figs. 7 and 8), the semiconductor memory device of the first embodiment is manufactured.

[0147] [Effect] As explained with reference to FIG1, in the semiconductor memory device of the first embodiment, the gate voltages of transistors TrRa and TrRb are common between the plurality of memory layers ML. Based on this configuration, as explained with reference to FIG12, the conductive layer 215, which functions as the gate electrode of transistors TrRa and TrRb, can be positioned at a height corresponding to the insulating layer 103, and can be provided as the common gate electrode for two adjacent transistors TrRa and TrRb in the Z direction. This allows for the thickening of the gate insulating film of transistors TrRa and TrRb without hindering the high integration of the semiconductor memory device. Therefore, the voltage VON' explained with reference to FIG2 can be set to a voltage significantly larger than VON, and the transmission of the voltage VON to the select word line WL during readout operations can be accelerated.

[0148] Herein, in order to connect the multiple layer select lines LL to the surrounding circuitry, for example, it is possible to provide a platform portion at the multiple conductive layers 501 (FIG. 5), and connect via contact electrodes at this platform portion. A platform portion, for example, is a portion of the conductive layer 501 that does not overlap with other conductive layers when viewed from above. At the memory cell array MCA, the number of platform portions is the same as the number of memory layers ML arranged side-by-side in the Z direction.

[0149] Here, as explained with reference to FIG2, two transistors TrRa and TrRb are connected at the character line WL. In implementing this configuration, for example, it is also possible to provide the transistor region RTrRa and the wiring region RLL, as explained with reference to FIG5, on one side and the other side of the memory cell region RMC (FIG. 5 and FIG. 6) in the Y direction, respectively. However, when using this configuration, it becomes necessary to provide the same number of platform portions as the number of memory layers ML arranged side-by-side in the Z direction on one side and the other side of the memory cell region RMC (FIG. 5 and FIG. 6), which may hinder the reduction of circuit area.

[0150] Therefore, in this embodiment, in the region on the other side of the memory cell region RMC in the Y direction, a plurality of conductive layers 621 arranged side by side in the Z direction are connected in a common manner with conductive layers 601 and 602 extending in the Z direction, and the wiring region RLL is omitted. With this configuration, the platform portion is omitted in the region on the other side of the memory cell region RMC in the Y direction, and the circuit area of ​​the memory cell array MCA can be reduced.

[0151] Furthermore, when multiple conductive layers 621 arranged side-by-side in the Z direction are connected in a common manner with conductive layers extending in the Z direction, for example, it is also possible to provide conductive layers extending in the Z direction at a position corresponding to the wiring region RLL in a region on the other side of the memory cell region RMC in the Y direction. However, in this embodiment, conductive layers 601 and 602 are provided in a position in the X direction alongside the semiconductor layer 613, the insulating layer 614, and the conductive layer 615. With this configuration, since there is no need to provide additional areas for conductive layers 601 and 602, the circuit area of ​​the memory cell array MCA can be further reduced.

[0152] Furthermore, in the transistor structure 110 of this embodiment, the conductive layer 113 is opposite to the top, bottom and two sides in the Y direction of the semiconductor layer 111.

[0153] In this configuration, interference of electric fields between a plurality of semiconductor layers 111 arranged side by side in the Z direction can be suppressed. Therefore, even when the memory cell array (MCA) is highly integrated in the Z direction, the semiconductor layers 111 can be appropriately controlled to be in the ON or OFF state, thereby providing a semiconductor memory device that can operate appropriately.

[0154] Furthermore, when the transistor TrC is set to the ON state, channels are formed on the top and bottom surfaces of the semiconductor layer 111 and on both sides in the Y direction. Therefore, the ON current of the transistor TrC can be set to a larger value. This allows for faster and more stable operation.

[0155] Furthermore, in this embodiment, the conductive layer 120, which functions as the character line WL, is disposed on the opposite side of the board line PL relative to the transistor structure 110, and is disposed at a position that does not overlap with the transistor structure 110 when viewed from the Z direction. Therefore, the conductive layer 120 and the transistor structure 110 can be formed independently of each other, making manufacturing easier. Furthermore, the wiring resistance of the conductive layer 120 can be set to a smaller value while suppressing the width of the memory layer ML in the Z direction.

[0156] [Second Embodiment] [Structure] Next, referring to FIG119, a semiconductor memory device according to the second embodiment will be described. FIG119 is a schematic XY cross-sectional view showing a portion of the structure of the semiconductor memory device according to the second embodiment.

[0157] The semiconductor memory device of the second embodiment is basically constructed in the same manner as the semiconductor memory device of the first embodiment.

[0158] However, as explained with reference to FIG5 and FIG6, in the first embodiment, the transistor region RTrRa corresponding to the transistor TrRa is disposed on one side of the memory cell region RMC in the Y direction, and the transistor region RTrRb corresponding to the transistor TrRb is disposed on the other side of the Y direction relative to the memory cell region RMC.

[0159] On the other hand, as shown in FIG119, in the second embodiment, the transistor region RTrRa' corresponding to the transistor TrRa is disposed on one side of the memory cell region RMC in the Y direction, and the transistor region RTrRb' corresponding to the transistor TrRb is disposed between the memory cell region RMC and the transistor region RTrRa'.

[0160] Between the transistor regions RTrRa' and RTrRb', a plurality of insulating layers 701 are disposed side-by-side in the X direction, corresponding to the insulating layer 101. The insulating layer 701 extends in both the X and Z directions and divides the plurality of memory layers ML in the Y direction. The insulating layer 701 may contain, for example, silicon oxide (SiO2).

[0161] The transistor regions RTrRa' and RTrRb' are basically constructed in the same manner as the transistor regions RTrRa and RTrRb. However, in place of the transistor regions RTrRa' and RTrRb', a conductive layer 722 is provided instead of conductive layers 222 and 622. The conductive layer 722 is basically constructed in the same manner as the conductive layers 222 and 622. However, the conductive layer 722 extends from the transistor region RTrRa' through the transistor region RTrRb' in the Y direction to the connection wiring region RCL1, and has the function of electrically connecting one of the electrodes of the transistor TrRa (FIG. 1) and the transistor TrRb (FIG. 1) and the word line WL (FIG. 1).

[0162] Based on this configuration, the number of connection wiring regions RCL1 used to connect the configurations between regions can be reduced, and the circuit area of ​​the memory cell array MCA can be further reduced.

[0163] [Other Embodiments] The above description pertains to the semiconductor memory device of the first and second embodiments. However, these semiconductor memory devices are merely examples and may be adjusted to suitably suit specific configurations.

[0164] For example, in the semiconductor memory devices of the first and second embodiments, the via wiring 104, which functions as a bit line, contains a conductive oxide such as indium tin oxide (ITO). However, this conductive oxide may not be contained in the via wiring 104 extending in the Z direction, but rather in the transistor structure 110. Furthermore, the via wiring 104 and the transistor structure 110 may also contain other materials.

[0165] Furthermore, in the semiconductor memory device of the first and second embodiments, the conductive layers 113, 215, and 615 that function as gate electrodes of transistors TrC, TrRa, and TrRb may also be opposite to only one of the upper and lower surfaces of the semiconductor layers 111, 213, and 613 that function as channel regions of transistors TrC, TrRa, and TrRb.

[0166] Furthermore, in the semiconductor memory devices of the first and second embodiments, the semiconductor layers 111, 213, and 613 that function as channel regions of transistors TrC, TrRa, and TrRb can also be positioned above and below the conductive layers 113, 215, and 615 that function as gate electrodes of transistors TrC, TrRa, and TrRb.

[0167] Furthermore, in the above description, the memory section connected to the transistor structure 110 was described with reference to an example using a capacitor CpC. However, the memory section may not be a capacitor CpC. For example, the memory section may also be a chalcogenide material containing strong dielectrics, strong magnetic materials, GeSbTe, or other materials, and utilize the properties of these materials to record data. For example, in any of the structures described above, any of these materials may be included in the insulating layer between the electrodes forming the capacitor CpC.

[0168] Furthermore, the manufacturing methods of the semiconductor memory device in the first and second embodiments can also be appropriately adjusted. For example, the order of any two of the above-mentioned processes can be interchanged, or any two of the above-mentioned processes can be performed simultaneously.

[0169] [Others] Although several embodiments of the present invention have been described, these embodiments are merely illustrative examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or their variations are also included in the scope or spirit of the invention, and are also included within the scope of the invention described in the claims and their equivalents. [Simplified Explanation of the Diagram]

[0005] [Figure 1] is a schematic circuit diagram showing the configuration of a portion of the semiconductor memory device according to the first embodiment. [Figure 2] is a schematic circuit diagram for explaining the read operation of the semiconductor memory device. [Figure 3] is a schematic perspective view showing the configuration of a portion of the semiconductor memory device. [Figure 4] is a schematic perspective view showing the configuration of a portion of the semiconductor memory device. [Figure 5] is a schematic XY cross-sectional view showing the configuration of a portion of the semiconductor memory device. [Figure 6] is a schematic XY cross-sectional view showing the configuration of a portion of the semiconductor memory device. [Figure 7] is a schematic XY cross-sectional view showing the configuration of a portion of the semiconductor memory device. [Figure 8] is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device. [Figure 9] is a schematic XY cross-sectional view showing the configuration of a portion of the semiconductor memory device. [Figure 10] is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device. [Figure 11] is a schematic XY cross-sectional view showing the configuration of a portion of the semiconductor memory device. [Figure 12] is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device. [Figure 13] is a schematic XY cross-sectional view showing the configuration of a portion of the semiconductor memory device. [Figure 14] is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device. [Figure 15] is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device. [Figure 16] is a schematic cross-sectional view illustrating a method for manufacturing the semiconductor memory device. [Figure 17] is a schematic cross-sectional view illustrating the manufacturing method. [Figure 18] is a schematic cross-sectional view illustrating the manufacturing method. [Figure 19] is a schematic cross-sectional view illustrating the manufacturing method. [Figure 20] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 21] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 22] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 23] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 24] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 25] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 26] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 27] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 28] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 29] is a schematic cross-sectional view for illustrating the manufacturing method.[Figure 30] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 31] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 32] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 33] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 34] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 35] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 36] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 37] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 38] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 39] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 40] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 41] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 42] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 43] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 44] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 45] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 46] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 47] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 48] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 49] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 50] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 51] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 52] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 53] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 54] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 55] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 56] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 57] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 58] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 59] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 60] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 61] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 62] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 63] is a schematic cross-sectional view used to illustrate the manufacturing method.[Figure 64] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 65] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 66] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 67] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 68] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 69] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 70] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 71] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 72] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 73] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 74] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 75] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 76] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 77] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 78] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 79] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 80] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 81] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 82] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 83] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 84] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 85] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 86] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 87] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 88] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 89] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 90] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 91] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 92] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 93] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 94] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 95] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 96] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 97] is a schematic cross-sectional view used to illustrate the manufacturing method.[Figure 98] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 99] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 100] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 101] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 102] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 103] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 104] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 105] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 106] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 107] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 108] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 109] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 110] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 111] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 112] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 113] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 114] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 115] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 116] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 117] is a schematic cross-sectional view for illustrating the manufacturing method. [Figure 118] is a schematic cross-sectional view used to illustrate the manufacturing method. [Figure 119] is a schematic XY cross-sectional view showing the configuration of a part of the semiconductor memory device of the second embodiment.

Claims

1. A semiconductor memory device comprising: a substrate; and a first via wiring extending in a first direction intersecting the surface of the substrate; and a plurality of first semiconductor layers arranged side-by-side in the first direction and electrically connected to the first via wiring; and a memory portion arranged side-by-side in the first direction and electrically connected to the plurality of first semiconductor layers; and a plurality of first gate electrodes arranged side-by-side in the first direction and facing the plurality of first semiconductor layers; and a plurality of first wirings arranged side-by-side in the first direction and extending in a second direction intersecting the first direction and electrically connected to the plurality of first gate electrodes. The first semiconductor layer is electrically connected to the first semiconductor layer; and the second semiconductor layer is arranged side by side in the first direction and electrically connected to the first wiring; the second gate electrode is arranged side by side in the first direction and faces the second semiconductor layer; the second via wiring extends in the first direction and is electrically connected to the second gate electrode; and the second wiring extends in the first direction and is electrically connected to the second semiconductor layer, and is arranged side by side with the second semiconductor layer in a third direction that intersects the first and second directions.

2. The semiconductor memory device as described in claim 1, wherein, The two ends of the two adjacent second gate electrodes in the aforementioned first direction and the aforementioned second direction and the aforementioned third direction of the aforementioned plurality of second gate electrodes are separated in the aforementioned first direction.

3. The semiconductor memory device as described in claim 1, wherein, The system comprises: a plurality of insulating layers arranged alternately with the aforementioned plurality of first semiconductor layers in the aforementioned first direction; and a plurality of second gate electrodes respectively disposed at positions corresponding to the aforementioned plurality of insulating layers in the aforementioned first direction.

4. The semiconductor memory device as described in claim 1, wherein, One of the aforementioned plurality of second gate electrodes is disposed between two adjacent second semiconductor layers in the aforementioned plurality of second semiconductor layers in the aforementioned first direction, and is opposite to these two second semiconductor layers.

5. The semiconductor memory device as described in claim 1, wherein, The aforementioned second semiconductor layer comprises at least one of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O).

6. The semiconductor memory device as described in claim 1, wherein, The aforementioned first gate electrode is opposite to one side and the other side of the aforementioned first semiconductor layer in the first direction and one side and the other side of the aforementioned second direction.

7. The semiconductor memory device as described in claim 1, wherein, The aforementioned memory unit includes: a first electrode, which is electrically connected to the aforementioned first semiconductor layer; The first electrode and the second electrode are opposite to the first electrode; and the insulating layer is disposed between the first electrode and the second electrode.

8. The semiconductor memory device as described in claim 1, wherein, The aforementioned first semiconductor layer comprises at least one of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O).

9. The semiconductor memory device as described in claim 1, wherein, The system comprises: a plurality of third semiconductor layers arranged side by side in the aforementioned first direction and electrically connected to the aforementioned plurality of first wirings; a plurality of third gate electrodes arranged side by side in the aforementioned first direction and facing the aforementioned plurality of third semiconductor layers; a third via wiring extending in the aforementioned first direction and electrically connected to the aforementioned plurality of third gate electrodes; and a plurality of third wirings arranged side by side in the aforementioned first direction and extending in the aforementioned third direction and electrically connected to the aforementioned plurality of third semiconductor layers.

10. The semiconductor memory device as described in claim 9, wherein, The position of the first through-hole wiring in the aforementioned second direction is located between the position of the second through-hole wiring in the aforementioned second direction and the position of the third through-hole wiring in the aforementioned second direction.

11. The semiconductor memory device as described in claim 9, wherein, The position of the second through-hole wiring described above in the second direction is located between the position of the first through-hole wiring described above in the second direction and the position of the third through-hole wiring described above in the second direction.

12. The semiconductor memory device as described in claim 9, wherein, The two ends of the two adjacent third gate electrodes in the aforementioned first direction in the aforementioned second direction and the aforementioned third direction are separated in the aforementioned first direction.

13. The semiconductor memory device as described in claim 9, wherein, The system comprises: a plurality of insulating layers arranged alternately with the aforementioned plurality of first semiconductor layers in the aforementioned first direction; and a plurality of third gate electrodes respectively disposed at positions corresponding to the aforementioned plurality of insulating layers in the aforementioned first direction.

14. The semiconductor memory device as described in claim 9, wherein, One of the aforementioned plurality of third gate electrodes is disposed between two adjacent third semiconductor layers in the aforementioned plurality of third semiconductor layers in the aforementioned first direction, and is opposite to these two third semiconductor layers.

15. The semiconductor memory device as described in claim 9, wherein, The aforementioned third semiconductor layer comprises at least one of gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O).

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