Methods for forming semiconductor device

Abstract

Various embodiments disclosed herein provide a method for forming a semiconductor device structure. The method includes forming a trench between two adjacent fin structures, each fin structure comprising an alternating stack of a plurality of first semiconductor layers and a plurality of second semiconductor layers; removing a second semiconductor layer in each fin structure to form a first cavity; filling the first cavity with a sacrificial dielectric layer; removing an edge portion of each sacrificial dielectric layer to form a second cavity; filling the second cavity with a dielectric spacer; forming epitaxial source / drain features in the trench; removing the sacrificial dielectric layer; and surrounding a portion of each first semiconductor layer with a gate electrode layer.

Description

[Technical Field]

[0001] None [Previous Technology]

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in generations of ICs, each with smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnects per die area) generally increases, while geometry (i.e., the smallest component (or wiring) that can be produced using manufacturing processes) decreases. This scaling down generally benefits production efficiency and reduces associated costs. However, as the dimensions of integrated circuits continue to shrink to even smaller sub-micron sizes in advanced node applications, reducing channel resistance while maintaining the current required by the device becomes an increasingly significant challenge. Therefore, improvements in structure and manufacturing methods are needed. [Summary of the Invention]

[0003] None

Implementation Method

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "above," "on," "top," "upper," and the like may be used herein to describe the relationship between one element or feature illustrated in the figures and another element(s) or feature(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted similarly accordingly.

[0007] Although the embodiments disclosed herein are discussed in relation to nanostructured channel field-effect transistors (FETs), some implementations of these embodiments can be used in other processes and / or other devices, such as planar FETs, FinFETs, Horizontal Gate All Around (HGAA) FETs, Vertical Gate All Around (VGAA) FETs, and other suitable devices. It will be readily understood by those skilled in the art that other modifications can be contemplated within the scope of this disclosure. When adapting to a gate all around (GAA) transistor structure, the GAA transistor structure can be patterned using any suitable method. For example, one or more optical lithography processes, including dual patterning or multiple patterning processes, can be used to pattern the structure. Generally, dual or multiple patterning processes, combining optical lithography with self-aligned processes, allow for the production of patterns with, for example, smaller pitches than those achievable using a single direct optical lithography process. For instance, in one embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are then formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0008] Figures 1 through 27 illustrate non-limiting processes for manufacturing a semiconductor device structure 100 according to embodiments of the present disclosure. It should be understood that additional embodiments of the method may provide additional operations before, during, and after the processes shown in Figures 1 through 27, and some of the operations described below may be replaced or eliminated. The order of operations / processes is not limited and may be interchanged.

[0009] Figures 1 through 5 are perspective views of various stages of manufacturing a semiconductor device structure 100 according to some embodiments. As shown in Figure 1, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed over a front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), indium phosphide (InP), or combinations thereof. In one embodiment, the substrate 101 is made of silicon. The substrate 101 may be doped or undoped. The substrate 101 may be a bulk semiconductor substrate, such as a bulk silicon substrate for a wafer, a silicon-on-insulator (SOI) substrate, a multilayer or gradient substrate, or the like.

[0010] The substrate 101 may include various regions that are doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopants may be, for example, phosphorus for n-well and / or n-type field-effect transistors (NFETs) and boron for p-well and / or p-type field-effect transistors (PFETs).

[0011] The semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanosheet channels, such as nanosheet channel field-effect transistors, in a multi-gate device. In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108 vertically stacked above a substrate 101. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layer 106 and second semiconductor layer 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, and the second semiconductor layer 108 may be made of SiGe. In some instances, the first semiconductor layer 106 may be made of SiGe, and the second semiconductor layer 108 may be made of Si. Alternatively, in some embodiments, either the first semiconductor layer 106 or the second semiconductor layer 108 may be or include other materials such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0012] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxy. For example, the epitaxial growth of the layers in the semiconductor layer stack 104 can be performed by a molecular beam epitaxy (MBE) process, a metal-organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0013] In a later manufacturing stage, the first semiconductor layer 106 or portions thereof may form one or more nanosheet channels of the semiconductor device structure 100. The term nanosheet is used herein to refer to any portion of material having nanoscale or even microscale dimensions and having an elongated shape, regardless of the cross-sectional shape of that portion. Thus, the term refers to elongated material portions with circular and substantially circular cross-sections, and beam or rod-shaped material portions, including, for example, cylindrical or substantially rectangular cross-sections. The one or more nanosheet channels of the semiconductor device structure 100 may be surrounded by gate electrodes. The semiconductor device structure 100 may include nanosheet transistors. Nanosheet transistors may be referred to as nanowire transistors, gate all around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having gate electrodes surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0014] Each first semiconductor layer 106 may have a thickness ranging from about 5 nm to about 30 nm. Each second semiconductor layer 108 may have a thickness equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness ranging from about 2 nm to about 50 nm. As shown in Figure 1, three first semiconductor layers 106 and three second semiconductor layers 108 are alternately arranged for illustrative purposes and are not intended to limit the specific references in the claims. It is understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels of the semiconductor device structure 100.

[0015] In Figure 2, the fin structure 112 is formed from a semiconductor layer stack 104. Each fin structure 112 has an upper portion including a first semiconductor layer 106 and a second semiconductor layer 108 and a well portion 116 formed from a substrate 101. The fin structure 112 can be formed by patterning a hard mask layer (not shown) formed on the semiconductor layer stack 104 using multiple patterning operations including optical lithography and etching processes. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The optical lithography process may include forming a photoresist layer (not shown) on the hard mask layer, exposing the photoresist layer to the pattern, performing a post-exposure baking process, and developing the photoresist layer to form a masking element including the photoresist layer. In some embodiments, an electron beam lithography process may be used to pattern the photoresist layer to form a masking element. The etching process forms trenches 114 in the unprotected area, penetrating the hard mask layer, passing through the semiconductor layer stack 104, and entering the substrate 101, thereby leaving a plurality of extending fin structures 112. The trenches 114 extend along the X direction (and also the Y and Z directions in the figure, which are perpendicular to each other). The trenches 114 can be etched using dry etching (e.g., RIE), wet etching, and / or combinations thereof.

[0016] In Figure 3, after the fin structure 112 is formed, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Next, planarization operations, such as chemical mechanical polishing (CMP) and / or etching-back methods, are performed to expose the top of the fin structure 112. The insulating material 118 may be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorinated silica glass (FSG), low-k dielectric material, or any suitable dielectric material. The insulating material 118 may be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD).

[0017] In Figure 4, the insulating material 118 is recessed to form an isolation region 120. The recesses in the insulating material 118 expose portions of the fin structures 112, such as the semiconductor layer stack 104. The recesses in the insulating material 118 reveal trenches 114 between adjacent fin structures 112. The isolation region 120 can be formed using suitable processes, such as dry etching, wet etching, or a combination thereof. The top surface of the insulating material 118 may be flush with or below the surface of the second semiconductor layer 108 that contacts the well portion 116 formed by the substrate 101.

[0018] In Figure 5, one or more sacrificial gate structures 130 (only two are shown) are formed over the semiconductor device structure 100. The sacrificial gate structure 130 is formed over a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a masking layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the masking layer 136 may be formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the masking layer 136, and then patterning these layers into the sacrificial gate structure 130. Gate spacers 138 are then formed on the sidewalls of the sacrificial gate structure 130. For example, the gate spacers 138 may be formed by conformally depositing one or more layers of gate spacers 138 and anisotropically etching the one or more layers. Although two sacrificial gate structures 130 are shown, in some embodiments, three or more sacrificial gate structures 130 may be configured along the direction X.

[0019] The sacrificial gate dielectric layer 132 may include one or more dielectric materials, such as silicon oxide (SiOx) or silicon oxide-based materials. The sacrificial gate electrode layer 134 may include silicon, such as polycrystalline silicon or amorphous silicon. The masking layer 136 may include one or more layers, such as oxide layers and nitride layers. The gate spacer 138 may be made of dielectric materials, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon carbide, SiOCN, and / or combinations thereof. In some embodiments, the gate spacer 138 may be a bilayer including a first dielectric layer (e.g., SiO2) and a second dielectric layer (e.g., SiN).

[0020] The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as a channel region of the semiconductor device structure 100. The fin structure 112, partially exposed on the opposite side of the sacrificial gate structure 130, defines the source / drain (S / D) region of the semiconductor device structure 100. In some cases, some S / D regions may be shared among various transistors. For example, various S / D regions may be connected together and implemented as a multifunctional transistor. It should be understood that since the epitaxial features formed in these regions are substantially the same, the source region and drain region can be used interchangeably. The source / drain region may refer to either the source or the drain, individually or jointly, depending on the context.

[0021] Figures 6 to 27 are cross-sectional side views of various stages of manufacturing a semiconductor device structure 100, taken along cross section AA of Figure 5 according to some embodiments.

[0022] Figures 7 through 16 illustrate various stages of a cyclic process for removing fin structure 112 to form trenches in an S / D region (e.g., a region on the opposite side of sacrificial gate structure 130). Specifically, the trenches (and thus the subsequent epitaxial S / D features) are formed with substantially straight vertical sidewall profiles. The cyclic process may include a plurality of process cycles, each process cycle comprising an etching step, a passivation step, and a processing step. The etching step in each process cycle is used to remove portions of the first semiconductor layer 106 and the second semiconductor layer 108. The passivation step in each process cycle is used to protect the exposed surfaces of the trench from over-etching in subsequent etching processes. The processing step in each process cycle is used to soften the previously formed passivation layer so that it is easily removed in subsequent etching steps in the next process cycle. The cyclic process is performed until the desired trench depth is reached.

[0023] Figure 7 shows an etching step 141 in the first process cycle of the cyclic process. Etching step 141 is performed to remove the first semiconductor layer 106 and the second semiconductor layer 108, thereby forming a trench 1802 with a first depth. A portion of the insulating material 118 surrounding the fin structure 112 may also be removed. Etching step 141 can be a dry etching process, such as RIE, NBE, or any suitable anisotropic etching process. In an exemplary embodiment, etching step 141 is a plasma etching process. Etching step 141 may be performed until the etching penetrates the topmost second semiconductor layer 108. After etching step 141, the trench 1802 may have a depth D1 defined by the distance between the top surface of the topmost first semiconductor layer 106 and the bottom surface 1802bs1 of the trench 1802. In some embodiments, the bottom surface 1802bs1 of the trench 1802 is located at or near the interface defined by the topmost second semiconductor layer 108 and the first semiconductor layer 106 immediately below the second semiconductor layer 108.

[0024] Etching step 141 is a plasma etching process using hydrocarbon-based etching chemicals, bromine-based etching chemicals, chlorine-based etching chemicals, or fluorine-based etching chemicals, or similar substances. Examples of hydrocarbon-based etching chemicals may include methane (CH4), ethane (C2H6), propane (C3H8), similar substances, or combinations thereof. Examples of bromine-based etching chemicals may include hydrogen bromide (HBr), bromine (Br2), boron tribromide (BBr3), similar substances, or combinations thereof. Examples of chlorine-based etching chemicals may include chlorine (Cl2), chloroform (CHCl3), carbon tetrachloride (CCl4), boron trichloride (BCl3), similar substances, or combinations thereof. Exemplary fluorine-based etching chemicals may include fluorine-containing gases, such as tetrafluoromethane (CF4), hexafluoroethane (C2F6), octafluorocyclobutane (C4F8), hexafluorobutadiene (C4F6), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), difluoromethane (CH2F2), difluoroethane (C2H4F2), trifluoromethane (CHF3), hexafluoroethane (C2F6), or similar substances, or combinations thereof. Diluent gases such as helium (He), nitrogen (N2), or similar substances may also be used in combination with the etching chemicals. Inert gases such as argon (Ar), neon (Ne), krypton (Kr), or similar substances may be provided with the etching chemicals to increase the impact effect, thereby improving the etching rate of the first semiconductor layer 106 and the second semiconductor layer 108.

[0025] In some embodiments, the plasma etching process may utilize a capacitively coupled plasma (CCP) source, an inductively coupled plasma (ICP) source, a dipole antenna plasma source, a resonant antenna plasma source, an electron cyclotron resonance (ECR) plasma source, or a glow discharge plasma (GDP) source driven by a radio frequency (RF) power generator or a microwave plasma source, using tunable frequencies ranging from about 2 MHz to about 2.45 GHz, such as about 13.56 MHz. The process chamber can operate at pressures ranging from about 5 mTorr to about 20 mTorr and temperatures ranging from about 20 degrees Celsius to about 240 degrees Celsius. The RF power generator is operated to provide source power between about 100 W and about 300 W. A bias power ranging from about 100 W to about 300 W is provided to the substrate support on which the semiconductor device structure 100 is disposed to provide etching directionality. The source power and bias power can be controlled so that the ion acceleration energy is between about 20 eV and about 200 eV. In some cases, pulsed plasma etching can be used. In such cases, the output of the power generator can be controlled by a pulse signal having a duty cycle in the range of about 5% to 95%. Alternatively, the plasma etching process can use only the bias power (source power is zero). In some embodiments, the plasma etching process can be performed in a plasma etching chamber with in-situ atomic layer deposition (ALD) capability. In one exemplary embodiment, the plasma etching process uses a plasma formed from a gas mixture, for example, containing CH4, Cl2, HBr, and CHF3.

[0026] In some embodiments, the plasma etching process may utilize a decoupled plasma process using an ICP source driven by an RF power generator. The RF power generator may use an adjustable frequency ranging from about 2 MHz to about 13.56 MHz, and the process chamber may operate for a processing time of about 3 seconds to about 200 seconds at a pressure ranging from about 1 mTorr to about 800 mTorr and a temperature ranging from about 0 degrees Celsius to about 140 degrees Celsius. The flow rate of the process gas (e.g., hydrogen-containing and nitrogen-containing gas) may be provided separately from about 200 sccm to about 5000 sccm. The RF power generator may be operated to provide power between about 50 watts and about 1000 watts, and the output of the RF power generator is controlled by a pulse signal having a duty cycle ranging from about 20% to about 80%.

[0027] Figure 8 shows the passivation step of the first process cycle in the cyclic process. The passivation step is performed to form a passivation layer 143a on the exposed surfaces of the trench 1802, such as the sidewalls 1802s and bottom surface 1802bs1 of the trench 1802. The passivation layer 143a protects the exposed surfaces of the trench 1802 from over-etching in the lateral direction during subsequent etching steps. In some embodiments, the passivation layer 143a can be used to reduce the etch selectivity of the exposed surfaces of the trench 1802 for etchants used in subsequent etching processes (such as etching step 147 shown in Figure 10). During the passivation step, bias power is applied to the substrate support such that most of the etching chemicals are directed toward the bottom of the trench 1802. Therefore, when the passivation layer 143a on the sidewalls 1802s and bottom surface 1802bs1 of the trench 1802 is exposed to the etchant, the passivation layer 143a on the bottom surface 1802bs1 of the trench 1802 is removed at a faster rate than the passivation layer 143a on the sidewalls 1802s of the trench 1802. In this way, the passivation layer 143a reduces the effect of the etchant on the sidewalls 1802s of the trench 1802, thereby allowing the trench 1802 to extend vertically with a straight and symmetrical sidewall profile during subsequent etching steps. In some embodiments, the passivation layer 143a may have a thickness between about 1 nm and about 3 nm.

[0028] The passivation layer 143a may be a dielectric material or an oxide-based passivation layer, such as SiO, SiON, SiN, SiO2, the like, or any combination thereof. In some embodiments, the passivation layer 143a may be formed by exposing the exposed surface of the trench 1802 to a gas mixture containing a silicon-containing precursor (e.g., SiCl4), an oxygen-containing precursor (e.g., O2), and / or a nitrogen-containing precursor (e.g., N2). The precursors may flow into the process chamber simultaneously or sequentially. In some embodiments, a hydrohalide such as hydrogen bromide (HBr) may flow together with the silicon-containing and oxygen-containing precursors. In some embodiments, the passivation layer 143a is deposited in the same chamber as the plasma etching process used for etching step 141 by an in-situ ALD process. For example, one in-situ ALD technology uses precursors such as DIPAS (di(isopropylamine)silane) and BTBAS (bis(tert-butylamine)silane) and combines them with Ar or O2 plasma treatment to form a silicon-containing film. For instance, the passivation layer 143a can be formed by supplying a silicon-containing source gas (such as DIPAS or BTBAS) to the process chamber and a plasma containing a reactive gas (such as an oxygen-containing gas or a nitrogen-containing gas) to the process chamber. Free radicals from the plasma of the reactive gas oxidize or nitrid the material derived from the silicon-containing source gas to form a silicon-containing film.

[0029] In some embodiments, the passivation step may utilize the same plasma source as the etching step 141. The process chamber may operate at a pressure ranging from about 5 mTorr to about 20 mTorr. An RF power generator is operated to provide a source power ranging from about 100 W to about 300 W. During the passivation step, a bias power ranging from about 10 W to about 50 W is provided to the substrate support. In some embodiments, the source power used during the passivation step (e.g., 200 W to about 500 W) is greater than the source power used during the etching step 141 (e.g., 100 W to about 300 W), and the bias power used during the passivation step process (e.g., 10 W to about 50 W) is lower than the bias power used during the etching step 141 (e.g., 100 W to about 300 W). In some embodiments, the etching step 141 and the passivation step may be performed in the same process chamber having in-situ ALD capability. In one exemplary embodiment, the passivation step in the first process cycle uses a plasma formed from a gas mixture, for example, containing N2 and / or O2.

[0030] Figure 9 shows processing step 145 of the first process cycle in the cyclic process. Processing step 145 is performed to bombard and soften the passivation layer 143a. Softening the passivation layer 143a allows it to be easily removed during subsequent etching steps in the next process cycle. Processing step 145 may be a bombardment process using plasma formed from hydrogen (H2), N2, Ar, or the like, or any combination thereof. In some embodiments, processing step 145 uses a neutral base of species formed from nitrogen-containing gases, hydrogen-containing gases, or combinations thereof.

[0031] In some embodiments, processing step 145 may utilize the same plasma source as etching step 141. The process chamber may operate at a pressure ranging from about 50 mTorr to about 100 mTorr. During processing step 145, bias power is applied to the substrate support such that most of the ions and / or free radicals are directed toward the bottom of trench 1802 to obtain greater directionality. Greater directionality may also be achieved by reducing the frequency of the bias power. In some embodiments, the source power used during processing step 145 (e.g., from 50 W to about 100 W) is less than the source power used in etching step 141 (e.g., from 100 W to about 300 W), and the bias power used during passivation step (e.g., from 200 W to about 400 W) is greater than the bias power used in etching step 141 (e.g., from 100 W to about 300 W). In some embodiments, processing step 145 in the first process cycle may be performed in the same process chamber as the passivation step of the first process cycle.

[0032] Figure 10 shows the etching step 147 of the second process cycle in the cyclic process. Etching step 147 is performed to remove the softened passivation layer 143a (Figure 9) and the first semiconductor layer 106 and the second semiconductor layer 108, thereby forming a trench 1802 with a second depth. The trench 1802 has a straight and symmetrical sidewall profile relative to a dashed line passing through the center of the trench 1802 in the depth direction of the trench 1802. Etching step 147 can be performed using etching chemicals similar to or the same as those used in etching step 141. Etching step 147 is substantially the same as etching step 141 except for using a higher bias power. In some embodiments, etching step 147 of the second process cycle uses a bias power greater than that used in processing step 145 of the first process cycle.

[0033] In one embodiment, the source power used during etching step 147 (e.g., about 100 W to about 300 W) is substantially the same as the source power used during etching step 141 (e.g., about 100 W to about 300 W), and the bias power used during etching step 147 (e.g., about 200 W to about 500 W) is greater than the bias power used during etching step 141 (e.g., about 100 W to about 300 W). Alternatively, the source power used during etching step 147 is greater than the source power used during etching step 141. The chamber pressure used during etching step 141 and etching step 147 is substantially the same (e.g., about 5 mTorr to about 20 mTorr). In an exemplary embodiment, etching step 147 uses a plasma formed from a gas mixture, for example, containing CH4, Cl2, HBr, and CHF3.

[0034] Etching step 147 extends the depth of trench 1802. In some embodiments, etching step 147 is performed until etching passes through the second highest second semiconductor layer 108 of the semiconductor layer stack 104. After etching step 147, trench 1802 may have a depth D2 defined by the distance between the topmost first semiconductor layer 106 and the bottom surface 1802bs2 of trench 1802. In other words, the depth of trench 1802 extends from depth D1 to depth D2. In some embodiments, the bottom surface 1802bs2 of trench 1802 is located at or near the interface defined by the second highest second semiconductor layer 108 of semiconductor layer stack 104 and the immediately below first semiconductor layer 106.

[0035] Figure 11 shows the passivation step of the second process cycle in the cyclic process. A passivation step is performed to form a passivation layer 143b on the exposed surfaces of trench 1802, such as the sidewalls 1802s and bottom surface 1802bs2 of trench 1802. Passivation layer 143b may be formed of the same material as passivation layer 143a. Similarly, passivation layer 143b protects the exposed surfaces of trench 1802 from over-etching in the lateral direction during subsequent etching steps. During the passivation step, bias power is also applied to the substrate support, causing most of the etch chemicals to be directed towards the bottom of trench 1802. Passivation layer 143b reduces the effect of the etchant on the sidewalls 1802s of trench 1802. Therefore, in subsequent etching steps, trench 1802 can extend vertically with a straight and symmetrical sidewall profile. In some embodiments, passivation layer 143b may have a thickness between about 1 nm and about 3 nm.

[0036] Except for using a larger bias power, the passivation step in the second process cycle is substantially the same as the passivation step in the first process cycle. In some embodiments, the bias power used during the passivation step of the second process cycle (e.g., about 20 W to about 80 W) is greater than the bias power of the passivation step performed in the first process cycle (e.g., about 10 W to about 50 W), and the source power used during the passivation phase of the second process cycle (e.g., about 200 W to about 500 W) is substantially the same as the source power of the passivation step performed in the first process cycle (e.g., about 200 W to about 500 W). In some embodiments, the passivation step in the second process cycle may be performed in the same process chamber as the etching step 147 of the second process cycle. The process chamber may be operated at a pressure ranging from about 5 mTorr to about 20 mTorr. In one exemplary embodiment, the passivation step in the second process cycle uses a plasma formed from, for example, a gas mixture containing N2 and / or O2.

[0037] Figure 12 shows processing step 149 of the second process cycle in the cyclic process. Processing step 149 is performed to bombard and soften the passivation layer 143b, thereby allowing it to be easily removed during a subsequent etching step in the next process cycle. Processing step 149 of the second process cycle is substantially the same as processing step 145 of the first process cycle, except that a greater bias power is used. In some embodiments, the bias power used during processing step 149 of the second process cycle (e.g., about 300 W to about 500 W) is greater than the bias power of processing step 145 performed in the first process cycle (e.g., about 200 W to about 400 W), and the source power used during processing step 149 of the second process cycle (e.g., about 50 W to about 100 W) is substantially the same as the source power of processing step 145 performed in the first process cycle (e.g., about 50 W to about 100 W). In some embodiments, processing step 149 in the second process cycle may be performed in the same process chamber as the passivation step of the second process cycle. The process chamber may operate at a pressure ranging from about 50 mTorr to about 100 mTorr.

[0038] Figure 13 shows the etching step 151 of the third process cycle in the cyclic process. Etching step 151 is performed to remove the softened passivation layer 143b (Figure 12) and the first semiconductor layer 106 and the second semiconductor layer 108, thereby forming a third portion of the trench 1802. The third portion of the trench 1802 has a straight and symmetrical sidewall profile relative to the dashed line passing through the center of the trench 1802 in the depth direction of the trench 1802. Etching step 151 can be performed using etching chemicals similar to or the same as those used in etching step 147. Etching step 151 is substantially the same as etching step 147 except for using a higher bias power. In some embodiments, etching step 151 of the third process cycle uses a bias power greater than that used in processing step 149 of the second process cycle.

[0039] In one embodiment, the source power used during etching step 151 (e.g., about 100 W to about 300 W) is substantially the same as the source power of etching step 147 performed in the second process cycle (e.g., about 100 W to about 300 W), and the bias power used during etching step 151 (e.g., about 300 W to about 600 W) is greater than the bias power of etching step 147 performed in the second process cycle (e.g., about 200 W to about 500 W). Alternatively, the source power used during etching step 151 is greater than the source power of etching step 147. The chamber pressure used during etching step 151 and etching step 147 is substantially the same (e.g., about 5 mTorr to about 20 mTorr). In an exemplary embodiment, etching step 151 uses a plasma formed from a gas mixture, for example, containing CH4, Cl2, HBr, and CHF3.

[0040] An etching step 151 is performed to further extend the depth of the trench 1802. In the case where the fin structure 112 includes three second semiconductor layers 108, the etching step 151 is performed until the third highest second semiconductor layer 108 of the semiconductor layer stack 104 is etched through. After the etching step 151, the trench 1802 may have a depth D3 defined by the distance between the topmost first semiconductor layer 106 and the bottom surface 1802bs3 of the trench 1802. In other words, the depth of the trench 1802 extends from depth D2 to depth D3. In some embodiments, the bottom surface 1802bs3 of the trench 1802 is located at or near the interface defined by the third highest second semiconductor layer 108 of the semiconductor layer stack 104 and the immediately below first semiconductor layer 106.

[0041] Figure 14 shows the passivation step of the third process cycle in the cyclic process. A passivation step is performed to form a passivation layer 143c on the exposed surfaces of trench 1802, such as the sidewalls 1802s and bottom surface 1802bs3 of trench 1802. Passivation layer 143c may be formed of the same material as passivation layer 143a. Similarly, passivation layer 143c protects the exposed surfaces of trench 1802 from over-etching in the lateral direction during subsequent etching steps. During the passivation step, bias power is also applied to the substrate support, causing most of the etch chemicals to be directed towards the bottom of trench 1802. Passivation layer 143c reduces the effect of the etchant on the sidewalls 1802s of trench 1802. Therefore, during subsequent etching steps, trench 1802 can extend vertically with a straight and symmetrical sidewall profile. In some embodiments, passivation layer 143c may have a thickness between about 1 nm and about 3 nm.

[0042] Except for using a higher bias power, the passivation step in the third process cycle is substantially the same as the passivation step in the second process cycle. In some embodiments, the bias power used during the passivation step of the third process cycle (e.g., about 50 W to about 100 W) is greater than the bias power of the passivation step performed in the second process cycle (e.g., about 20 W to about 80 W), and the source power used during the passivation phase of the third process cycle (e.g., about 200 W to about 500 W) is substantially the same as the source power of the passivation step performed in the second process cycle (e.g., about 200 W to about 500 W). In some embodiments, the passivation step in the third process cycle may be performed in the same process chamber as the etching step 151 of the third process cycle. The process chamber may be operated at a pressure ranging from about 5 mTorr to about 20 mTorr. In one exemplary embodiment, the passivation step in the third process cycle uses a plasma formed from, for example, a gas mixture containing N2 and / or O2.

[0043] Figure 15 shows processing step 153 of the third process cycle in the cyclic process. Processing step 153 is performed to impact and soften the passivation layer 143c, thereby allowing and facilitating its removal during subsequent etching steps in the next process cycle. Processing step 153 of the third process cycle is substantially the same as processing step 149 in the second process cycle, except that it uses a larger bias power. In some embodiments, the bias power used during processing step 153 of the third process cycle (e.g., about 500 W to about 1000 W) is greater than the bias power of processing step 149 performed in the second process cycle (e.g., about 300 W to about 500 W), and the source power used during processing step 153 of the third process cycle (e.g., about 50 W to about 100 W) is substantially the same as the source power of processing step 149 performed in the second process cycle (e.g., about 50 W to about 100 W). In some embodiments, processing step 153 in the third process cycle may be performed in the same process chamber as the passivation step of the third process cycle. The process chamber may operate at a pressure ranging from about 50 mTorr to about 100 mTorr.

[0044] Figure 16 shows a semiconductor device structure 100 undergoing an etching step 155. Etching step 155 is performed to remove a portion of the softened passivation layer 143c (Figure 15) and the substrate 101, thereby forming a fourth portion of a trench 1802. The fourth portion of the trench 1802 has a straight and symmetrical sidewall profile relative to a dashed line passing through the center of the trench 1802 in the depth direction. In some embodiments, the fourth portion of the trench 1802 has a curved profile at its bottom. In some embodiments, the fourth portion of the trench 1802 has a substantially flat profile at its bottom. In some embodiments, the fourth portion of the trench 1802 has a tapered profile at its bottom.

[0045] Etching step 155 may be performed using etching chemicals similar to or the same as those used in etching step 151. Etching step 155 is substantially the same as etching step 151, except that it uses a higher bias power. In some embodiments, etching step 155 uses a bias power greater than that used in processing step 153 in the third process cycle.

[0046] In one embodiment, the source power used during etching step 155 (e.g., about 100 W to about 300 W) is substantially the same as the source power used during etching step 151 performed in the third process cycle (e.g., about 100 W to about 300 W), and the bias power used during etching step 155 (e.g., about 400 W to about 700 W) is greater than the bias power used during etching step 151 performed in the third process cycle (e.g., about 300 W to about 600 W). The chamber pressure used during etching step 155 and etching step 151 is substantially the same (e.g., about 5 mTorr to about 20 mTorr). In an exemplary embodiment, etching step 155 uses a plasma formed from a gas mixture, for example, containing CH4, Cl2, HBr, and CHF3.

[0047] Etching step 155 further extends the depth of trench 1802. Etching step 155 may be performed until trench 1802 reaches a predetermined depth below the interface defined by the bottom second semiconductor layer 108 and substrate 101. After etching step 155, trench 1802 may have a depth D4 defined by the distance between the top first semiconductor layer 106 and the bottom surface 1802bs4 of trench 1802. In other words, the depth of trench 1802 extends from depth D3 to depth D4. In some embodiments, the bottom surface 1802bs4 of trench 1802 is about 5 nm to about 10 nm below the interface defined by the bottom second semiconductor layer 108 and substrate 101.

[0048] The process described in Figures 7 through 16 may be repeated two or more times until the desired depth of the trench 1802 is reached. In some embodiments, the total number of process cycles may correspond to the number of second semiconductor layers 108 in the fin structure 112. In any case, the formed trench 1802 has a straight vertical sidewall profile and a substantially uniform critical dimension (CD) from top to bottom. In some embodiments, a first portion of the trench 1802 at or near the topmost first semiconductor layer 106 of the semiconductor layer stack 104 has a first critical dimension CD1, a second portion of the trench 1802 at or near the second highest first semiconductor layer 106 of the semiconductor layer stack 104 has a second critical dimension CD2, and a third portion of the trench 1802 at or near the third highest first semiconductor layer 106 has a third critical dimension CD3. In some embodiments, the first critical dimension CD1, the second critical dimension CD2, and the third critical dimension CD3 are substantially the same. Each of the first semiconductor layers 106 in the fin structure 112 may have substantially the same width W1 as each other. In some embodiments where the gate pitch is about 40 nm to about 50 nm, the third critical dimension CD3 may be about 0 nm to about 1 nm wider than the width W1.

[0049] In some embodiments, the first critical dimension CD1 and the second critical dimension CD2 are substantially the same, and the third critical dimension CD3 is slightly smaller than the first critical dimension CD1 and the second critical dimension CD2, as shown in the embodiment of Figure 16-1. In such cases, the difference between the first critical dimension CD1 (or the second critical dimension CD2) and the third critical dimension CD3 is less than 2 nm, for example, about 0 nm to about 1 nm, such as about 0.5 nm, and the dimension of the first semiconductor layer 106 gradually increases along the direction away from the sacrificial gate dielectric layer 132.

[0050] In Figure 17, the second semiconductor layer 108 is removed. Removing the second semiconductor layer 108 forms an opening 137. The second semiconductor layer 108 can be removed by a selective etching process, such as a selective dry etching process, a selective wet etching process, or a combination thereof. The selective etching process does not substantially affect the gate spacer 138, the first semiconductor layer 106, the sacrificial gate electrode layer 130, and the substrate 101. In some embodiments, the selective etching process is a selective wet etching process. When the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 can be selectively etched using an etchant such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution.

[0051] In Figure 18, a sacrificial dielectric layer 139 is formed in the opening 137 and on the exposed surface of the semiconductor device structure 100. In some embodiments, the sacrificial dielectric layer 139 is an oxide formed by a flowable chemical vapor deposition (FCVD) process. In some embodiments, the oxide is carbon-containing silicon oxide. The use of the sacrificial dielectric layer 139 helps to maintain the surface profile of the first semiconductor layer 106 during subsequent wafer (or channel) formation stages. In the conventional case where the second semiconductor layer 108 comprises Ge and the first semiconductor layer 106 comprises silicon, Ge in the second semiconductor layer 108 can diffuse into the Si and react with Si to form SiGe due to the high temperatures used during the formation of subsequent epitaxial S / D features 146. When the second semiconductor layer 108 is selectively removed during the wafer formation stage, the surface portion of the first semiconductor layer 106 that is now SiGe due to the previous reaction with Ge is also removed. Therefore, removing the second semiconductor layer 108 would cause additional silicon loss (e.g., a thickness of approximately 1.5 to 2.5 nm) in the surface portion of the first semiconductor layer 106, resulting in a reduction in the thickness of the first semiconductor layer 106 and / or concave damage. When the thickness of the silicon nanosheet channel layer (i.e., the first semiconductor layer 106) is affected, the channel resistance (Rch) of the nanosheet channel layer may increase, and the ability of the nanosheet channel layer to conduct current (e.g., DC) may decrease. By replacing the second semiconductor layer 108 with a sacrificial dielectric layer 139 prior to the formation of the epitaxial S / D feature 146, the reaction between the first semiconductor layer 106 and the sacrificial dielectric layer 139 is minimized during the subsequent formation of the epitaxial S / D feature 146, and the sacrificial dielectric layer 139 can be removed over the first semiconductor layer 106 with enhanced etch selectivity. Since the surface profile of the first semiconductor layer 106 remains substantially intact during the wafer formation stage, the channel resistance of the nanosheet channel layer does not increase, thus avoiding the problems discussed herein.

[0052] In Figure 19, an etch-back process is performed to remove portions of the sacrificial dielectric layer 139 except for the portion formed in the opening 137 (Figure 17). In some embodiments, the etch-back process is an anisotropic etching process. The etch-back process may be a selective etching process that removes the sacrificial dielectric layer 139 without substantially affecting the sacrificial gate structure 130, the gate spacer 138, the first semiconductor layer 106, and the substrate 101. The selective etching process is performed until the edge portions of each sacrificial dielectric layer 139 between the first semiconductor layers 106 are removed. Therefore, after the etch-back process, most of the sacrificial dielectric layers 139 between the first semiconductor layers 106 are retained.

[0053] In Figure 20, after removing the edge portion of the sacrificial dielectric layer 139, a dielectric layer 144a is deposited in the cavity formed by removing the edge of the sacrificial dielectric layer 139. The dielectric layer 144a in the cavity forms a dielectric spacer 144, as shown in Figure 21. The dielectric layer 144a may be made of a dielectric material, such as SiO2, Si3N4, SiC, SiCP, SiON, SiOC, SiCN, SiOCN, and / or other suitable materials. The dielectric layer 144a may be deposited as a conformal dielectric layer using a conformal deposition process such as ALD.

[0054] In Figure 21, anisotropic etching is performed to remove portions of the conformal dielectric layer 144a other than the dielectric layer 144a formed in the cavity. The dielectric layer 144a in the cavity forms dielectric spacers 144 and is protected by a first semiconductor layer 106 during the anisotropic etching process. A sacrificial dielectric layer 139 covers the dielectric spacers 144 along direction X. In some embodiments, the dielectric spacers 144 and the sacrificial dielectric layer 139 comprise different materials with different etch selectivity.

[0055] In Figure 22, epitaxial S / D features 146 are formed in the source / drain (S / D) region. Epitaxial S / D features 146 can be grown vertically and horizontally to form facets, which may correspond to the crystal planes of the material of the first semiconductor layer 106. In some cases, epitaxial S / D features 146 of a fin structure can be grown and merged with epitaxial S / D features 146 of an adjacent fin structure. In any case, the epitaxial S / D features 146 are formed with a substantially uniform CD from top to bottom. For example, the epitaxial S / D features 146 may have dimensions corresponding to the first critical dimension CD1, the second critical dimension CD2, and the third critical dimension CD3 shown in Figure 16. The epitaxial S / D features 146 may include one or more layers of Si, SiP, SiC, and SiCP for n-type FETs, or Si, SiGe, and Ge for p-type FETs. The epitaxial S / D feature 146 can be formed using epitaxial growth methods such as selective epitaxial growth (SEG), CVD, ALD, or MBE. The epitaxial S / D feature 146 is in contact with the first semiconductor layer 106 and the internal dielectric spacer 144. The second semiconductor layer 108 below the sacrificial gate structure 130 is spaced apart from the epitaxial S / D feature 146 by the dielectric spacer 144.

[0056] The epitaxial S / D feature 146 may be an S / D region. For example, one of a pair of epitaxial S / D features 146 located on one side of the sacrificial gate structure 130 may be a source region, and the other of the pair of epitaxial S / D features 146 located on the other side of the sacrificial gate structure 130 may be a drain region. A pair of epitaxial S / D features 146 includes a source epitaxial feature and a drain epitaxial feature connected by a channel (i.e., the first semiconductor layer 106). The source / drain region may refer to a source or a drain, individually or jointly, depending on the context. In this disclosure, the source and drain are used interchangeably, and their structures are substantially the same.

[0057] In some embodiments, after the dielectric spacer 144 is formed, a faceted structure 148 is formed on the exposed surfaces of the first semiconductor layer 106 and the substrate 101 (e.g., well portion 116) to facilitate the subsequent epitaxial growth of epitaxial S / D features 146. In some embodiments, a portion of the faceted structure 148 may further contact the dielectric spacer 144. The faceted structure 148 may be grown vertically and horizontally to form facets that may correspond to the crystal planes of the material of the first semiconductor layer 106 and the exposed surfaces of the substrate 101. Facets may be formed due to different growth rates on different surface planes. For example, during the growth of the faceted structure 148, the growth rate on the (111) plane of the first semiconductor layer 106 (e.g., silicon) may be lower than the growth rate on other planes, such as the (110) and (100) planes of the first semiconductor layer 106. Therefore, facets are formed due to the different growth rates on different planes. In one embodiment, the faceted structure 148 has a rhomboid shape. Compared to the exposed surface of the first semiconductor layer 106, the facets of the faceted structure 148 provide an increased surface area to facilitate the epitaxial growth of the epitaxial S / D feature 146. Once the faceted structure 148 is formed, the epitaxial S / D feature 146 can grow on the faceted structure 148 and cover the exposed surface of the faceted structure 148.

[0058] In some embodiments, the faceted structure 148 comprises silicon. In some embodiments, the faceted structure 148 comprises silicon and an n-type or p-type dopant, depending on the conductivity type of the epitaxial S / D feature 146 to be grown thereon. For example, the faceted structure 148 at the n-type device region may be silicon doped with an n-type dopant (such as phosphorus or arsenic), and the faceted structure 148 at the p-type device region may be silicon doped with a p-type dopant (such as boron). The faceted structure 148 may be formed using selective epitaxial growth (SEG), ALD, MBE, or any suitable growth process. In some embodiments, the first semiconductor layer 106 may be exposed in a process chamber to (a plurality of) silicon-containing precursors and (a plurality of) n-type or p-type dopant-containing precursors to form the faceted structure 148. The growth process conditions are based on the crystal plane configuration of the first semiconductor layer 106 and the substrate 101 to promote the formation of facets in the facet structure 148. Once the facet structure 148 reaches a predetermined volume, the flow of precursors containing n-type or p-type dopants can be terminated, and multiple group IV or V precursors, along with multiple silicon-containing precursors, are introduced into the process chamber to form epitaxial S / D features 146. Therefore, the facet structure 148 is formed from a chemically different material from the epitaxial S / D features 146. Dopants in the epitaxial S / D features 146 can be added during the formation of the epitaxial S / D features 146 or after the epitaxial S / D features 146 are formed by the implantation process.

[0059] In Figure 23, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surfaces of the sacrificial gate structure 130, the insulating material 118, the epitaxial S / D feature 146, and the semiconductor layer stack 104. CESL 162 may comprise an oxygen-containing or nitrogen-containing material and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, a first interlayer dielectric (ILD) layer 164 is formed on the CESL 162 above the semiconductor device structure 100. The material used for the first ILD layer 164 may include compounds comprising Si, O, C, and / or H, such as silicon oxide, TEOS oxide, SiCOH, and SiOC. Organic materials such as polymers may also be used for the first ILD layer 164.

[0060] In Figure 24, after the formation of the first ILD layer 164, a planarization operation such as CMP is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed. After CMP, the top surfaces of the sacrificial gate electrode layer 134, the gate spacer 138, the CESL 162, and the first ILD layer 164 are substantially coplanar.

[0061] In Figure 25, the sacrificial gate structure 130, the sacrificial gate dielectric layer 132, and the sacrificial dielectric layer 139 are removed (i.e., during the sheet formation stage). Removal of the sacrificial gate structure 130 and the sacrificial dielectric layer 139 forms an opening 166 between the first semiconductor layer 106. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial dielectric layer 139, the sacrificial gate dielectric layer 134, and the sacrificial gate dielectric layer 132, but not the gate spacer 138, the first ILD layer 164, and the CESL 162. After removal of the sacrificial gate structure 130, the first semiconductor layer 106 and the internal dielectric spacer 144 are exposed through the opening 166.

[0062] The sacrificial dielectric layer 139 between the first semiconductor layers 106 helps maintain the integrity and surface profile of the first semiconductor layers 106 during the wafer formation stage because the sacrificial dielectric layer 139 does not react with or mix with the first semiconductor layers 106 during the previous high-temperature process of the epitaxial S / D feature 146. Therefore, the sacrificial dielectric layer 139 can be removed during the wafer formation stage without damaging the first semiconductor layers 106.

[0063] In Figure 26, an alternative gate structure 190 is formed. Each of the alternative gate structures 190 may include a gate dielectric layer 180 and a gate electrode layer 182. In some embodiments, an interfacial layer (IL) 178 may be formed between the gate dielectric layer 180 and the first semiconductor layer 106. The IL 178 may also be formed on the exposed surface of the substrate 101. The IL 178 may include or be made of oxides (e.g., silicon oxide), nitrides (e.g., silicon nitride, silicon oxynitride, oxynitride, etc.), and / or dielectric layers (e.g., hafnium silicate) formed by thermal or chemical oxidation of the first semiconductor layer 106. Next, the gate dielectric layer 180 is formed on the exposed surface of the semiconductor device structure 100 (e.g., on the IL (if present), the sidewalls of the gate spacer 138, the top surface of the first ILD layer 164, and the CESL 162). The gate dielectric layer 180 may be formed of a material chemically different from the sacrificial gate dielectric layer 132. The gate dielectric layer 180 may include or be made of a high-k dielectric material. The gate dielectric layer 180 may be a conformal layer formed by a conformal process such as ALD, PECVD, molecular beam deposition (MBD), or similar or combinations thereof.

[0064] After forming IL 178 and gate dielectric layer 180, gate electrode layer 182 is formed on gate dielectric layer 180. Gate electrode layer 182 fills opening 166 (Figure 25) and surrounds a portion of each of the first semiconductor layers 106. Gate electrode layer 182 includes one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicon, cobalt silicon, TiN, WN, WCN, TiAl, TiTaN, TiAlN, TaN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. Gate electrode layer 182 may be formed by PVD, CVD, ALD, electroplating, or other suitable methods. In some embodiments, one or more optional conformal layers (not shown) may be conformally (or sequentially, if more than one) deposited between gate dielectric layer 180 and gate electrode layer 182. One or more optional conformal layers may include one or more barrier layers and / or capping layers, and one or more work function tuning layers. The one or more barrier layers and / or capping layers may include nitrides, silicon nitrides, carbonitrides, and / or aluminum nitrides of tantalum and / or titanium; nitrides, carbonitrides, and / or carbides of tungsten; cobalt; platinum; the like; or combinations thereof. The one or more work function tuning layers may include nitrides, silicon nitrides, carbonitrides, aluminum nitrides, aluminum oxides, and / or aluminum carbides of titanium and / or tantalum; nitrides, carbonitrides, and / or carbides of tungsten; cobalt; platinum; the like; or combinations thereof.

[0065] The portion of the gate electrode layer 182, one or more optional conformal layers (if any), and the gate dielectric layer 180 above the top surfaces of the first ILD layer 164, CESL 162, and gate spacer 138 may be removed by a planarization process (such as a CMP process). After the CMP process, the top surfaces of the first ILD layer 164, CESL 162, gate spacer 138, gate dielectric layer 180, and gate electrode layer 182 are substantially coplanar.

[0066] In Figure 27, contact openings are formed via the first ILD layer 164 and CESL 162 to expose the epitaxial S / D feature 146. A silicate layer 184 is then formed on the epitaxial S / D feature 146, and source / drain (S / D) contacts 186 are formed in the contact openings on the silicate layer 184. The S / D contacts 186 may include conductive materials such as Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, or TaN. Although not shown, a barrier layer (e.g., TiN, TaN, or the like) may be formed on the sidewalls of the contact openings before the formation of the S / D contacts 186. The silicate layer 184 electrically couples the epitaxial S / D feature 146 to the subsequent S / D contacts 186 formed in the contact openings. The silicate layer 184 may include a metal or metal alloy silicate, and the metal includes noble metals, refractory metals, rare earth metals, alloys thereof, or combinations thereof. Next, a planarization process such as CMP is performed to remove excess deposits of contact material and expose the top surface of the gate electrode layer 182.

[0067] It should be understood that the semiconductor device structure 100 may undergo further complementary metal oxide semiconductor (CMOS) and / or back-end-of-line (BEOL) processes to form various features, such as transistors, contacts / vias, interconnect metal layers, dielectric layers, passivation layers, etc. The semiconductor device structure 100 may also include rear-side contacts (not shown) on the rear side of the substrate 101, such that the source or drain of the epitaxial S / D feature 146 is connected to a rear-side power rail (e.g., a positive voltage VDD or a negative voltage VSS) via the rear-side contacts.

[0068] The embodiments disclosed herein provide an improved wafer fabrication process and etching profile control for forming source / drain trenches. Etching profile control is achieved through a cyclic process including etching, passivation, and processing steps, thereby allowing the formation of source / drain trenches with straight vertical sidewall profiles and no curved profiles. Prior to forming the epitaxial S / D features, the SiGe layer between the Si nanosheet channel layers is replaced by a sacrificial dielectric layer. During the subsequent high-temperature process of the epitaxial S / D features, the sacrificial dielectric layer exhibits minimal reaction with the nanosheet channel layers and can be easily removed during the wafer fabrication process. Because the integrity and surface profile of the nanosheet channel layers are maintained during the wafer fabrication process, the channel resistance between the source and drain features can be reduced. Therefore, device performance is improved.

[0069] This disclosure provides a method for forming a semiconductor device structure. The method includes the following operations: forming a trench between two adjacent fin structures, each of the two adjacent fin structures comprising an alternately stacked plurality of first semiconductor layers and a plurality of second semiconductor layers. Removing the second semiconductor layers in each of the two adjacent fin structures to form a plurality of first cavities. Filling the first cavities with a sacrificial dielectric layer. Removing a plurality of edge portions of the sacrificial dielectric layer to form a plurality of second cavities. Filling the second cavities with dielectric spacers. Forming a plurality of epitaxial source / drain features in the trench. Removing the sacrificial dielectric layer. Surrounding a portion of each of the first semiconductor layers with a gate electrode layer.

[0070] This disclosure also provides a method for forming a semiconductor device structure. The method includes the following operations: Removing a portion of a fin structure at a source / drain region using a first etchant to form a trench having a first depth, the fin structure comprising alternating stacked plurality of first semiconductor layers and plurality of second semiconductor layers. Passivating a plurality of exposed surfaces of the trench to modify the etch selectivity of the exposed surfaces to a second etchant. Exposing the passivated surfaces to a processing step. Removing the passivated surfaces and a portion of the fin structure using a second etchant to form a trench having a second depth greater than the first depth. Replacing the second semiconductor layers in the fin structure with a sacrificial dielectric layer. Forming a plurality of epitaxial source / drain features in the trench. Removing the sacrificial dielectric layer. Surrounding a portion of each of the first semiconductor layers with a gate electrode layer.

[0071] This disclosure also provides a method for forming a semiconductor device structure. The method includes the following operations: Performing operation (1), which includes forming a fin structure, wherein the fin structure includes alternating stacked plurality of first semiconductor layers and plurality of second semiconductor layers. Performing operation (2), which includes performing a first etching process to form a trench having a first depth at the source / drain region of the fin structure, wherein the first etching process uses a first bias power. Performing operation (3), which includes passivating a plurality of exposed surfaces of the trench using a second bias power different from the first bias power. Performing operation (4), which includes processing the passivated exposed surfaces using a third bias power different from the first bias power. Performing operation (5), which includes performing a second etching process using a fourth bias power to extend the trench from the first depth to a second depth, wherein the fourth bias power is different from the third bias power. Performing operation (6), which includes replacing the second semiconductor layer in the fin structure with a sacrificial dielectric layer. Performing operation (7), which includes forming a plurality of epitaxial source / drain features in the trench. Performing operation (8) includes removing the sacrificial dielectric layer. Performing operation (9) includes surrounding a portion of each of the first semiconductor layers with a gate electrode layer.

[0072] The foregoing summarizes the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be easily used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, replaced, and substituted in various ways without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0004] The features disclosed herein are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standards, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of description. Figures 1, 2, 3, 4, and 5 are perspective views of various stages of manufacturing a semiconductor device structure according to some embodiments. Figures 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, and 27 are cross-sectional side views of various stages of manufacturing a semiconductor device structure, taken along cross section AA of Figure 5 according to some embodiments. Figure 16-1 is a cross-sectional side view of a semiconductor device structure taken along cross section AA of Figure 5 according to some alternative embodiments. [Biomaterial Storage]

[0074] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A method of forming a semiconductor device structure, comprising: forming a trench between two adjacent fin structures, each of the two adjacent fin structures comprising an alternately stacked plurality of first semiconductor layers and a plurality of second semiconductor layers; removing the second semiconductor layers in each of the two adjacent fin structures to form a plurality of first cavities; filling the first cavities with a sacrificial dielectric layer; removing a plurality of edge portions of the sacrificial dielectric layer to form a plurality of second cavities; filling the second cavities with a dielectric spacer; forming a plurality of epitaxial source / drain features in the trench; removing the sacrificial dielectric layer between the epitaxial source / drain features; and surrounding a portion of each of the first semiconductor layers with a gate electrode layer.

2. The method as described in claim 1, wherein the sacrificial dielectric layer is made of an oxide.

3. The method as described in claim 1, wherein each of the sacrificial dielectric layer and the dielectric spacer comprises a chemically distinct material.

4. The method as described in claim 1 further comprises: growing a faceted structure on one sidewall of each of the first semiconductor layers prior to forming the epitaxial source / drain features.

5. A method of forming a semiconductor device structure, comprising: removing a portion of a fin structure at a source / drain region using a first etchant to form a trench having a first depth, the fin structure comprising alternatingly stacked plurality of first semiconductor layers and plurality of second semiconductor layers; passivating a plurality of exposed surfaces of the trench to modify an etch selectivity of the exposed surfaces to a second etchant; subjecting the passivated surfaces to a processing step; removing the passivated surfaces and a portion of the fin structure using the second etchant to form the trench having a second depth greater than the first depth; replacing the second semiconductor layers in the fin structure with a sacrificial dielectric layer; forming a plurality of epitaxial source / drain features in the trench; removing the sacrificial dielectric layer between the epitaxial source / drain features; and surrounding a portion of each of the first semiconductor layers with a gate electrode layer.

6. The method as described in claim 5, wherein modifying the etching selectivity of the exposed surfaces is performed by forming a passivation layer on the exposed surfaces on a first portion of one of the trenches.

7. The method as described in claim 6, wherein the processing is performed by bombarding the passivation layer with neutral free radicals of multiple species formed from a nitrogen-containing gas and / or a hydrogen-containing gas.

8. A method of forming a semiconductor device structure, comprising: performing an operation (1) comprising forming a fin structure, wherein the fin structure comprises alternately stacked plurality of first semiconductor layers and plurality of second semiconductor layers; performing an operation (2) comprising performing a first etching process to form a trench having a first depth at a source / drain region of the fin structure, wherein the first etching process uses a first bias power; performing an operation (3) comprising passivating a plurality of exposed surfaces of the trench using a second bias power different from the first bias power; performing an operation (4) comprising processing the passivated exposed surfaces using a third bias power different from the first bias power; performing an operation (5) comprising performing a second etching process using a fourth bias power to extend the trench from the first depth to a second depth, wherein the fourth bias power is different from the third bias power; performing an operation (6) comprising replacing the second semiconductor layers in the fin structure with a sacrificial dielectric layer; Performing an operation (7) includes forming a plurality of epitaxial source / drain features in the trench; performing an operation (8) includes removing the sacrificial dielectric layer between the epitaxial source / drain features; and performing an operation (9) includes surrounding a portion of each of the first semiconductor layers with a gate electrode layer.

9. The method as described in claim 8 further comprises: after performing the operation (5), repeating the operation (2), the operation (3), the operation (4) and the operation (5) as a cycle process until the trench reaches a predetermined depth.

10. The method as claimed in claim 9, wherein the first bias power in a second cycle of one of the cyclic processes is greater than the first bias power in a first cycle of one of the cyclic processes.

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