Decoder, decoding method, memory system, and controller

Abstract

A decoder includes a first processing circuit, a second processing circuit, a processor, and a bit-flipping circuit. The first processing circuit is configured to obtain a checksum and checksum weights based on the codeword to be decoded in the current iteration and a check matrix; the second processing circuit is configured to obtain the energy of the codeword to be decoded based on the checksum, the check matrix, and the flipping state of the codeword to be decoded in the current iteration; the processor is configured to select one of a plurality of preset threshold sequences as an initial threshold sequence based on the checksum weights in the initial iteration; and assign a flipping threshold from the initial threshold sequence to the bit-flipping circuit; the bit-flipping circuit is configured to output the codeword to be decoded in the next iteration based on the comparison result between the energy of the codeword to be decoded in the current iteration and the flipping threshold assigned by the processor.

Description

[Technical Field]

[0001] This invention relates to the field of semiconductor technology, and in particular to a decoder, decoding method, memory system and controller. [Previous Technology]

[0002] Memory devices are storage devices used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND (Not-And) memory has gradually become the mainstream product in the storage market due to its high storage density, controllable production costs, and suitable write and erase speeds. However, as people's requirements for storage devices continue to increase, memory devices and their systems still have considerable room for improvement. [Summary of the Invention]

[0003] Embodiments of the present invention provide a decoder, a decoding method, a memory system, and a controller.

[0004] In a first aspect, embodiments of the present invention provide a decoder, including a first processing circuit, a second processing circuit, a processor, and a bit-flipping circuit; wherein, the first processing circuit is configured to: obtain a check expression and a check expression weight based on the codeword to be decoded in the current iteration and a check matrix; the second processing circuit is configured to: obtain the energy of the codeword to be decoded in the current iteration based on the check expression, the check matrix, and the flipping state of the codeword to be decoded in the current iteration; the processor is configured to: in an initial iteration, select a preset threshold sequence from a plurality of preset threshold sequences as an initial threshold sequence based on the check expression weight; and allocate a flipping threshold from the initial threshold sequence to the bit-flipping circuit; and the bit-flipping circuit is configured to: output the codeword to be decoded in the next iteration based on a comparison result between the energy of the codeword to be decoded in the current iteration and the flipping threshold allocated by the processor.

[0005] In some embodiments, the processor is specifically configured to: in the initial iteration, acquire N+1 preset threshold sequences, compare the verification weight with N first thresholds, and select a preset threshold sequence from the N+1 preset threshold sequences as the initial threshold sequence according to the comparison result; the initial threshold sequence includes M flip thresholds; N is a positive integer; M is an integer greater than 1; and in the Lth iteration, assign the Lth flip threshold in the initial threshold sequence to the bit flip circuit; L is a positive integer less than or equal to M.

[0006] In some embodiments, N is 1; the processor is configured to: in the initial iteration, compare the checksum weight with a first threshold; and select a preset threshold sequence corresponding to the checksum weight being greater than the first threshold as the initial threshold sequence, or select a preset threshold sequence corresponding to the checksum weight being less than or equal to the first threshold as the initial threshold sequence, based on the checksum weight being less than or equal to the first threshold.

[0007] In some embodiments, N is greater than 1; the processor is configured to: in the initial iteration, compare the check weight with a plurality of first thresholds to determine the threshold interval in which the check weight is located; and select a preset threshold sequence corresponding to the threshold interval in which the check weight is located as the initial threshold sequence.

[0008] In some embodiments, the processor is further configured to: in the M+Xth iteration, acquire a loop threshold sequence and assign a flip threshold in the loop threshold sequence to the bit flip circuit; where X is a positive integer.

[0009] In some embodiments, the processor is further configured to: in the (M+1)th iteration, acquire P+1 preset loop sequences, compare the check weight in the first iteration or the check weight in the (M+1)th iteration with P second thresholds, and select a preset loop sequence from the P+1 preset loop sequences as the loop threshold sequence according to the comparison result; where P is a positive integer.

[0010] In some embodiments, the second processing circuit is configured to: perform a first calculation on the check expression and the check matrix to obtain the number of errors corresponding to each bit in the codeword to be decoded in the current iteration; obtain a tag value corresponding to each bit according to the flip state of each bit in the codeword to be decoded in the current iteration; and perform a second calculation on the number of errors and the tag value corresponding to each bit in the codeword to be decoded in the current iteration to obtain the energy of the codeword to be decoded.

[0011] In some embodiments, the bit-flipping circuit is configured to: compare the energy of each bit in the codeword to be decoded in the current iteration with the flipping threshold; flip the bit if the energy of the bit is greater than the flipping threshold, or keep the bit unchanged if the energy of the bit is less than or equal to the flipping threshold, so as to obtain the decoded codeword in the current iteration; and output the decoded codeword in the current iteration as the codeword to be decoded in the next iteration.

[0012] In some embodiments, the first processing circuit is configured to: perform a third calculation on the codeword to be decoded in the current iteration and the check matrix to obtain the check expression; and calculate the number of bits that are 1 in the check expression to obtain the check expression weight.

[0013] In some embodiments, the decoder further includes: an output circuit configured to output the codeword to be decoded in the current iteration as the final decoded codeword based on the fact that each bit of the check expression in the current iteration is 0.

[0014] In a second aspect, embodiments of the present invention provide a decoding method, comprising: obtaining a check expression and a check expression weight based on the codeword to be decoded in the current iteration and a check matrix; obtaining the energy of the codeword to be decoded in the current iteration based on the check expression, the check matrix, and the flip state of the codeword to be decoded in the current iteration; in the first iteration, selecting a preset threshold sequence from a plurality of preset threshold sequences as an initial threshold sequence based on the check expression weight; and outputting the codeword to be decoded in the next iteration based on the comparison result between the energy of the codeword to be decoded in the current iteration and one of the flip thresholds in the initial threshold sequence.

[0015] In some embodiments, the step of selecting a preset threshold sequence as an initial threshold sequence from multiple preset threshold sequences based on the check weight in the first iteration, and the step of outputting the codeword to be decoded in the next iteration based on the comparison result of the energy of the codeword to be decoded in the current iteration and a flip threshold in the initial threshold sequence, includes: in the first iteration, obtaining N+1 preset threshold sequences, comparing the check weight with N first thresholds, and selecting a preset threshold sequence from the N+1 preset threshold sequences as the initial threshold sequence according to the comparison result; the initial threshold sequence includes M flip thresholds; N is a positive integer; M is an integer greater than 1; and in the Lth iteration, outputting the codeword to be decoded in the next iteration based on the comparison result of the energy of the codeword to be decoded in the current iteration and the Lth flip threshold in the initial threshold sequence; L is a positive integer less than or equal to M.

[0016] In some embodiments, N is 1; the step of comparing the verification weight with N first thresholds in the initial iteration, and selecting a preset threshold sequence from the N+1 preset threshold sequences as the initial threshold sequence according to the comparison result, includes: in the initial iteration, comparing the verification weight with a first threshold; and selecting a preset threshold sequence corresponding to the verification weight being greater than the first threshold as the initial threshold sequence according to the verification weight being greater than the first threshold, or selecting a preset threshold sequence corresponding to the verification weight being less than or equal to the first threshold as the initial threshold sequence according to the verification weight being less than or equal to the first threshold.

[0017] In some embodiments, N is greater than 1; the step of comparing the verification weight with N first thresholds in the initial iteration, and selecting a preset threshold sequence from the N+1 preset threshold sequences as the initial threshold sequence according to the comparison result, includes: in the initial iteration, comparing the verification weight with multiple first thresholds to determine the threshold interval where the verification weight is located; and selecting a preset threshold sequence corresponding to the threshold interval where the verification weight is located as the initial threshold sequence.

[0018] In some embodiments, the decoding method further includes: in the M+Xth iteration, obtaining a loop threshold sequence, and outputting the codeword to be decoded in the next iteration based on the comparison result between the energy of the codeword to be decoded in the current iteration and a flip threshold in the loop threshold sequence; where X is a positive integer.

[0019] In some embodiments, the decoding method further includes: in the (M+1)th iteration, obtaining P+1 preset loop sequences, comparing the check weight in the first iteration or the check weight in the (M+1)th iteration with P second thresholds, and selecting a preset loop sequence from the P+1 preset loop sequences as the loop threshold sequence according to the comparison result; where P is a positive integer.

[0020] In some embodiments, obtaining the energy of the codeword to be decoded in the current iteration based on the check expression, the check matrix, and the flip state of the codeword to be decoded in the current iteration includes: performing a first calculation on the check expression and the check matrix to obtain the number of errors corresponding to each bit in the codeword to be decoded in the current iteration; obtaining a tag value corresponding to each bit according to the flip state of each bit in the codeword to be decoded in the current iteration; and performing a second calculation on the number of errors and the tag value corresponding to each bit in the codeword to be decoded in the current iteration to obtain the energy of the codeword to be decoded.

[0021] In some embodiments, the step of outputting the codeword to be decoded in the next iteration based on the comparison result of the energy of the codeword to be decoded in the current iteration and a flip threshold in the initial threshold sequence includes: comparing the energy of each bit in the codeword to be decoded in the current iteration with the flip threshold; flipping the bit if the energy of the bit is greater than the flip threshold, or keeping the bit unchanged if the energy of the bit is less than or equal to the flip threshold, so as to obtain the decoded codeword in the current iteration; and outputting the decoded codeword in the current iteration as the codeword to be decoded in the next iteration.

[0022] In some embodiments, obtaining the check expression and check expression weight based on the codeword to be decoded and the check matrix in the current iteration includes: performing a third calculation on the codeword to be decoded and the check matrix in the current iteration to obtain the check expression; and calculating the number of bits that are 1 in the check expression to obtain the check expression weight.

[0023] In some embodiments, the decoding method further includes: outputting the codeword to be decoded in the current iteration as the final decoded codeword, based on the fact that each bit of the check expression in the current iteration is 0.

[0024] In a third aspect, embodiments of the present invention provide a memory system, comprising: a memory configured to output read data; and a decoder as described in any of the above embodiments, configured to decode codewords to be decoded in the read data.

[0025] In some embodiments, the memory system further includes: an encoder configured to receive write data and encode the write data; the memory is further configured to receive the encoded write data.

[0026] In some embodiments, the memory system includes a controller coupled to the memory, the controller including the decoder and the encoder.

[0027] In a fourth aspect, embodiments of the present invention provide a controller, including: an interface configured to receive read data; and a decoder as described in any of the above embodiments, configured to decode codewords to be decoded in the read data.

[0028] In the technical solution provided by the present invention, the processor can acquire multiple preset threshold sequences, and select one of the multiple preset threshold sequences as the initial threshold sequence according to the relationship between the initial check weight and the first threshold. In each iteration, a flip threshold in the initial threshold sequence is assigned to the bit flipping circuit, so that the bit flipping circuit can determine whether to flip the bits of the codeword to be decoded in the current iteration based on the relationship between the flip threshold and the check weight. On the one hand, selecting the initial threshold sequence based on the initial check weight can provide different flip thresholds for codewords to be decoded with different error rates, which can improve the flexibility and specificity of the flip threshold selection, thereby improving the decoding performance of the decoder. On the other hand, the initial threshold sequence includes multiple flip thresholds, which can avoid the extension of decoding time caused by the need to determine the corresponding flip threshold through complex algorithms in each iteration, thereby improving the decoding efficiency of the decoder.

Implementation Method

[0030] Exemplary embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the invention are shown in the drawings, it should be understood that the invention may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0031] Numerous specific details are set forth in the following description to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, to avoid confusion with the invention, some technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0032] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0033] It should be understood that spatial relation terms such as "below," "under," "below," "below," "above," "over," etc., may be used herein for convenience of description to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then the element or feature described as "below" or "under" or "below" the other element or feature will be oriented "over" the other element or feature. Thus, the exemplary terms "below" and "under" can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "compose" and / or "comprise," when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0035] To improve the reliability of data transmission and storage, error-correcting code (ECC) technology has been widely used in digital communication fields, such as wireless and fiber optic communication, and in data storage fields, such as memory systems. Among various error-correcting codes, LDPC (Low Density Parity Check) code is a parallel iterative decoding algorithm based on a sparse array. It has performance approaching the tractor limit, is simple to decode, and can be performed in parallel, making it one of the most widely used error-correcting codes.

[0036] As a typical non-volatile semiconductor memory, NAND (Not-And) memory has gradually become the mainstream product in the storage market due to its high storage density, controllable production cost, and suitable write and erase speed. During the transmission and storage of data in NAND memory, data errors may occur due to hardware failures, software failures, disk errors, etc. To ensure the integrity of user data, it has been proposed to use LDPC codes to detect and correct errors in data stored in memory systems including NAND memory. The memory system provided by this invention will be described below using a memory system including three-dimensional NAND memory as an example.

[0037] Figure 1 is a schematic diagram of an exemplary system with a memory system provided in an embodiment of the present invention. In this embodiment, system 100 may be a mobile phone, desktop computer, notebook computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having memory therein. As shown in Figure 1, system 100 may include a host 101 and a memory system 102, and memory system 102 may include one or more memory devices 103 and a memory controller 104. Host 101 may include a processor of an electronic device, such as a central processing unit (CPU), or a system on a chip (SoC), such as an application processor (AP). Host 101 may be configured to send data to memory system 102 or receive data from memory system 102.

[0038] In some embodiments, the memory controller 104 is coupled to the memory device 103 and the host 101 and is configured to control the memory device 103. The memory controller 104 can manage data stored in the memory device 103 and communicate with the host 101. In some embodiments, the memory controller 104 is designed to operate in low-duty-cycle environments, such as in secure digital cards, compact flash memory cards (CFC), and universal serial bus (USB) flash memory drives, or in other media used in electronic devices such as personal calculators, digital cameras, and mobile phones. In other embodiments, the memory controller 104 is designed to operate in high-duty-cycle environments, such as in solid-state drives or embedded multi-media cards (eMMC).

[0039] In some embodiments, the memory controller 104 and one or more memory devices 103 can be integrated into various types of storage devices, that is, the memory system 102 can be implemented and packaged into different types of terminal electronic products.

[0040] In one example shown in FIG. 2, the memory controller 104 and a single memory device 103 may be integrated into a memory card 201. The memory card 201 may be a compact flash memory card, a smart media card (SMC), a memory stick (MS), a multi-media card (MMC), such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card, such as a Mini SD card, Micro SD card, SDHC card, etc., or a general-purpose flash memory card. The memory card 201 may also include a memory card connector 202 that couples the memory card 201 to a host device (e.g., host 101 in FIG. 1). In another example shown in FIG. 3, the memory controller 104 and multiple memory devices 103 may be integrated into an SSD 203 (solid state disk or solid state drive). SSD 203 may also include an SSD connector 204 that couples SSD 203 to a host device (e.g., host 101 in FIG. 1). In some embodiments, the storage capacity and / or operating speed of SSD 203 is greater than the storage capacity and / or operating speed of memory card 201.

[0041] FIG4 is a circuit diagram of an exemplary memory device 300 including peripheral circuitry provided in an embodiment of the present invention. The memory device 300 may be an example of the memory device 103 in FIG1. ​​The memory device 300 may include a memory array 301 and peripheral circuitry 302 coupled to the memory array 301. Taking a three-dimensional NAND-type memory array as an example, the memory cells 305 are NAND memory cells, and the memory cells 305 are provided in the form of an array of memory cell strings 304, each memory cell string 304 extending vertically above a substrate (not shown). In some embodiments, each memory cell string 304 includes a plurality of memory cells 305 coupled in series and stacked vertically. Each memory cell 305 may maintain a continuous analog value, such as voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 305. Each memory cell 305 may be a float-gate type memory cell including a float-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0042] In some embodiments, each memory cell 305 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some embodiments, each memory cell 305 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, such as a multi-level cell (MLC) storing two bits per cell, a triple-level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0043] As shown in FIG. 4, each memory cell string 304 may include a bottom select transistor (BST) 307 at its source end and a top select transistor (TST) 306 at its drain end. The bottom select transistor 307 and the top select transistor 306 may be configured to activate the selected memory cell string 304 during read and programming operations. In some embodiments, the sources of memory cell strings 304 in the same memory block 303 may be coupled via a common source line (CSL) 310. In other words, all memory cell strings 304 in the same memory block 303 have a common source (ACS). According to some embodiments, the top select transistor 306 of each memory cell string 304 is coupled to a corresponding bit line (BL) 311, and data may be read from or written to the bit line 311 via an output bus (not shown). In some implementations, each memory cell string 304 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the top select transistor 306) or a deselect voltage (e.g., 0V) to the top select gate (TSG) of the corresponding top select transistor 306 via one or more top select lines (TSL) 308 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the bottom select transistor 307) or a deselect voltage (e.g., 0V) to the bottom select gate (BSG) of the corresponding bottom select transistor 307 via one or more bottom select lines (BSL) 309.

[0044] As shown in FIG. 4, the memory cell string 304 can be organized into multiple memory blocks 303, each of which can have a common source line 310. In some embodiments, each memory block 303 is the basic data unit for an erase operation, i.e., all memory cells 305 on the same memory block 303 are erased simultaneously. To erase memory cells 305 in a selected memory block, an erase voltage bias can be used to couple the common source line 310 to the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 305 of adjacent memory cell strings 304 can be coupled via word lines (WL) 312, which selects which row of memory cells 305 is affected by a read or program operation.

[0045] In some embodiments, the peripheral circuitry 302 may include any suitable analog, digital, and mixed-signal circuitry for applying voltage and / or current signals to each target memory cell 305 via bit lines 311, word lines 312, common-source lines 310, bottom select lines 309, and top select lines 308, and for sensing voltage and / or current signals from each target memory cell 305 to enable operation of the memory array 301. The peripheral circuitry 302 may include various types of peripheral circuitry formed using metal-oxide-semiconductor technology.

[0046] Figure 5 illustrates some exemplary memory devices 300, with peripheral circuitry 302 (not shown) including a page buffer / sensor amplifier 401, a column decoder / bit line (BL) driver 402, a row decoder / word line (WL) driver 403, a voltage generator 404, control logic 405, a register bank 406, a flash memory interface (I / F) 407, and a data bus 408. It should be understood that in some examples, the memory device 300 may also include additional peripheral circuitry not shown in Figure 5.

[0047] The page buffer / sensor amplifier 401 can be configured to read data from the memory array 301 and program (write) data to the memory array 301 according to control signals from the control logic 405. In one example, the page buffer / sensor amplifier 401 can store a page of programming data to be programmed into the memory array 301 (write data). In another example, the page buffer / sensor amplifier 401 can perform a programming verification operation to ensure that the data has been correctly programmed into the memory cell coupled to the selected word line. In yet another example, the page buffer / sensor amplifier 401 can also sense a low-power signal from the bit line representing the data bits stored in the memory cell and amplify a small voltage swing to a recognizable logic level during a read operation. The column decoder / bit line driver 402 can be configured to be controlled by the control logic 405 and to select one or more memory cell strings by applying a bit line voltage generated from the voltage generator 404.

[0048] The line decoder / word line driver 403 can be configured to be controlled by control logic 405 and to select / deselect memory blocks of the memory array 301 and to select / deselect word lines of the memory blocks. The line decoder / word line driver 403 can also be configured to drive word lines using word line voltages generated from voltage generator 404. In some embodiments, the line decoder / word line driver 403 can also select / deselect and drive bottom select lines and top select lines. As described in detail below, the line decoder / word line driver 403 is configured to perform programming operations on memory cells coupled to one or more selected word lines(s). Voltage generator 404 can be configured to be controlled by control logic 405 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 301.

[0049] Control logic 405 can be coupled to each part of the peripheral circuitry described above and is configured to control the operation of each part of the peripheral circuitry. Register group 406 can be coupled to control logic 405 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each part of the peripheral circuitry. Flash memory interface 407 can be coupled to control logic 405 and acts as a control buffer to buffer control commands received from a host device (not shown) and relay such control commands to control logic 405, and to buffer status information received from control logic 405 and relay such status information to the memory controller. Flash memory interface 407 can also be coupled to column decoder / bit line driver 402 via data bus 408 and acts as a data I / O interface and data buffer to buffer data and relay such data to or from memory array 301.

[0050] Figure 6 is a schematic diagram of a system including a host and a memory system provided in an embodiment of the present invention. As shown in Figure 6, the memory system 102 is connected to the host 101. The memory system 102 may include a memory controller 104 and a memory device 103. The memory controller 104 is used to control the memory device 103 to perform read, write, erase, and other operations. The memory controller 104 and the memory device 103 may also be coupled in any suitable manner. The memory controller 104 may include a host interface (I / F) 1041, a memory interface (I / F) 1042, a control unit 1043, a debugging module 1044, a cache memory 1047, and a bus 1040. The host interface 1041 is a connection interface between the host 101 and the memory controller 104. The host interface 1041 allows the host 101 and the memory controller 104 to communicate according to a specific protocol, send read and write requests, and perform other operations. The memory interface 1042 is a connection interface between the memory controller 104 and the memory device 103, and is used to realize data transmission between the memory controller 104 and the memory device 103. The control unit 1043 is used to control the memory system 102 as a whole.

[0051] In some specific embodiments, the control unit 1043 may include one or more units with logic operation capabilities, such as a central processing unit (CPU) and / or a microcontroller unit (MCU).

[0052] In some specific embodiments, the cache memory 1047 is used to cache data and can be a volatile memory device with relatively fast read and write speed, such as static random access memory (SRAM) and / or dynamic random access memory (DRAM).

[0053] In some specific embodiments, the error-detection module 1044 can be configured to encode and decode data in the memory system 102 using error-detection code technology. Specifically, the error-detection module 1044 may include an encoder 1045 and a decoder 1046, wherein the encoder 1045 can be configured to encode data to be written to the memory device during a write operation; and the decoder 1046 can be configured to decode codewords to be decoded in the read data during a read operation.

[0054] In some embodiments, during the decoding process of the codeword to be decoded in the read data using the decoder 1046, the flipping threshold used to determine whether the bits in the codeword to be decoded need to be flipped decreases monotonically to a fixed value as the number of decoding iterations increases, and the decoding performance of the decoder 1046 still needs to be improved. In this regard, the present invention proposes the following implementation method.

[0055] The present invention provides a decoder. Figure 7 is a schematic diagram of the composition of the decoder provided in an embodiment of the present invention. As shown in Figure 7, the decoder 1046 includes: a first processing circuit 501, a second processing circuit 502, a processor 503, and a bit-flipping circuit 504. The first processing circuit 501 is configured to: obtain a check expression and a check expression weight based on the codeword to be decoded in the current iteration and the check matrix; the second processing circuit 502 is configured to: obtain the energy of the codeword to be decoded in the current iteration based on the check expression, the check matrix, and the flipping state of the codeword to be decoded in the current iteration; the processor 503 is configured to: in the first iteration, select a preset threshold sequence from multiple preset threshold sequences as the initial threshold sequence based on the check expression weight; allocate a flipping threshold in the initial threshold sequence to the bit-flipping circuit; the bit-flipping circuit 504 is configured to: output the codeword to be decoded in the next iteration based on the comparison result between the energy of the codeword to be decoded in the current iteration and the flipping threshold allocated by the processor.

[0056] In this embodiment of the invention, the processor can be configured to select a preset threshold sequence as the initial threshold sequence from multiple preset threshold sequences in the first iteration based on the check weight calculated by the original codeword to be decoded and the check matrix. The initial threshold sequence may include multiple flip thresholds. In each iteration, the processor can allocate one flip threshold from the initial threshold sequence to the bit flip circuit, so that the bit flip circuit can determine whether to flip the codeword to be decoded based on the comparison result between the energy of the codeword to be decoded in the current iteration and the flip threshold. That is, the processor can be configured to select the corresponding initial threshold sequence based on the bit error rate of the original codeword to be decoded, instead of using the same flip threshold or a threshold sequence composed of multiple flip thresholds for any codeword to be decoded. This can improve the flexibility of the decoder in performing decoding operations, reduce decoding time, and improve decoding performance.

[0057] Figure 8 is a flowchart illustrating the decoding process provided in an embodiment of the present invention. Referring to Figure 8, the main process of decoding using a decoder in this embodiment of the present invention includes: multiplying the check matrix with the original codeword to be decoded to obtain a check expression. Each bit in the check expression represents the result of a check equation, where 0 represents passing and 1 represents a check error. The check expression weight can be obtained by calculating the number of bits that are 1 in the check expression. Here, the original codeword to be decoded can be a vector. If each bit in the check expression is 0, the check expression weight is 0, indicating successful decoding, and the decoder can output the original codeword to be decoded as the final decoded codeword. If there are bits that are 1 in the check expression, the check expression weight is not 0, and iteration is required. Specifically, the original codeword to be decoded is used as the codeword to be decoded in the first iteration. In the first iteration, the energy of the original codeword to be decoded is calculated. The energy of the original codeword to be decoded can be understood as the energy of each bit in the original codeword to be decoded, and the energy of the original codeword to be decoded is compared with the flip threshold. If the energy of a bit in the original codeword to be decoded is greater than the flip threshold, that bit is flipped. If the energy of a bit in the original codeword to be decoded is less than or equal to the flip threshold, that bit remains unchanged, thus obtaining the decoded codeword in the first iteration. The parity check matrix is ​​multiplied by the decoded codeword in the first iteration to obtain the parity check formula and its weight. If the parity check weight is 0, decoding is successful, and the decoder can output the decoded codeword from the first iteration as the final decoded codeword. If the parity check weight is not 0, the second iteration is executed, and the codeword to be decoded in the second iteration is the decoded codeword from the first iteration. The process of each iteration is similar and will not be described in detail. When the parity check weight is 0 in a certain iteration, decoding ends; otherwise, the next iteration is performed.

[0058] Figure 9 is a schematic diagram of a decoder provided in an embodiment of the present invention; Figure 10 is a schematic diagram of a first processing circuit provided in an embodiment of the present invention; Figure 11 is a schematic diagram of a second processing circuit provided in an embodiment of the present invention; Figure 12 is a schematic diagram of a bit-flipping circuit provided in an embodiment of the present invention. The decoder provided in the embodiment of the present invention and the decoding process of the decoder will be described in detail below with reference to Figures 9 to 12.

[0059] Referring to Figure 9, the decoder 1046 further includes a first selector 506, a first cache memory 507, and a second cache memory 508. The first selector 506 can select either the original codeword to be decoded or the iterative codeword to be decoded as the output based on whether the current iteration is the first iteration. If the current iteration is the first iteration, the first selector 506 selects the original codeword to be decoded as the output; if the current iteration is not the first iteration, the first selector 506 selects the iterative codeword to be decoded as the output. Here, the iterative codeword to be decoded is the codeword decoded in the previous iteration. The codeword output from the first selector 506 can be cached in the first cache memory 507, and the original codeword to be decoded can be cached in the second cache memory 508.

[0060] In some embodiments, the first processing circuit 501 is specifically configured to: perform a third calculation on the codeword to be decoded and the check matrix in the current iteration to obtain a check formula; and calculate the number of bits that are 1 in the check formula to obtain the check formula weight.

[0061] Referring to Figures 9 and 10, the first processing circuit 501 includes a third calculation circuit 515 and a fourth calculation circuit 516, wherein the third calculation circuit 515 is connected to the first cache memory 507, and the fourth calculation circuit 516 is connected to the third calculation circuit 515. In some specific embodiments, the third calculation circuit 515 may include a matrix multiplier, and the fourth calculation circuit 516 may include an adder. The decoder also includes a third cache memory 509, in which the parity check matrix is ​​cached, and the third cache memory 509 is connected to the third calculation circuit 515. The third calculation circuit 515 receives the codeword to be decoded in the current iteration from the first cache memory 507 and the parity check matrix from the third cache memory 509, and multiplies the parity check matrix by the codeword to be decoded to obtain the parity expression. In this embodiment of the invention, the check expression can be a vector, and each element in the vector can be obtained by performing a multiplication and addition operation on an element of the codeword to be decoded and a portion of the elements in the check matrix, and the addition operation is modulo-2 addition (1+1=0). The fourth calculation circuit 516 is configured to calculate the number of bits that are 1 in the check expression, thereby obtaining the check expression weight.

[0062] In some embodiments, referring to FIG9, the decoder further includes: an output circuit 505 configured to: output the codeword to be decoded in the current iteration as the final decoded codeword based on the fact that each bit of the check expression in the current iteration is 0.

[0063] In some specific examples, referring to Figure 9, the output circuit 505 includes a third logic circuit 512 and an output switch 518. The third logic circuit 512 is connected to the third calculation circuit 515, and the output switch 518 is connected to both the third logic circuit 512 and the first cache memory 507. Specifically, the third logic circuit 512 can be an OR gate, which can determine whether each bit in the check expression is 0. The output switch 518 can be in a closed state based on each bit in the check expression being 0, thereby causing the codeword to be decoded in the current iteration cached in the first cache memory 507 to be output as the final codeword. The output switch 518 can also be in an open state based on a bit in the check expression being 1. It should be noted that the third logic circuit 512 can also be other combinations of logic gates that achieve the same function.

[0064] In some embodiments, the second processing circuit 502 is specifically configured to: perform a first calculation on the check expression and check matrix to obtain the number of errors corresponding to each bit in the codeword to be decoded in the current iteration; obtain a tag value corresponding to each bit according to the flip state of each bit in the codeword to be decoded in the current iteration; and perform a second calculation on the number of errors and the tag value corresponding to each bit in the codeword to be decoded in the current iteration to obtain the energy of the codeword to be decoded in the current iteration.

[0065] Referring to Figures 9 and 11, the second processing circuit 502 may specifically include a first calculation circuit 513, a second calculation circuit 514, and a second logic circuit 511. The first calculation circuit 513 may be connected to both the third calculation circuit 515 and the third cache memory 509, and the second logic circuit 511 may be connected to both the first cache memory 507 and the second cache memory 508. The first calculation circuit 513 may specifically be a matrix multiplier. The first calculation circuit 513 can multiply the parity check matrix and the parity check expression to obtain the number of error bits. Here, the number of error bits can be a vector, where each element of the vector represents the number of errors corresponding to a bit in the codeword to be decoded in the current iteration. The second logic circuit 511 can be an XOR gate. Based on the codeword to be decoded in the current iteration cached in the first cache memory 507 and the original codeword to be decoded cached in the second cache memory 508, the second logic circuit 511 can determine whether any bits of the codeword to be decoded in the current iteration have been flipped. For example, if a bit in the codeword to be decoded in the current iteration is the same as that bit in the original codeword to be decoded, then that bit has not been flipped, and its flag value is 0; if a bit in the codeword to be decoded in the current iteration is different from that bit in the original codeword to be decoded, then that bit has been flipped, and its flag value is 1. It should be noted that the second logic circuit 511 can also be a combination of other logic gates that achieve the same function.

[0066] In some embodiments, the bit-flipping circuit 504 is specifically configured to: compare the energy of each bit in the codeword to be decoded in the current iteration with the flipping threshold in the current iteration; flip the bit if the energy of the bit is greater than the flipping threshold in the current iteration, or keep the bit unchanged if the energy of the bit is less than or equal to the flipping threshold in the current iteration, so as to obtain the decoded codeword in the current iteration; and output the decoded codeword in the current iteration as the codeword to be decoded in the next iteration.

[0067] Referring to Figures 9 and 12, the bit-flipping circuit 504 includes a bit-flipping determination circuit 517 and a first logic circuit 510. The bit-flipping determination circuit 517 is connected to the second calculation circuit 514, the processor 503, and the first logic circuit 510. The first logic circuit 510 is connected to the first cache memory 507 and the first selector 506. The bit-flipping determination circuit 517 can be configured to compare the energy of each bit in the codeword to be decoded in the current iteration with the flipping threshold in the current iteration. In some specific examples, if the energy of a bit in the codeword to be decoded in the current iteration is greater than the flipping threshold, the flipping flag value of that bit is set to 1; if the energy of a bit in the codeword to be decoded in the current iteration is less than or equal to the flipping threshold, the flipping flag value of that bit is set to 0. The first logic circuit 510 can be an XOR gate. The first logic circuit 510 performs an XOR operation on each bit in the codeword to be decoded in the current iteration with the corresponding bit's flipping flag value to obtain the decoded codeword in the current iteration. In other specific instances, if the energy of a bit in the codeword to be decoded in the current iteration is greater than the flip threshold, the flip flag value of that bit is recorded as 0; if the energy of a bit in the codeword to be decoded in the current iteration is less than or equal to the flip threshold, the flip flag value of that bit is recorded as 1. The first logic circuit 510 can be an XNOR gate. The first logic circuit 510 performs an XNOR operation on each bit in the codeword to be decoded in the current iteration with the corresponding bit's flip flag value, thereby obtaining the decoded codeword in the current iteration, which is the iterative codeword to be decoded in Figure 9. It should be noted that the first logic circuit 510 can also be other combinations of logic gates that achieve the same function.

[0068] In this embodiment of the invention, the flip threshold in each iteration can be allocated by the processor 503 to the bit flip circuit 504. Here, the processor 503 can be the control unit in the memory controller, or it can be a hardware processor independent of the control unit of the memory system.

[0069] In some embodiments, the processor 503 is specifically configured to: in the initial iteration, acquire N+1 preset threshold sequences, compare the check weight with N first thresholds, and select one preset threshold sequence from the N+1 preset threshold sequences as the initial threshold sequence based on the comparison result; N is a positive integer. Here, the check weight in the initial iteration is the initial check weight of the codeword to be decoded in the read data.

[0070] In some embodiments, N can be 1, and the processor 503 is specifically configured to: in the initial iteration, compare the verification weight with a first threshold; and, based on the verification weight being greater than the first threshold, select a preset threshold sequence corresponding to the verification weight being greater than the first threshold as the initial threshold sequence, or, based on the verification weight being less than or equal to the first threshold, select a preset threshold sequence corresponding to the verification weight being less than or equal to the first threshold as the initial threshold sequence.

[0071] In some embodiments, N can be greater than 1, and the processor 503 is specifically configured to: in the initial iteration, compare the verification weight with multiple first thresholds to determine the threshold interval in which the verification weight is located; and select a preset threshold sequence corresponding to the threshold interval in which the verification weight is located as the initial threshold sequence. Here, the values ​​of the multiple first thresholds can be different from each other.

[0072] In some embodiments, the initial threshold sequence includes M flip thresholds, where M is an integer greater than 1; the processor 503 is specifically configured to: in the Lth iteration, assign the Lth flip threshold in the initial threshold sequence to the bit flip circuit 504; L is a positive integer less than or equal to M.

[0073] In some specific examples, the processor 503 may sequentially allocate the M flip thresholds in the initial threshold sequence to the bit flip circuit 504 in a certain order. For example, the processor 503 may sequentially allocate the M flip thresholds in the initial threshold sequence to the bit flip circuit 504 in the order in which the flip thresholds are arranged in the initial threshold sequence, but the present invention is not limited thereto.

[0074] In this embodiment of the invention, the processor 503 can acquire multiple preset threshold sequences, and select one of the multiple preset threshold sequences as the initial threshold sequence according to the relationship between the initial check weight and the first threshold. In each iteration, a flip threshold in the initial threshold sequence is assigned to the bit flipping circuit, so that the bit flipping circuit can determine whether to flip the bits of the codeword to be decoded in the current iteration based on the relationship between the flip threshold and the check weight. On the one hand, selecting the initial threshold sequence based on the initial check weight can provide different flip thresholds for codewords to be decoded with different error rates, which can improve the flexibility and specificity of the flip threshold selection, thereby improving the decoding performance of the decoder. On the other hand, the initial threshold sequence includes multiple flip thresholds, which can avoid the extension of decoding time caused by the need to determine the corresponding flip threshold through a complex algorithm in each iteration, thereby improving the decoding efficiency of the decoder.

[0075] In some embodiments, when all M flip thresholds in the initial threshold sequence have been assigned to the bit flip circuit, and the bits in the check formula obtained by iterating the codeword to be decoded and the check matrix are still not all 0, it means that the decoding process still needs to continue. In this case, the processor 503 is further configured to: in the M+Xth iteration, obtain the loop threshold sequence and assign one flip threshold in the loop threshold sequence to the bit flip circuit; X is a positive integer.

[0076] In some embodiments, the processor 503 is further configured to: acquire P+1 preset loop sequences, compare the check weight in the first iteration or the check weight in the M+1th iteration with P second thresholds, and select a preset loop sequence as the loop threshold sequence from the P+1 preset loop sequences according to the comparison result; P is a positive integer.

[0077] In some specific examples, referring to FIG9, the decoder 1046 may also include a fourth cache memory 519, which may be configured to store a preset threshold sequence and a preset loop sequence, and the processor 503 may be configured to obtain the preset threshold sequence and the preset loop sequence from the fourth cache memory 519.

[0078] In a specific example, referring to Figures 6 and 9, for the decoder 1046 in the memory system 102, a preset threshold sequence and a preset loop sequence can be configured to be stored in the memory device 103. When the memory system 102 is powered on, multiple preset threshold sequences stored in the memory device 103 can be read out and cached in the fourth cache memory 519.

[0079] In this embodiment of the invention, after all the flip thresholds in the initial threshold sequence have been used up, the processor 503 can also use one of the multiple preset loop sequences as the loop threshold sequence. In each subsequent iteration, the processor 503 can allocate one flip threshold from the loop threshold sequence to the bit flip circuit 504, and the multiple flip thresholds in the loop threshold sequence can be reused in a loop, thereby saving cache space used to store the preset threshold sequence and the preset loop sequence. In addition, the processor 503 can select the corresponding preset loop sequence as the loop threshold sequence based on the threshold interval where the initial check weight or the check weight after the initial threshold sequence has been used up, which can further allocate different flip thresholds to codewords to be decoded with different error rates, thereby further improving decoding performance.

[0080] Figures 13 and 14 are schematic diagrams of part of the circuit structure in the processor 503 provided in two specific examples of the present invention. The flip threshold allocation process of the processor 503 will be described below in conjunction with specific examples.

[0081] In a specific example, as shown in FIG13, the processor 503 may include a second selector 521 and a third selector 522. The input of the second selector 521 may receive two preset threshold sequences (e.g., P_a0 P_a1 P_a2 P_a3 0 0 and P_b0 P_b1 P_b2 0 0 0). One of the two preset threshold sequences may correspond to the check weight being greater than the first threshold, and the other preset threshold sequence may correspond to the check weight being less than or equal to the first threshold. The control terminal of the second selector 521 may receive the comparison result between the initial check weight and the first threshold. The second selector 521 may be configured to: output the preset threshold sequence corresponding to the check weight being greater than the first threshold based on the check weight being greater than the first threshold, or output the preset threshold sequence corresponding to the check weight being less than or equal to the first threshold based on the check weight being less than or equal to the first threshold. The input of the third selector 522 can receive a loop threshold sequence (e.g., C_0 C_1 C_2 C_3 C_4 0). The third selector 522 can be configured to: output the flip threshold in the initial threshold sequence when the initial threshold sequence is not used up; and output the flip threshold in the loop threshold sequence after the initial threshold sequence is used up.

[0082] In another specific example, as shown in FIG14, the processor 503 may include a fourth selector 523, a fifth selector 524, and a sixth selector 525. The input of the fourth selector 523 may receive four preset threshold sequences (e.g., P_a0 P_a1 P_a2 P_a3 0 0, P_b0 P_b1 P_b2 0 0 0, P_c0 P_c1 P_c2 P_c3 P_c4 0, and P_d0 P_d1 P_d2 P_d3 P_d4 P_d5). The processor 503 may be configured to: in the initial iteration, compare the check weight with three first thresholds to determine the threshold interval in which the initial check weight is located; the fourth selector 523 may be configured to: output the preset threshold sequence corresponding to the threshold interval in the four preset threshold sequences as the initial threshold sequence according to the threshold interval in which the initial check weight is located. The input of the fifth selector 524 can receive three preset loop sequences (e.g., C_a0 C_a1 C_a2 C_a3 C_a4 0, C_b0 C_b1 C_b2 C_b3 C_b4 C_b5, and C_c0 C_c1 C_c2 C_c3 0 0). The processor 503 can be configured to: in the M+1th iteration, compare the initial check weight or the check weight in the current iteration with two second thresholds to determine the threshold interval in which the initial check weight or the check weight in the current iteration is located, where M is the number of flipped thresholds in the initial threshold sequence; the fifth selector 524 can be configured to: output the preset loop sequence corresponding to the threshold interval in which the initial check weight or the check weight in the current iteration is located as the loop threshold sequence based on the threshold interval in which the check weight is located. The sixth selector 525 can be configured to: output the flip threshold in the initial threshold sequence when the initial threshold sequence is not exhausted; and output the flip threshold in the loop threshold sequence after the initial threshold sequence is exhausted.

[0083] It should be noted that in the above examples, the number of preset threshold sequences, the number of preset loop sequences, and the number of flip thresholds in each sequence are just examples. The present invention does not impose specific limitations on these, nor does the present invention impose specific limitations on the size of each flip threshold.

[0084] In this embodiment of the invention, when the preset threshold sequence is N+1 and the preset cyclic sequence is P+1, the processor 503 can be configured to allocate the flip threshold in one of the threshold sequence combinations of (N+1)*(P+1) threshold sequences to the bit flip circuit when performing decoding operation on the codeword to be decoded, thereby improving the flexibility of the flip threshold allocation and improving the decoding efficiency and decoding performance of the decoder.

[0085] Based on the above decoder, the present invention also provides a controller, including: an interface configured to receive read data; and a decoder as described in any of the above embodiments, configured to decode the codeword to be decoded in the read data.

[0086] The controller here can be the memory controller 104 shown in Figure 1 and Figure 6. The interface here can be the memory interface 1042 shown in Figure 6.

[0087] Based on the above decoder, this embodiment of the invention also provides a memory system, including: a memory configured to output read data; and a decoder as described in any of the above embodiments, configured to decode the codeword to be decoded in the read data.

[0088] In some embodiments, the memory system further includes: an encoder configured to: receive write data and encode the write data; the memory is also configured to: receive the encoded write data.

[0089] In some embodiments, the memory system includes a controller coupled to the memory, the controller including the decoder and encoder described above.

[0090] The structure and composition of the memory system described here can be found in the detailed description of Figures 1 to 6. For the sake of brevity, they will not be repeated here. The memory here can be the memory device 103 shown in Figures 1 to 6. The controller here can be the memory controller 104 shown in Figures 1 and 6.

[0091] Based on the above decoder, this embodiment of the invention also provides a decoding method. Figure 15 is a flowchart of the decoding method provided by this embodiment of the invention. As shown in Figure 15, the decoding method includes: obtaining a check expression and a check expression weight based on the codeword to be decoded in the current iteration and the check matrix; obtaining the energy of the codeword to be decoded in the current iteration based on the check expression, the check matrix, and the flip state of the codeword to be decoded in the current iteration; in the first iteration, selecting a preset threshold sequence as the initial threshold sequence based on the check expression weight from multiple preset threshold sequences; and outputting the codeword to be decoded in the next iteration based on the comparison result between the energy of the codeword to be decoded in the current iteration and a flip threshold in the initial threshold sequence.

[0092] In some embodiments, in the initial iteration, a preset threshold sequence is selected as the initial threshold sequence from multiple preset threshold sequences based on the check weight, and the codeword to be decoded in the next iteration is output based on the comparison result of the energy of the codeword to be decoded in the current iteration and a flip threshold in the initial threshold sequence, including: in the initial iteration, obtaining N+1 preset threshold sequences, comparing the check weight with N first thresholds, and selecting a preset threshold sequence as the initial threshold sequence from the N+1 preset threshold sequences according to the comparison result; the initial threshold sequence includes M flip thresholds; N is a positive integer; M is an integer greater than 1; and in the Lth iteration, the codeword to be decoded in the next iteration is output based on the comparison result of the energy of the codeword to be decoded in the current iteration and the Lth flip threshold in the initial threshold sequence; L is a positive integer less than or equal to M.

[0093] In some embodiments, N is 1; in the initial iteration, the verification weight is compared with N first thresholds, and a preset threshold sequence is selected from N+1 preset threshold sequences as the initial threshold sequence based on the comparison result, including: in the initial iteration, the verification weight is compared with a first threshold; if the verification weight is greater than the first threshold, a preset threshold sequence corresponding to the verification weight being greater than the first threshold is selected as the initial threshold sequence, or if the verification weight is less than or equal to the first threshold, a preset threshold sequence corresponding to the verification weight being less than or equal to the first threshold is selected as the initial threshold sequence.

[0094] In some embodiments, N is greater than 1; in the initial iteration, the verification weight is compared with N first thresholds, and a preset threshold sequence is selected from N+1 preset threshold sequences as the initial threshold sequence based on the comparison result, including: in the initial iteration, the verification weight is compared with multiple first thresholds to determine the threshold interval where the verification weight is located; and a preset threshold sequence corresponding to the threshold interval where the verification weight is located is selected as the initial threshold sequence.

[0095] In some embodiments, the decoding method further includes: in the M+Xth iteration, obtaining a loop threshold sequence, and outputting the codeword to be decoded in the next iteration based on the comparison result between the energy of the codeword to be decoded in the current iteration and a flip threshold in the loop threshold sequence; X is a positive integer.

[0096] In some embodiments, the decoding method further includes: in the M+1th iteration, obtaining P+1 preset loop sequences, comparing the check weight in the first iteration or the check weight in the M+1th iteration with P second thresholds, and selecting a preset loop sequence from the P+1 preset loop sequences as the loop threshold sequence according to the comparison result; P is a positive integer.

[0097] In some embodiments, obtaining the energy of the codeword to be decoded in the current iteration based on the check expression, the check matrix, and the flip state of the codeword to be decoded in the current iteration includes: performing a first calculation on the check expression and the check matrix to obtain the number of errors corresponding to each bit in the codeword to be decoded in the current iteration; obtaining a tag value corresponding to each bit according to the flip state of each bit in the codeword to be decoded in the current iteration; and performing a second calculation on the number of errors and the tag value corresponding to each bit in the codeword to be decoded in the current iteration to obtain the energy of the codeword to be decoded.

[0098] In some embodiments, outputting the codeword to be decoded in the next iteration based on the comparison result of the energy of the codeword to be decoded in the current iteration and a flip threshold in the initial threshold sequence includes: comparing the energy of each bit in the codeword to be decoded in the current iteration with the flip threshold; flipping the bit if the energy of the bit is greater than the flip threshold, or keeping the bit unchanged if the energy of the bit is less than or equal to the flip threshold, so as to obtain the decoded codeword in the current iteration; and outputting the decoded codeword in the current iteration as the codeword to be decoded in the next iteration.

[0099] In some embodiments, obtaining the check expression and check expression weight based on the codeword to be decoded and the check matrix in the current iteration includes: performing a third calculation on the codeword to be decoded and the check matrix in the current iteration to obtain the check expression; and calculating the number of bits that are 1 in the check expression to obtain the check expression weight.

[0100] In some embodiments, the decoding method further includes: outputting the codeword to be decoded in the current iteration as the final decoded codeword, based on the fact that each bit of the check expression in the current iteration is 0.

[0101] Based on the above decoding method, this embodiment of the invention also provides a computer-readable storage medium storing a computer program, which executes the decoding method of any of the above embodiments when executed by a processor.

[0102] Here, all or part of the process in the decoding method in the above embodiments can be implemented by a computer program instructing the relevant hardware. The program can be stored in a computer-readable storage medium. When the program is executed, it can implement the process including the embodiments of the above methods. In some specific embodiments, the computer-readable storage medium may be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), flash memory, magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.; or it may be a device that includes one or any combination of the above memory devices.

[0103] The features disclosed in the several device embodiments provided by the present invention can be arbitrarily combined without conflict to obtain new device embodiments.

[0104] The methods disclosed in the several method embodiments provided by the present invention can be arbitrarily combined without conflict to obtain new method embodiments.

[0105] The above description is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the protection scope of the present invention. [Simplified Explanation of the Diagram]

[0029] Figure 1 is a schematic diagram of an exemplary system with a memory system according to an embodiment of the present invention. Figure 2 is a schematic diagram of an exemplary memory card with a memory system according to an embodiment of the present invention. Figure 3 is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of the present invention. Figure 4 is a schematic diagram of an exemplary memory device including peripheral circuitry according to an embodiment of the present invention. Figure 5 is a schematic diagram of an exemplary memory including a memory array and peripheral circuitry according to an embodiment of the present invention. Figure 6 is a schematic diagram of another exemplary system with a memory system according to an embodiment of the present invention. Figure 7 is a schematic diagram of a decoder according to an embodiment of the present invention. Figure 8 is a flowchart of a decoding process according to an embodiment of the present invention. Figure 9 is a schematic diagram of a decoder according to an embodiment of the present invention. Figure 10 is a schematic diagram of a first processing circuit according to an embodiment of the present invention. Figure 11 is a schematic diagram of a second processing circuit according to an embodiment of the present invention. Figure 12 is a schematic diagram of a bit-flipping circuit according to an embodiment of the present invention. Figure 13 is a schematic diagram of a processor circuit structure according to a specific example of the present invention. Figure 14 is a schematic diagram of a processor circuit structure according to a specific example of the present invention. Figure 15 is a flowchart of a decoding method according to an embodiment of the present invention.

Claims

1. A decoder, comprising a first processing circuit, a second processing circuit, a processor, and a bit-flipping circuit; wherein, The first processing circuit is configured to: obtain a check formula and a check formula weight based on the codeword to be decoded and the check matrix in the current iteration; the second processing circuit is configured to: obtain the energy of the codeword to be decoded in the current iteration based on the check formula, the check matrix, and the flip state of the codeword to be decoded in the current iteration; Perform a first calculation on the check expression and the check matrix to obtain the number of errors corresponding to each bit in the codeword to be decoded in the current iteration; obtain the tag value corresponding to each bit according to the flip state of each bit in the codeword to be decoded in the current iteration; The processor is configured to perform a second calculation on the number of errors and the flag value corresponding to each bit in the codeword to be decoded in the current iteration to obtain the energy of the codeword to be decoded; the processor is configured to: in the initial iteration, select a preset threshold sequence as an initial threshold sequence from a plurality of preset threshold sequences based on the check weights; and assign a flip threshold in the initial threshold sequence to the bit flip circuit; and the bit flip circuit is configured to: output the codeword to be decoded in the next iteration based on the comparison result between the energy of the codeword to be decoded in the current iteration and the flip threshold assigned by the processor.

2. The decoder as described in claim 1, wherein, The processor is configured to: in the initial iteration, acquire N+1 preset threshold sequences, compare the verification weight with N first thresholds, and select a preset threshold sequence from the N+1 preset threshold sequences as the initial threshold sequence based on the comparison result; the initial threshold sequence includes M flip thresholds; N is a positive integer; M is an integer greater than 1; And in the Lth iteration, the Lth flip threshold in the initial threshold sequence is assigned to the bit flip circuit; where L is a positive integer less than or equal to M.

3. The decoder as described in claim 2, wherein, The N is 1; the processor is configured to: in the initial iteration, compare the verification weight with a first threshold; and select a preset threshold sequence corresponding to the verification weight being greater than the first threshold as the initial threshold sequence, or select a preset threshold sequence corresponding to the verification weight being less than or equal to the first threshold as the initial threshold sequence, based on the verification weight being less than or equal to the first threshold.

4. The decoder as described in claim 2, wherein, The N is greater than 1; the processor is configured to: in the initial iteration, compare the verification weight with a plurality of first thresholds to determine the threshold interval in which the verification weight is located; and select a preset threshold sequence corresponding to the threshold interval in which the verification weight is located as the initial threshold sequence.

5. The decoder as described in claim 2, wherein, The processor is further configured to: in the M+Xth iteration, acquire a loop threshold sequence and assign a flip threshold from the loop threshold sequence to the bit flip circuit; where X is a positive integer.

6. The decoder as described in claim 5, wherein, The processor is further configured to: in the (M+1)th iteration, acquire P+1 preset cyclic sequences, compare the check weights in the initial iteration or the check weights in the (M+1)th iteration with P second thresholds, and select a preset cyclic sequence from the P+1 preset cyclic sequences as the loop threshold sequence based on the comparison result; where P is a positive integer.

7. The decoder as described in claim 1, wherein, The bit-flipping circuit is configured to: compare the energy of each bit in the codeword to be decoded in the current iteration with the flipping threshold; flip the bit if the energy of the bit is greater than the flipping threshold, or keep the bit unchanged if the energy of the bit is less than or equal to the flipping threshold, so as to obtain the decoded codeword in the current iteration; and output the decoded codeword in the current iteration as the codeword to be decoded in the next iteration.

8. The decoder as described in claim 1, wherein, The first processing circuit is configured to: perform a third calculation on the codeword to be decoded in the current iteration and the parity check matrix to obtain the parity check formula; and calculate the number of bits that are 1 in the parity check formula to obtain the parity check formula weight.

9. The decoder as described in claim 1, wherein, The decoder further includes an output circuit configured to output the codeword to be decoded in the current iteration as the final decoded codeword, based on the fact that each bit of the check expression in the current iteration is 0.

10. A decoding method, comprising: Based on the codeword to be decoded and the check matrix in the current iteration, the check formula and the check formula weight are obtained; The energy of the codeword to be decoded in the current iteration is obtained based on the check expression, the check matrix, and the flip state of the codeword to be decoded in the current iteration, including: performing a first calculation on the check expression and the check matrix to obtain the number of errors corresponding to each bit in the codeword to be decoded in the current iteration; obtaining a tag value corresponding to each bit according to the flip state of each bit in the codeword to be decoded in the current iteration; and performing a second calculation on the number of errors and the tag value corresponding to each bit in the codeword to be decoded in the current iteration to obtain the energy of the codeword to be decoded; in the initial iteration, selecting a preset threshold sequence as an initial threshold sequence from multiple preset threshold sequences based on the check expression weight; and outputting the codeword to be decoded in the next iteration based on the comparison result between the energy of the codeword to be decoded in the current iteration and a flip threshold in the initial threshold sequence.

11. The decoding method as described in claim 10, wherein, The steps of selecting a preset threshold sequence as the initial threshold sequence from multiple preset threshold sequences based on the check weight in the first iteration, and outputting the codeword to be decoded in the next iteration based on the comparison result of the energy of the codeword to be decoded in the current iteration and a flip threshold in the initial threshold sequence, include: In the first iteration, obtaining N+1 preset threshold sequences, comparing the check weight with N first thresholds, and selecting a preset threshold sequence from the N+1 preset threshold sequences as the initial threshold sequence according to the comparison result; the initial threshold sequence includes M flip thresholds; N is a positive integer; M is an integer greater than 1; and in the Lth iteration, outputting the codeword to be decoded in the next iteration based on the comparison result of the energy of the codeword to be decoded in the current iteration and the Lth flip threshold in the initial threshold sequence; L is a positive integer less than or equal to M.

12. The decoding method as described in claim 11, wherein, The N is 1; the step of comparing the verification weight with N first thresholds in the initial iteration, and selecting a preset threshold sequence from the N+1 preset threshold sequences as the initial threshold sequence based on the comparison result, includes: in the initial iteration, comparing the verification weight with a first threshold; and selecting a preset threshold sequence corresponding to the verification weight being greater than the first threshold as the initial threshold sequence based on the verification weight being greater than the first threshold, or selecting a preset threshold sequence corresponding to the verification weight being less than or equal to the first threshold as the initial threshold sequence based on the verification weight being less than or equal to the first threshold.

13. The decoding method as described in claim 11, wherein, The N is greater than 1; the step of comparing the verification weight with N first thresholds in the initial iteration, and selecting a preset threshold sequence from the N+1 preset threshold sequences as the initial threshold sequence based on the comparison result, includes: comparing the verification weight with multiple first thresholds in the initial iteration to determine the threshold interval in which the verification weight is located; and selecting a preset threshold sequence corresponding to the threshold interval in which the verification weight is located as the initial threshold sequence.

14. The decoding method as described in claim 11 further includes: In the (M+X)th iteration, a loop threshold sequence is obtained, and the codeword to be decoded in the next iteration is output based on the comparison result between the energy of the codeword to be decoded in the current iteration and a flip threshold in the loop threshold sequence; where X is a positive integer.

15. The decoding method as described in claim 14 further includes: In the (M+1)th iteration, P+1 preset cyclic sequences are obtained. The check weights in the first iteration or the check weights in the (M+1)th iteration are compared with P second thresholds. Based on the comparison result, a preset cyclic sequence is selected from the P+1 preset cyclic sequences as the loop threshold sequence; where P is a positive integer.

16. The decoding method as described in claim 10, wherein, The step of outputting the codeword to be decoded in the next iteration based on the comparison result between the energy of the codeword to be decoded in the current iteration and a flip threshold in the initial threshold sequence includes: comparing the energy of each bit in the codeword to be decoded in the current iteration with the flip threshold; flipping the bit if the bit energy is greater than the flip threshold, or keeping the bit unchanged if the bit energy is less than or equal to the flip threshold, to obtain the decoded codeword in the current iteration; and outputting the decoded codeword in the current iteration as the codeword to be decoded in the next iteration.

17. The decoding method as described in claim 10, wherein, The step of obtaining the check expression and check expression weight based on the codeword to be decoded and the check matrix in the current iteration includes: performing a third calculation on the codeword to be decoded and the check matrix in the current iteration to obtain the check expression; and calculating the number of bits that are 1 in the check expression to obtain the check expression weight.

18. The decoding method as described in claim 10, wherein, The decoding method further includes: outputting the codeword to be decoded in the current iteration as the final decoded codeword, based on the fact that each bit of the check expression in the current iteration is 0.

19. A memory system comprising: The memory is configured to output and read data. And the decoder described in any one of requests 1 to 9 is configured to decode the codewords to be decoded in the read data.

20. The memory system as described in claim 19, further comprising: The encoder is configured to receive written data and encode the written data; The memory is also configured to receive encoded write data.

21. The memory system as described in claim 20, wherein, The memory system includes a controller coupled to the memory, the controller including the decoder and the encoder.

22. A controller, comprising: The interface is configured to receive and read data. And the decoder described in any one of requests 1 to 9 is configured to decode the codewords to be decoded in the read data.

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