Selective etching of alternating layers of silicon oxide and silicon nitride for high aspect ratio contacts

Abstract

Exemplary semiconductor processing methods may include introducing a fluorine-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be positioned within the processing region. The substrate may include alternating layers of silicon nitride and silicon oxide. The method may include forming a plasma effluent of the fluorine-containing precursor. The method may include contacting the substrate with the plasma effluent of the fluorine-containing precursor. The contact may selectively etch exposed portions of the silicon nitride. The method may include introducing phosphorus- and fluorine-containing precursors into a processing region of a semiconductor processing chamber while maintaining the flow of the fluorine-containing precursor. The method may include forming a fluorine-containing precursor and a plasma effluent of phosphorus- and fluorine-containing precursors. The method may include contacting the substrate with the fluorine-containing precursor and the plasma effluent of the phosphorus- and fluorine-containing precursors. The contact may selectively etch exposed portions of the silicon oxide.

Description

[Technical Field]

[0001] This application claims the benefit and priority of U.S. Patent Application No. 18 / 593,014, filed March 1, 2024, entitled “SELECTIVE ETCHING OF ALTERNATING LAYERS OF SILICON OXIDE AND SILICON NITRIDE FOR HIGH ASPECT RATIO CONTACTS”, the entire contents of which are incorporated herein by reference.

[0002] This technology relates to semiconductor manufacturing processes and equipment. More specifically, this technology relates to the cyclic etching of silicon oxide and silicon nitride materials. [Previous Technology]

[0003] Integrated circuits may be fabricated through a process that creates a complex patterned material layer on the surface of a substrate. Creating a patterned material on the substrate requires a controlled method for removing exposed material. Chemical etching is used for various purposes, including transferring patterns from photoresist to underlying layers, thinning layers, or thinning the lateral dimensions of features already present on the surface. It is generally desirable to have etching processes that etch one material faster than another, thereby facilitating, for example, pattern transfer processes. This type of etching process is referred to as being selective for the first material. Due to the diversity of materials, circuits, and processes, selective etching processes for various materials have been developed.

[0004] Based on the materials used in the process, the etching process can be referred to as wet or dry. Compared to other dielectrics and materials, wet HF etching preferentially removes silicon oxide. However, wet processes may have difficulty penetrating some constrained trenches and may sometimes distort the remaining material. Dry etching, generated in localized plasma formed within the substrate processing area, can penetrate more constrained trenches and exhibits less distortion in the fine remaining structure. However, localized plasma can generate arcs during discharge, thereby damaging the substrate.

[0005] Therefore, there is a need for improved systems and methods for producing high-quality components and structures. This technology addresses these and other needs. [Summary of the Invention]

[0006] Exemplary semiconductor processing methods may include introducing a fluorine-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be positioned within the processing region. The substrate may include alternating layers of silicon nitride and silicon oxide. These methods may include forming a plasma effluent containing the fluorine-containing precursor. These methods may include contacting the substrate with the plasma effluent containing the fluorine-containing precursor. The contact may selectively etch exposed portions of the silicon nitride. These methods may include introducing phosphorus- and fluorine-containing precursors into a processing region of a semiconductor processing chamber while maintaining the flow of the fluorine-containing precursor. These methods may include forming a fluorine-containing precursor and a plasma effluent containing both phosphorus and fluorine precursors. These methods may include contacting the substrate with the fluorine-containing precursor and the plasma effluent containing both phosphorus and fluorine precursors. The contact may selectively etch exposed portions of the silicon oxide.

[0007] In some embodiments, the fluorinated precursor may be or include hydrogen fluoride (HF). The phosphorus and fluorine-containing precursor may be or include phosphorus trifluoride (PF3). The flow rate of the fluorinated precursor may be greater than or about 100 sccm. The flow rate of the phosphorus and fluorine-containing precursor may be less than or about 50 sccm. The fluorinated precursor may be carbon-free. When forming the plasma effluent of the fluorinated precursor and the plasma effluent of the fluorinated precursor and the phosphorus and fluorine-containing precursor, the source plasma power may be pulsed. These methods may include applying a bias power while contacting the stack layer with the plasma effluent of the fluorinated precursor and the plasma effluent of the fluorinated precursor and the phosphorus and fluorine-containing precursor. The bias power may be greater than or about 100 W. When the stack layer contacts the plasma effluent of the fluorinated precursor and the plasma effluent of the fluorinated precursor and the phosphorus and fluorine-containing precursor, the bias power may be pulsed. The method can be performed at a chamber operating pressure of less than or about 500 mTorr. The method can be performed at a substrate operating temperature of less than or about 0°C.

[0008] Some embodiments of this technology may cover semiconductor processing methods. These methods may include i) flowing a fluorine-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be positioned within the processing region. The substrate may include alternating layers of silicon nitride and silicon oxide. The substrate may include a patterned resist material covering the alternating layers of silicon nitride and silicon oxide. These methods may include ii) forming a plasma effluent of the fluorine-containing precursor. These methods may include iii) contacting a stacked layer with the plasma effluent of the fluorine-containing precursor. The contact may selectively etch an exposed layer of silicon nitride. These methods may include iv) flowing a phosphorus- and fluorine-containing precursor together with the fluorine-containing precursor into a processing region of a semiconductor processing chamber. These methods may include v) forming a plasma effluent of the fluorine-containing precursor and the phosphorus- and fluorine-containing precursor. These methods may include vi) contacting a stacked layer with the plasma effluent of the fluorine-containing precursor and the phosphorus- and fluorine-containing precursor. The contact may selectively etch an exposed layer of silicon nitride. These methods may include vii) repeating operation i) to vi) for at least a second cycle.

[0009] In some embodiments, the fluorine-containing precursor may further include hydrogen. The etching rate of the exposed silicon nitride layer may be greater than or about 250 nm / min. The etching rate of the exposed silicon nitride layer may be greater than or about 400 nm / min. Operations i) to vi) may be repeated for at least ten cycles. These methods may be performed at substrate operating temperatures below or about -20°C.

[0010] Some embodiments of this technology may cover semiconductor processing methods. These methods may include introducing a fluorine-containing precursor into a processing region of a semiconductor processing chamber. A substrate may be located within the processing region. The substrate may include alternating layers of silicon nitride and silicon oxide. These methods may include forming a plasma effluent of the fluorine-containing precursor. These methods may include contacting the substrate with the plasma effluent of the fluorine-containing precursor. The contact may selectively etch the exposed portion of silicon nitride relative to silicon oxide at a ratio greater than or about 5:1. These methods may include introducing phosphorus- and fluorine-containing precursors into a processing region of a semiconductor processing chamber while maintaining the flow of the fluorine-containing precursor. These methods may include forming a fluorine-containing precursor and a plasma effluent of phosphorus- and fluorine-containing precursors. These methods may include contacting the substrate with the plasma effluent of the fluorine-containing precursor and the plasma effluent of the phosphorus- and fluorine-containing precursors. The contact may selectively etch the exposed portion of silicon oxide relative to silicon nitride at a ratio greater than or about 5:1.

[0011] In some embodiments, the flow rate ratio of the fluorine-containing precursor to the phosphorus- and fluorine-containing precursor may be greater than or about 30:1.

[0012] This technology offers numerous advantages over conventional systems and techniques. For example, these processes can etch stacked layers comprising alternating layers of silicon nitride and silicon oxide within a semiconductor structure. Furthermore, these processes can uniformly etch through the alternating layers of silicon nitride and silicon oxide without the use of polymerization gases and / or greenhouse gases. These and other embodiments, along with their numerous advantages and features, are described in more detail below in conjunction with the accompanying drawings.

Implementation Method

[0020] In the transition from 2D NAND to 3D NAND, many process operations have been changed from horizontal to vertical. Furthermore, as the number of cells being formed in the 3D NAND structure increases, the aspect ratios of memory vias and other structures increase, sometimes dramatically. During 3D NAND processing, the stacking of placeholder layers and dielectric materials can form inter-electrode dielectrics or integrated passive device (IPD) layers. These placeholder layers may undergo various operations to house the structure before the material is completely removed and replaced with metal. For example, one or more memory vias or trenches can be etched in the stack of placeholder layers and dielectric materials before the placeholder layers are removed.

[0021] Many conventional techniques utilize etching processes that passivate the sidewalls of memory vias or trenches. Passivating the sidewalls maintains a uniform profile of the memory vias or trenches and minimizes lateral etching. However, the formation of the passivation material (which may be a polymer) on the sidewalls may be uneven throughout the entire depth of the memory vias or trenches. Therefore, conventional techniques may suffer from pattern loading and / or bending. Furthermore, conventional techniques for forming polymeric passivation materials may deposit polymeric materials on wafer bevels, which could lead to arcing.

[0022] This technology overcomes these problems by performing an etching process using cyclic exposure first to a fluorine-containing precursor, then to a fluorine-containing precursor and finally to phosphorus- and fluorine-containing precursors. The etching process can be performed at low temperatures, which increases the directionality of the etching without the need for polymer passivation materials. Due to the high directionality of the etching, the problem of memory hole or trench contours is reduced and / or eliminated. In addition, arc discharge is mitigated because polymer materials are not unintentionally deposited on the wafer ramps.

[0023] Although the remainder of the disclosure will, as is customary, identify specific etching processes utilizing the disclosed techniques, it will be readily understood that these systems and methods are equally applicable to deposition and cleaning processes that may occur within the chamber. Therefore, this technique should not be construed as being limited to etching processes or etching chambers only. Furthermore, although exemplary chambers have been described to provide a basis for this technique, it should be understood that this technique can indeed be applied to any semiconductor processing chamber that allows the operation of the single chamber.

[0024] Figure 1 illustrates a top view of one embodiment of a processing system 10 with deposition, etching, baking, and / or curing chambers according to an embodiment. The tool or processing system 10 illustrated in Figure 1 may include a plurality of processing chambers 24a to d, a transfer chamber 20, a maintenance chamber 26, an integrated metering chamber 28, and a pair of loading gate chambers 16a to b. The processing chambers may include any number of structures or components, and any number of processing chambers or combinations of processing chambers.

[0025] To transfer substrates between chambers, transfer chamber 20 may include a robotic transfer mechanism 22. Transfer mechanism 22 may have a pair of substrate transfer blades 22a respectively attached to the distal end of an extendable arm 22b. Blades 22a can be used to carry individual substrates in and out of processing chambers. In operation, one of the substrate transfer blades, such as those of transfer mechanism 22, can retrieve substrate W from one of the loading gate chambers, such as chambers 16a to 16b, and carry substrate W to a first stage of processing, such as the processing steps described below in chambers 24a to 16d. These chambers may be included to perform individual or combined operations of the technology. For example, while one or more chambers may be configured to perform deposition or etching operations, one or more other chambers may be configured to perform the preprocessing operations and / or one or more post-processing operations. This technology covers any number of configurations that can also perform any number of additional manufacturing operations typically performed in semiconductor processing.

[0026] If a chamber is occupied, the robot can wait until processing is complete, then use a blade 22a to remove the processed substrate from the chamber and insert a new substrate using a second blade. Once the substrate has been processed, it can be moved to the second stage of processing. For each move, the transfer mechanism 22 typically has one blade carrying the substrate and one empty blade to perform the substrate exchange. The transfer mechanism 22 can wait in each chamber until the exchange can be completed.

[0027] Once processing is complete in the processing chamber, the transfer mechanism 22 can move the substrate W from the previous processing chamber and transfer the substrate W to a cassette in the loading gate chambers 16a to b. The substrate can be moved from the loading gate chambers 16a to b to the factory interface 12. The factory interface 12 is generally operable to transfer substrates between the cassette loaders 14a to d and the loading gate chambers 16a to b in an atmospheric pressure clean environment. The clean environment in the factory interface 12 can generally be provided by an air filtration process, such as HEPA filtration. The factory interface 12 may also include a substrate aligner / aligner for properly aligning the substrates prior to processing. At least one substrate robot (such as robots 18a to b) can be positioned in the factory interface 12 to transfer substrates between different locations / sites within the factory interface 12 and to other sites associated with it. Robots 18a to b can be configured to travel from a first end to a second end of the factory interface 12 along a track system within the factory interface 12.

[0028] The processing system 10 may further include an integrated metrology chamber 28 to provide control signals that can provide adaptive control for any process being performed in the processing chamber. The integrated metrology chamber 28 may include any of a variety of metrology devices to measure various film properties, such as thickness, roughness, composition, and the metrology devices may further be able to characterize grating parameters, such as critical dimensions, sidewall angles, and characteristic height under vacuum, in an automated manner.

[0029] Each processing chamber 24a to d may be configured to perform one or more process steps in semiconductor structure fabrication, and any number of processing chambers and combinations thereof may be used on the multi-chamber processing system 10. For example, any processing chamber may be configured to perform multiple substrate processing operations, including any number of deposition processes, including cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, and other operations, including etching, pre-cleaning, pretreatment, post-treatment, annealing, plasma treatment, degassing, orientation, and other substrate processes. Some specific processes that may be performed in any chamber or any combination of chambers may be metal deposition, surface cleaning and preparation, thermal annealing (such as rapid thermal processing), and plasma treatment. Those skilled in the art will readily understand that any other processes may be similarly performed in specific chambers incorporated into the multi-chamber processing system 10, including any of the processes described below.

[0030] Figure 2 shows a schematic cross-sectional view of an exemplary processing chamber 100 suitable for patterning a material layer disposed on a substrate 302 within the processing chamber 100. The exemplary processing chamber 100 is suitable for performing a patterning process; however, it should be understood that the present invention can be performed in any number of chambers, and a substrate support according to the present invention can be included in an etching chamber, a deposition chamber, a treatment chamber, or any other processing chamber. The plasma processing chamber 100 may include a chamber body 105 defining a chamber volume 101 in which a substrate can be processed. The chamber body 105 may have sidewalls 112 coupled to a ground plane 126 and a bottom 118. The sidewalls 112 may have pads 115 to protect the sidewalls 112 and extend the time between maintenance cycles of the plasma processing chamber 100. The size of the chamber body 105 and related components of the plasma processing chamber 100 is not limited and can be substantially larger than the size of the substrate 302 to be processed therein. Examples of substrate sizes include 200 mm, 250 mm, 300 mm, and 450 mm diameters, as well as other sizes, such as display or solar cell substrates.

[0031] The chamber body 105 may support the chamber cover assembly 110 to enclose the chamber volume 101. The chamber body 105 may be made of aluminum or other suitable materials. A substrate in / out port 113 may be formed through the sidewall 112 of the chamber body 105 to facilitate the transfer of the substrate 302 into and out of the plasma processing chamber 100. As previously described, the in / out port 113 may be coupled to a transfer chamber and / or other chambers of the substrate processing system. A pumping port 145 may be formed through the sidewall 112 of the chamber body 105 and connected to the chamber volume 101. A pumping device may be coupled to the chamber volume 101 through the pumping port 145 to vent and control the pressure within the processing volume. The pumping device may include one or more pumps and throttle valves.

[0032] The gas panel 160 may be coupled to the chamber body 105 via a gas line 167 to supply process gases to the chamber volume 101. The gas panel 160 may include one or more process gas sources 161, 162, 163, 164, and may additionally include inert gases, non-reactive gases, and reactive gases, as applicable to any number of processes. Examples of process gases that may be provided by the gas panel 160 include, but are not limited to, hydrocarbon gases, including methane, sulfur hexafluoride, silicon chloride, carbon tetrafluoride, hydrogen bromide, hydrocarbon gases, argon, chlorine, nitrogen, helium, or oxygen, and any number of additional materials. In addition, the treated gases may include gases containing nitrogen, chlorine, fluorine, oxygen and hydrogen, such as H2, NH3, H2O, H2O2, NF3, HF, F2, CF4, CHF3, C2F6, C2F4, C3F6, C4F6, C4F8, BrF3, ClF3, SF6, CH3F, CH2F2, BCl3, PF3, PH3, COS and SO2, as well as any number of additional precursors.

[0033] Valve 166 controls the flow rate of process gas from sources 161, 162, 163, 164 of gas panel 160 and can be managed by controller 165. The gas flow rate supplied from gas panel 160 to chamber body 105 may include a combination of gases from one or more sources. Cover assembly 110 may include nozzle 114. Nozzle 114 may be one or more ports for introducing process gas from sources 161, 162, 164, 163 of gas panel 160 into chamber volume 101. After the process gas is introduced into plasma processing chamber 100, the gas can be agitated to form plasma. Antenna 148, such as one or more sensor coils, may be provided adjacent to plasma processing chamber 100. Antenna power supply 142 can power antenna 148 via matching circuit 141 to inductively couple energy (such as RF energy) to the processing gas, thereby retaining plasma formed by the processing gas within the chamber volume 101 of plasma processing chamber 100. Alternatively, or in addition to antenna power supply 142, processing electrodes below and / or above substrate 302 can be used to couple RF power capacitors to the processing gas to retain plasma within chamber volume 101. Operation of power supply 142 can be controlled by a controller (such as controller 165) that also controls the operation of other components within plasma processing chamber 100.

[0034] A substrate support base 135 may be disposed in the chamber volume 101 to support the substrate 302 during processing. The substrate support base 135 may include an electrostatic chuck (ESC) 122 for holding the substrate 302 during processing. The electrostatic chuck 122 may use electrostatic attraction to hold the substrate 302 to the substrate support base 135. The ESC 122 may be powered by an RF power supply 125 integrated with matching circuitry 124. The ESC 122 may include electrodes 121 embedded in a dielectric. The electrodes 121 may be coupled to the RF power supply 125 and may provide a bias voltage that attracts plasma ions formed by the processing gas in the chamber volume 101 to the ESC 122 and the substrate 302 located on the base. During processing of the substrate 302, the RF power supply 125 may be cyclically switched on or off or pulsed. ESC 122 may have an isolator 128 to reduce the attraction of the sidewalls of ESC 122 to plasma, thereby extending the maintenance life cycle of ESC 122. Additionally, the substrate support base 135 may have a cathode pad 136 to protect the sidewalls of the substrate support base 135 from plasma gases and extend the time between maintenance of the plasma processing chamber 100.

[0035] Electrode 121 may be coupled to power supply 150. Power supply 150 may provide electrode 121 with a clamping voltage of approximately 500 volts to approximately 15,000 volts. Power supply 150 may also include a system controller for controlling the operation of electrode 121 by directing DC current to electrode 121 to clamp and release substrate 302. For example, similar to RF power supply 125, power supply 150 may provide a bias voltage that attracts plasma ions formed by the processing gas in chamber volume 101 to ESC 122 and substrate 302 located on the pedestal. During processing of substrate 302, power supply 150 may cycle on and off or pulse. In embodiments, power supply 150 may supply RF power, DC current, or voltage for clamping and / or biasing, or a combination thereof. In additional embodiments, multiple power supplies may be configured to provide RF power and DC current or voltage for clamping and / or biasing. ESC 122 may include a heater disposed within a base and connected to a power source for heating the substrate, while a cooling substrate 129 supporting ESC 122 may include conduits for circulating heat transfer fluid to maintain the temperature of ESC 122 and the substrate 302 disposed thereon. ESC 122 may be configured to operate within the temperature range required by the thermal budget of the components manufactured on the substrate 302. For example, ESC 122 may be configured to maintain the substrate 302 at a temperature of about -150°C or lower to about 500°C or higher, depending on the process being performed.

[0036] A cooling substrate 129 may be provided to assist in controlling the temperature of the substrate 302. To reduce process drift and time, the temperature of the substrate 302 may be kept substantially constant by the cooling substrate 129 throughout the time the substrate 302 is in the cleaning chamber. In some embodiments, the temperature of the substrate 302 may be maintained between about -150°C and about 500°C throughout the subsequent cleaning process, but any temperature may be used. A cover ring 130 may be disposed on the ESC 122 and positioned along the periphery of the substrate support base 135. The cover ring 130 may be configured to confine the etching gas to a desired portion of the exposed top surface of the substrate 302 while shielding the top surface of the substrate support base 135 from the plasma environment inside the plasma processing chamber 100. A lifting pin may be selectively translated through the substrate support base 135 to lift the substrate 302 above the substrate support base 135 to facilitate access to the substrate 302 by a transfer robot or other suitable transfer mechanism, as previously described.

[0037] The controller 165 can be used to control the process sequence, regulate the gas flow rate entering the plasma processing chamber 100 from the gas panel 160, and other process parameters. When executed by the CPU, the software routines transform the CPU into a dedicated computer, such as a controller, which controls the plasma processing chamber 100 to perform the process according to this disclosure. The software routines can also be stored and / or executed by a second controller associated with the plasma processing chamber 100.

[0038] The chambers discussed above can be used to perform exemplary methods, including etching methods, but any number of chambers can be configured to perform one or more patterns used in embodiments of the present technology. Turning to Figure 3, this figure illustrates exemplary operations in method 300 according to an embodiment of the present technology. Method 300 may include one or more operations prior to the commencement of the method, including front-end processing, deposition, etching, polishing, cleaning, or any other operations that may be performed prior to said operations. According to embodiments of the present technology, such methods may include multiple optional operations that may or may not be specifically associated with some embodiments of the method. For example, many operations are described to provide a broader scope of the process performed, but such operations are not essential to the present technology or may be performed by alternative methods discussed further below. Method 300 may describe the operations schematically illustrated in Figures 4A to 4D, and the illustration of such operations will be described in conjunction with the operations of method 300. It should be understood that the figures show only partial schematics, and the substrate may contain any number of additional materials and features having various properties and patterns as shown in the figures.

[0039] Method 300 may or may not involve an optional operation of forming a semiconductor structure as a particular manufacturing operation. It should be understood that method 300 can be performed on any number of semiconductor structures 500 or substrate 405, as shown in Figure 4A, including exemplary structures on which silicon oxide and silicon nitride etching operations can be performed. As shown in Figure 4A, substrate 405 may have a plurality of stacked layers covering the substrate, such stacked layers being silicon, silicon germanium, or other substrate materials. These layers may include IPD layers comprising a dielectric material 410, which may be silicon oxide, and alternating with a placeholder material 420, which may be, for example, silicon nitride or polysilicon. The placeholder material 420 may be or include a material that will be removed in subsequent operations to produce individual memory cells. Although the remainder of the disclosure will discuss silicon nitride and silicon oxide IPD layers, any other known material used in these two layers may replace one or more of these layers. Although only seven layers are shown, the exemplary structure may include any number of layers, including hundreds of layers, and it should be understood that the figures are merely schematic diagrams illustrating various aspects of the art. Furthermore, to allow the formation of one or more memory vias or trenches through the IPD layers, a masking material 425 may be formed on alternating layers of dielectric material 410 and placeholder material 420. The masking material 425, such as a resistive material, may be patterned to form one or more holes 430, thereby exposing a portion of the underlying alternating layers. Although only a single hole 430 is shown, it should be understood that the exemplary structure 400 may include any number of holes across the entire substrate 405. Some or all of these operations may be performed in a chamber or system tool as described above, or in different chambers on the same system tool, which may include a chamber for performing the operations of method 300.

[0040] Method 300 can be performed to etch or otherwise remove portions of dielectric material 410 and placeholder material 420, thereby forming memory vias or trenches in structure 400, as shown. This method can be performed to control the profile through the structure and improve etching characteristics, such as the uniformity of memory vias or trenches as etching proceeds into alternating layers. In operation 305, method 300 may include flowing a fluorinated precursor into a processing region of a substrate-holding semiconductor processing chamber. A plasma effluent of the fluorinated precursor may be formed in operation 315. In operation 310, the plasma effluent of the fluorinated precursor may contact substrate 405 and selectively etch exposed portions of placeholder material 420, such as material exposed through holes 430 in masking material 425. For example, the first material exposed through holes 430 may be placeholder material 420. The plasma effluent of the fluorine-containing precursor can selectively etch the site material 420 to expose the underlying dielectric material layer 410.

[0041] In an embodiment, method 300 may include: in operation 320, introducing a phosphorus- and fluorine-containing precursor into a processing region of a semiconductor processing chamber while maintaining the flow of the fluorine-containing precursor. The phosphorus- and fluorine-containing precursor and its plasma effluent may be formed in operation 325. The phosphorus- and fluorine-containing precursor and its plasma effluent may contact substrate 405 in operation 330, and may selectively etch exposed portions of dielectric material in operation 330. The phosphorus- and fluorine-containing precursor and its plasma effluent may selectively etch dielectric material 410 to expose the underlying placeholder material 420 layer. The phosphorus- and fluorine-containing precursor may increase the etching rate of oxide materials (such as dielectric material 410) while having a smaller effect on the etching rate of nitrides (such as placeholder material 420). Therefore, method 300 may switch the flow of the phosphorus- and fluorine-containing precursor to selectively etch oxide materials, such as dielectric material 410. As shown in Figure 4B, alternating etching of dielectric material 410 and placeholder material 420 can form memory vias or trenches 435 in the stacked layers. The memory vias or trenches 435 can be aligned with holes 430 in masking material 425. Furthermore, although only a single memory via or trench 435 is shown, it should be understood that the exemplary structure 400 can include any number of memory vias or trenches throughout the substrate 405.

[0042] As shown in Figures 4C to 4D, the operation of method 300 can be repeated in a second cycle, and can be repeated an arbitrary number of cycles. The number of cycles may depend on the desired depth of the memory via or trench 435, which may be based on the number of alternating layers of dielectric material 410 and placeholder material 420. In an embodiment, the depth of the memory via or trench 435 may extend through all stacked layers of dielectric material 410 and placeholder material 420, which may ultimately expose the substrate 405.

[0043] The fluorinated precursor flowing during operations 305 and 320 may include hydrogen fluoride (HF), nitrogen trifluoride (NF3), diatomic fluorine (F2), bromide trifluoride (BrF3), chlorine trifluoride (ClF3), sulfur hexafluoride (SF6), xenon difluoride (XeF2), or any other fluorinated precursor used or useful in semiconductor processing. In some embodiments, the fluorinated precursor may include hydrogen. In some embodiments, the fluorinated precursor may be carbon-free. For example, the fluorinated precursor may be HF. In embodiments, the fluorinated precursor may be free of polymerization gases and / or greenhouse gases. The fluorinated precursor may also flow with any number of additional precursors or carrier gases, including nitrogen, argon, helium, or any number of additional materials, but in some embodiments, the precursor may be limited to controlling side reactions or other states that may affect etching.

[0044] The phosphorus and fluorine-containing precursor flowing in operation 320 may include phosphorus trifluoride (PF3), phosphorus tetrafluoride (P2F4), or any other phosphorus and fluorine-containing precursor used or useful in semiconductor processing. In embodiments, the phosphorus and fluorine-containing precursor may be free of polymerization gases and / or greenhouse gases. Thus, in some embodiments, the phosphorus and fluorine-containing precursor may be carbon-free. The phosphorus and fluorine-containing precursor may also flow with any number of additional precursors or carrier gases, including nitrogen, argon, helium, or any number of additional materials, but in some embodiments, the precursor may be limited to controlling side reactions or other states that may affect etching.

[0045] In operations 305 and / or 320, the flow rate of the fluorinated precursor may be greater than or about 100 sccm, and may be greater than or about 125 sccm, greater than or about 150 sccm, greater than or about 175 sccm, greater than or about 200 sccm, greater than or about 225 sccm, greater than or about 250 sccm, greater than or about 260 sccm, greater than or about 270 sccm, greater than or about 280 sccm, greater than or about 290 sccm, greater than or about 300 sccm, or greater. At flow rates less than, for example, 100 sccm, reduced fluorine may occur, potentially leading to slower etching and reduced throughput. However, excessive fluorine can cause lateral etching, thereby affecting the uniformity of the etching. Therefore, the flow rate of the fluorinated precursor at operation 305 and / or operation 320 may be less than or about 500 sccm, and may be less than or about 450 sccm, less than or about 400 sccm, less than or about 350 sccm, less than or about 300 sccm, or even less. The flow rate of the fluorinated precursor may be constant between operation 305 and operation 320. However, it is also contemplated that the flow rate of the fluorinated precursor may be adjusted between operation 305 and operation 320.

[0046] In operation 320, the flow rate of the phosphorus and fluorine precursor may be less than or about 100 sccm, and may be less than or about 90 sccm, less than or about 80 sccm, less than or about 70 sccm, less than or about 60 sccm, less than or about 50 sccm, less than or about 40 sccm, less than or about 30 sccm, less than or about 20 sccm, less than or about 10 sccm, less than or about 9 sccm, less than or about 8 sccm, less than or about 7 sccm, less than or about 6 sccm, less than or about 5 sccm, less than or about 4 sccm, less than or about 3 sccm or less. At the increased flow rate, the etching rate of the dielectric material 410 increases due to the presence of phosphorus in the dielectric material 410, such as silicon oxide. However, excessive phosphorus may be detrimental to the etching rate.

[0047] The flow rate ratio of the fluorine-containing precursor to the phosphorus- and fluorine-containing precursors can be adjusted to control the amount of phosphorus present in the plasma effluent. When the flow rate ratio of the fluorine-containing precursor to the phosphorus- and fluorine-containing precursors decreases, the additional phosphorus interacts with the dielectric material 410 (such as silicon oxide), which increases the etching rate of the dielectric material 410. Phosphorus can enter the silicon and oxygen lattice and increase the etching rate of the dielectric material 410. When there is too much phosphorus in the plasma effluent, the etching rate may be too high, and the precise control of etching may be reduced. Therefore, the flow rate ratio of the fluorine-containing precursor to the phosphorus- and fluorine-containing precursors can be greater than or about 30:1, and can be greater than or about 35:1, greater than or about 40:1, greater than or about 45:1, greater than or about 50:1, greater than or about 55:1, greater than or about 60:1, greater than or about 65:1, greater than or about 70:1, greater than or about 75:1, greater than or about 80:1, greater than or about 85:1, greater than or about 90:1, or greater. However, when the flow rate ratio of the fluorine-containing precursor to the phosphorus- and fluorine-containing precursors is extremely high, the effect of phosphorus on the etching dielectric material 410 will decrease.

[0048] The source plasma power used to form fluorine-containing precursors and / or phosphorus- and fluorine-containing precursors and plasma effluents containing fluorine precursors can be relatively high. Relatively high plasma power allows for the formation of fluorine radicals. At lower plasma power, phosphorus- and fluorine-containing precursors and fluorine-containing precursors may suffer reduced dissociation, and the amount of etching per cycle may be reduced. Therefore, plasma effluents containing fluorine precursors and / or phosphorus and fluorine precursors can be formed at or above 500 W, and can be formed at power levels greater than or above 750 W, greater than or above 1000 W, greater than or above 1250 W, greater than or above 1500 W, greater than or above 1750 W, greater than or above 2000 W, greater than or above 2250 W, greater than or above 2500 W, greater than or above 2750 W, greater than or above 3000 W, greater than or above 3250 W, greater than or above 3500 W, greater than or above 3750 W, greater than or above 4000 W, or higher. However, extremely high plasma power may cause damage to structure 400. Therefore, the plasma effluents of fluorine-containing precursors and / or phosphorus- and fluorine-containing precursors can be formed at less than or about 6000 W, and can be formed at power greater than or about 5500 W, less than or about 5000 W, less than or about 4500 W, less than or about 4000 W, or less. The plasma power used to form the plasma effluent of the fluorine-containing precursor in operation 310 can be the same as or different from the plasma power used to form the plasma effluents of the fluorine-containing precursors and phosphorus- and fluorine-containing precursors in operation 325.

[0049] In an embodiment, the source plasma power may be pulsed while forming the plasma effluent containing the fluorine precursor, and simultaneously forming the plasma effluent containing both the fluorine and phosphorus and fluorine precursors, or both. The duty cycle of the source plasma power may be lower than or about 95%, and may be lower than or about 90%, or lower than or about 85%, to reduce the effective plasma power.

[0050] As previously described, contact with the plasma effluent of the fluorinated precursor in operation 315 can selectively etch the exposed portion of the site material 420. The contact at operation 315 can selectively etch the exposed portion of the site material 420 relative to the dielectric material 410 at a ratio greater than or about 5:1, such as greater than or about 7:1, greater than or about 8:1, greater than or about 9:1, greater than or about 10:1, or greater. In embodiments, the etching rate of the exposed site material 420 can be greater than or about 250 nm / min, and can be greater than or about 300 nm / min, greater than or about 350 nm / min, greater than or about 400 nm / min, greater than or about 450 nm / min, greater than or about 500 nm / min, greater than or about 550 nm / min, or greater.

[0051] Similarly, in operation 325, contact with the phosphorus- and fluorine-containing precursors and the plasma effluent of the fluorine-containing precursors can selectively etch the exposed portions of the dielectric material 410. The contact in operation 325 can selectively etch the exposed portions of the dielectric material 410 relative to the berth material 420 at a ratio greater than or about 5:1, such as greater than or about 7:1, greater than or about 8:1, greater than or about 9:1, greater than or about 10:1, or greater. In embodiments, the etching rate of the exposed berth material 420 can be greater than or about 350 nm / min, and can be greater than or about 400 nm / min, greater than or about 450 nm / min, greater than or about 500 nm / min, greater than or about 550 nm / min, greater than or about 600 nm / min, greater than or about 650 nm / min, greater than or about 700 nm / min, or greater.

[0052] When plasma effluent is formed in operations 310 and 325, and / or when the substrate is brought into contact with the plasma effluent in operations 315 and / or 330, bias power may be applied. The bias power may be provided via an RF power source (such as a bias power supply) or as a voltage via a base or substrate support. In an embodiment, the bias power may be provided at a frequency of 2 MHz. The bias power may increase the directionality of the plasma effluent from the inert precursor. The increased directionality may attract the plasma effluent to the substrate 405. Therefore, the plasma effluent may bombard and remove exposed portions of the stacked layers of dielectric material 410 and placer material 420. In embodiments, the applied bias power may be greater than or about 100 W, and may be formed at powers greater than or about 200 W, greater than or about 300 W, greater than or about 400 W, greater than or about 500 W, greater than or about 600 W, greater than or about 700 W, greater than or about 750 W, greater than or about 800 W, greater than or about 900 W, greater than or about 1000 W, or greater. However, at higher bias powers, bombardment may increase, and material on substrate 405 or in structure 400 may begin to sputter. Therefore, the applied bias power may be less than or about 5500 W, less than or about 5000 W, less than or about 4500 W, less than or about 4000 W, or less. In embodiments, the bias power may be pulsed or have discontinuous on-time. For example, the on-time of the bias power may be less than or about 75%, and may be less than or about 50%, less than or about 45%, less than or about 40%, less than or about 35%, less than or about 30%, less than or about 25%, less than or about 20%, or less.

[0053] Controlled directional etching of the stacked layer of dielectric material 410 and site material 420 can be performed by removing or etching a certain amount of nitride material (such as site material 420) followed by removing or etching a certain amount of oxide material (such as dielectric material 410). As shown in Figures 4C to 4D, to further facilitate directional etching, the technique can be performed in multiple cycles of providing a fluorine-containing precursor and providing phosphorus-containing and fluorine-containing precursors, thereby achieving efficient etching of the stacked layer of dielectric material 410 and site material 420. In some embodiments, method 300 may include repeating operations 305 to 330 at least twice, and may include repeating operations 305 to 335 at least three times, at least four times, at least five times, at least ten times, at least fifteen times, at least twenty times, or more. It is contemplated that operations 305 to 330 of method 300 may be repeated any number of times, depending on the depth of the memory via or trench 435 to be etched. Furthermore, although the foregoing description discusses Figures 4A to 4D, which illustrate the etching of the placeholder material 420 occurring first, it is conceivable that the method could first involve the etching of the dielectric material 410.

[0054] Process conditions can also affect the operations performed in method 300. In some embodiments, each operation of method 300 may be performed at a constant temperature, while in others, the temperature may be adjusted at different times. The temperature may be maintained within any range; however, at higher temperatures, the directionality of the plasma effluent decreases. As the directionality decreases, the contour control of the memory vias or trenches 435 being etched is affected. Furthermore, at lower temperatures, water (H2O), a byproduct of silicon oxide removal, may condense on the stack of dielectric material 410 and placer material 420, and act as an acceleration of etching. Therefore, in some embodiments, any or all operations of method 300 may be performed at a substrate operating temperature below or about 20°C, and may be performed at a substrate operating temperature below or about 10°C, below or about 0°C, below or about -10°C, below or about -20°C, below or about -30°C, below or about -40°C, below or about -50°C, below or about -60°C, below or about -70°C, below or about -80°C, or lower.

[0055] In some embodiments, each operation of method 300 may be performed during a constant pressure, while in others, the pressure may be adjusted during different operations. The pressure may be maintained within any range; however, at higher pressures, further dissociation of the fluorinated precursor may occur, potentially generating more fluorine radicals. As the amount of fluorine radicals increases, the directionality of the etching decreases, and the contour control of the memory vias or trenches 435 is affected. Therefore, in some embodiments, any or all operations of method 300 can be performed at a chamber operating pressure greater than or about 5 mTorr, and can be performed at chamber operating pressures greater than or about 10 mTorr, greater than or about 15 mTorr, greater than or about 20 mTorr, greater than or about 25 mTorr, greater than or about 30 mTorr, greater than or about 35 mTorr, greater than or about 40 mTorr, greater than or about 45 mTorr, greater than or about 50 mTorr, greater than or about 55 mTorr, greater than or about 60 mTorr, greater than or about 75 mTorr, greater than or about 100 mTorr, greater than or about 200 mTorr, greater than or about 300 mTorr, greater than or about 400 mTorr, or greater. Conversely, at lower pressures, the directionality of etching increases, as does the ion energy and the amount of etching per cycle. Therefore, any or all of the operations of method 300 can be performed at a chamber operating pressure of less than or about 500 mTorr, and can be performed at a chamber operating pressure of less than or about 400 mTorr, less than or about 300 mTorr, less than or about 200 mTorr, less than or about 100 mTorr, less than or about 90 mTorr, less than or about 80 mTorr, less than or about 70 mTorr, less than or about 65 mTorr, less than or about 60 mTorr, less than or about 55 mTorr, less than or about 50 mTorr, less than or about 45 mTorr, less than or about 40 mTorr, less than or about 35 mTorr, less than or about 30 mTorr, less than or about 25 mTorr, less than or about 20 mTorr, less than or about 15 mTorr, less than or about 10 mTorr, less than or about 5 mTorr or less.

[0056] In the preceding description, numerous details have been set forth for illustrative purposes in order to provide an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that certain embodiments may be practiced without some of these details or with additional details.

[0057] Several embodiments have been disclosed herein, and those skilled in the art will recognize that various modifications, alternative constructions, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, to avoid unnecessarily obscuring the present technology, many well-known processes and components have not been described. Therefore, the above description should not be considered as limiting the scope of the present technology. In addition, methods or processes may be described as sequential or step-by-step, but it should be understood that such operations may be performed simultaneously or in a different order than listed.

[0058] Where a numerical range is provided, it should be understood that, unless the context explicitly specifies otherwise, each intermediate value between the upper and lower limits of the range is the smallest fraction of the lower limit unit. Any specified or unspecified intermediate value within the specified range and any smaller range between any other specified or intermediate value within the specified range are included. The upper and lower limits of such smaller ranges may be independently included or excluded from the range, and each range in which any one or both limits are included, or in which neither limit is included, is also included in the technique, based on any specifically excluded limit value within the specified range. When a specified range includes one or two limits, ranges that do not include one or both of the included limits are also included.

[0059] As used herein and in the appended claims, the singular forms “a(a)”, “an”, and “the” include plural references unless the context clearly indicates otherwise. Thus, for example, a reference to “a precursor” includes a plurality of such precursors, and a reference to “the layer” includes a reference to one or more layers and equivalents known to those skilled in the art, etc.

[0060] Furthermore, the terms “comprise”, “comprising”, “contain”, “containing”, “include” and “including” used in this specification and the following claims are intended to describe the presence of the stated features, integers, components or operations, but do not exclude the presence or addition of one or more other features, integers, components, operations, actions or groups. [Simplified Explanation of the Diagram]

[0013] A further understanding of the nature and advantages of the disclosed technology can be achieved through the remaining parts of the specification and the accompanying drawings.

[0014] Figure 1 illustrates a top view of one embodiment of an exemplary processing system according to some embodiments of the present technology.

[0015] Figure 2 illustrates a cross-sectional schematic diagram of an exemplary processing chamber according to some embodiments of the present technology.

[0016] Figure 3 illustrates exemplary operations in a method according to some embodiments of the present technology.

[0017] Figures 4A to 4D illustrate cross-sectional views of a substrate being processed according to some embodiments of the present technology.

[0018] Some diagrams are included as illustrations. It should be understood that these diagrams are for illustrative purposes and should not be considered to be to scale unless specifically stated otherwise. Furthermore, as illustrations, these diagrams are provided to aid understanding and may not include all appearances or information compared to a true representation, and may include illustrative material for illustrative purposes.

[0019] In the accompanying drawings, similar parts and / or features may have the same element symbol. Furthermore, various parts of the same type may be distinguished by adding a letter after the element symbol to differentiate similar parts. If only the first element symbol is used in the specification, the description applies to any similar part having the same first element symbol, regardless of the letter following the symbol.

Claims

1. A semiconductor processing method, the method comprising the steps of: flowing a fluorine-containing precursor into a processing region of a semiconductor processing chamber, wherein the fluorine-containing precursor is carbon-free, wherein a substrate is positioned within the processing region, and wherein the substrate comprises alternating layers of silicon nitride and silicon oxide; forming a plasma effluent of the fluorine-containing precursor; contacting the substrate with the plasma effluent of the fluorine-containing precursor, wherein the contact selectively etches an exposed portion of silicon nitride; introducing a phosphorus- and fluorine-containing precursor into the processing region of the semiconductor processing chamber while maintaining a flow of the fluorine-containing precursor; forming the fluorine-containing precursor and the plasma effluent of the phosphorus- and fluorine-containing precursor; and contacting the substrate with the fluorine-containing precursor and the plasma effluent of the phosphorus- and fluorine-containing precursor, wherein the contact selectively etches an exposed portion of silicon oxide.

2. The semiconductor processing method as claimed in claim 1, wherein the fluorine-containing precursor comprises hydrogen fluoride (HF).

3. The semiconductor processing method as claimed in claim 1, wherein the phosphorus- and fluorine-containing precursor comprises phosphorus trifluoride (PF3).

4. The semiconductor processing method as claimed in claim 1, wherein a flow rate of the fluorine-containing precursor is greater than or equal to 100 sccm.

5. The semiconductor processing method as claimed in claim 1, wherein the flow rate of the phosphorus and fluorine-containing precursor is less than or equal to 50 sccm.

6. The semiconductor processing method of claim 1, wherein a pulsed plasma power is applied simultaneously with the formation of the plasma effluents of the fluorine-containing precursor and the plasma effluents of the fluorine-containing precursor and the phosphorus- and fluorine-containing precursor.

7. The semiconductor processing method of claim 1, further comprising the steps of: applying a bias power while contacting the stacked layers with the plasma effluent of the fluorine-containing precursor and the plasma effluent of the phosphorus- and fluorine-containing precursors.

8. The semiconductor processing method as described in claim 7, wherein the bias power is greater than or equal to 100 W.

9. The semiconductor processing method of claim 7, wherein the bias power is pulsed while the stacked layers are contacted with the plasma effluent of the fluorine-containing precursor and the plasma effluent of the phosphorus- and fluorine-containing precursors.

10. The semiconductor processing method as claimed in claim 1, wherein the method is performed at a chamber operating pressure of less than or equal to 500 mTorr.

11. The semiconductor processing method as claimed in claim 1, wherein the method is performed at a substrate operating temperature below or equal to 0°C.

12. A semiconductor processing method comprising the steps of: i) flowing a fluorine-containing precursor into a processing region of a semiconductor processing chamber, wherein a substrate is positioned within the processing region, wherein the substrate includes alternating layers of silicon nitride and silicon oxide, and wherein the substrate includes a patterning resist material covering the alternating layers of silicon nitride and silicon oxide; ii) forming a plasma effluent of the fluorine-containing precursor; iii) contacting the stacked layers with the plasma effluent of the fluorine-containing precursor, wherein the contact selectively etches an exposed layer of silicon nitride relative to silicon oxide at a ratio greater than or equal to 5:1; iv) flowing a phosphorus- and fluorine-containing precursor together with the fluorine-containing precursor into the processing region of the semiconductor processing chamber; v) forming the fluorine-containing precursor and the plasma effluent of the phosphorus- and fluorine-containing precursor; vi) Contact the stacked layers with the fluorine-containing precursor and the plasma effluent of the phosphorus- and fluorine-containing precursor, wherein the contact selectively etches an exposed layer of silicon oxide relative to silicon nitride at a ratio greater than or equal to 5:1; and vii) repeat operations i) to vi) at least for a second cycle.

13. The semiconductor processing method as claimed in claim 12, wherein the fluorine-containing precursor further comprises hydrogen.

14. The semiconductor processing method of claim 12, wherein an etching rate of the exposed silicon nitride layer is greater than or equal to 250 nanometers per minute.

15. The semiconductor processing method of claim 12, wherein an etching rate of the exposed silicon nitride layer is greater than or equal to 400 nanometers per minute.

16. The semiconductor processing method as described in claim 12, wherein operations i) to vi) are repeated for at least ten cycles.

17. The semiconductor processing method as claimed in claim 12, wherein the method is performed at a substrate operating temperature below or equal to -20°C.

18. A semiconductor processing method comprising the steps of: flowing a fluorine-containing precursor into a processing region of a semiconductor processing chamber, wherein a substrate is positioned within the processing region, and wherein the substrate comprises alternating layers of silicon nitride and silicon oxide; forming a plasma effluent of the fluorine-containing precursor; contacting the substrate with the plasma effluent of the fluorine-containing precursor, wherein the contact selectively etches an exposed portion of silicon nitride relative to silicon oxide at a ratio greater than or equal to 5:1; introducing a phosphorus- and fluorine-containing precursor into the processing region of the semiconductor processing chamber while maintaining a flow of the fluorine-containing precursor; forming the fluorine-containing precursor and the plasma effluent of the phosphorus- and fluorine-containing precursor; and contacting the substrate with the fluorine-containing precursor and the plasma effluent of the phosphorus- and fluorine-containing precursor, wherein the contact selectively etches an exposed portion of silicon oxide relative to silicon nitride at a ratio greater than or equal to 5:

1.

19. The semiconductor processing method of claim 18, wherein a flow rate ratio of the fluorine-containing precursor to the phosphorus- and fluorine-containing precursor is greater than or equal to 30:1.

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