Phased array system with distributed processing

Abstract

The phased array system comprises multiple subarray units. Each subarray unit includes a set of antennas and processing circuitry. The antennas couple an input signal incident on the phased array system into a set of electrical signals. The processing circuitry, coupled to the antennas, calculates N subarray responses corresponding to the N candidate directions based on the set of electrical signals and N pointing vectors associated with the N candidate directions. The processing circuitry of the first subarray unit further combines the subarray responses from the multiple subarray units for each candidate direction to generate N combined responses corresponding to the N candidate directions, and determines the azimuth information of the input signal based on the N combined responses.

Description

Phase array system with distributed processing This disclosure relates to antenna systems, and more particularly to a phase array system employing distributed processing. Phased array systems are advanced technologies used in various fields such as radar, communications, and remote sensing. By adjusting the relative phase of signals between multiple array elements, phased array systems electronically perform beam steering and shaping without mechanical movement, thus providing greater adaptability and accuracy in dynamic environments. For example, in radar applications, the absence of moving parts in phased array systems results in faster response times and higher system reliability. Furthermore, phased array systems can support simultaneous beamforming and signal processing, enabling multi-functional radar capabilities and further enhancing operational efficiency and adaptability. The embodiments disclosed herein provide a phase array system employing distributed processing. The disclosed embodiments provide a phase array system comprising a plurality of subarray units. Each subarray unit includes a set of antennas and a processing circuit. The set of antennas is used to couple an input signal incident on the phase array system into a set of electrical signals. The processing circuit is coupled to the set of antennas and is used to calculate N subarray responses corresponding to the N candidate directions based on the set of electrical signals and N pointing vectors associated with the N candidate directions. N is an integer greater than 1. The processing circuit of a first subarray unit among the plurality of subarray units is further used to combine the subarray responses from the plurality of subarray units for each candidate direction to generate N combined responses corresponding to the N candidate directions, and to determine the azimuth information of the input signal based on the N combined responses. Some embodiments disclosed herein include a phase array system comprising a plurality of subarray elements. Each subarray element includes a set of antennas and a processing circuit. The set of antennas is used to couple an input signal incident on the phase array system into a set of electrical signals. The processing circuit is coupled to the set of antennas and is used to calculate N subarray responses corresponding to the N candidate directions based on the set of electrical signals and N pointing vectors associated with the N candidate directions. N is an integer greater than 1. When a first subarray element among the plurality of subarray elements is configured as a first type element, the processing circuit of the first subarray element is further used to determine the azimuth information of the input signal based on the subarray responses from each of the plurality of subarray elements corresponding to the N candidate directions. When the first subarray element is configured as a second type element different from the first type element, the processing circuit of the first subarray element is further used to output a portion of the response including the corresponding subarray response for each candidate direction. Some embodiments disclosed herein include a phase array system comprising a plurality of subarray elements. Each subarray element includes a set of antennas and a processing circuit. The set of antennas is used to couple an input signal incident on the phase array system into a set of electrical signals. The processing circuit is coupled to the set of antennas and is used to calculate N subarray responses corresponding to the N candidate directions based on the set of electrical signals and N pointing vectors associated with the N candidate directions. N is an integer greater than 1. The plurality of subarray elements includes a first subarray element, a second subarray element, and a third subarray element. For each candidate direction, the processing circuit of the second subarray element is used to combine the subarray response generated by the second subarray element with the subarray response from the third subarray element to generate a partial response. The processing circuit of the first subarray element is used to combine the subarray response generated by the first subarray element with the partial response from the second subarray element for each candidate direction to determine the azimuth information of the input signal. The distributed architecture disclosed herein allows subarray units to have similar storage capacity requirements and achieve a balanced storage load without (or almost without) requiring the relocation of stored data to provide storage space. Furthermore, the distributed architecture allows subarray units to distribute metric calculations and maintain a balanced input / output flow load. The distributed architecture also effectively reduces the design cost of control nodes. Moreover, the storage complexity, computational complexity, and flow complexity of the phase array system using the distributed architecture disclosed herein are independent (or almost independent) of the total number of subarray units, thus providing good scalability. The phase array system disclosed herein also allows subarray units to be selectively configured as control units, effectively solving the single point of failure problem and providing a robust design. The following disclosure provides various implementations or examples that can be used to achieve different features of this disclosure. Specific examples of parameter values, components, and configurations described below are used to simplify this disclosure. It is understood that these descriptions are illustrative only and are not intended to limit the scope of this disclosure. For example, component symbols and / or reference numerals may be reused in embodiments. Such reuse is for the purpose of brevity and clarity and does not in itself represent a relationship between the different embodiments and / or configurations discussed. Furthermore, it is understood that if a component is described as "connected to" or "coupled to" another component, then the two components can be directly connected or coupled, or there may be other intervening components between them. Furthermore, for ease of description, spatial relative terms such as "below," "above," "left," "right," and similar terms may be used herein to describe the relationship between one element or component depicted in the diagram and another element or component(s). Spatial relative terms are intended to cover different orientations of the device in use or operation other than those shown in the diagram. The device may be oriented in other ways (rotated 90 degrees or based on other orientations), and the spatial relative descriptions used herein shall be interpreted accordingly. By estimating the direction of arrival (DOA) of an incident signal, a phased array system can achieve target tracking, navigation, and / or spatial awareness. The DOA estimation can utilize mathematical constructs (such as steering vectors) to evaluate the spatial characteristics of signals received by multiple antenna elements and determine their DOA. To improve beamforming performance and the accuracy of DOA estimation, phased array systems increasingly include a greater number of antennas. Please refer to Figure 1, which is a schematic diagram of a phased array system according to certain embodiments of this disclosure. The phased array system 100 can be used to estimate the input signal S. IN The direction of arrival, where the input signal S IN It can be (but is not limited to) electromagnetic waves (such as plane waves) emitted / reflected from a target. The phase array system 100 may include multiple subarray elements 102_1 to 102_M, where M is an integer greater than 1. Each subarray element may include multiple antennas to support the requirement for high-precision direction of arrival estimation. In this embodiment, subarray unit 102_i may include multiple antennas 104. 1,i Up to 104 P,i Analog-to-digital converter 106 1,i Up to 106 P,i And a digital processing unit 108_i, where P is an integer greater than 1, and i is an integer from 1 to M. Antenna 104 1,i Up to 104 P,i Used to input signal S IN Coupled to multiple electrical signals (such as radio frequency (RF) signals) SE 1,i to SE P,iAnalog-to-digital converter 106 1,i Up to 106 P,i Used to transmit the electrical signal SE 1,i to SE P,i Converted to digital signals SD 1,i To SD P,i The digital processing unit 108_i can process digital signals via SD card. 1,i To SD P,i Collected as data D i and data D i The data is transmitted to the digital processing unit 112. The digital processing unit 112 can process the data D output by each of the subarray units 102_1 to 102_M. 1 to D M The process involves searching for a metric that meets the judgment criteria, thereby estimating the input signal S. IN The direction of arrival. For example (but not limited to this disclosure), the digital processing unit 112 may use an open-loop search method to estimate the input signal S. IN The direction of arrival. In the case where each subarray element has 8 antennas (P equals 8), and the phase array system 100 contains 4 subarray elements (M equals 4), given a search direction (or angle) k, the digital processing unit 112 can calculate the metric f(k) based on the following: (1) where r i w represents the signal from the i-th antenna. i f(k) represents the pointing factor (or weighting factor) of the i-th antenna in the search direction k. Based on the metric value f(k) corresponding to different search directions k, the digital processing unit 112 can find the direction k corresponding to the maximum metric value. 0 Based on this, the input signal S is estimated. IN The direction of arrival. Direction k 0The following arg max function can be used to obtain it: (2) In other words, the phase array system 100 adopts a hierarchical architecture with a first level L1 and a second level L2 to estimate the direction of arrival. The subarray units 102_1 to 102_M located in the first level L1 are used for signal digitization and data transmission, while the digital processing unit 112 located in the second level L2 is used for metric calculation and decision-making. However, as the number of antennas increases, the hierarchical architecture shown in Figure 1 may encounter problems such as load imbalance, heavy traffic load, limited scalability, and serious single points of failure. For example, as the number of antennas in the first layer L1 increases, the second layer L2 not only bears a heavier input traffic load but also requires more storage space to accommodate the large amount of data from the first layer L1. The second layer L2 also needs to perform more complex calculations, resulting in a significant load imbalance between the first layer L1 and the second layer L2. Furthermore, since the amount of data transferred from the first layer L1 to the second layer L2 increases exponentially with the number of subarray units in the first layer L1, the time complexity of the second layer L2's load can be expressed as O(N), which reduces the scalability of the phase array system 100. Moreover, when the digital processing unit 112 of the second layer L2 fails, the entire phase array system 100 will malfunction. This disclosure provides an exemplary phase array system employing a distributed processing architecture to determine location information (such as direction of arrival), identify / track targets, and / or process incoming signals. For example, the exemplary phase array system can distribute metric calculations across multiple subarray units (or the processing circuitry of each subarray unit). Furthermore, the exemplary phase array system can preprocess the metric calculations of adjacent subarray units to simplify computational complexity. The phase array system employing a distributed processing architecture provided in this disclosure maintains balanced load distribution, good scalability, and / or stability. Further details are provided below. Figure 2 is a schematic diagram of an exemplary phase array system according to certain embodiments of the present disclosure. The phase array system 200 may include (but is not limited to) a plurality of subarray units 202_1 to 202_4, wherein each subarray unit can undertake a portion of the metric calculations to implement a distributed processing architecture. Subarray unit 202_j (j = 1, 2, 3, 4) includes (but is not limited to) a set of antennas 204_j and a processing circuit 210_j. This set of antennas 204_j is used to transmit the input signal S incident on the phase array system 200. IN(Such as electromagnetic signals) are coupled into a set of electrical signals SE_j (such as a set of radio frequency signals). For example, this set of antennas 204_j can utilize (but is not limited to) P antennas 204 1,j Up to 204 P,j To implement this, a set of electrical signals SE_j contains P electrical signals SE. 1,j to SE P,j , where P is an integer greater than 1. Please note that the number and / or arrangement of subarray cells shown in Figure 2 are for illustrative purposes and are not intended to limit the scope of this disclosure. Processing circuits 210_j (j = 1, 2, 3, 4) are coupled to a set of antennas 204_j to calculate the metric values ​​corresponding to N search directions (or N candidate directions). For each search direction, each processing circuit shares a portion of the metric value calculation for that search direction. The metric value calculation result for each search direction can indicate the correlation between the signal received by the antenna and that search direction, or represent the response of the signal received by the antenna in that search direction. The phase array system 200 can determine the input signal S based on the metric value calculation results corresponding to the N search directions. IN Location information. In this embodiment, the processing circuit 210_j is used to process a set of electrical signals SE_j and N pointing vectors V. j (1) to V j (N), calculate N candidate directions A 1 to A N The corresponding N subarray responses SR j (1) to SR j (N), where N is an integer greater than 1, pointing to vector V. j (1) to V j (N) correspond to N candidate directions A. 1 to A N For example, in the phase array system 200 used to calculate candidate direction A In the case of a corresponding search metric value, the processing circuit 210_1 can determine the corresponding pointing vector V. 1(1) to process the electrical signal SE 1,1 to SE P,1 This generates the subarray response SR 1(1), the processing circuit 210_2 can determine the direction vector V according to the corresponding direction vector V 2(1) to process the electrical signal SE 1,2 to SE P,2 This generates the subarray response SR 2(1); and so on. The phase array system 200 can be based on the subarray response SR generated by the processing circuits 210_1 to 210_4 respectively. 1(1) to SR 4(1) Combination or summation to calculate candidate direction A 1. Corresponding search metric. Processing circuit 210_j can convert a set of electrical signals SE_j into a corresponding set of digital signals SD_j, and perform digital processing on this set of digital signals SD_j to obtain the corresponding subarray response. For example (but not limited thereto), processing circuit 210_j may include analog-to-digital converter circuit 206_j and digital processing unit 208_j. Analog-to-digital converter circuit 206_j is coupled to a corresponding set of antennas 204_j and is used to convert a set of electrical signals SE_j into a set of digital signals SD_j (which includes digital signals SD_j). 1,1 To SD P,1 The analog-to-digital converter circuit 206_j may contain (but is not limited to) P analog-to-digital converters (ADCs) 206. 1,j Up to 206 P,j They are respectively coupled to antenna 204 1,j Up to 204 P,j Furthermore, the digital processing unit 208_j is coupled to the analog-to-digital converter circuit 206_j for processing based on N pointing vectors V. j (1) to V j (N) is used to process a set of digital signals SD_j, and then to calculate the responses SR of N subarrays. j (1) to SR j (N). For illustrative purposes, the distributed processing architecture provided in this disclosure is described below based on a non-feedback search method used to calculate the metric of the direction of arrival. Those skilled in the art will understand that the distributed processing architecture provided in this disclosure can be applied to other methods of estimating the direction of arrival, determining azimuth information, and / or other signal processing of signals received by the antenna without departing from the scope of this disclosure. First, given a search direction k (e.g., candidate direction A) 1 to A N In the case of (one of the cases), the corresponding metric f(k) can be represented by the inner product of the signal vector SG (representing the signal received by the antenna) and the pointing vector V(k): (3) Where, r 1,1 to r P,1 Antennas 204, which can represent subarray element 202_1 respectively, 1,1 Up to 204 P,1 Received signals (such as digital signals SD) 1 ,1 To SD P,1 Or signal SE 1,1 to SE P,1 ), r 1,2 to r P,2 These can represent antenna 204 respectively. 1,2 Up to 204 P,2 The received signals, and so on. Furthermore, w 1,1 (k) to w P,1 (k) can be represented by the pointing vector V(k) related to the search direction k; Antenna 204 1,1 Up to 204 P,1 Each corresponding weighting factor (or pointing factor), w 1,2 (k) to w P,2 (k) can represent the antenna 204 in the pointing vector V(k) related to the search direction k. 1,2 Up to 204 P,2 Each has its corresponding weighting factor (or pointing factor); and so on. In other words, the metric f(k) corresponding to the search direction k can be represented by the square of the sum of the products of the signal received by each antenna and the corresponding weighting factor. The metric f(k) can be represented by the sum of the responses of subarray elements 202_1, 202_2, 202_3, and 202_4: (4) Among them, This can represent the sum of the products of the signal corresponding to subarray unit 202_1 and the weighting factor. This can represent the sum of the products of the signal corresponding to subarray cell 202_2 and the weighting factor. This can represent the sum of the signal corresponding to subarray element 202_3 and the weighting factor, and This represents the sum of the signal corresponding to subarray cell 202_4 and the weighting factor. Each summation term represents the contribution of the corresponding subarray cell to the metric f(k). The calculation of the metric f(k) can be shared by processing circuits 210_1 to 210_4 (or digital processing units 208_1 to 208_4). For example, processing circuit 210_j (or digital processing unit 208_j) (j = 1, 2, 3, 4) can calculate the signal vector SG. j (Represents the signal received by the antenna, such as a set of electrical signals SE_j or a set of digital signals SD_j) and the pointing vector V j The inner product of (k) and (corresponding to the search direction k) determines the subarray response g corresponding to the search direction k. j (k). Subarray response g j (k) can be the subarray response SR j (1) to SR j (N) is one of them, and can be represented as follows: (5) Furthermore, one of the processing circuits 210_1 to 210_4 (or one of the digital processing units 208_1 to 208_4) can respond the subarray to g. 1(k) to g 4(k) are combined (e.g., summed) to produce a combined response G(k), which in turn yields a metric f(k). The combined response G(k) can represent N candidate directions A. 1 to A N The corresponding N merged responses CR 1 to CR N One of them: (6) Based on the metric values ​​f(k) corresponding to different search directions k, the phase array system 200 can find the search direction k corresponding to the maximum metric value. 0 Then, the input signal S is estimated. IN The direction of arrival. For example, one of the processing circuits 210_1 to 210_4 can be used to calculate N combined responses CR. 1 to CR N The square values ​​of each individual response are then used to determine the candidate direction (search direction k) corresponding to the merged response with the largest square value. 0 The signal is determined to be input signal S. IN The direction of arrival. Alternatively, the candidate direction corresponding to the merged response with the largest square value can be determined as the direction closest to the direction of arrival. By distributing the metric calculation of the same candidate direction to subarray cells 202_1 to 202_4, the phase array system 200 can significantly reduce the occurrence of computational load imbalance. Furthermore, the phase array system 200 can employ a distributed data link architecture, distributing the data links used to transmit subarray responses among adjacent subarray elements. Compared to an architecture where all data links used to transmit subarray responses converge to a single subarray element used for estimating the direction of arrival, the phase array system 200 achieves good input / output traffic load balancing. For example, one of the subarray units 202_1 to 202_4 can be configured as a first type of unit, while the other subarray units can be configured as a second type of unit, different from the first type of unit. The processing circuit (or digital processing unit) of the first type of unit can be configured according to the relationship between each of the subarray units 202_1 to 202_4 and the candidate direction A. 1 to A N The corresponding subarray response determines the input signal S. INThe location information (such as direction of arrival) is provided. For each candidate direction, the processing circuitry (or digital processing unit) of the second type of unit can output a partial response containing one of the subarray responses corresponding to that candidate direction. This partial response can be the subarray response itself, or a combination or merging of multiple subarray responses. This partial response can be output to adjacent subarray units configured as first type units, or to adjacent subarray units configured as second type units, thereby realizing a distributed data link architecture. For ease of explanation, a subarray unit configured as a first type of unit can be referred to as a control unit or decision unit, and its contained digital processing units can be referred to as control nodes or decision nodes; a subarray unit configured as a second type of unit can be referred to as a processing unit, and its contained digital processing units can be referred to as processing nodes. However, these names are not intended to limit the scope of this disclosure. For each candidate direction, the processing circuitry (or control node) of the control unit can combine its own generated subarray response with a partial response output by the processing circuitry (or processing node) of the processing unit to generate a corresponding combined response. Alternatively, for each candidate direction, the processing circuitry (or processing node) of the processing unit can combine its own generated subarray response with a subarray response (or partial response) from the processing circuitry (or processing node) of another processing unit to generate a corresponding partial response. In the embodiment shown in Figure 2, subarray unit 202_4 can be configured as a control unit (i.e., digital processing unit 208_4 can be configured as a control node), while subarray units 202_1 to 202_3 can all be configured as second-type units (i.e., digital processing units 208_1 to 208_3 can all be configured as processing nodes). The following description, based on certain implementations of the operation flow of the phase array system 200, further illustrates the distributed processing architecture provided in this disclosure. During operation, the processing circuit 210_4 (or the digital processing unit 208_4) can generate a search command (indicating the direction to be searched) and assign the search command to the subarray unit configured as a processing unit. For example, the processing circuit 210_4 can send a command SC (which can indicate the search direction k, such as N candidate directions A). 1 to A N (One) The instruction SC is given to processing circuits 210_1 to 210_3 to notify them that the desired search direction is search direction k. Processing circuits 210_1 to 210_3 (or digital processing units 208_1 to 208_3) can determine the corresponding pointing vector according to the instruction SC, such as the pointing vector V corresponding to search direction k. 1(k) / V 2(k) / V 3(k). In this embodiment, processing circuit 210_2 can forward the instruction SC from processing circuit 210_4 to processing circuit 210_1; processing circuit 210_1 can determine the pointing vector V according to the instruction SC forwarded by processing circuit 210_2. 1(k). Furthermore, the processing circuit 210_4 can determine the pointing vector V based on the instruction SC it generates. 4(k). For the search direction k, each processing circuit can process the signal received by the corresponding set of antennas according to the corresponding pointing vector, and calculate the subarray response accordingly. In this embodiment, the digital processing unit 208_1 can process the signal received by the corresponding set of antennas according to the pointing vector V. 1(k) and a set of digital signals SD_1 are used to calculate the subarray response g. 1(k), and the subarray response g 1(k) as a partial response PR 1(k) is provided to the digital processing unit 208_2 (or processing circuit 210_2). The digital processing unit 208_2 can then process the data according to the pointing vector V. 2(k) and a set of digital signals SD_2 are used to calculate the subarray response g. 2(k), and the subarray response g 2(k) and partial response PR Adding 1(k) produces a partial response PR 2(k). The digital processing unit 208_3 can determine the direction of the vector V. 3(k) and a set of digital signals SD_3 are used to calculate the subarray response g. 3(k), and the subarray response g 3(k) as a partial response PR 3(k) is provided to the digital processing unit 208_4 (or processing circuit 210_4). The digital processing unit 208_4 can then process the data according to the pointing vector V. 4(k) and a set of digital signals SD_4 are used to calculate the subarray response g. 4(k). Furthermore, the digital processing unit 208_4 can process the subarray response g 4(k), Partial Response PR 2(k) and partial response PR The sum of 3(k) produces a combined response G(k), which in turn yields the metric f(k). In this embodiment, a processing node can receive one or more partial responses output by one or more other processing nodes via one or more data links, wherein each data link is used to connect adjacent processing nodes; a processing node can combine its own generated subarray response with the received one or more partial responses to generate a partial response for that processing node. That is, the data links used to transmit the subarray response can be distributed among adjacent processing nodes. For example, digital processing unit 208_2 can receive the partial response PR output by digital processing unit 208_1 via a data link. 1(k), and the subarray response g 2(k) and partial response PR 1(k) merging, thus producing a partial response PR 2(k). Please note that at least one of the subarray units 202_1 to 202_4 may be selectively configured as a first type unit or a second type unit. For example, in some embodiments, subarray unit 202_1 may be configured as a control unit (i.e., digital processing unit 208_1 may be configured as a control node), while subarray units 202_2 to 202_4 may all be configured as second type units (i.e., digital processing units 208_2 to 208_4 may all be configured as processing nodes). As another example, subarray units 202_1 to 202_4 may have the same or similar structures. Furthermore, the control node can receive one or more partial responses output by one or more processing nodes, thereby obtaining the subarray response from each processing node; the control node can obtain a combined result of all subarray responses by merging its own generated subarray response with one or more partial responses from one or more processing nodes. As the system size increases (e.g., as the number of subarray elements in the phase array system increases), the data flow to the control node remains approximately constant, and the computational complexity of the control node also remains approximately constant. Figure 3 is a schematic diagram of a phase array system according to certain embodiments of the present disclosure. The phase array system 300 may include (but is not limited to) a plurality of subarray units 302_1 to 302_9, wherein each subarray unit may have a structure substantially the same as / similar to the subarray unit shown in Figure 2. For example, subarray unit 302_j (j = 1, 2, ..., 9) may include a set of antennas 304_j (containing P antennas) and a processing circuit 310_j; the processing circuit 310_j may include an analog-to-digital converter circuit 306_j (containing P analog-to-digital converters (ADCs)) and a digital processing unit 308_j. In the embodiment shown in Figure 3, subarray unit 302_5 can be configured as a control unit (i.e., digital processing unit 308_5 can be configured as a control node), while subarray units 302_1 to 302_4 and 302_6 to 302_9 can be configured as processing units (i.e., digital processing units 308_1 to 308_4 and 308_6 to 308_9 can be configured as processing nodes). Processing circuit 310_5 (or digital processing unit 308_5) can determine the input signal S based on the subarray responses of subarray units 302_1 to 302_9 corresponding to each candidate direction. IN Location information (such as direction of arrival). During operation, for a search direction k (e.g., one of multiple candidate directions), processing circuit 310_5 (or digital processing unit 308_5) can send an instruction SC (indicating the search direction k) to the processing circuits (or processing nodes) of each processing unit. Each processing circuit (or processing node) can determine the corresponding pointing vector based on the instruction SC. In this embodiment, processing circuit 310_2 can forward the instruction SC from processing circuit 310_5 to processing circuits 310_1 and 310_3; processing circuit 310_8 can forward the instruction SC from processing circuit 310_5 to processing circuits 310_7 and 310_9. For each candidate direction, the processing circuitry (or control node) of the control unit can combine the subarray responses from subarray units 302_1 to 302_9 to generate a corresponding combined response, and can determine the input signal S based on the combined responses corresponding to each of the multiple candidate directions. IN The location information (such as direction of arrival). In this embodiment, for the search direction k (e.g., one of multiple candidate directions), the digital processing units 308_1, 308_3, 308_4, 308_6, 308_7 and 308_9 can each generate their own subarray response (i.e., subarray response g). 1(k), g 3(k), g 4(k), g 6(k), g 7(k) and g One of the 9(k) outputs a partial response (i.e., the partial response PR). 1(k), PR 3(k), PR 4(k), PR 6(k), PR 7(k) and PR (One of 9(k)). Furthermore, the digital processing unit 308_2 can process the subarray response g it generates. 2(k) and partial responses PR from adjacent digital processing units 308_1 and 308_3 1(k) and PR 3(k) merging to produce a partial response PR 2(k) (i.e., the subarray response g) 1(k), g 2(k) and g (summation of 3(k)); the digital processing unit 308_8 can generate its own subarray response g 8(k) and partial responses PR from adjacent digital processing units 308_7 and 308_9 7(k) and PR 9(k) merging to produce a partial response PR 8(k) (i.e., the subarray response g) 7(k), g 8(k) and g (Sum of 9(k)); the digital processing unit 308_5 can handle the subarray response g 5(k), Partial Response PR 2(k), Partial Response PR 4(k), Partial Response PR 6(k) and partial response PR 8(k) are merged to produce a merged response, thereby obtaining a metric corresponding to the search direction k. Please note that as the system scales up from the phase array system 200 shown in Figure 2 (e.g., a 2x2 subarray configuration) and the phase array system 300 shown in Figure 3 (e.g., a 3x3 subarray configuration) to phase array systems containing even more subarray units, the maximum data storage requirement, computational load, and input / output throughput of each subarray unit remain approximately constant. For example (but not limited to this disclosure), the maximum data storage requirement, computational load, and input / output throughput of each subarray unit can be maintained at the maximum data storage requirement, computational load, and input / output throughput corresponding to up to four data links. In other words, as the number of subarray units increases, the amount of stored data, computational complexity, and input / output throughput of the phase array system provided by this disclosure remain constant, and the storage complexity, computational complexity, and throughput complexity of the phase array system provided by this disclosure can be expressed as O(1). Therefore, the phase array system provided by this disclosure has good system scalability. In some embodiments, the subarray units provided in this disclosure can be selectively configured as control units or processing units (that is, the digital processing units in the subarray units can be selectively configured as control nodes or processing nodes), thereby realizing a robust phase array system. For example, as shown in FIG4, when a subarray unit 302_5 configured as a control unit malfunctions or fails, the subarray unit 302_5 (or digital processing unit 308_5) can be disabled, or the data link connected to the subarray unit 302_5 (or digital processing unit 308_5) can be disabled, so that the subarray unit 302_5 does not participate in the operation of the phase array system 300. In addition, the subarray unit 302_6 can be reconfigured as a control unit (i.e., the digital processing unit 308_6 can be reconfigured as a control node) to maintain the normal operation of the phase array system 300. In the embodiment shown in Figure 4, the digital processing unit 308_6 can send a command SC (indicating a search direction k, such as one of a plurality of candidate directions) to subarray units 302_1 to 302_4 and 302_7 to 302_9. The respective subarray responses of subarray units 302_1 to 302_4 and 302_7 to 302_9 can be transmitted to subarray unit 302_6 via one or more corresponding data links. That is, the data transmission path of the phase array system 300 can be reconfigured. By selectively configuring subarray units as control units (or selectively configuring digital processing units as control nodes), the phase array system disclosed herein can handle single-point-of-failure problems, thereby providing a robust design. Since those skilled in the art should understand the operational details of the phase array system 300 shown in Figures 3 and 4 after reading the above descriptions of Figures 1 and 2, similar descriptions will not be repeated here. In some embodiments, the subarray units provided in this disclosure can be selectively configured as control units or processing units (i.e., the digital processing units in the subarray units can be selectively configured as control nodes or processing nodes), thereby realizing a phase array system with load balancing. For example, please refer to FIG5, which is a schematic diagram of one embodiment of the phase array system 200 shown in FIG2 for performing different batch search tasks batch1, batch2, batch3, and batch4. In the embodiment shown in FIG5, the batch search tasks batch1, batch2, batch3, and batch4 may correspond to different distances or different Doppler frequencies. During the execution of each batch search task by the phase array system 200, subarray unit 202_4 is configured as a control unit (i.e., digital processing unit 208_4 is configured as a control node), while subarray units 202_1 to 202_3 are all configured as processing units (i.e., digital processing units 208_1 to 208_3 are all configured as control nodes). For each batch search task, the computation and data transfer load of digital processing units 208_1, 208_2, 208_3 and 208_4 can be represented as 1, 1, 1 and 2 respectively. Therefore, the total load of digital processing units 208_1, 208_2, 208_3 and 208_4 for executing batch search tasks batch1 to batch4 can be represented as 4, 4, 4 and 8 respectively. Please refer to Figure 6, which is a schematic diagram of another implementation of the phase array system 200 shown in Figure 2 performing different batch search tasks batch1, batch2, batch3, and batch4. In the embodiment shown in Figure 6, when the phase array system 200 is used to perform batch search task batch1, subarray unit 202_1 is configured as a control unit, while the other subarray units are configured as processing units. The computational and data transfer loads of digital processing units 208_1, 208_2, 208_3, and 208_4 can be represented as 2, 1, 1, and 1, respectively. When the phase array system 200 is used to perform batch search task batch2, subarray unit 202_3 is configured as a control unit, while the other subarray units are configured as processing units. The computational and data transfer loads of digital processing units 208_1, 208_2, 208_3, and 208_4 can be represented as 1, respectively. 1, 2, and 1; When the phase array system 200 is used to execute batch search task batch3, subarray unit 202_4 is configured as a control unit, while the other subarray units are configured as processing units. The computational and data transfer loads of digital processing units 208_1, 208_2, 208_3, and 208_4 can be represented as 1, 1, 1, and 2, respectively. When the phase array system 200 is used to execute batch search task batch4, subarray unit 202_2 is configured as a control unit, while the other subarray units are configured as processing units. The computational and data transfer loads of digital processing units 208_1, 208_2, 208_3, and 208_4 can be represented as 1, 2, 1, and 1, respectively. Therefore, the total load of digital processing units 208_1, 208_2, 208_3, and 208_4 executing batch search tasks batch1 to batch4 can be represented as 5, 5, 5, and 5, respectively. In other words, the workload of computation and data transmission can be evenly distributed among the digital processing units 208_1, 208_2, 208_3, and 208_4. Compared to the system configuration shown in Figure 5, the dynamic configuration shown in Figure 6 can achieve load balancing. Since those skilled in the art should be able to understand the operational details of the phase array system 200 shown in Figures 5 and 6 after reading the above descriptions of Figures 1 to 4, similar descriptions will not be repeated here. The distributed architecture disclosed herein allows subarray units to have similar storage capacity requirements and achieve a balanced storage load without (or almost without) requiring the relocation of stored data to provide storage space. Furthermore, the distributed architecture allows subarray units to distribute metric calculations and maintain a balanced input / output flow load. The distributed architecture also effectively reduces the design cost of control nodes. Moreover, the storage complexity, computational complexity, and flow complexity of the phase array system using the distributed architecture disclosed herein are independent (or almost independent) of the total number of subarray units, thus providing good scalability. The phase array system disclosed herein also allows subarray units to be selectively configured as control units, effectively solving the single point of failure problem and providing a robust design. The term "approximately" as used in this disclosure is used to describe and indicate minor variations. When these terms are used in conjunction with an event or situation, they can cover examples of an event or situation occurring precisely or very close to occurring. For example, when the term "approximately" is used with a given value or range, it generally means ±10%, ±5%, ±1%, or ±0.5% of that given value or range. In this disclosure, a numerical range is expressed as a range from one endpoint to another or between two endpoints. Unless otherwise stated, numerical ranges described in this disclosure may include endpoints. Furthermore, when multiple values ​​or characteristics are mentioned as "approximately" the same, it can cover situations where these values ​​are all within ±10%, ±5%, ±1%, or ±0.5% of the average of these values. The foregoing description briefly outlines the features of certain embodiments of this disclosure, enabling those skilled in the art to gain a more comprehensive understanding of the various forms of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis to design or modify other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should understand that these equivalent embodiments remain within the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure. 100, 200, 300: Phase array system 102_1~102_M, 202_1~202_4, 302_1~302_9: Subarray unit 104 1,1 ~104 P,1 , 104 1,2 ~104 P,2 , 104 1,M ~104 P,M Antenna 106 1,1 ~106 P,1 , 106 1,2 ~106 P,2 , 106 1,M ~106 P,M Analog-to-digital converters 108_1~108_M, 112, 208_1~208_4, 308_1~308_9; Digital processing units 204_1~204_4, 304_1~304_9; A set of antennas 204 1,1 ~204 P,1 , 204 1,2 ~204 P,2 , 204 1,3 ~204 P,3 , 204 1,4 ~204 P,4 Antennas 206_1~206_4, 306_1~306_9; Analog-to-digital converter circuit 206 1,1 ~206 P,1 , 206 1,2 ~206 P,2 Analog-to-digital converter 206 1,3 ~206 P,3 , 206 1,4 ~206 P,4 Analog-to-digital converters 210_1~210_4, 310_1~310_9; Processing circuits batch1~batch4; Batch search task CR 1~CR N G(k): Combined response D 1~D M Document L1: First Level L2: Second Level PR 1(k)~PR 4(k), PR 6(k)~PR 9(k): Partial response SC: Instructions SD_1~SD_4: A group of digital signals SD 1,1 ~SD P,1 SD 1,2 ~SD P,2 Digital signal SD 1,3 ~SD P,3 SD 1,4 ~SD P,4 SD 1,M ~SD P,M Digital signals SE_1~SE_4: A group of electrical signals SE 1,1 ~SE P,1 SE 1,2 ~SE P,2 :Signal SE 1,3 ~SE P,3 SE 1,4 ~SE P,4 SE 1,M ~SE P,M :Signal S IN Input signal SR 1(1)~SR 1(N), SR 2(1)~SR 2(N): Subarray response SR 3(1)~SR 3(N), SR 4(1)~SR 4(N), g 1(k)~g 9(k): Subarray response V 1(1)~V 1(N), V 2(1)~V 2(N), V 3(1)~V 3(N), V 4(1)~V 4(N): Pointer vector The various embodiments disclosed herein can be clearly understood by reading the accompanying drawings. It should be noted that, according to standard practice in the art, the various features in the drawings are not necessarily drawn to scale. In fact, the dimensions of certain features may be arbitrarily enlarged or reduced for clear description. Figure 1 is a schematic diagram of a phase array system according to some embodiments of this disclosure. Figure 2 is a schematic diagram of an exemplary phase array system according to some embodiments of this disclosure. Figure 3 is a schematic diagram of an exemplary phase array system according to some embodiments of this disclosure. Figure 4 is a schematic diagram of an exemplary phase array system according to some embodiments of this disclosure. Figure 5 is a schematic diagram of an embodiment of the phase array system shown in Figure 2 according to some embodiments of this disclosure for performing different batch search tasks. Figure 6 is a schematic diagram of another embodiment of the phase array system shown in Figure 2 according to some embodiments of this disclosure for performing different batch search tasks. 200: Phase Array System 202_1~202_4: Subarray Units 204_1~204_4: A set of antennas 204 1,1 ~204 P,1 204 1,2 ~204 P,2 204 1,3 ~204 P,3 204 1,4 ~204 P,4 :antenna 206_1~206_4: Analog to Digital Conversion Circuits 206 1,1 ~206 P,1 206 1,2 ~206 P,2 Analog-to-digital converter 206 1,3 ~206 P,3 206 1,4 ~206 P,4 Analog-to-digital converter 208_1~208_4: Digital processing unit 210_1~210_4: Processing Circuit CR 1~CR N G(k): Combined Response PR 1(k)~PR 3(k): Partial Response SC: Command SD_1~SD_4: A group of digital signals SD 1,1 ~SD P,1 SD 1,2 ~SD P,2 SD 1,3 ~SD P,3 SD 1,4 ~SD P,4 Digital signal SE_1~SE_4: A group of electrical signals SE 1,1 ~SE P,1 SE 1,2 ~SE P,2 SE 1,3 ~SE P,3 SE 1,4 ~SE P,4 Telephone signal S IN Input signal SR 1(1)~SR 1(N),SR 2(1)~SR 2(N): Subarray response SR 3(1)~SR 3(N),SR 4(1)~SR 4(N),g 1(k)~g 3(k): Subarray response V 1(1)~V 1(N),V 2(1)~V 2(N),V 3(1)~V 3(N),V 4(1)~V 4(N): Pointer vector

Claims

1. A phase array system, comprising: a plurality of subarray units, wherein each subarray unit comprises: a set of antennas for coupling an input signal incident on the phase array system into a set of electrical signals; and a processing circuit coupled to the set of antennas for calculating N subarray responses corresponding to the N candidate directions based on the set of electrical signals and N pointing vectors associated with the N candidate directions, where N is an integer greater than 1; wherein the processing circuit of a first subarray unit among the plurality of subarray units is further configured to, for each candidate direction, combine the subarray responses from the plurality of subarray units to generate N combined responses corresponding to the N candidate directions, and determine azimuth information of the input signal based on the N combined responses. The plurality of subarray units further includes a second subarray unit; for each candidate direction, the processing circuit of the second subarray unit is used to output a partial response, the partial response including the subarray response generated by the processing circuit of the second subarray unit; the processing circuit of the first subarray unit is used to merge the subarray response generated by the processing circuit of the first subarray unit with the partial response output by the second subarray unit to generate a merged response, wherein the plurality of subarray units further includes a third subarray unit; for each candidate direction, the processing circuit of the second subarray unit is used to merge the subarray response generated by the processing circuit of the second subarray unit with the subarray response from the third subarray unit to generate the partial response.

2. The phase array system as described in claim 1, wherein the orientation information includes the direction of arrival of the input signal; the processing circuit of the first subarray unit is used to calculate the square value of each of the N combined responses, and to determine the candidate direction corresponding to the combined response with the largest square value as the direction of arrival of the input signal.

3. The phase array system as described in claim 1, wherein the processing circuitry of each subarray unit is used to calculate the inner product of the pointing vector corresponding to each candidate direction and the signal vector representing the group of electrical signals to determine the corresponding subarray response.

4. The phase array system as claimed in claim 1, wherein the processing circuitry for each subarray comprises: an analog-to-digital converter circuit coupled to the group of antennas for converting the group of electrical signals into a group of digital signals; and a digital processing unit coupled to the analog-to-digital converter circuit for processing the group of digital signals according to the N pointing vectors to calculate the responses of the N subarrays.

5. A phase array system, comprising: a plurality of subarray units, wherein each subarray unit comprises: a set of antennas for coupling an input signal incident on the phase array system into a set of electrical signals; and a processing circuit coupled to the set of antennas for calculating N subarray responses corresponding to the N candidate directions based on the set of electrical signals and N pointing vectors associated with the N candidate directions, where N is an integer greater than 1; wherein the processing circuit of a first subarray unit among the plurality of subarray units is further configured to, for each candidate direction, combine the subarray responses from the plurality of subarray units to generate N combined responses corresponding to the N candidate directions, and determine azimuth information of the input signal based on the N combined responses; wherein the plurality of subarray units further comprises a second subarray unit; the processing circuit of the first subarray unit is further configured to send a command to the processing circuit of the second subarray unit, the command indicating one of the N candidate directions; the processing circuit of the second subarray unit is configured to determine the corresponding pointing vector based on the command.

6. The phase array system as claimed in claim 5, wherein the plurality of subarray units further includes a third subarray unit; the processing circuit of the second subarray unit is used to forward the instruction to the processing circuit of the third subarray unit; the processing circuit of the third subarray unit is used to determine the corresponding pointing vector according to the instruction.

7. A phase array system comprising: a plurality of subarray units, wherein each subarray unit comprises: a set of antennas for coupling an input signal incident on the phase array system into a set of electrical signals; and a processing circuit coupled to the set of antennas for calculating N subarray responses corresponding to the N candidate directions based on the set of electrical signals and N pointing vectors associated with the N candidate directions, where N is an integer greater than 1; wherein when a first subarray unit among the plurality of subarray units is configured as a first type of unit, the processing circuit of the first subarray unit is further configured to determine azimuth information of the input signal based on the subarray responses of the plurality of subarray units corresponding to the N candidate directions; when the first subarray unit is configured as a second type of unit different from the first type of unit, the processing circuit of the first subarray unit is further configured to output a portion of the response including the corresponding subarray response for each candidate direction.

8. The phase array system as claimed in claim 7, wherein for each candidate direction, the processing circuitry of the first subarray unit is configured to combine subarray responses from multiple subarray units to generate a combined response, and to determine the azimuth information based on the N combined responses corresponding to the N candidate directions.

9. The phase array system as claimed in claim 8, wherein the plurality of subarray units further includes a second subarray unit configured as a second type of unit; for each candidate direction, the processing circuit of the second subarray unit is configured to output a portion of the response, the portion of the response including the subarray response generated by the processing circuit of the second subarray unit; the processing circuit of the first subarray unit is configured to combine the subarray response generated by the processing circuit of the first subarray unit with the portion of the response output by the second subarray unit to generate a combined response.

10. The phase array system as claimed in claim 7, wherein the plurality of subarray units further includes a second subarray unit configured as a second type of unit; for each candidate direction, the processing circuitry of the first subarray unit is used to combine the subarray response generated by the processing circuitry of the second subarray unit with the subarray response from the second subarray unit to generate the partial response.

11. The phase array system as claimed in claim 7, wherein the plurality of subarray units further includes a second subarray unit configured as a first type of unit; for each candidate direction, the partial response output by the processing circuitry of the first subarray unit is passed to the processing circuitry of the second subarray unit.

12. The phase array system as claimed in claim 7, wherein the plurality of subarray units further includes a second subarray unit configured as a second type of unit; the processing circuit of the first subarray unit is further configured to send an instruction to the processing circuit of the second subarray unit, the instruction indicating one of the N candidate directions; the processing circuit of the second subarray unit is configured to determine a corresponding pointing vector according to the instruction.

13. The phase array system as claimed in claim 7, wherein the plurality of subarray units further includes a second subarray unit configured as a first type of unit; the processing circuit of the second subarray unit is further configured to send an instruction to the processing circuit of the first subarray unit, the instruction indicating one of the N candidate directions; the processing circuit of the first subarray unit is configured to determine a corresponding pointing vector according to the instruction.

14. The phase array system as claimed in claim 13, wherein the plurality of subarray units further includes a third subarray unit configured as a second type of unit; the processing circuit of the first subarray unit is used to forward the instruction to the processing circuit of the third subarray unit; the processing circuit of the third subarray unit is used to determine a corresponding pointing vector according to the instruction.

15. The phase array system as claimed in claim 7, wherein the processing circuitry of each subarray unit is used to calculate the inner product of the pointing vector corresponding to each candidate direction and the signal vector representing the group of electrical signals to determine the corresponding subarray response.

16. The phase array system as claimed in claim 7, wherein the processing circuitry for each subarray comprises: an analog-to-digital converter coupled to the group of antennas for converting the group of electrical signals into a group of digital signals; and a digital processing unit coupled to the analog-to-digital converter for processing the group of digital signals according to the N pointing vectors to calculate the responses of the N subarrays.

17. A phase array system comprising: a plurality of subarray units, wherein each subarray unit comprises: a set of antennas for coupling an input signal incident on the phase array system into a set of electrical signals; and a processing circuit coupled to the set of antennas for calculating N subarray responses corresponding to the N candidate directions based on the set of electrical signals and N pointing vectors associated with the N candidate directions, where N is an integer greater than 1; wherein the plurality of subarray units comprises a first subarray unit, a second subarray unit, and a third subarray unit; for each candidate direction, the processing circuit of the second subarray unit is used to combine the subarray response generated by the second subarray unit with the subarray response from the third subarray unit to generate a partial response; the processing circuit of the first subarray unit is used to combine the subarray response generated by the first subarray unit with the partial response from the second subarray unit for each candidate direction to determine the azimuth information of the input signal.

18. The phase array system as claimed in claim 17, wherein the processing circuit of the first subarray unit is further configured to send an instruction to the processing circuit of the second subarray unit, the instruction indicating one of the N candidate directions; the processing circuit of the second subarray unit is configured to forward the instruction to the processing circuit of the third subarray unit; both the processing circuit of the second subarray unit and the processing circuit of the third subarray unit determine the corresponding pointing vector according to the instruction.

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