Substrate, frame structure and packaging process

TWI941098BActive Publication Date: 2026-10-01ASE GLOBAL INTEGRATED SOLUTIONS CO LTD
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Patent Information

Application Number
TW114107774
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Filing Date
2025-03-03
Publication Date
2026-10-01
Estimated Expiration
2045-03-02

Smart Images

  • Figure TWG2TB001913732_001
    Figure TWG2TB001913732_001
  • Figure TWG2TB001913732_002
    Figure TWG2TB001913732_002
  • Figure TWG2TB001913732_003
    Figure TWG2TB001913732_003
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Abstract

This invention relates to a substrate, a frame structure, and a packaging process. The substrate includes at least one strip region. The strip region includes a usable area, wherein the usable area comprises a plurality of unit areas. The area of ​​the usable area is at least 90% of the area of ​​the strip region.
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Claims

1. A substrate comprising: A plurality of strip areas, each of which is a strip area formed after the cutting process, wherein the strip area does not include positioning holes and positioning marks, each of the strip areas includes an available area, wherein the available area includes a plurality of unit areas, the available area is filled with the unit areas, the area occupied by the unit areas is the available area, wherein the area of ​​the available area is more than 90% of the area of ​​the strip area.

2. The substrate of claim 1, wherein the area of ​​the usable region is equal to the area of ​​the strip region.

3. The substrate of claim 1, wherein the at least one strip region is configured for assembly with a bonding element and a frame structure for a packaging process, wherein the available region is used for mounting at least one electronic component thereon.

4. The substrate of claim 3, wherein the frame structure includes positioning holes and / or positioning marks for performing packaging process operations on such unit areas.

5. The substrate of claim 1, wherein the at least one strip region includes a first strip region and a second strip region, wherein the substrate further includes a plurality of substrate dicing channels for defining the first strip region and the second strip region, wherein the first strip region includes a first usable region, the second strip region includes a second usable region, and the distance between the first usable region and the second usable region is substantially equal to the width of one of the substrate dicing channels, wherein there is no sacrificial region between the first usable region and the second usable region.

6. The substrate of claim 5, wherein the strip regions are defined by a plurality of substrate dicing channels, and the unit regions are defined by a plurality of boundary lines, wherein the width of the boundary lines is smaller than the width of the substrate dicing channels.

7. The substrate of claim 3, wherein the frame structure includes: A plurality of sides, which together define an opening to receive the strip, wherein the sides have a gap with the strip, and the bonding element is used to cover the gap.

8. The substrate of claim 7, wherein the inner side surface of the such sides defines a plurality of equally spaced notches.

9. The substrate as claimed in claim 7 further includes: At least one positioning mark is located on at least one of the sides; and at least one positioning hole is located on at least one of the sides.

10. The substrate of claim 7, wherein the bonding element is an adhesive tape.

11. The substrate of claim 10, wherein the bonding element is frame-shaped and defines an opening to expose the usable area.

12. The substrate of claim 7, wherein the material of the frame structure is different from that of the strip, and the thickness of the frame structure is substantially the same as that of the strip.

13. The substrate of claim 7, wherein the sides have a non-flat inner side surface.

14. The substrate of claim 7, wherein, from a top view, the sides have non-uniform widths.

15. A packaging process, comprising: Provides a strip and a frame structure separate from the strip, wherein the strip does not include positioning holes and positioning marks, wherein the strip includes an available area, wherein the available area includes a plurality of unit areas, the available area is distributed throughout the unit areas, the area occupied by the unit areas is the available area, and the area of ​​the available area is more than 90% of the area of ​​the strip; assembles a bonding element, the strip and the frame structure, wherein the frame structure at least partially surrounds the strip; and attaches a plurality of electronic components to the strip.

16. The packaging process of claim 15, wherein the bonding element is an adhesive tape, wherein the frame structure includes positioning holes and / or positioning marks, wherein the step of assembling the bonding element, the tape, and the frame structure includes: The frame structure is then attached to the bonding element. And to attach the strip to the bonding element.

17. The packaging process, as described in claim 16, further includes: To form a package to encapsulate these electronic components; And to perform single-cutting operations to form multiple individual units.

18. The packaging process of claim 15, wherein the bonding element is frame-shaped and surrounds the electronic components.

19. The packaging process, as described in claim 15, further includes: Remove the bonding element; And to set multiple external components on the strip.

20. The packaging process of claim 17, wherein the step of forming the package to encapsulate the electronic components includes: The package is formed in the gap between the frame structure and the strip.

Citation Information

Patent Citations

  • Strip substrate and manufacturing method thereof

    CN106783789A

  • Substrate strip

    KR100872129B1