Methods and systems for symbolic electronic transmission

Abstract

The present invention relates to a method and a system for symbolic electronic transmission from a first user terminal to a second user terminal, the two user terminals being connected via a common multi-wire system having at least a first wire, a second wire, and a third wire, wherein the first user terminal has at least three series circuits, each operated by an upper electronic switch and a lower electronic switch, and each series circuit has a wire connected between the upper electronic switch and the lower electronic switch.

Description

Technical Field

[0001] This invention relates to the problem of electronic information transmission between two or more user terminals connected to an electrical conductor (bus) via a common group. A particular challenge is to increase the transmission rate while maintaining the same resilience to both internal and external interference.

[0002] This invention relates to a system for symbol transmission between a first user terminal and a second user terminal via a common multi-wire system.

[0003] The present invention also relates to a method for transmitting a symbol from a first user terminal to a second user terminal, the two user terminals being connected via a common multi-wire system having at least a first electrical wire, a second electrical wire, and a third electrical wire, wherein the first user terminal has at least three series lines, each operated by an upper electronic switch and a lower electronic switch, and the electrical wires are connected between the upper electronic switch and the lower electronic switch. Prior Technology

[0004] There are currently several methods for wired information transmission. In a traditional parallel bus, multiple asymmetrical conductors are bundled together, and the potential difference between each conductor pair and a common reference signal carries the information, typically one bit of the binary potential of each conductor. The receiver usually evaluates the information based on a hard decision threshold. This transmission method is sensitive to its own interference and external interference, and may typically have a lower transmission rate due to various high-frequency effects (reflection, limited signal power, crosstalk, EMV interference, etc.).

[0005] Different conductor systems, such as LVDS, CML, or PECL, do not have this signal fidelity issue and can achieve extremely high transmission rates. However, these systems are poor in terms of information transmission efficiency, cost, and power consumption. Typically, one coupled two-strand conductor is 1 bit, equivalent to 0.5 bits per conductor.

[0006] The ET200SP system, a Siemens distributed automation system, employs a special backplane bus system to address this issue. It utilizes a unique coding method to propose a conventional parallel bus that eliminates signal fidelity interference and achieves a considerable data transmission rate on a reliable bus of considerable length with multiple user terminals. However, this system does not allow for further (significant) functional enhancements.

[0007] The communication interface and digital data transmission method described in EP 1 038 232 B1 are used for the sequential transmission of digital data and for the bit transmission of digital data.

[0008] This solution addresses the interference and synchronization issues in sequential data transmission. It comprises a communication interface and a data transmission method, allowing for interference resistance and efficient digital data transmission. Its innovative use of at least three signal wires, each capable of displaying a "high" or "low" potential, is key. Data bits are encoded by the potential switching of two of the three wires, with the transition of the potential state determined within the encoding scheme. This allows for rapid synchronization and high data rates, eliminating the drawbacks of clock reversion or asynchronous transmission compared to synchronous transmission. Start / stop synchronization is achieved via potential reversal, which is particularly effective for short data packets. This invention is particularly suitable for automated devices used to control and monitor technical processes.

[0009] EP 2 154 590 B1 relates to a method for identifying receptacles of control modules in a modularly built controller. The method described in EP 2 154 590 B1 is used in modularly built controllers, such as programmable logic controllers (SPS). Its innovation lies in the clear and simple location of control modules through receptacle identification. This is achieved through a special data format transmitted by a communication bus and arranged in the transitions between each receptacle, ensuring that each receptacle receives a unique format. Bus wires are grouped and arranged within groups, increasing the number of receptacles that can be matched. This method eliminates the need for module reconfiguration during operation. Advantages include high availability and modular scalability of the controller, no need to activate backplane bus assemblies, improved reliability, and reduced space requirements. Useful data can be transmitted simultaneously with addressing data, improving system efficiency.

[0010] EP 0 150 540 A2 describes a method for data transmission between multiple stations via a shared data bus, where signals are connected via an OR function. The core of this scheme involves the periodic transmission of multiple data bits within a defined time period, which are interconnected. At the start of each period, a signal transmission is generated, determining the total time of the period and the position of the portion of the period. A signal is sent in the first portion of the period to declare "occupancy" of the data bus; the actual data bits are transmitted in the second portion of the period; and a signal without information content is sent in the third portion of the period. Stations can detect the time period from the signal changes and determine the state of the data bus and the value of the transmitted data bits. This results in efficient data transmission, even when clock frequencies differ within the stations, and supports multi-master operation.

[0011] The publication in EP 0 977 126 A2 relates to an interface circuit that connects devices via a bidirectional bus, particularly an I2C bus, which utilizes a data wire and a clock wire for transmission. The invention lies in the fact that the I2C bus signal is divided into transmit and receive branches, with the separate transmit and receive blocks transmitted via different wires. This results in long-distance, interference-resistant data transmission because physical interference is minimized by separating the signal transmission. The circuit design on the device includes optical couplers for electroplating isolation and to avoid potential difference interference. The receiver of the bus driver is always active, while the transmitter is only activated when a "0" is transmitted, controlled by a release logic. A resistor, representing a wave resistance, is connected to the separator wire at its end, generating the bus potential when the transmitter is deactivated. This bus circuit is particularly suitable for error-free transmission between instruments in microsurgical procedures, such as in a TEM endoscopic surgical system, while maintaining transmission frequency and the I2C bus protocol. This invention improves the exchange of data between medical instruments, which requires precise and reliable data exchange.

[0012] DE 60 126 191 T2 discloses a CMOS bus driver circuit, specifically addressing the problem of output voltages exceeding the supply voltage. This can occur when circuits with different supply voltages are integrated and connected via the same bus. The circuit consists of an input stage with two complementary MOS transistors and an output stage with two complementary MOS transistors. A key feature of this invention is the integration of an additional MOS transistor, which is gated and connected in both the output and output stages. This transistor is controlled by the supply voltage, protecting the circuit by turning on the corresponding output transistor when the output voltage is too high. A diode in the input stage prevents current from flowing towards the transistor connected to the supply voltage, preventing reverse current. The other MOS transistor is parallel to the diode, ensuring that the diode is bypassed during normal operation, allowing the circuit to quickly enter the blocking state. One blocking circuit section consists of an additional MOS transistor, a Negator, and a NOR circuit. When there is no start signal, it places the output stage in a high-impedance state to prevent current from flowing into the circuit through the bus. This method enables the circuit to operate reliably even within the supply voltage range and protects it from damage caused by voltages higher than the supply voltage.

[0013] EP 4 226 254 A1 discloses a method and apparatus for data exchange via a serial three-wire bus interface, particularly relating to the MIPI-Allianz C-PHY interface. The invention addresses the generation of multiple differential signals, each representing a voltage difference between a pair of conductors in a three-wire bus. A key feature of the invention is the identification of a differential signal with a maximum voltage value within a specific time period, i.e., a so-called unit segment (UI), and the determination of the three-wire bus signal state within that UI based on the identification of the conductor pair transmitting the first differential signal and the polarity of this signal in the UI. The invention allows a first edge to be generated in a clock signal, which responds in the UI upon the arrival of the first differential signal. This improves clock signal responsiveness and reliably monitors conductor states at high data rates. The invention includes a correction circuit to adapt the balancing circuitry in the differential receiver according to the number of UIs marked in a C-PHY start flag, where the first differential signal has a maximum voltage value. This invention significantly improves data transmission and processing, which is of great importance in mobile devices such as smartphones and tablets, cameras and displays, which are connected via a C-PHY interface.

[0014] US 9,692,555 B2 relates to information transmission, specifically the transmission of a set of symbols received via a multi-wire bus. A key feature of this invention is the use of a first two-input comparator connected to a multi-wire bus, which generates a first output signal based on the comparison of a pair of symbols with different values. An arithmetic circuit loop receives the symbol pair and generates an arithmetic result, which is then passed to a second two-input comparator to generate a second output signal. This second output signal represents the result of comparing the arithmetic result with a third symbol, which is not part of the symbol pair. This invention reduces the number of comparators required, resulting in a simple and energy-efficient symbol configuration. The invention is also reusable, eliminating larger sparse comparator units from smaller sparse comparator units (SCUs), improving system flexibility and scalability.

[0015] The apparatus and method proposed in DE 10 2006 061 651 B4 are for encoding conversion coefficient blocks for digital construct compression methods such as JPEG2000. Coefficients are represented by multiple amount bits, located in the bit plane. The encoding device passes through this amount tuple and encodes it in a data stream. Each amount tuple belongs to one of three channels. A key feature is the prediction device, which predicts which amount bit in the next tuple should be encoded. This is based on a prior prediction and information about the coefficient's state. The prediction allows the encoding device to effectively determine which bits should be encoded while still adhering to the passing order.

[0016] This device achieves efficient hardware implementation of image compression by reducing the number of processing steps and allowing multiple coefficients to be processed in parallel. This optimizes computational power and is beneficial for the expensive modularization of coefficient bits.

[0017] EP 3 637 715 B1 relates to a transmitter and a receiver for efficient data stream transmission, particularly for transmitting image data via multiple parallel transmission paths. This invention allows for a training process to be performed when specific parameters affecting the physical layer change, synchronizing and correcting time differences between paths (trajectories), such as the number of transmission paths or the transmission rate. However, when parameters of the connection layer change, such as the pixel bit length or the number of rows and columns, data stream transmission can continue without this training process. This improves efficiency because there is no unnecessary interruption. The invention also includes a method for signaling parameter changes, using flags or directly transmitting the changed parameters in the packet header. This technique is particularly useful for systems requiring fast and reliable transmission of large amounts of data, such as medical imaging or endoscopic systems.

[0018] EP 2 683 124 B1 relates to a digital data transmission / reception device based on a Low Voltage Differential Signaling (LVDS) standard specifically applied in automation technology. The device includes a transmitting unit, a receiving unit, and a protocol method. Its novelty lies in a special circuit arrangement that allows for faster signal fluctuations in the receiving unit, thus ensuring error-free signal transmission over longer distances. This is achieved by incorporating capacitors and resistors in the receiving longitudinal branch, the values ​​of which are specifically tuned. Furthermore, an AC coupling agent allows for potential separation, making the component easily usable with different current supplies. This invention solves the problems of limited conductor length and potential differences in conventional LVDS connections, improving and enhancing data transmission robustness in automation systems.

[0019] DE10 155 526 C2 discloses an LVDS (Low Voltage Differential Signal Driver) for low supply voltages less than 2 volts, particularly relevant to high-density integrated circuit loops. This invention is specifically designed for pull-up and pull-down functions of PMOS transistors, allowing for symmetrical switching behavior and operation in the linear region. By limiting the maximum amplitude of the control signal to a value slightly above the transistor's turn-on threshold voltage, it ensures that the transistor can effectively switch between off and on states without compromising switching quality due to low supply voltages. Summary of the Invention

[0020] The purpose of this invention is to further develop known symbol transmission systems and methods, thereby improving the efficiency of data transmission in terms of data rate.

[0021] The solution of this invention includes, in particular, a system for symbol transmission between a first user terminal and a second user terminal, connected via a common multi-wire system to a first wire, a second wire, and a third wire. The first user terminal includes a symbol encoder, a power module, and a control block, the control block having an upper control block and a lower control block. The upper control block closes and opens an upper switch, and the lower control block closes and opens a lower switch. The upper switch has at least three upper electronic switches, the lower switch has at least three lower electronic switches, and there are at least three series circuits, each consisting of an upper electronic switch and a lower electronic switch. Wires are connected between the upper and lower electronic switches in each series circuit, and wires are also connected in the series circuits. The objective of this invention is that the symbol encoder provides a current loop-control vector to the control block, and the control block operates the electronic switches by the current loop-control vector, causing current to flow into the connected wires. The current loop-control vector has a switching combination of electronic switches. The symbol decoder determines the current loop-control vector by sequentially selecting a conductor from the multi-conductor system's conductor inventory to encode the symbol to be transmitted. A conductor pair includes one conductor as the current-carrying conductor, flowing from the first user terminal to the second user terminal, and another conductor as the loop conductor. Additionally, there is a termination unit, to which the symbol encoder provides a termination vector. The termination unit connects a termination resistor network to the conductors in the multi-conductor system via a termination switch. The second user terminal has a comparator network designed to detect the voltage levels between the two conductors to decode the symbol, which is encoded in the different voltage levels between the conductors.

[0022] In the context of this invention, an upper electronic switch and a lower electronic switch are understood as a half-bridge consisting of two switches, connecting a series circuit to a voltage source and a power supply. Accordingly, in this invention, the upper and lower electronic switches are, for example, each semiconductor switch, with the upper electronic switch positioned in an upper current loop relative to a terminating resistor, and the lower electronic switch positioned in a lower current loop relative to a terminating resistor. They can also be referred to as a high-side driver (current supply - switch to the first output terminal of the power module) and a low-side driver (ground - switch to the second output terminal of the power module). In an advantageous embodiment, the switches can be manipulated so that the potentials of the power supply and voltage source are not completely switched on, thus allowing different currents to be supplied to the terminating resistor and generating different high signal voltages, particularly more than two different signal voltages.

[0023] Advantageously, symbol encoding is performed using selectable signal paths. The basic concept of this method is to sequentially select one or more conductor pairs from a multi-conductor system supply to encode transmitted information. Information is encoded in the sequential selection of conductors. This invention is particularly suitable for controlling and monitoring technical processes in automated devices. Traditional digital parallel bus systems offer high information density per bus but are prone to signal fidelity issues, thus unable to operate at high signal rates. One-point or multi-point differential conductor systems are very resilient to their own interference or external interference but cannot provide high information density. Analog or hybrid transmission methods (such as OFDM) address this problem but require expensive system components, which are also noticeable in terms of power consumption during operation. This invention eliminates the disadvantages of traditional methods in a cost-effective manner within a single system.

[0024] In another embodiment, the symbol encoder provides multiple current loop-control vectors, and the control block is designed to operate a common multi-wire system with multiple current loops.

[0025] Therefore, in a multi-wire system with N wires, there are a total of N×(N-1) different possibilities, extracted from the transmitted signal stream by the symbol encoder via a first current loop-control vector. The second current loop can be selected from a set of decreasing wires in the same manner, resulting in (N-2)×(N-3) different possibilities for opening the second current loop-control vector. This control vector is also extracted from the transmitted signal stream by the symbol encoder. This method can continue for other current loops, provided the remaining wire supply is sufficiently large. According to this approach, a total of N! / (N-2L)! symbols are generated, which are L current loops generated on N wires. Therefore, to continue encoding the symbols to be transmitted, L current loops are selected from the N wires, thus increasing the symbol capacity.

[0026] To further increase symbol capacity, different signal currents are injected into individual current loops in the control block and / or power module. The most important factor in using multi-wire systems is that the signal currents differ in magnitude and their interrelationships are stable.

[0027] During the receiving operation, the comparator network starts and continuously detects voltage levels in a (digital) receive vector of a multi-wire system. A symbol encoder detects the output symbol stream from this receive vector, and the comparator network assigns the detected voltage levels to a receive vector as elements.

[0028] In another embodiment, there is a symbol encoder that receives a received vector and performs a maximum-detection and a minimum-detection in a sequence of elements of the received vector, and provides a binary sequence in which the positions of the maximum and minimum levels in the sequence are marked.

[0029] The system is further improved through a progressively decreasing receive vector; for this purpose, the system has a first discriminator, a second discriminator, a first decrementer, and a second decrementer. The first discriminator is designed as a Min-Max wire pair, capable of receiving the receive vector and detecting the maximum and minimum relative levels in a multi-wire system, and further providing the detection results as first wire pair information. The first discriminator is connected to the first decrementer, providing the first wire pair information to a decreasing receive vector. The second discriminator is designed as another Min-Max wire pair discriminator, receiving the decreasing receive vector, detecting the wires with the maximum and minimum relative potentials in the multi-wire system from the fewer wire pairs already identified, and further providing the detection results as second wire pair information. The second discriminator is connected to the second decrementer, providing the second wire pair information to another decreasing receive vector.

[0030] This invention constructs a multi-wire system with efficient buses using a simple and CMOS-based chip architecture, achieving signal fidelity and transmission rate similar to, for example, LVDS, while exhibiting significantly higher information encoding efficiency, with only a small increase in power consumption. The following feature is important: at any given time, only a few current loops of varying intensities exist within the wire system. Thus, current loops are clearly formed on the transmitting side by their relative current intensity ratios and can be identified on the receiving side. Information encoding is achieved by filtering individual wires within each current loop and determining their flow direction. The receiver can identify each current loop and determine its direction through a rapid iterative process. This requires only a simple pure binary query using a comparator. Using impedance-controlled and low-reflection wire guiding techniques and appropriate terminations, the transmission system essentially achieves maximum signal scalability with appropriately low complexity and moderate current consumption.

[0031] The aforementioned objective is also achieved through an electronic symbol transmission method. This method involves transmission from a first user terminal to a second user terminal, with the two user terminals connected via a common multi-wire system. This multi-wire system has at least a first conductor, a second conductor, and a third conductor. The first user terminal has at least three series circuits, each controlled by an upper electronic switch and a lower electronic switch. Conductors are connected between the upper and lower electronic switches of each series circuit. The encoding method for the symbol to be transmitted involves selecting a switch combination of electronic switches and sequentially selecting a conductor pair from the supply of conductors in the multi-wire system for encoding. During this process, current from a power source flows from the first user terminal into the multi-wire system via a closed upper electronic switch and a conductor serving as a forward conductor. A terminating resistor network is connected to the electronic conductors in the multi-wire system, connecting the current path of the current in the forward conductor to another electronic conductor. The other electronic conductor, acting as a loop conductor, is used by the first user terminal via a closed electronic switch. At the second user terminal, the voltage level between the two conductors is detected, and the symbol is recovered from the different voltage levels of the two conductors, and then decoded. This achieves selective signal path establishment. The basic idea of ​​the method is to encode the transmission information of one or more conductor pairs in an orderly manner from the supply of a multi-conductor system. The conductor pairs are used for the conduction of one or more signal flows.

[0032] In a multi-conductor system with N conductors, there are a total of N×(N-1) different possibilities for the first current loop. For the second current loop, there are a total of (N-2)×(N-3) different possibilities. According to this method, the space of symbols for the current loops on N conductors is N! / (N-2L)! possibilities. L is the number of current loops. Accordingly, the common multi-conductor system operates with N conductors, and current loops are constructed between the first and second user terminals via electronic switches on the conductors and terminating resistor networks. To further encode the symbols to be transmitted, a number L of current loops are selected based on the number of conductors, thereby increasing the symbol supply. Advantageously, among the selected L number of current loops, different signal flows are formed, and thus the symbol supply is further improved.

[0033] The voltage levels between wires are best detected using a comparator network, and the detected voltage levels are assigned to a receiving vector as elements. The receiving vector is constructed by conventionally scanning each wire sequentially, and the relative voltage levels in the wire system are detected sequentially in the receiving vector. A common practice, for example, can be based on theoretical notation: each wire represents a node, set on a loop. In a 4-wire system, there is a node A, a node B, a node C, and a node D. Starting clockwise from node A, the edges between nodes can be marked. When reaching the output node, diagonal or cross-connections can be marked as edges. The resulting edges represent the voltage levels between nodes and wires: A->B, B->C, C->D, D->A, A->C, and B->D. A receiving vector can be as follows: Receive vector = {+1V,+2V,-1V,1V,1V,1V} However, this is not the only convention to follow; other conventions are also acceptable.

[0034] The received vector is ideally guided to a symbol decoder, where one element of the received vector's string is used for maximum value detection, and another element of the received vector's string is used for minimum value detection, each providing a binary sequence with the positions of the maximum and minimum potentials marked in the string. Symbol decoding in the symbol decoder can be performed on an undiluted and fully meshed comparator network in a multi-stage and iterative process. For this purpose, a "minimum-maximum wire pair discriminator" identifies the wire pairs with the maximum and minimum relative potentials in the wire system and feeds this information back as wire pair information.

[0035] If multiple current loops with different signal currents operate between the first user terminal and the second user terminal, the symbol decoding is explained as follows:

[0036] In the first step, a comparator network detects the voltage level between the conductors, and the detected voltage level is assigned to a receiving vector as an element.

[0037] In the second step, the received vector is directed to a symbol decoder. On the one hand, the maximum value is detected in one element string of the received vector, and on the other hand, the minimum value is detected in another element string of the received vector. Each provides a binary sequence, and the positions of the maximum and minimum levels are marked in the string.

[0038] In the third step, the received vector is reduced by the position identified in the second step to obtain a reduced received vector; the first step is repeated with the reduced received vector until the reduced received vector or another reduced received vector corresponds to a multi-wire system with a conduction number N=3.

[0039] In a preferred embodiment with maximum efficiency, the comparator network maintains one comparator for each individual wire pair in the wire system. If not the same number of comparators as the wire pairs, the size of the receive vector is limited, as is the complexity of the symbol decoder, resulting in a smaller number of symbols and limiting the system's throughput. Refining the comparator network requires caution; asymmetric refinement leads to a loss of wire switching tolerance in multi-wire systems, thus potentially rendering the address resolution and slot identification method proposed in EP 2 154 590 B1 unusable. A compromise is to refine based on equidistant wires, which maintains switching tolerance.

[0040] After the first step, it is known which wire pair has the maximum current in the current loop. Using this information, the receiving network and receiving vector can be refined and reduced for this wire pair in the preparation for the second step.

[0041] This invention constructs a bus-capable multi-wire system using a simple and CMOS-integrable group for information transmission, achieving signal fidelity characteristics and transmission rates similar to, for example, LVDS, while also providing clear and efficient information encoding with a low-proportion increase in current consumption. To this end, a semiconductor element serves as a wire driver for symbolic electronic transmission between a first user terminal and a second user terminal connected via a common multi-wire system having at least a first wire, a second wire, and a third wire. The proposed wire driver executes the method claimed in this invention. Simple Explanation of the Diagram

[0042] Several embodiments of a data transmission system symbolized by a common multi-wire system between a first user terminal and a second user terminal are shown in the figures, illustrating the method of the present invention. The figures show: Figure 1 illustrates the principle of electronic transmission of symbols, from a first user terminal to a second user terminal via a common multi-wire system; Figure 2. A 4-wire system for symbol transmission "BC"; Figure 3. The 4-wire system for symbol transmission "CB" as shown in Figure 2; Figure 4. A 4-wire system with two current loops; Figure 5. A typical transceiver setup in a multi-wire system; Figure 6. Block diagram of a transceiver; Figure 7. Principle of a control block; Figure 8. A comparator network; Figure 9. Block diagram of a symbol encoder; Figure 10. Block diagram of a terminal unit; Figure 11. Comparison of different conductor systems; Figure 12 shows an example of a decoder, which extends to Figures 12A, 12B, 12C, and 12D; Figure 13 is a view of the receiving vector reduction, which extends to Figures 13A, 13B, 13C, and 13D; Figure 14 shows a possible embodiment of the comparator; Figure 15 shows the first step of receiving vector estimation, which has a subsequent reduction; Figure 16 shows the second step of the reduction process; Figure 17 Summary of Reductions; Figure 18 shows the third step in the reduction process; Figure 19 shows the fourth step in the reduction process; Figure 20 shows the fifth step in the reduction process; Figure 21 shows a schematic diagram of the unit integrated into a transceiver switching circuit; Figure 22 shows the transceiver switching circuit connected in a multi-wire system; Figure 23 Possible bus topologies; Figure 24 Parallel operation of different conductor systems; Figure 25 shows a terminal operating in parallel. Figure 26 shows a dynamic terminal, and Figure 27 shows the hybrid operation between LVDS and multi-wire systems. Implementation

[0043] Figure 1 shows a first user terminal 1 and a second user terminal 2, which can communicate with each other via a common multi-wire system 200 using symbolic electronic transmission. The first user terminal 1 is connected to the second user terminal 2 via the multi-wire system 200 using a first wire 201, a second wire 202, and a third wire 203. For signal electronic transmission and therefore symbolic electronic transmission, at least three series circuits P1, P2, and P3 operate at the first user terminal 1, each consisting of an upper electronic switch A1, B1, C1, and a lower electronic switch A2, B2, C2. Series circuit P1 includes a first upper electronic switch A1 and a first lower electronic switch A2, with a wire 201 connecting between the two switches A1 and A2. Series circuits P2 and P3 are similarly connected to the second wire 202 and the third wire 203. The switches are designed as, for example, C-MOS-based integrated semiconductor devices.

[0044] The encoding method for the symbol Sym (also shown in Figure 2) to be transmitted is as follows: Switch combination SK is selected by electronic switches A1, B1, C1, A2, B2, and C2; corresponding electronic switches A1, B1, and C1 are controlled; and a wire pair is sequentially selected from the wire supplies 201, 202, and 203 of the multi-wire system 200, and encoding is performed. Current from a power source Q is conducted from the first user terminal through each of the closed electronic switches A1, B1, and C1 to one of the wires 201, 202, and 203, and then flows as a forward conductor HL to the multi-wire system 200.

[0045] At or outside the second user terminal 2, a terminating resistor network 501 is connected to the conductors 201, 202, and 203 of the multi-conductor system 200, connecting the current path SW of the current I on the forward conductor HL to another conductor 201, 202, and 203 via a neutral point SP. The second conductor allows the current I to be utilized by the first user terminal 1, flowing through a closed lower electronic switch A2, B2, and C2 as a loop conductor RL. To decode the transmitted symbol Sym, at the second user terminal 2, voltage levels AB, CB, and CA are detected between each pair of conductors 201, 202, and 203, and the symbol Sym is recovered from the different voltage levels between the conductors.

[0046] The voltage between conductors 201, 202, and 203 is measured in the terminating resistor network 501.

[0047] Figure 2 further illustrates the transmission principle in Figure 1. The figure shows that it is similar to switching the switch combination SK to electronic switches A1, B1, C1, A2, B2, C2, and can transmit a symbol Sym = "BC".

[0048] This invention employs selective generation of a signal path. The basic concept of the method is to encode the transmission information of one or more wire pairs selected in an orderly manner from the supply of the multi-wire system 200.

[0049] Figure 2 basically shows the first user terminal 1 and its upper and lower electronic switches A1, B1, C1, A2, B2, C2, a terminating resistor network 501, the measurement diagram of voltage levels AB, BC, CA, CB, DB, AC, and a coding criterion from which the switch combination SK is obtained.

[0050] The wires 201, 202, and 203 of the upper electronic switches A1, B1, and C1 are connected to the first output terminal of the power supply Q, and the wires 201, 202, and 203 of the lower electronic switches A2, B2, and C2 are connected to the second output terminal of the power supply Q.

[0051] Assume that the symbol Sym = "BC" is transmitted on the multi-wire system 200. According to the encoding criteria of the encoding table, the symbol Sym = "BC" is in the fourth position of the encoding table. The switch combination "B" for "B" is 1011, and the switch combination "C" for "C" is 0010. The encoding table is divided into switch combinations SK for the upper electronic switches A1, B1, and C1 and switch combinations SK for the lower electronic switches A2, B2, and C2. This will be referred to as the control block 300 as a whole. The upper electronic switches A1, B1, and C1 constitute the upper control block 301, and the lower electronic switches A2, B2, and C2 constitute the lower control block 302.

[0052] The symbol Sym = "BC" is read from the encoding table, which displays column GP1 (gate positive 1) and column GN1 (gate negative 1), detecting the symbols "B" and "C" respectively. Therefore, the upper control block 301 has one switch combination SK, and the lower control block 302 also has one switch combination SK. Let's look at the upper control block 301 first. The upper control block 301 receives switch combination SK = 1011, which means that the first upper electronic switch A1 is controlled by "1", the second upper electronic switch B1 is controlled by "0", the third electronic switch C1 is also controlled by "1", and the fourth electronic switch D1 is also controlled by "1". Since the upper control block 301's electronic switches A1, B1, C1, and D1 have an inverted input, only the second electronic switch B1 is controlled so that current I can flow from power supply Q into the multi-wire system 200. Current I flows to the second conductor 202 through the closed and controlled second upper electronic switch B1. This second conductor 202 serves as the forward conductor HL for the current I to flow to the other user terminal and the terminating resistor network 501. The current I then flows to the terminating resistor network 501 and can take a current path through the star-connected resistors there to return to the first user terminal 1 via the third conductor 203. Since the first user terminal 1 selects the switch combination SK=0010 for the lower control block 302, the lower control block 302 controls the third lower electronic switch C2, allowing the current to flow back to the power supply Q.

[0053] To decode the transmitted information, for example at the second user terminal 2 or at any other location, voltage levels AB, BC, and CA are generated and detected between two conductors 201, 202, and 203 via the terminating resistor network 501. The symbol Sym = "BC" can be recovered from the different voltage levels AB, BC, and CA between conductors 201, 202, and 203. An example diagram of a 4-wire system N=4 is shown in the middle of Figure 2. This example diagram corresponds to the four nodes of the 4-wire system N=4, namely, a first node A, a second node B, a third node C, and a fourth node B. The dashed lines in the diagram representing the multi-conductor system 200 indicate the captured voltage levels. A voltage level AB can be measured between the first node A and the second node B. The first node A is connected to the first conductor 201, and the second node B is connected to the second conductor 202. A voltage level BC can be measured between the second node B and the third node C; for this purpose, the third node C is connected to the third conductor 203. Since the fourth node D is connected to the fourth conductor 204, the voltage level CD between conductors 203 and 204 can be measured between the third node C and the fourth node D. For this 4-wire system with N=4, six different voltage potentials can be measured between nodes A, B, C, and D. A table is shown on the right side of the diagram, with elements representing voltage levels. A receiving vector 402 is generated from the elements by measuring the voltage levels between conductors 201, 202, 203, and 204. Using the aforementioned switch combinations SK=1011 and SK=0010, the table displays the voltages AB, BC, CD, DA, AC, and BD between conductors 201, 202, 203, and 204.

[0054] To determine what symbol Sym represents, a symbol decoder 450 (see Figure 8) on the element sequence 402 of the received vector performs both minimum and maximum value detection, generating Max and Min in binary order, marking the positions of the maximum and minimum potentials in the sequence. In the example, the symbol "BC" has a maximum value between the two nodes "BC" and a minimum value between the two nodes "CD". This generates another vector "010000" and "001000". Based on these two Min-Max vectors, the transmitted symbol Sym can be read back from a decoding table.

[0055] Figure 3 shows the transmission of the symbol Sym = "CB". Due to different switch combinations SK, SK = "1101" and SK = "0100", the other wires 201, 202, 203, and 204 are selected as the forward conductor HL and the return conductor RL, respectively, for the transmission of the symbol Sym = "CB" in Figure 3. It is precisely because of the different selection of the forward conductor HL and the return conductor RL that a symbol Sym can be encoded by the selection of the conductors. According to the switch combination SK = "1101", the upper control block 301 controls the conduction of the third upper switch C1. The current I flows through the forward conductor HL through the third wire 203 to the terminating resistor circuit 501, and returns through the current path SW of the terminating circuit, becoming the return conductor RL through the second wire 202. Since the lower control block 302 controls the second lower switch B2 according to the switch combination SK = 0100, the current I can flow back to the power supply Q, so that the current loop is closed. On the right side of the diagram for nodes A, B, C, and D, a small table displays the voltage levels, and the maximum and minimum vectors can be read from the receiving vector 402.

[0056] Figure 4 illustrates a principle that may improve symbol supply. According to Figure 4, between the first user terminal 1, the second user terminal 2, and a terminating resistor network 501, there is a second current loop 122 in addition to the first current loop 121. The first user terminal 1 has a first voltage source Q1 and a second voltage source Q2 for this purpose. The electrical switches in each upper control block 301 and lower control block 302 are duplicated, and each current loop Q1, Q2 has its own switch. If there are multiple current loops 121, 122 between the first user terminal 1 and the second user terminal 2, running different signal currents I1, I2, the decoding of the symbol Sym is performed as follows:

[0057] In a first step, voltage levels AB, BC, and CA are detected using a comparator network 400 between conductors 201, 202, 203, 204 and nodes A, B, C, and D. The comparator network 400 is described in detail later in Figures 6 and 8. The detected voltage levels AB, BC, and CA are detected in the manner illustrated in Figures 2 and 3, and the voltage levels AB, BC, and CA constitute a reception vector 402, where voltage levels AB, BC, and CA are elements of the reception vector 402.

[0058] In a second step, the received vector 402 is directed to the symbol decoder 450, which performs maximum value determination on one element sequence of the received vector 402 and minimum value determination on the other, providing a binary sequence Max and Min. These binary sequences Max and Min (see also Figures 2 and 3) illustrate the positions of the maximum and minimum levels in the sequence.

[0059] In the third step, the received vector 402 is reduced at the known location. Then, the maximum value detection and minimum value determination are performed again using the reduced received vector 402.

[0060] Following the procedure shown in Figure 4, the following advantages are obtained: each available wire pair can supply another current loop, improving symbol supply. Using currents of different intensities also generates defined potentials between the wires of each current. This allows for incremental encoding and decoding later on the existing number of wires using multiple currents. In this way, more information can be encoded with less energy consumption on fewer wires. Encoding and decoding can also be done using purely digital and simple circuitry.

[0061] Figure 5 shows the arrangement of a typical transceiver 100 connected to a common multi-wire system 200. In this invention, a transceiver is understood as a transmit-receiver, and transceiver 100 is preferably implemented in an integrated circuit. This means that the transceiver includes a transmitter, a receiver, a resistor network, and corresponding control logic. This invention describes a transceiver 100 that provides access to a multi-wire system 200 shared with other user terminals. This invention also describes an encoding method for energy-efficient information transmission between two or more transceivers 100 via the multi-wire system 200. This invention establishes a bus-capable multi-wire system 200 for information transmission using a relatively simple and CMOS-integrated module, achieving signal fidelity and transmission rate similar to LVDS, but with clearly effective information encoding at a low percentage increase in power consumption. The following features are crucial: 1) At each point in time, only a small number of current loops of varying intensities are supplied to the conductor system. 2) The current loops can be clearly formed on the transmitting side by the ratio of their relative current intensities and can be identified on the receiving side. Based on this, the conductors of each current loop are selected as forward conductors and loop conductors for information encoding. 3) A receiver can identify each current loop and determine its direction through a fast iterative process. This only requires a simple binary query using a comparator. 4) By using impedance-controlled and low-reflection wiring techniques and appropriate terminations, the transmission system achieves high signal rates with relatively low complexity and moderate power consumption.

[0062] The encoding method for symbolic electronic transmission is the method for which this invention is claimed. A transceiver 100 directly accesses a multi-wire system 200 and provides an interface for control via an information processing system in the form of symbol streams in the receiving and transmitting directions, i.e., transmitting symbol stream 102 and outputting symbol stream 103. A control signal 101 is used, for example, to switch between transmitting and receiving, between a terminal and / or a dynamic terminal. The transceiver 100 includes a control unit having a symbol encoder 110, a power module 120, and a suitable number of control blocks 300 (see FIG. 6). The transceiver 100, which is only shown in principle in FIG. 5, is described in detail in FIG. 6. A particular advantage of the invention is that the transmission information of one or more wire pairs is encoded by the orderly selection of wire pairs supplied by the multi-wire system 200, and each wire allows one or more signal streams to pass through. Using multiple wire pairs can increase the signal stream to varying degrees and exist in a reliable, interference-resistant manner.

[0063] Figure 6 shows a block diagram of a transceiver 100. A symbol encoder 110 includes a transmit symbol stream 102 as input and a control signal 101. The symbol encoder 110 transmits a first current loop control vector 111 to a control block 300. Furthermore, the symbol encoder 110 can transmit a second current loop control vector 112 to another control block 300. Depending on the design, x current loop control vectors 11x can be transmitted to more control blocks 300. The xth current loop control vector 11x is used to transmit to another control block 300. A first current loop 121, or a second current loop 122 and an xth current loop 12x are formed via each current source module 120. Corresponding to control block 300, as illustrated in Figures 2 and 3, the corresponding signal stream is transmitted through a multi-wire system 200, and the voltage level of the conductors in the multi-wire system 200 is measured by a comparator network 400 at a receiver. Therefore, a transceiver 100 includes a control unit with a symbol encoder 480 (see Figure 9), one or more connected current sources, and a suitable number of control blocks 300, each control block having an upper control block 301 and a lower control block 302. For receiving operations, there is also a comparator network 400 with a symbol decoder 450.

[0064] Figure 8 shows the symbol decoder 450 in detail. The symbol decoder 450 produces the output symbol stream 103.

[0065] The current loop driver is a unit consisting of a coupled power supply, i.e., power module 120, and a current distributor, i.e., a control block 300 having an upper control block 301 and a lower control block 302. With this current loop driver, a directional and definite current can be supplied to the multi-wire system 200 in various ways. The forward current I, the HL, and the loop current I, can be freely selected from the N wires of the multi-wire system 200. The control block 300 (see Figure 7) can be configured as a "differential tuple" from at least N=3 wires for encoding or decoding. Unlike differential pairs, as is known in LVDS technology, more information can be encoded or decoded because multiple wire paths can be selected by multiple of the aforementioned control circuits.

[0066] In contrast to differential pairing, "differential tuple" is supplied with multiple wire paths by a control circuit, namely control block 300, which controls a half-bridge combination to select wire pairs to establish current loops while still considering current intensity. In the control, it is necessary to prevent lateral current from being caused by the high-side and low-side drivers (upper control block 301 and lower control block 302) simultaneously selecting the same wires.

[0067] The minimum configuration of the transmission channel consists of two transceivers 100, a multi-wire system 200, and a neutral point termination 503. The termination is necessary because it represents the current path (Pfad) and current loop (Weg) SW within the current loop, and the voltage drop and voltage level difference can only be measured through the termination resistor R. In its simplest case, it can be a suitable, continuously effective resistor network. However, it is also advantageous to integrate the termination unit 500 within the transceiver 100. This allows for selective switching on and off of the termination resistor R along the multi-wire system 200. This can be used for an expanded bus with multiple distributed user terminals and transceivers 100, providing targeted responses to reflections. It can also temporarily switch on and off the termination of all or individual bus wires, precisely affecting the signal flow. For this purpose, the termination unit 500 is selectively controlled by a symbol encoder 110 via a termination switch 502 and a termination vector 104 located therein. Figure 7 shows the control block 300. A current loop vector 11x is routed to both the upper control block 301 and the lower control block 302. The upper control block 301 can be called a "high-side thermal" encoder, and the lower control block 302 can be called a "low-side thermal" encoder. The upper control block 301 can close or open the upper switch 303 of the half-bridge. The lower control block 302 can close or open the lower switch 304 of the half-bridge. For 7 wires N=7, there are 7 upper switches 303 and 7 lower switches 304. Each wire 201…207 is equipped with an upper switch 303 and a lower switch 304. In Figures A, B, C, D, E, F, and G, the first wire 201 corresponds to node A, and the seventh wire 207 corresponds to node G.

[0068] Figure 8 shows a comparator network 400, where a 7-wire system (N=7) has 21 comparators available. One comparator group is formed and configured for the farthest neighbor (3D). Another comparator group is configured for the intermediate neighbor (2D), and yet another comparator group is configured for the nearest neighbor (1D). Observing Figures A, B, C, D, E, F, and G, among the seven nodes, the farthest neighbor (3D) represents a distance of 3 edges between the two nodes, the intermediate neighbor (2D) represents a distance of 2 edges between the two nodes, and the nearest neighbor (1D) represents a direct neighbor.

[0069] Receive operation and symbol recognition

[0070] After comparing voltage levels with 21 comparators, the symbol encoder 450 can provide an output symbol stream 103. During reception, the comparator network 400 activates, continuously detecting the relative ratios of voltage levels in the multi-wire system 200 and mapping them to a digital receive vector 402. The symbol encoder 450 then uses this receive vector 402 to determine the output symbol stream 103. In a preferred embodiment for maximum performance, the comparator network 400 maintains one comparator 401 for each individual wire pair in the multi-wire system 200. However, the required number of comparators can also be reduced by refining the comparator network 400. This limits the size of the receive vector 402 and the complexity of the symbol encoder 450, and results in a reduced number of possible symbols, limiting the system's throughput. When refining the comparator network 400, it is important to note that asymmetric refinement leads to a loss of wire switching tolerance in the wire system 200.

[0071] Symbol decoding in the symbol encoder 450 can only be performed in a multi-step and iterative process for the unrefined and fully meshed comparator network 400. For this purpose, a first discriminator 461 (see FIG. 9), acting as a minimum-maximum wire pair discriminator, identifies the wire pair with the maximum and minimum relative levels in the multi-wire system 200 and reports this as wire pair information 451, 454, 457. In a preferred embodiment, a simple multi-wire system-and-logic gate (see FIG. 14) detects whether a wire potential is consistently greater than or less than the potentials of all other logic wires. When the maximum and minimum cannot be accurately identified, error signals 452, 455, 458 are activated. Error signals occur when the bus is stationary or multiple wire loops 12x are started with the same current intensity. In this case, it is impossible to clearly assign each current loop.

[0072] Figure 9 shows a block diagram of a symbol encoder 480. To extract a reduced receive vector 453 and a further reduced receive vector 456 from a receive vector 402, a first discriminator 461, a second discriminator 462, and a third discriminator 463 are provided to implement a multi-step and iterative procedure. The symbol encoder 450 in Figure 8 provides 21 values, which are examined by the first discriminator 461. When a minimum and a maximum value cannot be identified, a first error signal 452 is generated. Using the minimum and maximum value estimates, the symbol encoder 480 can provide a first wire pairing information 451 via the first discriminator 461. A multi-wire system 200 with N=7 is reduced to a multi-wire system with N=5 by a first decrementer 471. A reduced receive vector 453 is generated by the first decrementer 471. The reduced receive vector 453 becomes the input of the second discriminator 462 for minimum-maximum estimation. The second discriminator 462 can also provide a second wire pairing information 454 to the symbol encoder 480. In the next step, the reduced receive vector 453 is converted into a further reduced receive vector 456 by a second reducer 472. This second reduced receive vector 456 is then checked for minimum and maximum values ​​by a third discriminator 463, which can then provide a third wire pairing information 457 to the symbol encoder 480. If the first discriminator 461, the second discriminator 462, and / or the third discriminator 463 finds an error in the minimum-maximum-estimate, they respectively provide a first error signal 452, a second error signal 455, and / or a third error signal 458 to the symbol encoder 480.

[0073] After the first step, it is known which wire pair has the largest current loop in the forward and return current loops. This information prepares for the second step, where the receiving network refines this wire pair. In the example of Figure 9, a multi-wire system 200 with N=7 has a total of L=3 current loops. After the first step, the first current loop through nodes B and F is identified, with the remaining nodes A, C, D, E, and G still existing. In the same step, the comparator connecting the removed nodes B and F is invalidated and can be removed from the receive vector 402. The "decrease" block of the receive vector and the receiving network removes these invalid bits, generating a new reduced receive vector 453, which is reduced to a new length of 10 bits, corresponding to the receive vector of a 5-wire system with N=5. Then, another "minimum-maximum-wire pair discriminator" can be used to find the forward and return current loops of the remaining largest current loops. When preparing to end the iteration, the reduced receive vector is identified based on the wire pairing information 454. This vector now corresponds to a 3-line system with N=3 nodes A, C, and E.

[0074] The symbol encoder 480 recognizes wire pairing information 452, 445, and 458 (A, B, and C) and can easily identify a received symbol from this wire pairing information. An error symbol is generated whenever any of the error signals 452, 455, or 458 is activated. The output symbol stream 103, decoded from the receive vector 402, initially requires no synchronization logic; essentially, clock recovery methods can also be applied to the output symbol stream 103. For this purpose, the lowest error signal can be selectively used, in this case, the third error signal 458. Therefore, it is possible for the transmitter to periodically interrupt the third current loop control vector 113, inducing a clock signal in the third error signal 458.

[0075] Figure 10 shows a block diagram of a terminal unit 500. Terminal unit 500 receives a terminal vector 104 as input. Terminal vector 104 controls a terminal switch 502, causing a terminal resistor network 501 to be connected to the corresponding wires 201…207. Terminal switch 502 is configured to the corresponding nodes A…G in the diagram.

[0076] Figure 11 shows diagrams of different numbers of conductors in a multi-conductor system 200. For a 3-conductor system with N=3, a diagram with 3 nodes A, B, and C is used to detect the voltage levels AB, BC, and CA. In a multi-conductor system 200 with N=4, a diagram with 4 nodes A, B, C, and D is used, resulting in 7 voltage levels. In a multi-conductor system 200 with N=5, a diagram with 5 nodes A, B, C, D, and E is used, generating a total of 10 voltage levels AB, BC, CA… For a multi-conductor system 200 with N=7, 21 comparison points and 21 voltage levels are generated. Solid arrows between nodes represent closely adjacent 1D, dashed arrows represent intermediate adjacent 1D, and dotted arrows represent distant adjacent 3D.

[0077] Figure 12 shows a decoding table for one of the different multi-wire systems 200, extending to Figures 12A, 12B, 12C, and 12D. When establishing an iterative embodiment for decoding multi-wire systems of different designs, a table is generated, clearly showing that the diagrams of this invention cannot fit on a single page. The diagrams show the connections between the method steps. In this example, the diagrams need to fill four pages (12A, 12B, 12C, 12D). The four pages can be joined together to view the complete diagram.

[0078] The leftmost column displays the number of wires and the current in the system. For example, 3 wires with 1 current, or 4 wires with 1 current, or 4 wires with 2 current, or 7 wires with 1 current, or 7 wires with 3 current. The corresponding symbols that need to be decoded are also displayed in a column. According to the encoding and decoding indication principle, the block diagram in Figure 9 shows which step to perform as you move vertically.

[0079] Parameters, variations and performance

[0080] An important parameter of this invention is the number of conductors N in the multi-conductor system 200, and the number of current loops L that exist simultaneously. For example, see "4 conductors 2 current loops" on the far left of the column, which means N=4 and L=2. Accordingly, 4 conductors and 2 current loops are used. All accompanying figures take this parameter into consideration by indicating appropriate adjustments and showing examples based on specific parameters.

[0081] The symbol supply can be estimated by the degree of freedom in conductor selection. In a multi-conductor system 200 with N conductors, there are N×(N-1) possibilities for a first current loop 121, which is extracted from the transmitted symbol stream 102 by the symbol encoder 110 via a current loop control vector 111. The flow rate of the second current loop 122 can be selected in the same manner from a set of reduced N-2 conductors, such that there are (N-2)×(N-3) possibilities for the second current loop control vector 112. This current loop control vector 112 is also extracted from the transmitted symbol stream 102 by the symbol encoder 110. This approach can be continued for other current regions as long as the remaining conductor supply is sufficient.

[0082] This approach generates a total of N! / (N-2L)! symbols, representing how the L current loops can flow into N conductors. This is because, when current loops 121, 122, ..., 12x are implemented with strictly decreasing current intensities, complete information about which pair of forward and loop conductors the current flows through is contained in the receiving vector 402.

[0083] In a preferred embodiment, the symbol encoder 110 ensures at all times that each conductor 20x in the multi-conductor system is selected by at most one control block 300, excluding overlapping current loops 121, 122, ... 12X. This limits the voltage level in the multi-conductor system 200 to a maximum of 2×L+1 possibilities, which has a positive effect on interference resistance.

[0084] Encoding and decoding generally begin with the current loop 121 with the highest current and continue in a strictly current amplitude degradation manner 122…12X. In preferred embodiments, the power supply module 120 is appropriately adjusted to ensure this. With multiple current loops, the detected current paths can be correctly assigned even with level differences in the multi-wire system 200, further increasing information density. Decoding may also be performed with current loops of the same strength or overlapping, at the cost of reduced symbol supply.

[0085] Figure 13 shows the reduction of the received vector from an 8-wire system (N=8) to a 2-wire system (N=2). Figures 13A, 13B, and 13C should be referenced sequentially here. According to Figure 13A, starting from an 8-wire system (N=8), the diagrams A, B, C, D, E, F, G, and H are used. In the diagrams and in the multi-wire system 200, the minimum and maximum voltage levels are displayed using a discriminator. Assuming the symbol "CF" is transmitted, a maximum value is identified for C, and a minimum value is identified for F. After reducing N=8 to N=6, the identified nodes C and F are discarded.

[0086] Figure 13B illustrates further reduction. The current 6-wire system N=6 generates diagrams A, B, C, D, E, and F, and the maximum and minimum voltage levels MAX and MIN can be identified. Symbol transmission is then determined: node F (previously H) generates the maximum value MAX, and node D (previously E) generates the minimum value MIN. This produces the symbol "CFHE". The transition from a 6-wire system N=6 to a 4-wire system N=4, along with other reduction nodes D and F following this method, is discarded. The receive vector is reduced to the equivalent of a 4-wire system, represented by diagrams A, B, C, and D (see Figure 13C). Here, further symbols are decoded using minimum and maximum value identification, generating the complete receive symbol "CFHEBG". Finally, the 4-wire system N=4 is reduced to a 2-wire system N=2.

[0087] In summary, starting with an 8-wire system, the maximum-minimum pairings for each step are randomly selected in a demonstrative manner, and the reduction is performed three times. The wire mapping, that is, the sequential mapping of the larger wire systems at the nodes (wires) of each reduction wire system, is shown on the right side of the diagram. According to Figure 13A, wire-mapping diagram 603 shows the configuration of wires from N=8 to N=6. Reduction-mapping diagram 604 shows the bit and position configuration of receive vector 402 in receive vector 453.

[0088] In each step, in the complete diagram, each pair of wires is labeled as minimum (MIN) and maximum (MAX), while the edges of consecutive numbers (1 to 28) correspond to the bit digits on the right side of the decrement-mapping diagram 604. These two wires, as minimum (MIN) and maximum (MAX), are the decoder results of the identification examples in each step, which are now decremented by the received vector 402. Each box ("symbol") contains the identified symbol, which extends the newly identified wire pair in each step: N=8 in Figure 13A: "CF", N=6 in Figure 13B: "CFHE", and N=4 in Figure 13B: "CFHEBG".

[0089] The purpose of the reduction is to find a complete graph of size (N-2) again in the next decoding step of the symbol encoder 480, while maintaining the wire order of the corresponding wire-mapping graph 603, so that the entire program begins to iterate over the ever-shrinking "virtual" wire system. Each N wire corresponds to a node in the complete N-graph, and each bit of the received vector 402 corresponds to an edge between two nodes. Each step reduces the graph by 2 nodes, which is equivalent to the wire detected in this step being identified as a wire and a node, and the wire and node are identified by the minimum and maximum value detectors. All edges (bits) entering and leaving this node (wire) are eliminated. The affected wires and nodes in Figures 13A, B, and C are circled and marked with an x ​​to indicate that they have been eliminated and reduced.

[0090] The remaining bits and positions also appear in the new graph, and the corresponding wire-mapping graph 603 is configured with the bits and positions of the newly reduced receive vector 453 so that it correctly maps the original relationship of the output graph. It should be noted that when the wire sequence is swapped (edge ​​direction reversed), sometimes a reversal occurs. This happens, for example, when the receive vector 402 of an 8-wire system N=8, bit 23 ("GB") transitions to the receive vector 453 of a reduced 6-wire system N=6, bit 14 ("BE"). This is because the original mapping provides "GB" -> "EB", but the reduced graph provides the opposite edge direction "BE".

[0091] Based on this instruction, professionals can derive a digital circuit using familiar design methods, such as by using multiplexers and inverters to achieve the appropriate configuration.

[0092] Figure 14 shows a possible embodiment of a comparator. In a 4-wire system N=4, including Figures A, B, C, and D, there are six possibilities for generating six different measured voltage levels. Therefore, the six comparators must be integrated into a single circuit loop. These six comparators are represented by a comparator network 400. Voltage levels AB, BC, CA, ... are detected by the comparator network 400 between conductors 201, 202, 203, 204 and between nodes. The detected voltage levels AB, BC, CA, ... are assigned as elements to a receiver vector 402. The receiver vector 402 is constructed in such a way that, according to general practice, each conductor is scanned sequentially, and the relative relationships of the voltage circuits of the receiver vector 402 in the conductor system are also detected sequentially. This general practice can be, for example, based on graphical theory.

[0093] Each conductor represents a node, situated on a loop. In a 4-conductor system, there are nodes A, B, C, and D. Starting from node A, edges can be drawn between nodes in a clockwise direction. Upon returning to the starting node, diagonal or transverse lines can also be drawn as edges. Therefore, voltage levels are obtained between the nodes and conductors AB, BC, CD, DA, AC, and BD as edges. A possible receiving vector is as follows: Receive vector = (+1 volt, +2 volt, -1 volt, +1 volt, +1 volt, +1 volt)

[0094] A maximum and a minimum value are determined on the received vector using a simple AND connection. This maximum and minimum value detection can be performed via a simple AND loop. If a maximum value cannot be detected, a first error signal 452 is generated. Otherwise, the task proceeds; when an AND loop node signals, it indicates which wire has a maximum value. The same applies to the minimum value.

[0095] As shown in Figure 13, the reduction is illustrated in Figures 15 to 20, which are plots A, B, C, D, E, F, and G of a 7-wire system. The plot of a 7-wire system has 21 edges. This indicates that 21 voltage levels need to be evaluated. Through minimum-maximum-evaluation, a minimum and a maximum value can always be detected at the receiver vector 402.

[0096] Figure 15 shows a graph with 21 (0 to 20) connections 600, which are shown as edges in the graph and represent voltage levels. After the first reduction, Figure 16 shows the transition from a 7-wire system N=7 to a 5-wire system N=5. A configuration table 601, in which node mapping is performed, transforms the previously larger graph into the smaller, reduced graph, showing which nodes were deleted.

[0097] Next, Figure 17 shows a receive vector 402 reduced from a 7-wire system N=7 to a 5-wire system N=5. The reduced receive vector 453 is derived from receive vector 402. This is a reduction from 21 bits to 10 bits. This is shown in the vertical columns of the table in Figure 17. An edge BC in the 7-wire system becomes an edge A'B' in the 5-wire system. The reduction in Figure 18 produces a 5-wire system N=5; a minimum-maximum detection must also be performed here. This is shown in Figure 19, where a configuration table 602 (see Figure 20) shows the mapping from a 5-wire system N=5 to a 3-wire system N=3.

[0098] Figure 21 shows a transmitting unit TX, a receiving unit RX, and a terminal unit 500 combined in a transceiver circuit. This combination is implemented as a easily scalable IP block for a semiconductor device 50. An IP block is an intellectual property core or IP-core. In microelectronics, it represents a pre-built functional block (structural diagram or circuit design) that can be used in many aspects of chip design. This chip design implements the method steps of this invention. A distinction is made between software IP-cores and hardware IP-cores: Software IP-cores exist in source code form in a specific hardware data description language such as Verilog or VHTL. They can also exist as a list of networks already synthesized by the manufacturer, serving as an organizational description of the circuit diagram. In this case, it is called a vendor-IP-core. A hardware IP-core is a block with a completed design. Therefore, the user needs little or no modification to the IP and connects directly to a program. To protect process confidentiality, the hardware IP-core purchased by the user usually only has a black box description. The preferred IP-blocks are implemented using complementary metal-oxide (CMOS) semiconductor technology. CMOS stands for a semiconductor device in which P-channel and N-channel MOSFETs are applied to a common substrate.

[0099] Figure 22 shows another embodiment of the transceiver unit and transceiver circuit, and a semiconductor element 50. It can be used in a 4-wire system N=4 with one power supply, or in a 4-wire system N=4 with two power supplies, to support different current loops.

[0100] Figure 23 shows possible bus topologies. All bus topologies are shared, with at least two user terminals connected to a conductor system, particularly a multi-conductor system 200 (bus). Data transmission in this method and invention mostly uses a 3-wire system. There must be at least one user terminal as the transmitter and one resistor network as the receiver. This means that in the bus system, there must be at least one terminating resistor in the conductor system (bus), for example, as an intermediate termination (or as a Thevenin equivalent).

[0101] Figure 23 shows, from left to right, a 3-wire system, a 4-wire system, a 7-wire system, and finally a 3-wire system with an external terminal unit.

[0102] Figure 24 illustrates parallel operations using different conductor systems. This demonstrates that on a multi-conductor system with N=7 conductors, a 7-wire system, a 4-wire system, and a 3-wire system can be connected to corresponding transceivers. This is an example of user terminals with different numbers of conductors connected to a common conductor system (bus). Its advantage can be seen as a common conductor system (bus) divided into multiple smaller lower-level buses. User terminals can transmit simultaneously and without collisions on independent lower-level buses. A user terminal on a main bus can participate in all transmission paths, as well as in the transmission paths of lower-level buses.

[0103] Figure 25 illustrates a terminal operating in parallel, for example, a terminal may be segmented on a lower bus. A terminal operating on a main bus may also be an alternative to a separate terminal on the main bus, connected to the midpoint of a lower bus terminal (see dashed line).

[0104] Figure 26 shows a dynamic terminal. The terminal can also be integrated into the user terminal via the bus end resistor and is activated only when needed.

[0105] Figure 27 illustrates the hybrid operation of a known LVDS (Low Voltage Differential System) and the MLVDS (Multi-Wire Low Voltage Differential System) of this invention. The new semiconductor components can be integrated into existing LVDS connections. A transceiver can operate as an LVDS-RX receiver on any wire pair. Each current loop in the transceiver can be connected to an LVDS-TX transmitter unit.

[0106] This invention allows for the construction of a bus-capable multi-wire system for information transmission using simple and CMOS-integrable components, achieving signal fidelity characteristics and transmission rates similar to, for example, LVDS, while also providing clear and efficient information encoding with a low proportion of increased current consumption.

[0107] The following characteristics are important for this: - At any given time, there are only a few current loops of varying intensities in the conductor system. - Current loops clearly constitute the transmitting side by their relative current intensity relationship with each other, and can be identified on the receiving side. Based on this, individual conductors are selected for the forward conductors and loop conductors in each current loop for information encoding. - A receiver can identify each current loop and determine its direction through a fast iterative process. This can be achieved simply by performing a pure binary query using a comparator. - By using impedance-controlled and low-reflection wire guidance techniques and appropriate terminations, the transmission system can achieve the highest signaling efficiency with relatively low complexity and only moderate current consumption.

[0108] Other thinking methods and advantages are listed below: • In a multi-wire system (bus), at least 3 wires are used for data transmission. A star-shaped impedance (terminal) allows current to flow between all conductors. • A current is symmetrically supplied to the busbar through any two wires. • The potential difference of current can be detected between the conductors of the bus through the impedance of the terminal. Information is encoded in an ordered selection of wires. • The binary determinant between all conductors allows symbolic decoding based on conductor potential. • Having the same wire potential on two or more unused wires results in 0 or 1 on the corresponding determinant. Nevertheless, the sign remains clearly configurable. • When the conductors on the high and low sides are switched, the potential in the conductor system changes, and the receiving vector also changes. The receiving vector constitutes the decision state of the comparator. • By freely selecting from N and N-1 unused wires, N·(N-1) possible symbols are generated. • Each available wire pair can supply an additional current loop. • Using current of different intensities, a definite potential is also generated between the conductors of different currents. This allows for incremental encoding and decoding of multiple currents, each corresponding to the number of (still) available wires. This method allows for the encoding of a large amount of information on a small number of wires with relatively low energy consumption. Encoding and decoding are performed using pure digital data and simple circuits. • Multiple current loops of different strengths can be used to achieve both the use of different power supplies and the use of a common power supply to double the high-side and low-side transistors (Figure 21). • The transmitting unit (Tx), receiving unit (Rx), and terminal can be integrated into a single transceiver circuit loop. • Dynamically connect the terminal as needed to prevent the busbar from having low impedance. This enables easily scalable IP blocks for use in integrated circuits. • At least one terminal bus in the conductor system (busbar), for example as an intermediate terminal (Thevenin equivalent) Figure 26. • User terminals with different numbers of conductors operate in a common conductor system (bus) as shown in Figure 24. A common main conductor system (bus) is divided into multiple smaller lower busbars. • Clients on independent lower-level buses can send simultaneously without conflict. • The main bus user terminal can participate in all transmission paths (including lower-level buses). • Terminals can be segmented on lower-level busbars. • A self-contained terminal on the main bus can be an alternative to a separate terminal on the main bus, in such a way that the midpoint of the underlying bus terminal is connected (see dashed line) Figure 25, Figure 26. • The terminal can also be integrated into the user terminal and only activated when needed.

[0109] 1: First User Terminal 2: Second User Terminal 50: Semiconductor components 100: Transceiver 101: Control Signal 102: Send symbolic stream 103: Output symbol stream 104: Terminal Vector 111: Current loop control vector 112: Current loop control vector 120: Symbol Encoder 121: Current loop 122: Current loop 200: Multi-wire system 201,202,…207: Electrical wires 300: Control Block 301: Upper Control Block 302: Lower Control Block 303: Upper switch 304: Down switch 400: Comparator Network 402: Receive Vector 450: Symbol Decoder 451: First wire pairing information 452: Error signal 453: Decrease in the receive vector 454: Wire Pairing Information 455: Error signal 456: Decrease in the receive vector 457: Wire Pairing Information 458: Error signal 461: First Discriminator 462: Second Discriminator 463: Third Discriminator 471: First reducer 472: Second reducer 480: Symbol Encoder 500: Terminal Unit 501: Terminal power group network 502: Terminal Switch 600: Connection 601: Configuration Table 603: Conductor Mapping Diagram 604: Reduction Mapping Diagram A, B, C, D, E, F, G: Nodes A1, B1, C1, D1: Switches AB,CB,CA,CB,DB,AC: Voltage Levels HL: Forward Conductor I: Current I1, I2: Signal current Max: Maximum value Min: Minimum value P1, P2, P3: Series circuit Q: Power supply RL: Loop wire RX: Receiver Unit SK: Switch combination SP: Neutral Point Sym: Symbol TX: Transmitting Unit

Claims

1. A symbol transmission system for transmitting symbols between a first user terminal (1) and a second user terminal (2) via a common multi-wire system (200), the common multi-wire system (200) having a first electrical wire (201), a second electrical wire (202), and a third electrical wire (201, 202, ... 207), The first user terminal (1) includes a symbol encoder (110), a power module (120), and a control block (300). The control block (300) has an upper control block (301) and a lower control block (302). The upper control block (301) closes or opens an upper switch (303) to a first output of the power module (120), and the lower control block (302) closes or opens a second output of the power module (120). The upper switch (303) has at least three upper electronic switches (A1, B1, C1), and the lower switch ( 304) has at least three lower electronic switches (A2, B2, C2), and at least three series circuits (P1, P2, P3) formed by an upper electronic switch (A1, B1, C1) and a lower electronic switch (A2, B2, C2). Electrical wires (201, 202, 203) are connected between the upper electronic switch (A1, B1, C1) and the lower electronic switch (A2, B2, C2) in each series circuit (P1, P2, P3). A power supply module (120) is connected to each series circuit (P1, P2, P3). Its characteristic is that... The symbol encoder (110) provides a current loop-control vector (111) to the control block (300), and the control block (300) is designed to use the current loop-control vector (111), which has a switch combination (SK) for electronic switches (A1, B1, C1, A2, B2, C2), to switch the electronic switches (A1, B1, C1, A2, B2, C2) and allow current to flow into the connected wires (201, 202, ... 207). The symbol encoder (110) determines the current loop-control vector (111) by sequentially selecting a wire pair from the supply of electrical wires (201, 202, 203) of the multi-wire system (200), determining and encoding the symbol (Sym) to be transmitted, and a wire pair containing one of the electrical wires (201, 202, 203) serves as the forward current conductor (HL) flowing from the first user terminal (1) to the second user terminal (2), and contains electrical wires (201, 202, 203). In 203), another line serves as the current loop conductor (RL), and there is also a terminal unit (500). The symbol encoder (110) is designed to provide a terminal vector (104) to the terminal unit (500). The terminal unit (500) is designed to connect a terminal electrical network (501) to the electrical conductors (201, 202, 203) of the multi-conductor system (200) via a terminal switch (502). The second user terminal (2) has a comparator network (400).The comparator network (400) decodes the symbol (Sym) by detecting voltage levels (AB, BC, CA) between two electrical wires (201, 202, 203). The different voltage levels (AB, BC, CA) between the electrical wires (201, 202, 203) contain the encoded symbol (Sym).

2. The system of claim 1, wherein the symbol encoder (110) provides multiple current loop-control vectors (111, 112, 113, ... 11x), and the control block (300) operates a common multi-wire system (200) with multiple current loops (121, 122, ... 127).

3. The system as requested in item 2, wherein the control block (300) and / or power module (120) supplies each current loop (121, 122, ... 127) with different signal currents (I1, I2, ... Ix).

4. In any of the requests 1 to 3, the voltage levels (AB, BC, CA) detected by the comparator network (400) are assigned to a receiving vector (402) as elements.

5. The system of claim 4 has a symbol decoder (450) that receives a receive vector (402) and performs a maximum value determination and a minimum value determination on a cascaded sequence of elements of the receive vector (402), and provides a binary sequence (MAX, MIN) in which the positions of the maximum and minimum potentials are marked.

6. The system of claim 5, having a first discriminator (461), a second discriminator (462), a first decrementer (471), and a second decrementer (472), wherein the first discriminator (461) is designed as a Min-Max wire pair discriminator and receives a receive vector (402) to detect the wire pairs with the maximum and minimum relative potentials in the multi-wire system (200) and provides the detection result as first wire pairing information (451); the first discriminator (461) is connected to the first decrementer (471) and provides a decremented receive vector (453) with the first wire pairing information (451). The second discriminator (462) is designed as another maximum-minimum wire pair discriminator, receiving the decremented receiving vector (453) and detecting the wire pairs with the maximum and minimum relative potentials in the multi-wire system (200) with the already identified decremented wire pairs. In addition, it provides the detection result as second wire pairing information (454). The second discriminator (462) is connected to the second decrementer (472) and provides another decremented receiving vector (456) with the second wire pairing information (451).

7. A method for electronic symbol transmission, from a first user terminal (1) to a second user terminal (2), via a common multi-wire system (200) having at least a first conductor (201), a second conductor (202), and a third conductor (203), wherein - at least three series circuits (P1, P2, P3) are present at the first user terminal (1), each operated by an upper electronic switch (A1, B1, C1) and a lower electronic switch (A2, B2, C2), and conductors (201, 202, 203) are provided between the upper electronic switch (A1, B1, C1) and the lower electronic switch (A2, B2, C2) in each series circuit. The upper electronic switches (A1, B1, C1) switch to or from the first output wire (201, 202, 203) of the power supply (Q), and the lower electronic switches (A2, B2, C2) switch to or from the second output wire (201, 202, 203) of the power supply (Q). The characteristic feature is that a switch combination (SK) is selected from the electronic switches (A1, B1, C1, A2, B2, C2) to encode a wire selected sequentially from the wires (201, 202, 203) supplied by the multi-wire system (200), and a symbol (Sym) to be transmitted on that wire is encoded. Then, via the power supply (Q), a current (I) flows through a closed upper electronic switch (A1, B1, C1) from the first user terminal (1) through a wire (201, 202, 203) acting as a forward conductor (HL) into the multi-wire system (200). A terminating resistor network (501) is connected to the conductors (201, 202, 203) of the multi-conductor system (200), so that the current (I) flowing in the forward conductor (HL) flows through a current path (SW) to another conductor (201, 202, 203), and the other conductor (201, 202, 203) becomes the loop conductor (RL) of the current (I), which is used by the first user terminal (1) via a closed electronic switch (A2, B2, C2). In the second user terminal (2), in order to decode the symbol (Sym), the voltage levels (AB, BC, CA) between the two conductors (201, 202, 203) are detected, and the symbol (Sym) is recovered from the different voltage levels (AB, BC, CA) between the conductors (201, 202, 203).

8. The method of claim 7, wherein the common multi-wire system (200) operates with the number of wires (N) on the electrical wires (201, 202, ... 207), and the current loops (121, 122, ... 127) are formed between the first user terminal (1) and the second user terminal (2) by electronic switches (A1, B1, C1, A2, B2, C2), electrical wires (201, 202, ... 207), and terminating resistor network (501). In order to continue encoding the symbols (Sym) to be transmitted, the number (L) of selected current loops (121, 122, ... 127) is determined by the number of wires (N) on the electrical wires (201, 202, ... 20x), thereby improving the symbol supply.

9. As in request item 8, select a number (L) of individual current loops (121, 122, ... 127) to supply signal currents (I1, I2, ... Ix) of different amplitudes to improve the symbol supply.

10. The method of any of claims 7 to 9, wherein a comparator network (400) detects voltage levels (AB, BC, CA) between electrical conductors (201, 202, 203), and the detected voltage levels (AB, BC, CA) are assigned to a receiving vector (402) as elements.

11. The method of claim 10, wherein the receive vector (402) is directed to a symbol decoder (450) that performs a maximum value determination on one hand and a minimum value determination on the other hand on a sequence of elements of the receive vector (402), and provides a binary sequence (MAX, MIN) wherein the positions of the maximum and minimum potentials in the sequence are marked.

12. As in any of the requests 9 to 11, multiple current loops (121, 122, ... 127) between the first user terminal (1) and the second user terminal (2) have different signal currents (I1, I2, ... Ix) operating, and the symbol (Sym) encoding steps are as follows: a) First step, voltage levels (AB, BC, CA) are detected between the conductors (201, 202, 203) using a comparator network (400), and the detected voltage levels (AB, BC, CA) are assigned to a receiving vector (402) as elements; b) Second step, the receiving vector (402) is guided to a symbol decoder (450), which performs maximum value determination on one side and minimum value determination on the other side of an element sequence of the receiving vector (402), and provides binary sequences (MAX, MIN), the positions of the maximum and minimum potentials are marked in the sequence; c) In the third step, the receiving vector (402) is decremented for the position identified in the second step, resulting in a decremented receiving vector (453). The decremented receiving vector (402) continues in the first step until the decremented receiving vector (453) or another decremented receiving vector (456) corresponds to a multi-wire system (200) with a wire number N=3.

13. A semiconductor element (50) designed as a wire driver for symbol transmission between a first user terminal (1) and a second user terminal (2), the two user terminals being connected via a common multi-wire system (200) having at least one first electrical wire (201), one second electrical wire (202), and one third electrical wire (201, 202, ... 207), characterized in that its system is designed to implement the method according to any one of claims 7 to 12.

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