Driving circuit and driving method thereof

Abstract

A driving circuit for driving a synchronous rectified transistor includes a first comparator, a second comparator, a third comparator, and a gate driving circuit. When the voltage at the drain terminal of the synchronous rectified transistor is less than a first threshold value, the first comparator enables a first comparison signal. When the voltage at the drain terminal is not less than a second threshold value, the second comparator enables a second comparison signal. When the voltage at the drain terminal is not less than a third threshold value, the third comparator enables a third comparison signal. The gate driving circuit provides a gate voltage to the gate terminal of the synchronous rectified transistor based on the first, second, and third comparison signals.

Description

[Technical Field]

[0001] The present invention relates to a driving circuit and driving method for a synchronous rectifier transistor, and particularly to a driving circuit and driving method for a synchronous rectifier transistor capable of quickly turning off. [Previous Technology]

[0002] In traditional offline flyback converter circuits, diodes are typically used as rectifiers on the secondary side to transfer energy to the output capacitor. However, in high-power applications, diodes cause significant power losses and heat generation problems. To address these issues, synchronous rectifier transistors can be used to replace diodes. While synchronous rectifier transistors can improve conversion efficiency and thermal performance, synchronous rectification control methods are extremely challenging in isolated topologies because the primary-side signal cannot be directly transmitted to the synchronous rectifier controller. [Summary of the Invention]

[0003] This invention proposes a driving circuit and method for rapidly turning off a synchronous rectifier transistor. It utilizes a plurality of comparators to determine the voltage across the drain and source terminals of the synchronous rectifier transistor, gradually reducing the voltage across the gate and source terminals, thereby reducing the charge that needs to be removed when turning off the synchronous rectifier transistor. Furthermore, by using a plurality of comparators to gradually reduce the voltage across the gate and source terminals of the synchronous rectifier transistor, stability issues are eliminated, significantly reducing design complexity.

[0004] This invention provides a driving circuit for driving a synchronous rectified transistor. The driving circuit includes a first comparator, a second comparator, a third comparator, and a gate driving circuit. When the voltage at one drain terminal of the synchronous rectified transistor is less than a first threshold value, the first comparator enables a first comparison signal. When the voltage at the drain terminal of the synchronous rectified transistor is not less than a second threshold value, the second comparator enables a second comparison signal. When the voltage at the drain terminal of the synchronous rectified transistor is not less than a third threshold value, the third comparator enables a third comparison signal. The gate driving circuit provides a gate voltage to one gate terminal of the synchronous rectified transistor based on the first comparison signal, the second comparison signal, and the third comparison signal. The gate driving circuit turns on the synchronous rectified transistor based on the enabled first comparison signal. The gate driving circuit turns off the synchronous rectified transistor based on the enabled second comparison signal. The gate drive circuit described above increases the on-resistance of the synchronous rectifier transistor based on the enabled third comparison signal.

[0005] According to one embodiment of the present invention, the driving circuit further includes a flip-flop. The flip-flop includes a setting terminal, a reset terminal, and an output terminal. The setting terminal receives the first comparison signal, the reset terminal receives the second comparison signal, and the output terminal outputs an enable signal. The gate driving circuit further turns the synchronous rectifier transistor on or off based on the enable signal.

[0006] According to one embodiment of the present invention, the first threshold value, the second threshold value and the third threshold value are all less than zero.

[0007] According to one embodiment of the present invention, the second threshold value is greater than the third threshold value. The third threshold value is greater than the first threshold value.

[0008] According to one embodiment of the present invention, the driving circuit further includes a voltage adjustment device. The voltage adjustment device adjusts the gate voltage based on the third comparison signal. The gate driving circuit provides the gate voltage to the gate terminal to increase the on-resistance of the synchronous rectifier transistor.

[0009] According to one embodiment of the present invention, when the voltage at the drain terminal is less than a fourth threshold value, the third comparator disables the third comparison signal.

[0010] According to one embodiment of the present invention, the voltage adjustment device reduces the gate voltage based on the enabled third comparison signal. Alternatively, the voltage adjustment device maintains the gate voltage based on the disabled third comparison signal.

[0011] According to another embodiment of the present invention, the driving circuit further includes: a fourth comparator. When the voltage at the drain terminal is less than a fourth threshold value, the fourth comparator enables a fourth comparison signal.

[0012] According to one embodiment of the present invention, the voltage adjustment device reduces the gate voltage based on the enabled third comparison signal. The voltage adjustment device maintains the gate voltage based on the enabled fourth comparison signal.

[0013] According to one embodiment of the present invention, the fourth threshold value is less than zero. The third threshold value is greater than the fourth threshold value. The fourth threshold value is greater than the first threshold value.

[0014] According to one embodiment of the present invention, the above-mentioned synchronous rectifier transistor system is an N-type transistor. The gate voltage is reduced to increase the on-resistance of the above-mentioned synchronous rectifier transistor.

[0015] According to another embodiment of the present invention, the above-mentioned synchronous rectifier transistor system is a P-type transistor. The gate voltage is increased to increase the on-resistance of the above-mentioned synchronous rectifier transistor.

[0016] According to one embodiment of the present invention, the above-mentioned synchronous rectifier is used in a synchronous flyback voltage conversion circuit.

[0017] The present invention further proposes a driving method for driving a synchronous rectifier transistor. The driving method includes: detecting a drain voltage between the drain terminal and the source terminal of the synchronous rectifier transistor; determining whether the drain voltage is less than a first threshold value; when the drain voltage is less than the first threshold value, turning on the synchronous rectifier transistor; when the synchronous rectifier transistor is turned on, determining whether the drain voltage is less than a second threshold value; when the drain voltage is not less than the second threshold value, turning off the synchronous rectifier transistor; when the synchronous rectifier transistor is turned on, determining whether the drain voltage is less than a third threshold value; and when the drain voltage is not less than the third threshold value, increasing the on-resistance of the synchronous rectifier transistor.

[0018] According to one embodiment of the present invention, the first threshold value, the second threshold value and the third threshold value are all less than zero.

[0019] According to one embodiment of the present invention, the second threshold value is greater than the third threshold value. The third threshold value is greater than the first threshold value.

[0020] According to one embodiment of the present invention, the driving method further includes: after increasing the on-resistance of the synchronous rectifier transistor, determining whether the drain voltage is less than a fourth threshold value; and when the drain voltage is less than the fourth threshold value, maintaining the on-resistance of the synchronous rectifier transistor.

[0021] According to one embodiment of the present invention, the fourth threshold value is less than zero. The third threshold value is greater than the fourth threshold value. The fourth threshold value is greater than the first threshold value.

[0022] According to one embodiment of the present invention, the above-mentioned synchronous rectifier transistor system is an N-type transistor. The gate voltage supplied to one of the gate terminals of the above-mentioned synchronous rectifier transistor is reduced to increase the on-resistance of the above-mentioned synchronous rectifier transistor.

[0023] According to another embodiment of the present invention, the above-mentioned synchronous rectifier transistor system is a P-type transistor. An increased gate voltage is provided to one of the gate terminals of the above-mentioned synchronous rectifier transistor to increase the on-resistance of the above-mentioned synchronous rectifier transistor.

Implementation Method

[0025] The following description is an embodiment of this disclosure. Its purpose is to illustrate the general principles of this disclosure and should not be regarded as a limitation of this disclosure. The scope of this disclosure shall be defined by the claims.

[0026] It is worth noting that the following disclosure provides multiple embodiments or examples for practicing different features of this disclosure. The specific examples and arrangements of components described below are only used to briefly illustrate the spirit of this disclosure and are not intended to limit the scope of this disclosure. Furthermore, the same component symbols or words may be used repeatedly in multiple examples in the following description. However, the purpose of repetition is only to provide a simplified and clear explanation and is not intended to limit the relationship between the multiple embodiments and / or configurations discussed below.

[0027] Furthermore, the description in the following specification of a feature being connected to, coupled to, and / or formed on another feature may actually include multiple different embodiments, including the features being in direct contact, or including other additional features formed between the features, such that the features are not in direct contact.

[0028] Furthermore, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe the relative relationship of one element of the diagram to another element. It is understood that if the arrangement of the diagram is flipped so that it is upside down, the element described as being on the "lower" side will become the element on the "higher" side.

[0029] It is understood that although the terms "first," "second," "third," etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or portions. Therefore, a first element, component, region, layer, and / or portion discussed below may be referred to as a second element, component, region, layer, and / or portion without departing from the teachings of some embodiments disclosed herein.

[0030] Some embodiments disclosed herein can be understood in conjunction with the accompanying drawings, which are also considered part of the description of the embodiments disclosed herein. It should be understood that the drawings of the embodiments disclosed herein are not drawn to scale with actual devices and components. The shape and thickness of the embodiments may be exaggerated in the drawings to clearly show the features of the embodiments disclosed herein. Furthermore, the structures and devices in the drawings are drawn schematically to clearly show the features of the embodiments disclosed herein.

[0031] Here, the terms "about," "approximately," and "roughly" generally mean within 20%, more preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. The quantities given here are approximate quantities, that is, even without specific explanation of "about," "approximately," or "roughly," the meaning of "about," "approximately," or "roughly" may still be implied.

[0032] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of this disclosure, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of this disclosure.

[0033] In some embodiments disclosed herein, terms such as "connection" and "interconnection" used to refer to joining or connecting, unless otherwise defined, may refer to two structures being in direct contact, or to two structures not being in direct contact, wherein other structures are disposed between the two structures. Furthermore, these terms regarding joining or connecting may also include situations where both structures are movable or both structures are fixed.

[0034] In the diagram, similar elements and / or features may have the same element symbol. Various elements of the same type may be distinguished by adding letters or numbers after the element symbol to differentiate similar elements and / or similar features.

[0035] Figure 1 shows a circuit diagram of a synchronous flyback power conversion circuit according to one embodiment of the present invention. As shown in Figure 1, the synchronous flyback power conversion circuit 100 includes a transformer TM, a first transistor S1, a synchronous rectifier transistor S2, an output capacitor COUT, and a drive circuit 110. According to some embodiments of the present invention, this is described and explained using a synchronous flyback power conversion circuit, and is not intended to limit the invention in any way. According to other embodiments of the present invention, the synchronous flyback power conversion circuit may be replaced with other synchronous power conversion circuits.

[0036] According to one embodiment of the present invention, when the first transistor S1 is turned on, the input voltage VIN magnetizes the transformer TM to store energy. According to another embodiment of the present invention, when the first transistor S1 is turned off and the synchronous rectifier transistor S2 is turned on, the transformer TM demagnetizes and charges the output capacitor COUT, thereby generating the output voltage VOUT. The drive circuit 110 is used to control the synchronous rectifier transistor S2 to be turned on or off.

[0037] As shown in Figure 1, the drive circuit 110 includes a transconductance amplifier GM, a first comparator CMP1, and a drive switch SW. According to some embodiments of the present invention, the transconductance amplifier GM and the first comparator CMP1 are powered by a supply voltage VCC. The transconductance amplifier GM generates a gate voltage VG based on the difference between a first voltage V1 and a drain voltage VD, wherein the drain voltage VD is the voltage across the drain-source terminals of the synchronous rectifier transistor S2, and the gate voltage VG is the voltage across the gate-source terminals of the synchronous rectifier transistor S2. According to some embodiments of the present invention, here the drain voltage VD represents the voltage across the drain-source terminals of the synchronous rectifier transistor S2, and the gate voltage VG represents the voltage across the gate-source terminals of the synchronous rectifier transistor S2.

[0038] According to some embodiments of the present invention, the transconductance amplifier GM is used to adjust the gate voltage VG based on the difference between the drain voltage VD and the first voltage V1 to maintain the on-resistance of the synchronous rectifier transistor S2, such that the drain voltage VD is close to the first voltage V1. When the drain voltage VD exceeds the second voltage V2, the first comparator CMP1 enables the first comparison signal SC1 and turns on the drive switch SW, causing the drive switch SW to pull down the gate voltage VG to zero and turn off the synchronous rectifier transistor S2. According to some embodiments of the present invention, the first voltage V1 and the second voltage V2 are both less than zero. In other words, the first voltage V1 and the second voltage V2 are both negative values.

[0039] Figure 2 shows a waveform diagram of the drive circuit according to one embodiment of the present invention. The following description of the waveform 200 in Figure 2 will be provided in conjunction with the drive circuit 110 in Figure 1 for detailed explanation. As shown in Figure 1, when the transformer TM begins charging the output capacitor COUT and the synchronous rectifier transistor S2 is not yet turned on, the parasitic diode of the synchronous rectifier transistor S2 turns on first, causing the drain voltage VD to drop to a negative voltage. As shown in Figure 2, when the drain voltage VD is less than the initial voltage V0, the drive circuit 110 turns on the synchronous rectifier transistor S2 (not shown in Figure 1). According to one embodiment of the present invention, the initial voltage V0 is negative.

[0040] After the first time T1, the gate voltage VG exceeds the threshold voltage VTH of the synchronous rectifier S2, thus turning on the synchronous rectifier S2. In other words, the first time T1 is the turn-on delay time. When the drain voltage VD rises to the first voltage V1, the transconductance amplifier GM is used to reduce the gate voltage VG to increase the on-resistance of the synchronous rectifier S2, so that the drain voltage VD is maintained at the first voltage V1. As shown in Figure 2, the second time T2 is the time during which the transconductance amplifier GM drives the synchronous rectifier S2.

[0041] As the charging current of the transformer TM to the output capacitor COUT gradually decreases, the drain voltage VD rises. When the first comparator CMP1 determines that the drain voltage VD is not less than the second voltage V2, the first comparator CMP1 controls the drive switch SW to pull the gate voltage VG down to zero. As shown in Figure 2, when the gate voltage VG is less than the threshold voltage VTH of the synchronous rectifier transistor SW, the synchronous rectifier transistor S2 is turned off. The third time T3 is the turn-off delay time of the synchronous rectifier transistor S2.

[0042] According to some embodiments of the present invention, since the synchronous rectifier S2 gradually decreases during the second time T2, less charge needs to be removed when the drive switch SW turns off the synchronous rectifier S2, thereby achieving the effect of quickly turning off the synchronous rectifier S2. That is, shortening the third time T3. However, the synchronous rectifier S2 is controlled by the transconductance amplifier GM during the second time T2, thus having a stability problem. In order to simplify the design complexity, it is necessary to optimize the drive circuit 110.

[0043] Figure 3 shows a circuit diagram of a driving circuit according to another embodiment of the present invention. As shown in Figure 3, the driving circuit 300 is used to drive a synchronous rectified transistor S2, wherein the synchronous rectified transistor S2 corresponds to the synchronous rectified transistor S2 in Figure 1. The driving circuit 300 includes a second comparator CMP2, a third comparator CMP3, a fourth comparator CMP4, a flip-flop 310, a voltage adjustment device 320, and a gate driving circuit 330.

[0044] The second comparator CMP2 compares the third voltage V3 with the drain voltage VD of the synchronous rectifier transistor S2 to generate a second comparison signal SC2. According to one embodiment of the present invention, when the drain voltage VD is less than the third voltage V3, the second comparator CMP2 enables the second comparison signal SC2. According to another embodiment of the present invention, when the drain voltage VD is not less than the third voltage V3, the second comparator CMP2 disables the second comparison signal SC2.

[0045] The third comparator CMP3 compares the drain voltage VD of the synchronous rectifier transistor S2 with the fourth voltage V4 to generate a third comparison signal SC3. According to one embodiment of the present invention, when the drain voltage VD is not less than the fourth voltage V4, the third comparator CMP3 enables the third comparison signal SC3. According to another embodiment of the present invention, when the drain voltage VD is less than the fourth voltage V4, the third comparator CMP3 disables the third comparison signal SC3.

[0046] The fourth comparator CMP4 compares the drain voltage VD of the synchronous rectifier transistor S2 with the fifth voltage V5 to generate a fourth comparison signal SC4. According to one embodiment of the present invention, the fourth comparator CMP4 enables the fourth comparison signal SC4 when the drain voltage VD is not less than the fifth voltage V5. According to some embodiments of the present invention, the fourth comparator CMP4 has a hysteresis function, such that when the drain voltage VD is less than the sixth voltage V6, the fourth comparator CMP4 disables the fourth comparison signal SC4, wherein the sixth voltage V6 is less than the fifth voltage V5.

[0047] The flip-flop 310 includes a setting terminal S, a reset terminal R, and an output terminal Q. The setting terminal S receives a first comparison signal CMP1, the reset terminal R receives a second comparison signal CMP2, and the output terminal Q outputs an enable signal EN. According to one embodiment of the present invention, when the drain voltage VD is less than the third voltage V3, causing the second comparator CMP2 to enable the second comparison signal SC2, the flip-flop 310 enables the enable signal EN. According to another embodiment of the present invention, when the drain voltage VD is not less than the fourth voltage V4, causing the third comparator CMP3 to enable the third comparison signal SC3, the flip-flop 310 disables the enable signal EN.

[0048] The voltage adjustment device 320 generates an adjustment voltage VR based on the fourth comparison signal SC4. The gate drive circuit 330 generates a gate voltage VG based on the enable signal EN and the adjustment voltage VR. According to some embodiments of the present invention, the third voltage V3, the fourth voltage V4, the fifth voltage V5, and the sixth voltage V6 are negative values.

[0049] Figure 4 shows a waveform diagram of the drive circuit according to another embodiment of the present invention. The following description of the waveform diagram 400 in Figure 4 will be carried out in conjunction with the synchronous flyback power conversion circuit 100 in Figure 1 and the drive circuit 300 in Figure 3 for detailed explanation.

[0050] As shown in Figure 4, when the transformer TM starts charging the output capacitor COUT, the synchronous rectifier transistor S2 is not yet turned on. The parasitic diode of the synchronous rectifier transistor S2 turns on, causing the rectified current IR to continuously increase and the drain voltage VR to continuously decrease. When the second comparator CMP2 determines that the drain voltage VR is less than the third voltage V3, the flip-flop 310 enables the enable signal EN.

[0051] The gate drive circuit 330 turns on the synchronous rectifier transistor S2 at a first time point TP1 based on the enable signal EN. According to some embodiments of the present invention, when the gate drive circuit 330 turns on the synchronous rectifier transistor S2 at the first time point TP1, the synchronous rectifier transistor S2 is fully turned on. In other words, the gate voltage VG at the first time point TP1 is the maximum value of the adjustment voltage VR.

[0052] Between the first time point TP1 and the second time point TP2, as the rectified current IR gradually decreases, the drain voltage VD gradually increases and approaches zero. At the second time point TP2, the fourth comparator CMP4 determines that the drain voltage VD is not less than the fifth voltage V5 and enables the fourth comparison signal SC4. Based on the enabled fourth comparison signal SC4, the voltage adjustment device 320 reduces the adjustment voltage VR. The gate drive circuit 330 outputs the reduced adjustment voltage VR as the gate voltage VG.

[0053] At the third time point TP3, the fourth comparator CMP4 determines that the drain voltage VD is less than the sixth voltage V6 and disables the fourth comparison signal SC4. The voltage adjustment device 320 maintains the adjustment voltage VR based on the disabled fourth comparison signal SC4. According to some embodiments of the present invention, the drive circuit 300 is used to control the drain voltage VD between the fifth voltage V5 and the sixth voltage V6.

[0054] At the fourth time point TP4, the third comparator CMP3 determines that the drain voltage VD is not less than the fourth voltage V4 and enables the third comparison signal SC3. The flip-flop 310 disables the enable signal EN based on the enabled third comparison signal SC3. The gate drive circuit 330 pulls the gate voltage VG down to zero based on the disabled enable signal EN, thereby turning off the synchronous rectifier transistor S2.

[0055] According to some embodiments of the present invention, since the second comparison signal SC2, the third comparison signal SC3 and the fourth comparison signal SC4 are digital signals and the gate drive circuit 330 controls the gate voltage VG based on the digital signals, the drive circuit 300 does not need to consider the stability issue during the design process, thereby reducing the complexity of the drive circuit 300.

[0056] Figure 5 shows a circuit diagram of a driving circuit according to another embodiment of the present invention. Compared with the driving circuit 300 in Figure 3, the driving circuit 500 in Figure 5 further includes a fifth comparator CMP5, and the fourth comparator CMP4 of the driving circuit 500 does not have a hysteresis function.

[0057] According to one embodiment of the present invention, when the drain voltage VD is not less than the fifth voltage V5, the fourth comparator CMP4 enables the fourth comparison signal SC4. According to another embodiment of the present invention, when the drain voltage VD is less than the fifth voltage V5, the fourth comparator CMP4 disables the fourth comparison signal SC4.

[0058] The fifth comparator CMP5 compares the sixth voltage V6 with the drain voltage VD of the synchronous rectifier transistor S2 to generate a fifth comparison signal SC5. According to one embodiment of the present invention, when the drain voltage VD is less than the sixth voltage V6, the fifth comparator CMP5 enables the fifth comparison signal SC5. According to another embodiment of the present invention, when the drain voltage VD is not less than the sixth voltage V6, the fifth comparator CMP5 disables the fifth comparison signal SC5.

[0059] The voltage adjustment device 320 generates the adjustment voltage VR based on the fourth comparison signal SC4 and the fifth comparison signal SC5. Detailed operation of the drive circuit 500 will be explained in conjunction with Figure 4.

[0060] At the second time point TP2, the fourth comparator CMP4 determines that the drain voltage VD is not less than the fifth voltage V5, and enables the fourth comparison signal SC4. Based on the enabled fourth comparison signal SC4, the voltage adjustment device 320 reduces the adjustment voltage VR. At the third time point TP3, the fifth comparator CMP5 determines that the drain voltage VD is less than the sixth voltage V6, and enables the fifth comparison signal SC5. Based on the enabled fifth comparison signal SC5, the voltage adjustment device 320 maintains the adjustment voltage VR.

[0061] Figure 6 shows a flowchart of a driving method according to one embodiment of the present invention. The following description of the driving method 600 will be accompanied by the waveform diagram in Figure 4 for detailed explanation.

[0062] First, the drain voltage VD of the synchronous rectifier transistor S2 is detected (step S610). According to one embodiment of the present invention, as shown in Figures 3 and 5, the drain voltage VD is the voltage across the drain terminal to the source terminal of the synchronous rectifier transistor S2. Next, it is determined whether the drain voltage VD is lower than a first threshold value (step S620).

[0063] As shown in Figure 4, step S620 is used to determine whether the drain voltage VD is lower than the third voltage V3. According to some embodiments of the present invention, when the transformer TM begins to charge the output capacitor COUT and the synchronous rectifier transistor S2 has not yet been turned on, the parasitic diode of the synchronous rectifier transistor S2 is turned on to generate the rectified current IR shown in Figures 3 and 5. In other words, the first threshold value corresponds to the third voltage V3 in Figure 4.

[0064] When it is determined in step S620 that the drain voltage VD is less than the first threshold value (i.e., the third voltage V3 in Figure 4), the synchronous rectifier transistor S2 is turned on (step S630). When it is determined in step S620 that the drain voltage VD is not less than the first threshold value (i.e., the third voltage V3 in Figure 4), the process returns to step S610 and continues to monitor the drain voltage VD.

[0065] After the synchronous rectifier transistor S2 is turned on in step S630, it is determined whether the drain voltage VD is less than the second threshold value (step S640). When it is determined in step S640 that the drain voltage VD is not less than the second threshold value, the synchronous rectifier transistor S2 is turned off (step S690), and the driving method 600 ends. When it is determined in step S640 that the drain voltage VD is less than the second threshold value, it is determined whether the drain voltage VD is less than the third threshold value (step S650).

[0066] As shown in Figure 4, step S640 is used to determine whether the drain voltage VD is less than the fourth voltage V4. According to some embodiments of the present invention, when the drain voltage VD is not less than the fourth voltage V4, it means that the rectified current IR has dropped to a very low level, causing the drain voltage VD to approach zero. Therefore, when the determination is negative in step S640, the synchronous rectifier transistor S2 is turned off. In other words, the second threshold value corresponds to the fourth voltage V4 in Figure 4.

[0067] Furthermore, step S650 is used to determine whether the drain voltage VD is less than the fifth voltage V5. In other words, the third threshold value corresponds to the fifth voltage V5 in Figure 4. When step S650 determines that the drain voltage VD is not less than the third threshold value (i.e., the fifth voltage V5), the on-resistance of the synchronous rectifier S2 is increased (step S660). In the embodiment of Figures 3-5, the synchronous rectifier S2 is an N-type transistor, and reducing the gate voltage VG can increase the on-resistance of the synchronous rectifier S2.

[0068] According to other embodiments of the present invention, the synchronous rectifier S2 may also be a P-type transistor, wherein the source terminal of the synchronous rectifier S2 is coupled to the transformer TM, and the drain terminal of the synchronous rectifier S2 is coupled to the output voltage VOUT. Furthermore, increasing the gate voltage VG can increase the on-resistance of the P-type synchronous rectifier S2. In other words, regardless of whether the synchronous rectifier S2 is an N-type or P-type transistor, reducing the voltage across the gate and source terminals of the synchronous rectifier S2 helps to increase the on-resistance of the synchronous rectifier S2.

[0069] After step S660, it is determined whether the drain voltage VD is less than the fourth threshold value (step S670). As shown in Figure 4, it is determined whether the drain voltage VD is less than the sixth voltage V6. In other words, the fourth threshold value corresponds to the sixth voltage V6 in Figure 4. When it is determined in step S670 that the drain voltage VD is not less than the fourth threshold value (i.e., the sixth voltage V6), the process returns to step S660, and the on-resistance of the synchronous rectifier transistor S2 is increased. When it is determined in step S670 that the drain voltage VD is less than the fourth threshold value (i.e., the sixth voltage V6), the on-resistance of the synchronous rectifier transistor S2 is maintained (step S680).

[0070] Returning to step S650, when it is determined that the drain voltage VD is less than the third threshold value (i.e., the fifth voltage V5), step S680 is executed to maintain the on-resistance of the synchronous rectifier transistor S2. According to some embodiments of the present invention, maintaining the on-resistance of the synchronous rectifier transistor S2 is equivalent to maintaining the gate voltage VG. After step S680, returning to step S640, it is determined whether the drain voltage VD is less than the second threshold value.

[0071] According to some embodiments of the present invention, step S640 or S650 may be performed after step S630. In the embodiment of Figure 6, step S640 is described and explained as being performed after step S630, and is not limited thereto in any way.

[0072] This invention proposes a driving circuit and driving method for rapidly turning off a synchronous rectifier transistor. It utilizes a plurality of comparators to determine the voltage across the drain and source terminals of the synchronous rectifier transistor, gradually reducing the voltage across the gate and source terminals, thereby reducing the charge that needs to be removed when turning off the synchronous rectifier transistor. Furthermore, by using a plurality of comparators to gradually reduce the voltage across the gate and source terminals of the synchronous rectifier transistor, stability issues are eliminated, significantly reducing design complexity.

[0073] Although the embodiments and advantages of this disclosure have been disclosed above, it should be understood that anyone skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of this disclosure. Furthermore, the scope of protection of this disclosure is not limited to the processes, machines, manufacturing, material composition, apparatus, methods, and steps described in the specific embodiments of this specification. Anyone skilled in the art can understand from the disclosure of some embodiments of this disclosure the current or future development of processes, machines, manufacturing, material composition, apparatus, methods, and steps, as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein, and can be used according to some embodiments of this disclosure. Therefore, the scope of protection of this disclosure includes the aforementioned processes, machines, manufacturing, material composition, apparatus, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of this disclosure also includes combinations of various claim claims and embodiments. [Simplified Explanation of the Diagram]

[0024] Figure 1 shows a circuit diagram of a synchronous flyback power conversion circuit according to one embodiment of the present invention; Figure 2 shows a waveform diagram of a drive circuit according to one embodiment of the present invention; Figure 3 shows a circuit diagram of a drive circuit according to another embodiment of the present invention; Figure 4 shows a waveform diagram of a drive circuit according to another embodiment of the present invention; Figure 5 shows a circuit diagram of a drive circuit according to yet another embodiment of the present invention; and Figure 6 shows a flowchart of a drive method according to one embodiment of the present invention.

Claims

1. A driving circuit for driving a synchronous rectified transistor, comprising: A first comparator, wherein the first comparator enables a first comparison signal when the voltage at one drain terminal of the synchronous rectifier transistor is less than a first threshold value; a second comparator, wherein the second comparator enables a second comparison signal when the voltage at the drain terminal of the synchronous rectifier transistor is not less than a second threshold value; a third comparator, wherein the third comparator enables a third comparison signal when the voltage at the drain terminal of the synchronous rectifier transistor is not less than a third threshold value; and a gate drive circuit, based on the first comparison signal and the second comparator... The third comparator provides a gate voltage to one gate terminal of the synchronous rectifier transistor based on the first comparator signal and the third comparator signal mentioned above; wherein the gate drive circuit turns on the synchronous rectifier transistor based on the enabled first comparator signal; wherein the gate drive circuit turns off the synchronous rectifier transistor based on the enabled second comparator signal; wherein the gate drive circuit increases the on-resistance of the synchronous rectifier transistor based on the enabled third comparator signal; wherein when the voltage at the drain terminal is less than a fourth threshold value, the third comparator disables the third comparator signal.

2. The drive circuit of claim 1 further includes: A flip-flop includes a setting terminal, a reset terminal, and an output terminal; wherein the setting terminal receives the first comparison signal, the reset terminal receives the second comparison signal, and the output terminal outputs an enable signal; wherein the gate drive circuit further turns on or off the synchronous rectifier transistor based on the enable signal.

3. The drive circuit of claim 1, wherein the first threshold value, the second threshold value and the third threshold value are less than zero.

4. The drive circuit of claim 3, wherein the second threshold value is greater than the third threshold value; wherein the third threshold value is greater than the first threshold value.

5. The drive circuit of claim 1 further includes: A voltage adjustment device adjusts the gate voltage based on the third comparison signal; wherein the gate drive circuit provides the gate voltage to the gate terminal to increase the on-resistance of the synchronous rectifier transistor.

6. The drive circuit of claim 5, wherein the voltage adjustment device reduces the gate voltage based on the enabled third comparison signal; wherein the voltage adjustment device maintains the gate voltage based on the disabled third comparison signal.

7. The drive circuit of claim 5 further includes: A fourth comparator, wherein the fourth comparator enables a fourth comparison signal when the voltage at the drain terminal is less than a fourth threshold value.

8. The drive circuit of claim 7, wherein the voltage adjustment device reduces the gate voltage based on the enabled third comparison signal; wherein the voltage adjustment device maintains the gate voltage based on the enabled fourth comparison signal.

9. The drive circuit of claim 7, wherein the fourth threshold value is less than zero; wherein the third threshold value is greater than the fourth threshold value; wherein the fourth threshold value is greater than the first threshold value.

10. The drive circuit of claim 1, wherein the synchronous rectifier transistor system is an N-type transistor; wherein the gate voltage is reduced to increase the on-resistance of the synchronous rectifier transistor.

11. The driving circuit of claim 1, wherein the synchronous rectifier transistor system is a P-type transistor; wherein the gate voltage is increased to increase the on-resistance of the synchronous rectifier transistor.

12. The drive circuit of claim 1, wherein the aforementioned synchronous rectifier transistor system is used in a synchronous flyback voltage conversion circuit.

13. A driving method for driving a synchronous rectifier transistor, wherein the driving method comprises: The system detects the drain voltage from the drain terminal to the source terminal of the synchronous rectifier transistor; determines whether the drain voltage is less than a first threshold value; when the drain voltage is less than the first threshold value, turns on the synchronous rectifier transistor; when the synchronous rectifier transistor is turned on, determines whether the drain voltage is less than a second threshold value; when the drain voltage is not less than the second threshold value, turns off the synchronous rectifier transistor; when the synchronous rectifier transistor is turned on, determines whether the drain voltage is less than a third threshold value; when the drain voltage is not less than the third threshold value, increases the on-resistance of the synchronous rectifier transistor; after increasing the on-resistance of the synchronous rectifier transistor, determines whether the drain voltage is less than a fourth threshold value; and when the drain voltage is less than the fourth threshold value, maintains the on-resistance of the synchronous rectifier transistor.

14. The driving method of request item 13, wherein the first threshold value, the second threshold value and the third threshold value are less than zero.

15. The driving method of request item 13, wherein the second threshold value is greater than the third threshold value; wherein the third threshold value is greater than the first threshold value.

16. The driving method of request item 15, wherein the fourth threshold value is less than zero; wherein the third threshold value is greater than the fourth threshold value; wherein the fourth threshold value is greater than the first threshold value.

17. The driving method of claim 13, wherein the synchronous rectifier transistor system is an N-type transistor; wherein reducing one of the gate voltages supplied to the gate terminals of the synchronous rectifier transistor increases the on-resistance of the synchronous rectifier transistor.

18. The driving method of claim 13, wherein the synchronous rectifier transistor system is a P-type transistor; wherein an additional gate voltage is provided to the gate terminal of the synchronous rectifier transistor to increase the on-resistance of the synchronous rectifier transistor.

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