Semiconductor device and forming method of the same

Abstract

A semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, and a plurality of first P-type gallium nitride islands. The active layer includes an active region. The source electrode, drain electrode, and gate electrode are disposed on the active region of the active layer and extend in a first direction. The first P-type gallium nitride islands are disposed on the active region and below the drain electrode. The vertical projection of the drain electrode on the active region covers the entire vertical projection of each of the first P-type gallium nitride islands on the active region.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor device and a method for manufacturing the same. [Previous Technology]

[0002] Power semiconductor devices can be used as switches under high voltage conditions. However, with increasing usage, the on-resistance gradually increases. Therefore, providing a semiconductor device that can solve the above problem remains one of the most pressing research directions. [Summary of the Invention]

[0003] One embodiment of the present disclosure is a semiconductor device.

[0004] In one embodiment, the semiconductor assembly includes an active layer, a source electrode, a drain electrode, a gate electrode, and a plurality of first P-type gallium nitride islands. The active layer includes an active region. The source electrode, drain electrode, and gate electrode are disposed on the active region of the active layer and extend in a first direction. The first P-type gallium nitride islands are disposed on the active region and below the drain electrode. The vertical projection of the drain electrode on the active region covers the entire vertical projection of each of the first P-type gallium nitride islands on the active region.

[0005] In one embodiment, the first P-type gallium nitride islands are arranged along a first direction, and the sidewalls of each first P-type gallium nitride island are surrounded by a drain electrode.

[0006] In one embodiment, the semiconductor device further includes a plurality of field plates and a plurality of second P-type gallium nitride islands. The field plates are disposed between the source electrode and the drain electrode, and extend along a first direction. The second P-type gallium nitride islands are disposed on the active region and below the field plates.

[0007] In one embodiment, the second P-type gallium nitride islands are arranged in the first direction and the second direction.

[0008] In one embodiment, the gate electrode includes a gate P-type gallium nitride layer and a Schottky metal layer. The semiconductor device further includes a plurality of ohmic metal islands disposed between the gate P-type gallium nitride layer and the Schottky metal layer.

[0009] In one embodiment, the ohmic metal islands are arranged along a first direction.

[0010] In one embodiment, the material of the ohmic metal island is the same as the material of the source electrode and the drain electrode.

[0011] In one embodiment, the gate electrode includes a gate P-type gallium nitride layer and a Schottky metal layer disposed on the gate P-type gallium nitride layer.

[0012] In one embodiment, the semiconductor device further includes a first source metal layer and a first drain metal layer. The first source metal layer is disposed above the source electrode and the gate electrode, wherein the first source metal layer is electrically connected to the source electrode and extends in a first direction. The first drain metal layer is disposed above the drain electrode, wherein the first drain metal layer is electrically connected to the drain electrode and extends in a first direction.

[0013] In one embodiment, the semiconductor device further includes a second source metal layer, a second drain metal layer, a source pad, and a drain pad. The second source metal layer is disposed above the first source metal layer and the first drain metal layer, wherein the second source metal layer is electrically connected to the first source metal layer and extends in a second direction. The second drain metal layer is disposed above the first source metal layer and the first drain metal layer, wherein the second drain metal layer is electrically connected to the first drain metal layer and extends in a second direction. The source pad is disposed above the second source metal layer and the second drain metal layer, wherein the source pad is electrically connected to the second source metal layer. The drain pad is disposed above the second source metal layer and the second drain metal layer, wherein the drain pad is electrically connected to the second drain metal layer.

[0014] In one embodiment, the semiconductor device further includes a second source metal layer, a second drain metal layer, a source pad, and a drain pad. The second source metal layer is disposed above the first source metal layer, wherein the second source metal layer is electrically connected to the first source metal layer and extends in a first direction. The second drain metal layer is disposed above the first source metal layer, wherein the second drain metal layer is electrically connected to the first drain metal layer and extends in the first direction. The source pad is disposed above the second source metal layer and the second drain metal layer, wherein the source pad is electrically connected to the second source metal layer. The drain pad is disposed above the second source metal layer and the second drain metal layer, wherein the drain pad is electrically connected to the second drain metal layer.

[0015] In one embodiment, the semiconductor device further includes a source pad and a drain pad. The source pad is disposed above the first source metal layer and the first drain metal layer, wherein the source pad is electrically connected to the first source metal layer. The drain pad is disposed above the first source metal layer and the first drain metal layer, wherein the drain pad is electrically connected to the first drain metal layer.

[0016] One embodiment of the present disclosure is a semiconductor device.

[0017] In one embodiment, a semiconductor device includes an active layer, a source electrode, a drain electrode, a gate electrode, and a plurality of ohmic metal islands. The active layer includes an active region. The source electrode, drain electrode, and gate electrode are disposed on the active region of the active layer and extend in a first direction. The gate electrode includes a gate P-type gallium nitride layer and a Schottky metal layer. The ohmic metal islands are disposed between the gate P-type gallium nitride layer and the Schottky metal layer, wherein the material of the ohmic metal islands is the same as the material of the source electrode and the drain electrode.

[0018] In one embodiment, the ohmic metal islands are arranged along a first direction.

[0019] In one embodiment, the semiconductor device further includes a plurality of first P-type gallium nitride islands disposed on the active region and below the drain electrode. The vertical projection of the drain electrode onto the active region covers the entire vertical projection of each of the first P-type gallium nitride islands onto the active region. The first P-type gallium nitride islands are arranged in a first direction, and the sidewalls of each of the first P-type gallium nitride islands are surrounded by the drain electrode.

[0020] In one embodiment, the semiconductor device further includes a plurality of field plates and a plurality of second P-type gallium nitride islands. The field plates are disposed between a source electrode and a drain electrode, wherein the field plates extend along a first direction. The second P-type gallium nitride islands are disposed in the active region and below the field plates, wherein the second P-type gallium nitride islands are arranged in the first direction and the second direction.

[0021] One embodiment of the present invention is a method for manufacturing a semiconductor device.

[0022] In one embodiment, a method of manufacturing a semiconductor device includes simultaneously forming a gate P-type gallium nitride layer, a plurality of first P-type gallium nitride islands, and a plurality of second P-type gallium nitride islands on an active layer, wherein the gate P-type gallium nitride layer extends along a first direction; simultaneously forming a drain electrode, a source electrode, and a plurality of ohmic metal islands, wherein the source electrode is disposed on the active layer, the drain electrode covers the first P-type gallium nitride islands, and the ohmic metal islands are disposed on the gate P-type gallium nitride layer; and forming a plurality of field plates disposed on the second P-type gallium nitride islands.

[0023] In one embodiment, the method of manufacturing a semiconductor device further includes performing an annealing process on the ohmic metal islands after forming them.

[0024] In one embodiment, the source electrode and the drain electrode extend along a first direction, and the ohmic metal islands are arranged along the first direction.

[0025] In one embodiment, a first P-type gallium nitride island extends along a first direction, and a second P-type gallium nitride island extends along both the first and second directions.

[0026] In one embodiment, the method of manufacturing a semiconductor device further includes forming a first source metal layer disposed above a source electrode and a gate electrode, wherein the first source metal layer is electrically connected to the source electrode and extends in a first direction; and forming a first drain metal layer disposed above a drain electrode, wherein the first drain metal layer is electrically connected to the drain electrode and extends in a first direction.

[0027] In one embodiment, the method of manufacturing a semiconductor device further includes forming a second source metal layer disposed above a first source metal layer and a first drain metal layer, wherein the second source metal layer is electrically connected to the first source metal layer; forming a second drain metal layer disposed above the first source metal layer and the first drain metal layer, wherein the second drain metal layer is electrically connected to the first drain metal layer; forming a source pad disposed above the second source metal layer and the second drain metal layer, wherein the source pad is electrically connected to the second source metal layer; and forming a drain pad disposed above the second source metal layer and the second drain metal layer, wherein the drain pad is electrically connected to the second drain metal layer.

[0028] In the above embodiments, a first P-type gallium nitride island serves as a hole injection layer to neutralize trapped charges in the region below and around the drain electrode, as well as at the interface between the first P-type gallium nitride island and its underlying layer. A second P-type gallium nitride island serves as a hole injection layer to neutralize trapped charges in the region below and around the field plate. An ohmic metal layer serves as a hole injection layer to neutralize trapped charges in the region below and around the gate electrode. Therefore, the semiconductor device disclosed herein can reduce on-resistance by providing a first P-type gallium nitride island below the drain electrode, providing a second P-type gallium nitride island below the field plate, and providing an ohmic metal layer between the gate P-type gallium nitride layer and the metal layer of the gate electrode.

Implementation Method

[0030] Several embodiments of the present invention will be disclosed below with reference to the drawings. For clarity, many practical details will be described in the following description. However, it should be understood that these practical details should not be used to limit the present invention.

[0031] Figure 1 is a top view of a semiconductor device 10 according to some embodiments of the present disclosure. Figure 2A is a cross-sectional view along line 2A-2A of Figure 1. The semiconductor device 10 includes an active layer 110, a source electrode 120, a drain electrode 130, a gate electrode 140, a plurality of first P-type gallium nitride islands 150, a plurality of second P-type gallium nitride islands 160, a plurality of ohmic metal islands 170, and a plurality of field plates 180.

[0032] Referring to Figures 1 and 2A. The active layer 110 includes a channel layer 116 and a barrier layer 118 disposed on the channel layer 116. The barrier layer 118 may be made of GaN (or AlGaN or other III-V group materials). The active layer 110 also includes an insulating region 114 surrounding the active region 112. The insulating region 114 may be shallow trench isolation (STI). The active layer 110 may be selectively disposed on the substrate 100.

[0033] Referring to Figures 1 and 2A. A source electrode 120, a drain electrode 130, and a gate electrode 140 are disposed on the active region 112 of the active layer 110 and extend along a first direction D1. The semiconductor device 10 also includes a plurality of metal layers 200. The metal layers 200 include a first source metal layer 210 disposed above the source electrode 120 and the gate electrode 140, a first drain metal layer 220 disposed above the drain electrode 130, and a second source metal layer 230 disposed above the first source metal layer 210. A second drain metal layer 240, a source pad 250, and a drain pad 260 are disposed above the first source metal layer 210 and the first drain metal layer 220.

[0034] The first source metal layer 210 is electrically connected to the source electrode 120. The first drain metal layer 220 is electrically connected to the drain electrode 130. The second source metal layer 230 is electrically connected to the first source metal layer 210. The second drain metal layer 240 is electrically connected to the first drain metal layer 220. The source pad 250 is electrically connected to the second source metal layer 230, and the drain pad 260 is electrically connected to the second drain metal layer 240.

[0035] In this embodiment, the first source metal layer 210 and the first drain metal layer 220 extend along a first direction D1. The second source metal layer 230 and the second drain metal layer 240 extend along a second direction D2. The source pad 250 includes a main body portion 252 extending along the first direction D1 and a plurality of branch portions 254 extending along the second direction D2. The drain pad 260 includes a main body portion 262 extending along the first direction D1 and a plurality of branch portions 264 extending along the second direction D2.

[0036] Figure 3A is a top view of the semiconductor device 10, omitting the second source metal layer 230, the second drain metal layer 240, the source pad 250, and the drain pad 260. Referring to Figures 2A and 3A, a first P-type gallium nitride island 150 is disposed on the active region 112 and below the drain electrode 130. The first P-type gallium nitride islands 150 are arranged along a first direction D1, and the sidewalls of each first P-type gallium nitride island 150 are surrounded by the drain electrode 130. The vertical projection of the drain electrode 130 onto the active region 112 covers the entire vertical projection of each first P-type gallium nitride island 150 onto the active region 112.

[0037] After use, charge is trapped in the area below and around the drain electrode 130 and at the interface between the first P-type gallium nitride island 150 and the barrier layer 118, thus increasing the on-resistance of the semiconductor device 10. The first P-type gallium nitride island 150 serves as a hole injection layer to neutralize the trapped charge in the aforementioned area. Therefore, the on-resistance can be reduced by positioning the first P-type gallium nitride island 150 between the active layer 110 and the drain electrode 130.

[0038] Referring to Figures 2A and 3A. Multiple field plates 180 are disposed between the source electrode 120 and the drain electrode 130 and on the active region 112. A second p-type gallium nitride island 160 is disposed in the active region 112 and located below the field plates 180.

[0039] Referring to Figures 2A and 3A. Field plate 180 includes a second field plate 184 with the same metal as the Schottky metal layer 144 of the gate electrode 140, a first field plate 182 covered by the second field plate 184, and a third field plate 186 covering the first field plate 182 and the second field plate 184.

[0040] Referring to Figures 2A and 3A. The second P-type gallium nitride island 160 includes a first pillar 162, a second pillar 164, a third pillar 166, and a fourth pillar 168. The first pillar 162 is located between the gate electrode 140 and the second pillar 164. The first pillar 162 overlaps with the edge of the first field plate 182. The second pillar 164 is located between the first pillar 162 and the third pillar 166. The second pillar 164 overlaps with the edge of the second field plate 184. The third pillar 166 is located between the second pillar 164 and the fourth pillar 168. The third pillar 166 overlaps with the edge of the third field plate 186. The fourth pillar 168 is located between the third pillar 166 and the first P-type gallium nitride island 150. The fourth pillar 168 overlaps with the edge of the first source metal layer 210.

[0041] The second P-type gallium nitride island 160 serves as a hole injection layer to neutralize trapped charges in the region below and around the field plate 180. Therefore, the on-resistance can be reduced by disposing the second P-type gallium nitride island 160 between the active layer 110 and the field plate 180.

[0042] The gate electrode 140 includes a gate P-type gallium nitride layer 142 and a Schottky metal layer 144 located above the gate P-type gallium nitride layer 142. The gate P-type gallium nitride layer 142 and the Schottky metal layer 144 extend along a first direction D1. Ohmic metal islands 170 are disposed between the gate P-type gallium nitride layer 142 and the Schottky metal layer 144 and are arranged along the first direction D1. The material of the ohmic metal islands 170 is the same as the material of the drain electrode 130 and the source electrode 120.

[0043] The ohmic metal island 170 serves as a hole injection layer to neutralize the trapped charge in the area below and around the gate electrode 140. Therefore, the on-resistance can be reduced by disposing the ohmic metal island 170 between the gate P-type gallium nitride layer 142 and the Schottky metal layer 144 of the gate electrode 140.

[0044] The semiconductor device 10 further includes a dielectric layer 270. The dielectric layer 270 covers the second source metal layer 230 and the second drain metal layer 240. Source pads 250 and drain pads 260 are disposed on the dielectric layer 270. The source pad 250 is electrically connected to the second source metal layer 230 through a via 256 disposed in the dielectric layer 270. The drain pad 260 is electrically connected to the second drain metal layer 240 through a via 266 disposed in the dielectric layer 270.

[0045] The semiconductor device 10 further includes dielectric layers 280 and 290. For clarity, dielectric layers 280 and 290 are shown only in Figure 2A. Dielectric layer 280 is disposed on active layer 110. Dielectric layer 280 covers source electrode 120, drain electrode 130, and gate electrode 140. A first source metal layer 210 is disposed on dielectric layer 280 and covers source electrode 120 and / or gate electrode 140, and a first drain metal layer 220 is disposed on dielectric layer 280 and covers drain electrode 130.

[0046] Dielectric layer 290 covers the first source metal layer 210 and the first drain metal layer 220. In other words, the first source metal layer 210 and the first drain metal layer 220 are disposed between dielectric layers 290 and 280, and the second source metal layer 230 and the second drain metal layer 240 are disposed between dielectric layers 290 and 270.

[0047] A second source metal layer 230 is disposed on the dielectric layer 290 and electrically connected to the first source metal layer 210 through a via 232 disposed in the dielectric layer 290. A second drain metal layer 240 is disposed on the dielectric layer 290 and electrically connected to the first drain metal layer 220 through a via 242 disposed in the dielectric layer 290.

[0048] Figure 2B is a cross-sectional view of a semiconductor device 10a according to another embodiment of the present disclosure. Figure 3B is a top view of the semiconductor device 10a in Figure 2B, omitting the second source metal layer 230, the second drain metal layer 240, the source pad 250, and the drain pad 260. In this embodiment, an ohmic metal layer 170a is disposed on the gate P-type gallium nitride layer 142. The ohmic metal layer 170a extends along a first direction D1. This embodiment does not include a Schottky metal layer 144.

[0049] Figure 4A is a top view of a semiconductor device 10b according to another embodiment of the present disclosure. Figure 5A is a cross-sectional view along line segment 5A-5A of Figure 4A. Referring to Figures 4A and 5A, the semiconductor device 10a is similar to the semiconductor device 10 of Figures 1 to 3A, except for the arrangement of the metal layers 200a. The first source metal layer 210a, the first drain metal layer 220a, the second source metal layer 230a, and the second drain metal layer 240a extend along a first direction D1. The main body portion 252a of the source pad 250a and the main body portion 262a of the drain pad 260a extend along a second direction D2. The branch portion 254a of the source pad 250a and the branch portion 264a of the drain pad 260a extend along the first direction D1. The semiconductor device 10a has the same advantages as the semiconductor device 10, and therefore will not be described again.

[0050] Figure 4B is a top view of a semiconductor device 10c according to another embodiment of the present disclosure. Figure 5B is a cross-sectional view along line segment 5B-5B of Figure 4B. Semiconductor device 10c is similar to semiconductor device 10b, except that semiconductor device 10c does not have the second source metal layer 230a and the second drain metal layer 240a shown in Figures 4A and 5A.

[0051] Figure 6 is a cross-sectional view of an intermediate stage of a method for forming a semiconductor device according to an embodiment of the present invention. Figure 7 is a top view of Figure 6. Referring to Figures 6 and 7, the method for forming a semiconductor device firstly forms a gate P-type gallium nitride layer 142, a first P-type gallium nitride island 150, and a second P-type gallium nitride island 160 simultaneously on an active layer 110. Specifically, this step is to define all the P-type gallium nitride layers by patterning. In this way, the gate P-type gallium nitride layer 142 is defined to extend along a first direction D1. The first P-type gallium nitride island 150 is defined to be arranged along the first direction D1. The second P-type gallium nitride island 160 is defined to be arranged along the first direction D1 and the second direction D2.

[0052] Figure 8 is a cross-sectional view of an intermediate stage of a method for forming a semiconductor device according to an embodiment of the present invention. Figure 9 is a top view of Figure 8. Referring to Figures 8 and 9, the formation method proceeds to simultaneously form a drain electrode 130, a source electrode 120, and a plurality of ohmic metal islands 170. Specifically, this step involves patterning to define all the layers made of ohmic metals.

[0053] The drain electrode 130 is defined as extending along the first direction D1 and covering the first P-type gallium nitride island 150. The ohmic metal island 170 is defined as disposed on the gate P-type gallium nitride layer 142 and arranged along the first direction D1. After forming the drain electrode 130, the source electrode 120, and the ohmic metal island 170, an annealing process is performed on them. The ohmic metal island 170 becomes a half-ohmic region that can serve as a hole injection layer.

[0054] Figure 10 is a cross-sectional view of an intermediate stage of a method for forming a semiconductor device according to an embodiment of the present invention. Figure 11 is a top view of Figure 10. Referring to Figures 10 and 11, the formation method continues to form a first field plate 182 such that the edge of the first field plate 182 overlaps with the first pillar 162 of the second P-type gallium nitride island 160.

[0055] Figure 12 is a cross-sectional view of an intermediate stage of a method for forming a semiconductor device according to an embodiment of the present invention. Figure 13 is a top view of Figure 12. Referring to Figures 12 and 13, the formation method proceeds to form a second field plate 184 and a Schottky metal layer 144. The Schottky metal layer 144 extends along a first direction D1 and covers a gate P-type gallium nitride layer 142 and an ohmic metal island 170. The edge of the second field plate 184 overlaps with the second pillar 164 of the second P-type gallium nitride island 160.

[0056] The forming method further continues to form a third field plate 186, such that the edge of the third field plate 186 overlaps with the third pillar 166 of the second P-type gallium nitride island 160.

[0057] Figure 14 is a cross-sectional view of an intermediate stage of a method for forming a semiconductor device according to an embodiment of the present disclosure. The method proceeds to form a first source metal layer 210 and a first drain metal layer 220, such that the edge of the first source metal layer 210 overlaps with the fourth pillar 168 of the second P-type gallium nitride island 160.

[0058] In summary, the first P-type gallium nitride island serves as a hole injection layer to neutralize trapped charges in the region below and around the drain electrode, as well as at the interface between the first P-type gallium nitride island and its underlying layer. The second P-type gallium nitride island serves as a hole injection layer to neutralize trapped charges in the region below and around the field plate. An ohmic metal layer serves as a hole injection layer to neutralize trapped charges in the region below and around the gate electrode. Therefore, the semiconductor device disclosed herein can reduce on-resistance by providing a first P-type gallium nitride island below the drain electrode, providing a second P-type gallium nitride island below the field plate, and providing an ohmic metal layer between the gate P-type gallium nitride layer and the metal layer of the gate electrode.

[0059] Although the present invention has been disclosed above by way of embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims. [Simplified Explanation of the Diagram]

[0029] Figure 1 is a top view of a semiconductor device according to an embodiment of the present invention. Figure 2A is a cross-sectional view along line segment 2A-2A of Figure 1. Figure 2B is a cross-sectional view of a semiconductor element according to another embodiment of the present disclosure. Figure 3A is a top view of a semiconductor device omitting the second source metal layer, the second drain metal layer, the source pad, and the drain pad. Figure 3B is a top view of the semiconductor device in Figure 2B omitting the second source metal layer, the second drain metal layer, the source pad, and the drain pad. Figure 4A is a top view of a semiconductor device according to another embodiment of the present disclosure. Figure 4B is a top view of a semiconductor device according to another embodiment of the present disclosure. Figure 5A is a cross-sectional view along line segment 5A-5A of Figure 4A. Figure 5B is a cross-sectional view along line segment 5B-5B of Figure 4B. Figure 6 is a cross-sectional view of an intermediate stage of a method for forming a semiconductor device according to an embodiment of the present invention. Figure 7 is a top view of Figure 6. Figure 8 is a cross-sectional view of an intermediate stage in a method for forming a semiconductor device according to an embodiment of the present invention. Figure 9 is a top view of Figure 8. Figure 10 is a cross-sectional view of an intermediate stage in a method for forming a semiconductor device according to an embodiment of the present invention. Figure 11 is a top view of Figure 10. Figure 12 is a cross-sectional view of an intermediate stage in a method for forming a semiconductor device according to an embodiment of the present invention. Figure 13 is a top view of Figure 12. Figure 14 is a cross-sectional view of an intermediate stage in a method for forming a semiconductor device according to an embodiment of the present invention.

Claims

1. A semiconductor device comprising: an active layer including an active region; a source electrode, a drain electrode, and a gate electrode disposed on the active region of the active layer and extending in a first direction; and a plurality of first P-type gallium nitride islands disposed on the active region and below the drain electrode, wherein the vertical projection of the drain electrode on the active region covers the entire vertical projection of each of the first P-type gallium nitride islands on the active region, and one sidewall of each of the first P-type gallium nitride islands is completely covered and surrounded by the drain electrode.

2. The semiconductor device as claimed in claim 1, wherein the first P-type gallium nitride islands are arranged along the first direction.

3. The semiconductor device as claimed in claim 1, further comprising: a plurality of field plates disposed between the source electrode and the drain electrode, wherein the field plates extend along the first direction; and a plurality of second P-type gallium nitride islands disposed on the active region and below the field plates.

4. The semiconductor device as claimed in claim 3, wherein the second P-type gallium nitride islands are arranged in the first direction and a second direction.

5. The semiconductor device as claimed in claim 1, wherein the gate electrode comprises a gate P-type gallium nitride layer and a Schottky metal layer, and the semiconductor device further comprises: a plurality of ohmic metal islands disposed between the gate P-type gallium nitride layer and the Schottky metal layer.

6. The semiconductor device as claimed in claim 5, wherein the ohmic metal islands are arranged along the first direction.

7. The semiconductor device as claimed in claim 5, wherein the material of the ohmic metal islands is the same as the material of the source electrode and the drain electrode.

8. The semiconductor device as claimed in claim 1, wherein the gate electrode comprises a gate P-type gallium nitride layer and a Schottky metal layer disposed on the gate P-type gallium nitride layer.

9. The semiconductor device as claimed in claim 1, further comprising: a first source metal layer disposed on the source electrode and the gate electrode, wherein the first source metal layer is electrically connected to the source electrode and extends in the first direction; and a first drain metal layer disposed on the drain electrode, wherein the first drain metal layer is electrically connected to the drain electrode and extends in the first direction.

10. The semiconductor device of claim 9, further comprising: a second source metal layer disposed above the first source metal layer and the first drain metal layer, wherein the second source metal layer is electrically connected to the first source metal layer and extends in a second direction; a second drain metal layer disposed above the first source metal layer and the first drain metal layer, wherein the second drain metal layer is electrically connected to the first drain metal layer and extends in the second direction; a source pad disposed above the second source metal layer and the second drain metal layer, wherein the source pad is electrically connected to the second source metal layer; and a drain pad disposed above the second source metal layer and the second drain metal layer, wherein the drain pad is electrically connected to the second drain metal layer.

11. The semiconductor device of claim 9, further comprising: a second source metal layer disposed above the first source metal layer, wherein the second source metal layer is electrically connected to the first source metal layer and extends in the first direction; a second drain metal layer disposed above the first drain metal layer, wherein the second drain metal layer is electrically connected to the first drain metal layer and extends in the first direction; a source pad disposed above the second source metal layer and the second drain metal layer, wherein the source pad is electrically connected to the second source metal layer; and a drain pad disposed above the second source metal layer and the second drain metal layer, wherein the drain pad is electrically connected to the second drain metal layer.

12. The semiconductor device as claimed in claim 9 further comprises: a source pad disposed above the first source metal layer and the first drain metal layer, wherein the source pad is electrically connected to the first source metal layer; and a drain pad disposed above the first source metal layer and the first drain metal layer, wherein the drain pad is electrically connected to the first drain metal layer.

13. A semiconductor device, further comprising: an active layer including an active region; a source electrode, a drain electrode, and a gate electrode disposed on the active region of the active layer and extending in a first direction, wherein the gate electrode includes a gate P-type gallium nitride layer and a Schottky metal layer; a plurality of ohmic metal islands disposed between the gate P-type gallium nitride layer and the Schottky metal layer, wherein the ohmic metal islands are made of the same material as the source electrode and the drain electrode; and a plurality of first P-type gallium nitride islands disposed on the active region and below the drain electrode, wherein the vertical projection of the drain electrode on the active region covers the entire vertical projection of each of the first P-type gallium nitride islands on the active region, and one sidewall of each of the first P-type gallium nitride islands is completely covered and surrounded by the drain electrode.

14. The semiconductor device as claimed in claim 13, wherein the ohmic metal islands are arranged along the first direction.

15. The semiconductor device as claimed in claim 13, wherein the first P-type gallium nitride islands are arranged in the first direction.

16. The semiconductor device of claim 13, further comprising: a plurality of field plates disposed between the source electrode and the drain electrode, wherein the field plates extend along the first direction; and a plurality of second P-type gallium nitride islands disposed in the active region and below the field plates, wherein the second P-type gallium nitride islands are arranged in the first direction and a second direction.

17. A method of manufacturing a semiconductor device, comprising: simultaneously forming a gate P-type gallium nitride layer with a gate electrode, a plurality of first P-type gallium nitride islands, and a plurality of second P-type gallium nitride islands on an active layer, wherein the gate P-type gallium nitride layer extends along a first direction; simultaneously forming a drain electrode, a source electrode, and a plurality of ohmic metal islands, wherein the source electrode is disposed on the active layer, the vertical projection of the drain electrode on the active layer covers the entire vertical projection of each of the first P-type gallium nitride islands on the active layer, the drain electrode completely covers one sidewall surrounding the first P-type gallium nitride islands, and the ohmic metal islands are disposed on the gate P-type gallium nitride layer; and forming a plurality of field plates disposed on the second P-type gallium nitride islands.

18. The method of manufacturing a semiconductor device as claimed in claim 17 further comprises: performing an annealing process on the ohmic metal islands after forming them.

19. A method of manufacturing a semiconductor device as claimed in claim 17, wherein the source electrode and the drain electrode extend along the first direction, and the ohmic metal islands are arranged along the first direction.

20. A method of manufacturing a semiconductor device as claimed in claim 17, wherein the first P-type gallium nitride islands extend along the first direction, and the second P-type gallium nitride islands extend along the first direction and a second direction.

21. The method of manufacturing a semiconductor device as claimed in claim 17, further comprising: forming a first source metal layer disposed above the source electrode and the gate electrode, wherein the first source metal layer is electrically connected to the source electrode and extends in the first direction; and forming a first drain metal layer disposed above the drain electrode, wherein the first drain metal layer is electrically connected to the drain electrode and extends in the first direction.

22. The method of manufacturing a semiconductor device as claimed in claim 21, further comprising: forming a second source metal layer disposed above the first source metal layer and the first drain metal layer, wherein the second source metal layer is electrically connected to the first source metal layer; forming a second drain metal layer disposed above the first source metal layer and the first drain metal layer, wherein the second drain metal layer is electrically connected to the first drain metal layer; forming a source pad disposed above the second source metal layer and the second drain metal layer, wherein the source pad is electrically connected to the second source metal layer; and forming a drain pad disposed above the second source metal layer and the second drain metal layer, wherein the drain pad is electrically connected to the second drain metal layer.

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