Three dimensional NAND memory component

Abstract

A semiconductor device includes a stack, a first block having a first step formed in the stack, a second block having a second step formed in the stack, and a connection region. The stack includes word line layers and insulating layers alternately stacked on a substrate. The first block includes a first array region and a second array region, and the first step extends between the first array region and the second array region. The second block includes a third array region and a fourth array region, and the second step extends between the third array region and the fourth array region. The connection region is formed in the stack and between the first step and the second step.

Description

Three-dimensional NAND memory device and method for forming the same The present invention relates to a memory device and a method for forming the same, and more particularly to a three-dimensional NAND memory device and a method for forming the same. Flash memory devices have experienced rapid development in recent years. Flash memory devices can retain stored data for extended periods of time without the application of voltage. Furthermore, flash memory devices have relatively high read rates and are easy to erase and rewrite. Consequently, flash memory devices have been widely used in devices such as microcomputers and automated control systems. To increase the bit density and reduce the unit cost of flash memory devices, three-dimensional (3D) NAND flash memory devices have been developed. A 3D NAND flash memory element may include one or more memory planes, and each memory plane in the memory planes may include multiple memory blocks. Each memory block in the memory block may have an array region and one or more staircase regions. In such a 3D NAND flash memory element, each memory plane in the memory planes may have one or more decoding structures located at the boundary of the plane. The staircase region may be coupled to the decoding structure via a contact structure formed on the staircase region. The decoding structure is configured to be limited to the accessed block and drive the required voltage to the word line layer of the block. In a 3D NAND flash memory device, one or more decoding structures can be located at the boundaries of a memory plane (also known as a plane) in the 3D NAND flash memory device to drive the memory cells in that plane. Because the decoding structure is located at the boundary of the plane, the drive current applied by the decoding structure to the wordline layer of the plane needs to flow across the entire length of the plane to drive each memory cell in the plane. As 3D NAND flash memory transitions to higher density and higher capacity, especially from a 64-layer (64L) architecture to a 128-layer (128L) architecture, the layer (or film) size of the 3D NAND flash memory has correspondingly decreased. The reduced layer (or film) size can result in increased sheet resistance, which in turn causes resistance-capacitance (RC) delay. The inventive concept herein relates to a novel structure for a 3D NAND flash memory device, and more specifically, to a stepped region disposed midway between the planes of the 3D NAND flash memory device. The stepped region can be further coupled to a decoding structure. The decoding structure can accordingly drive the plane over a half-plane range. This can alleviate the RC delay issue caused by reduced layer (or film) size. In the present invention, a semiconductor component is provided. The semiconductor component may include a stacked body formed by word line layers and insulating layers alternately stacked on a substrate. A first step of a first block may be formed in the stacked body and extend between a first array region of the first block. A second step of a second block may be formed in the stacked body and extend between a second array region of the second block. The semiconductor component may further include a connection region formed in the stacked body between the first step and the second step. The first step may have steps extending in a step-down direction and steps extending in an opposite step-up direction. The steps of the first step may further extend in a transverse step-down direction perpendicular to the step-up direction and the step-down direction. The second step may have steps extending in a descending step direction and steps extending in an opposite ascending step direction. The steps of the second step may also extend in a direction perpendicular to the descending step direction and the ascending step direction and opposite to the lateral descending step direction. The semiconductor element includes a channel structure. The channel structure may be formed in the connection region, the first array region, and the second array region, wherein the channel structure extends from the substrate and extends through the word line layer and the insulating layer of the stack. The semiconductor element may have a first contact structure formed on the first step and connected to the word line layer in the first step, and a second contact structure formed on the second step and connected to the word line layer in the second step. In some embodiments, the first ladder and the second ladder are coupled to the decoding structure via a first contact structure and a second contact structure. In a semiconductor element, a gap structure may be located in a connection region between a first step and a second step. The gap structure divides the connection region into a first portion and a second portion. The first block includes a first portion of the connection region, a first array region, and a first step, wherein the first portion of the connection region is disposed adjacent to the first step and connected to the first array region. The second block includes a second portion of the connection region, a second array region, and a second step, wherein the second portion of the connection region is disposed adjacent to the second step and connected to the second array region. According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided. In the disclosed method, an initial stack of sacrificial word line layers and insulating layers is formed on a substrate of the semiconductor device. The sacrificial word line layers and insulating layers are alternately arranged on the substrate. Afterwards, a connection area, a first step area, and a second step area are patterned in the initial stack. Subsequently, the first step area in the initial stack is trimmed to form a first step, and the second step area in the initial stack is trimmed to form a second step. The first step is formed in a first block of the initial stack and extends between the first array areas of the first block. The second step is formed in a second block of the initial stack and extends between the second array areas of the second block. The connection area is formed in the initial stack between the first step and the second step. In some embodiments, to form the first and second steps, the sacrificial word line layer and the insulating layer in the first step region may be trimmed to form a first step extending in the first lateral downward step direction, wherein the first step divides the sacrificial word line layer and the insulating layer in the first step region into a first section and a second section. The sacrificial word line layer and the insulating layer in the second step region may be trimmed to form a second step extending in the first lateral downward step direction, wherein the second step divides the sacrificial word line layer and the insulating layer in the second step region into a third section and a fourth section. The first and second step regions are separated by a connecting region. The sacrificial word line layer and the insulating layer in the first stepped region are also trimmed to form one or more steps extending in a second lateral step-down direction, wherein the second lateral step-down direction is perpendicular to the first lateral step-down direction. The sacrificial word line layer and the insulating layer in the second stepped region are trimmed to form one or more steps extending in a direction perpendicular to the first lateral step-down direction and opposite to the second lateral step-down direction. Subsequently, a resist trimming process and an etching process are sequentially performed on the sacrificial word line layer and the insulating layer in the first stepped region and the second stepped region to form a first step and a second step in the first stepped region and the second stepped region, respectively. In the disclosed method, a channel structure can then be formed in the connection region, the first array region, and the second array region of the initial stack, wherein the channel structure extends from the substrate and extends through the sacrificial word line layer and the insulating layer in the connection region, the first array region, and the second array region of the initial stack. Thereafter, the sacrificial word line layer can be replaced with a word line layer composed of a conductive material. Furthermore, a first contact structure can be formed on the first step, and a second contact structure can be formed on the second step. The first contact structure is connected to the word line layer in the first step, and the second contact structure is connected to the word line layer in the second step. According to another aspect of the present invention, a semiconductor component is provided. The semiconductor component includes a first portion of a plane of a memory cell, wherein the plane of the memory cell is formed in a stack of word line layers and insulating layers. The word line layers and insulating layers are alternately stacked on a substrate. The semiconductor component includes a second portion of the plane of the memory cell formed in the stack. In the semiconductor component, a step region is formed in the stack, wherein the step region is located between the first portion and the second portion of the plane and is coupled to a decoding structure. The semiconductor component also includes a plurality of connection regions formed in the stack. The connection region extends across the step region between the first portion of the plane and the second portion of the plane to connect the first portion of the plane and the second portion of the plane, wherein a plurality of steps are provided in the step region, and the plurality of steps are arranged in an alternating manner between the connection regions. The semiconductor element may further include a channel structure disposed in the first and second portions of the plane and in the connection region, wherein the channel structure extends from the substrate and extends through the word line layer and the insulating layer of the stack. In some embodiments, each step in the staircase further includes a rung extending in a step-down direction and a rung extending in an opposite step-up direction. The rungs in each step in the staircase further extend in a transverse step-down direction or a direction opposite to the transverse step-down direction, wherein the transverse step-down direction is perpendicular to the step-up direction and the step-down direction. Furthermore, each step in the staircase can be located between a first array region of a first portion of the plane and a second array region of a second portion of the plane. In some embodiments, each of the steps is coupled to a corresponding decoding structure capable of driving the plane. For example, a step extending in a descending step direction can be connected to a first array region and provide control for driving the first array region. A step extending in an ascending step direction can be connected to a second array region and provide control for driving the second array region. The disclosure below provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and their arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature on or above a second feature in the description below may include an embodiment in which the formed first and second features are features that can be in direct contact, and may also include an embodiment in which additional features can be formed between the first and second features so that the first and second features may not be in direct contact. In addition, the present disclosure may repeat the digits and / or letters of the figure marks in each example. This repetition is for the purpose of simplifying and clarifying the present invention and does not itself indicate the relationship between the various embodiments and / or configurations discussed. Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "beneath," "above," and the like, may be used herein to describe an element or feature in its relationship to other elements or features as depicted in the figures. Spatially relative terms are intended to encompass different orientations of the element in use or operation in addition to the orientation depicted in the figures. The device may be depicted in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. Figure 1 illustrates a schematic diagram of a 3D NAND flash memory device according to a preferred embodiment of the present invention. As shown in Figure 1 , device 100 includes a memory portion 102 formed from three-dimensional (3D) memory cells. Memory portion 102 may include one or more memory planes (also referred to as planes) 104, and each memory plane within memory plane 104 may include multiple memory blocks (also referred to as blocks) 106. In some examples, concurrent operations may occur within memory planes 104. In some embodiments, each memory block within memory blocks 106 is the minimum unit for performing erase operations. In the example of FIG1 , the memory portion 102 includes two memory planes 104, and each of the two memory planes 104 includes eight memory blocks 106. Each memory block in the memory blocks 106 can include multiple memory cells, and each memory cell can be addressed via interconnects such as bit lines and word lines. In some examples, the bit lines and word lines can be arranged vertically, thereby forming an array of metal lines. For example, the word lines extend in direction X, and the bit lines extend in direction Y. Still referring to Figure 1 , each memory plane 104 may include one or more decoding structures located at the boundaries of the memory plane. For example, a first decoding structure 110 is located at the upper left corner of memory plane 104, and a second decoding structure 108 is located at the lower right corner of memory plane 104. Decoding structures 108-110 may be circuits used to select the block to be accessed within the memory plane and drive the required voltages onto the wordline layer of the memory plane. Because the decoding structures are located at the boundaries of the planes, the drive current (e.g., 112) applied by the decoding structures to the wordline layer of the plane must flow across the entire plane to drive every memory cell in the plane. As 3D NAND flash memory transitions to higher density and capacity, particularly from a 64L architecture to a 128L architecture, the layer (or film) size of 3D NAND flash memory has correspondingly decreased. This reduced layer (or film) size may result in increased sheet resistance, which in turn causes resistance-capacitance (RC) delay. 2 illustrates a schematic diagram of a 3D NAND flash memory component in a better embodiment of the present invention. As shown in FIG. 2 , half of the conductor element 200 includes a storage portion 202 formed by a three-dimensional (3D) storage unit. The storage portion 202 may include one or more storage planes 204 formed in the stack body of the word line layer and the insulation layer, wherein the word line layer and the insulation layer are stacked alternately on the base of the 3D NAND flash memory element. In an exemplary embodiment of FIG., two storage planes are included in the storage portion 202 . Still with reference to FIG. The cascade area 206 may be located between the first part 204A and the second part 204B of the plane 204 and coupled to the decoding structure (not shown). In the example, the decoding structure may be located in the terraced area 206 . In another example, the decoding structure may be located in a dedicated location (e.g., a peripheral location) of the 3D NAND flash memory element 200 . In some embodiments, a pseudo-step zone 208 enclosing plane 204 can be formed. Pseudo-terraced areas can be formed in a steep manner to conserve the layout area of ​​the plane. In some embodiments, the pseudo-step zone may be configured to separate the planes 204 in the 3D NAND flash memory element 200 from each other. In the terraced area, several staircases are formed. The step is formed in the stacked body of the word line layer and the insulation layer and can be coupled to the decoding structure via multiple contact structures as shown in Figure 4A , Figure 4B . Correspondingly, the decoding structure can apply the driving voltage to the flat word line via a staircase in the step zone. Since the terraced area is set in the middle of the plane, the driving current generated by the decoding structure only needs to flow across half a plane length to drive each storage unit in the plane. For example, the storage plane 204 is capable of being driven by a one-drive current 210 flowing across the first part 204A , and a one-driver current 212 flowing across the second part 204B . In the 3D NAND flash memory element 200 , each plane in the plane is driven in a direction from the middle position of the plane to both sides of the plane, and the effective flow length of the driving current is halved accordingly. Thus, it is possible to reduce the total resistance via a reduced flow length, which in turn compensates for the increased thin layer resistance caused by the reduced layer (or film) size. Figure 3 illustrates an enlarged schematic diagram of a 3D NAND flash memory device according to a preferred embodiment of the present invention. As shown in Figure 3 , a plurality of connection regions 302 may be formed in the stack and extend across the step region 206 between the first portion 204A and the second portion 204B of the memory plane 204 to connect the first and second portions 204A-204B. Furthermore, a plurality of steps 304 may be disposed in the step region 206 and arranged in an alternating pattern between the connection regions 302. To form the connection regions and the steps, a block layer (e.g., a TiN layer) may be disposed over the step region 206. A patterning process (e.g., a combination of photolithography and etching) may then be applied to remove portions of the block layer, forming a plurality of uncovered regions in the step region. The remaining portions of the block layer become the connection regions 302. A resist trim process and an etching process may be sequentially applied to the uncovered regions of the step region to form the steps 304. Intermediate steps for forming the steps can be depicted in Figures 6-9. Figure 4A illustrates a top-down, enlarged schematic diagram of a stair region in a 3D NAND flash memory device according to a preferred embodiment of the present invention. The enlarged image may be taken from a region 300 of the stair region 206 shown in Figure 3 . Region 300 may include two first array regions 402a-402b and a first stair 404 located between the two first array regions 402a-402b. First array regions 402a-402b and first stair 404 may be included in a first block (Block N), where N may be a positive integer. Region 300 may also include two second array regions 406a-406b and a second stair 408 located between the two second array regions 406a-406b. Second array regions 406a-406b and second stair 408 may be included in a second block (Block N+1). The connection region 302 is located between a first step 404 and a second step 408. A gap structure 422 is located in the connection region 302 between the first step 404 and the second step 408, dividing the connection region 302 into a first portion 302a and a second portion 302b. The first block (e.g., block N) includes the first portion 302a of the connection region 302, first array regions 402a-402b, and the first step 404. The first portion 302a of the connection region is located adjacent to the first step 404 and connected to the first array regions 402a-402b. The second block (e.g., block N+1) includes the second portion 302b of the connection region 302, second array regions 406a-406b, and the second step 408. The second portion 302b of the connection region 302 is located adjacent to the second step 408 and connected to the second array regions 406a-406b. The first step 404 and the second step 408 may have a plurality of dummy channel structures 414. The dummy channel structures may be provided in appropriate locations for process variation control during manufacturing and / or for additional mechanical support. The first step 404 and the second step 408 may also have a plurality of contact structures 412, which are located on the rungs of the first step and the second step and connected to the word line layers of the first and second steps. The contact structures 412 may extend from the rungs of the first step and the second step and further connect to the metal layers (e.g., M0 layer, M1 layer) of the back end of line (BEOL), wherein the metal layers are stacked above the contact structures 412. In some embodiments, the contact structures 412 may connect the first step and the second step to a decoding structure, so that the decoding structure can apply a driving voltage to the word line layers in the first step and the second step. A plurality of channel structures 410 are provided in the connection region 302, the first array region 402a-402b and the second array region 406a-406b. The channel structure 410 may extend from the substrate and extend through the word line layer to form an array of vertical memory cell strings. Each of the vertical memory cell strings may include a corresponding channel structure coupled to the word line layer to form one or more bottom selection transistors (BST), a plurality of memory cells (MC) and one or more top selection transistors (TST). The bottom selection transistors (BST), the memory cells (MC) and the top selection transistors (TST) are arranged sequentially and in series above the substrate. Each of the channel structures may further include a channel layer, a tunnel layer surrounding the channel layer, a charge trapping layer surrounding the tunnel layer, and a barrier layer surrounding the charge trapping layer and further in direct contact with the word line layer. In some embodiments, a layer such as HfO A high-K (high dielectric constant) layer of 2 or AlO may be disposed between the word line layer and the barrier layer. Region 300 may include a plurality of slot structures (or gate line slots) 416-428. The slot structures may have a trench profile and extend from the substrate and through a stack 600. In some embodiments, the slot structures may be formed of a conductive material and located on an array common source (ACS) region formed in the substrate to serve as a common source, thereby serving as a contact node. In some embodiments, the slot structures may be formed of a dielectric material to serve as a separation structure. Slit structure 422 may be a slit structure shared by block N and block N+1, separating the two blocks N and N+1 from each other. Slit structures 416-420 may be included in block N. Slit structure 416 is located in a continuous configuration at the bottom boundary of block N. Slit structures 418 and 420 are arranged in a discontinuous configuration within block N, with one or more gaps (e.g., 430) provided within slit structures 418-420. Accordingly, the channel structures in block N may be coupled to each other. Similarly, slit structures 424-428 may be included in block N+1. Slit structure 424 is located in a continuous configuration at the top boundary of block N+1. Slit structures 426 and 428 are arranged in a discontinuous configuration within block N+1, with one or more gaps provided within slit structures 426-428. Accordingly, the channel structures in block N+1 may be coupled to each other. Figure 4B schematically illustrates the flow path of a drive current within a stair region of a 3D NAND flash memory device in accordance with a preferred embodiment of the present invention. As shown in Figure 4B , a first stair 404 may include a first set of steps 404A and a second set of steps 404B. A second stair 408 may include a third set of steps 408A and a fourth set of steps 408B. In some embodiments, the first set of steps 404A may provide control for the first array region 402a, and the second set of steps 404B may provide control for the first array region 402b. The third set of steps 408A may provide control for the second array region 406a, and the fourth set of steps 408B may provide control for the second array region 406b. The first portion 302a of the connection region 302 may be configured to couple control to the first array regions 402a-402b, and the second portion 302b of the connection region 302 may be configured to couple control to the second array regions 406a-406b. Still referring to FIG4B , for simplicity and clarity, the path of the drive current generated by the decoding structure is depicted in block N+1. When a drive voltage is applied to the wordline layer in the second step 408 via the contact structure 412 by the decoding structure (not shown), the generated drive current may have a first current portion 431 and a second current portion 432. The first current portion 431 may flow from the third group of steps 408A toward the second array region 406a. The first current portion 431 may also flow through the gap between the slit structures 426 and 428 and flow to the second array region 406b via the second portion 302b of the connection region 302. Similarly, second current portion 432 can flow from fourth set of steps 408B toward second array region 406b. Second current portion 432 can also flow through the gap between gap structures 426 and 428 and flow to second array region 406a via second portion 302b of connection region 302. In some embodiments, second array region 406a can be included in first portion 204A of plane 204 in FIG. 3, and second array region 406b can be included in second portion 204B of plane 204. Thus, the drive current can flow from the step region to both the first and second portions of the plane simultaneously, driving the memory cells in the plane with a reduced flow range compared to a related 3D NAND flash memory device (e.g., 3D NAND flash memory device 100 in FIG. 1). Figure 5 illustrates a three-dimensional, enlarged schematic diagram of a stair region in a 3D NAND flash memory device according to a preferred embodiment of the present invention. For simplicity and clarity, the channel structure 410, dummy channel structure 414, and contact structure 412 are not included in Figure 5. As shown in Figure 5, a first staircase 404 may include a first set of steps 404A extending in a descending stair direction (e.g., direction X) and a second set of steps 404B extending in an opposite ascending stair direction (e.g., direction X). Furthermore, the first and second sets of steps in the first staircase extend in a lateral descending stair direction (e.g., direction -Y) perpendicular to the ascending and descending stair directions. In the exemplary embodiment of Figure 5, the first and second sets of steps may have four steps along the lateral descending stair direction. These four steps can divide the first and second sets of steps into four partitioned regions along the lateral descending stair direction. Similarly, the second step 408 may have a third set of steps 408A extending in a descending step direction (e.g., direction X) and a fourth set of steps 408B extending in an opposite ascending step direction (e.g., direction X). The third and fourth sets of steps within the second step also extend in a direction perpendicular to the ascending and descending step directions and opposite to the lateral descending step direction (e.g., direction Y). 4A, 4B, and 5 are merely examples, and the first and second steps 404, 408 may have any number of rung groups. In addition, each of the rung groups may have any number of runs depending on the element structure. Figures 6-9 illustrate three-dimensional schematic diagrams of various intermediate steps in the fabrication of a 3D NAND flash memory device according to a preferred embodiment of the present invention. In Figure 6, a stack 600 of wordline layers and insulating layers is provided. The wordline layers and insulating layers are alternately disposed on a substrate (not shown). In some embodiments, the wordline layers formed in stack 600 may be sacrificial wordline layers, and conductive materials may be used to replace the sacrificial wordline layers to form wordline layers in subsequent fabrication steps. In some embodiments, the sacrificial wordline layers may be composed of silicon nitride (SiN), and the insulating layers may be composed of silicon oxide (SiO). Any suitable deposition process may be used to form the sacrificial wordline layers and insulating layers. For example, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, a diffusion process, an atomic layer deposition (ALD) process, or other suitable deposition processes may be used. Still referring to FIG. 6 , a patterning process can be used to form a connection region 602, a first stepped region 604, and a second stepped region 606 in the initial stack. For example, a block layer (not shown) (e.g., a titanium nitride (TiN) layer) can be deposited on the top surface of the initial stack 600. An etching lithography process can be applied to form a patterned mask layer (e.g., a patterned photoresist layer) that exposes the block layer in the first and second stepped regions 604, 606. Subsequently, an etching process can be applied to remove the block layer in the first and second stepped regions 604, 606, leaving the wordline layer in the first and second stepped regions 604-606 uncovered. Accordingly, the region with the remaining block layer becomes the connection region 602. In FIG7 , lithography and etching processes can be further applied to form a first step 608 in the first stepped region 604 and a second step 610 in the second stepped region 606. The sacrificial word line layer and the insulating layer in the first stepped region 604 can be trimmed to form a first step 608 extending in a first lateral step-down direction (e.g., direction -X) parallel to the substrate. The first step 608 divides the sacrificial word line layer and the insulating layer in the first stepped region 604 into a first segment 604A and a second segment 604B. Furthermore, the sacrificial word line layer and the insulating layer in the second stepped region 606 of the stack 600 can be trimmed to form a second step 610 extending in the first lateral step-down direction. The second step 610 divides the sacrificial word line layer and the insulating layer in the second stepped region 606 into a third segment 606A and a fourth segment 606B. To form the first step 608 and the second step 610, a photolithography process may apply a patterned mask layer to the top surface of the stack 600, wherein the patterned mask layer exposes the first segment 604A of the first stepped region 604 and the third segment 606A of the second stepped region 606. An etching process may then be applied to remove portions of the sacrificial wordline layer and the insulating layer in the first segment 604A of the first stepped region 604 and the third segment 606A of the second stepped region 606. Upon completion of the etching process, the first step 608 and the second step 610 are formed accordingly. In FIG8 , the sacrificial word line layer and the insulating layer in the first stepped region 604 can be trimmed to form one or more steps extending in a second lateral step-down direction (e.g., direction -Y), wherein the second lateral step-down direction is perpendicular to the first lateral step-down direction (e.g., direction -X). For example, as shown in FIG8 , three steps can be formed along the -Y direction in the first and second sections 604A-604B of the first stepped region 604. Furthermore, the sacrificial word line layer and the insulating layer in the second stepped region 606 can be trimmed to form one or more steps extending in a third lateral step-down direction (e.g., direction Y) that is opposite to the second lateral step-down direction. To form one or more steps in the first and second stepped regions along the second and third lateral step-down directions, resist trimming and etching processes can be performed sequentially. For example, a resist layer can be deposited on the first segment 604A of the first stepped region 604. A photolithography process can expose a first portion S1 of the first segment 604A along the second lateral step-down direction (e.g., direction -Y). A plasma etching process can be applied to remove portions of the wordline layer and the insulating layer within the exposed first portion S1. Subsequently, a resist trimming process (e.g., a plasma ashing process) can be applied to expose a second portion S2 of the first segment 604A along the second lateral step-down direction. A plasma etching process can then be applied to remove the exposed second portion S2 and portions of the wordline layer and the insulating layer within the exposed first portion S1. A plasma ashing process can then be applied again to remove the remaining resist layer. When the remaining resist layer is removed, three steps may be formed in the first section 604A of the first stepped region 604 along the second lateral down-step direction (direction −Y). 9 , a resist trimming process and an etching process can be sequentially applied to the sacrificial word line layer and the insulating layer in the first and second stepped regions 604-606 to form a first step 904 and a second step 908 in the first and second stepped regions 604, 606, respectively. As shown in FIG9 , after the resist trimming process and the etching process are completed, the stack 600 can have a configuration similar to the stack 300 in FIG5 . For example, as shown in FIG9 , first step 904 includes a first set of steps 904A extending in a descending step direction (e.g., direction X) in first section 604A, and a second set of steps 904B extending in an ascending step direction (e.g., direction X) in second section 604B. Second step 908 includes a third set of steps 908A extending in a descending step direction (e.g., direction X) in third section 606A, and a fourth set of steps 908B extending in an ascending step direction (e.g., direction X) in fourth section 606B. Furthermore, first step 904 may extend in a transverse descending step direction (e.g., direction -Y), and second step 908 may extend in a direction opposite to the transverse descending step direction (e.g., direction Y). Furthermore, a connection region 912 formed based on the connection region 602 may be disposed between the first step 904 and the second step 908. A gap structure 910 may be located in the connection region 912 and between the first step 904 and the second step 908. Block N may include first array regions 902a-902b, a first portion 912a of the connection region 912, and the first step 904. Block N+1 may include second array regions 906a-906b, a second portion 912b of the connection region 912, and the second step 908. FIG10 illustrates a schematic flow diagram of a process for manufacturing a 3D NAND flash memory device according to a preferred embodiment of the present invention. A process 1000 begins ( S1002 ) with a step ( S1004 ) in which an initial stack of sacrificial wordline layers and insulating layers may be formed on a substrate of the 3D NAND flash memory device. A patterning process may then be performed to pattern a connection region, a first stepped region, and a second stepped region within the initial stack. The connection region may be located between the first stepped region and the second stepped region. In some embodiments, step ( S1004 ) may be performed as illustrated in FIG6 . Next, process 1000 proceeds to step S1006, in which the sacrificial word line layer and the insulating layer in the first stepped region may be trimmed to form a first step extending in a first lateral step-down direction (e.g., direction -X). The first step divides the sacrificial word line layer and the insulating layer in the first stepped region into a first section and a second section. In step S1008, process 1000 proceeds to step S1008, in the second stepped region, the sacrificial word line layer and the insulating layer may be trimmed to form a second step extending in the first lateral step-down direction. The second step divides the sacrificial word line layer and the insulating layer in the second stepped region into a third section and a fourth section. In some embodiments, steps S1006 and S1008 may be performed as described with reference to FIG. 7 . In step S1010 of process 1100, the sacrificial word line layer and the insulating layer in the first stepped region may be trimmed to form one or more steps extending in a second lateral step-down direction (e.g., direction -Y), wherein the second lateral step-down direction is perpendicular to the first lateral step-down direction (e.g., direction -X). In step S1012 of process 1000, the sacrificial word line layer and the insulating layer in the second stepped region may be trimmed to form one or more steps extending in a direction opposite to the second lateral step-down direction (e.g., direction Y). In some embodiments, steps 1010 and S1012 may be performed as illustrated with reference to FIG. 8 . Next, process 1000 proceeds to step S1014, where a resist trimming process and an etching process are sequentially applied to the sacrificial word line layer and the insulating layer in the first and second stepped regions to form first and second steps in the first and second stepped regions, respectively. In some embodiments, step S1014 can be performed as illustrated with reference to FIG. 9 , and the process ends at step S1016. It should be noted that additional steps may be provided before, during, and after process 1000, and that some of the steps described may be replaced, deleted, or performed in a different order for additional embodiments of process 1000. For example, in a subsequent process step, a channel structure may be formed in the two array regions of the initial stack, wherein the channel structure extends from the substrate and extends through the sacrificial word line layer and the insulating layer in the two array regions and the connection region of the initial stack. A plurality of gap structures may be formed, and a conductive material may be used instead of the sacrificial word line layer to form the word line layer. In addition, a first contact structure may be formed on the first step, and a second contact structure may be formed on the second step. The first contact structure is connected to the word line layer in the first step, and the second contact structure is connected to the word line layer in the second step. Furthermore, various additional interconnect structures (e.g., metallization layers with conductive lines and / or vias) may be formed above the first and second contact structures of the 3D NAND flash memory device. Such interconnect structures electrically connect the 3D NAND flash memory device to other contact structures and / or active components to form functional circuits. Additional device features such as passivation layers and input / output structures may also be formed. The various embodiments described herein provide several advantages for related memory devices. For example, in the context of the present invention, a 3D NAND flash memory device can have multiple memory planes. Each memory plane can have a corresponding decoding structure disposed in the middle of the memory plane. Thus, each memory plane can be driven by the corresponding decoding structure in a direction from the middle of the memory plane to both sides of the memory plane, and the effective flow length of the drive current is correspondingly halved compared to the drive current in the related 3D NAND flash memory device. Therefore, the reduced flow length can reduce the total resistance, thereby compensating for the increased sheet resistance caused by the reduced layer (or film) size in the 3D NAND flash memory device. The foregoing has summarized the features of several embodiments so that those skilled in the art can better understand the various aspects of the present invention. Those skilled in the art should recognize that they can easily use the present invention as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present invention. The foregoing is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the scope of the present invention should fall within the scope of the present invention. 100: Element 102, 202: Storage Portion 104, 204: Storage Plane 106: Storage Block 108: Second Decoding Structure 110: First Decoding Structure 112, 210, 212: Drive Current 200: Semiconductor Element 204A, 302a, 912a, S1: First Portion 204B, 302b, 912b, S2: Second Portion 206: Step Region 208: Pseudo Step Region 300: Region 302, 602, 912: Connection Region 304: Steps 402a, 402b, 902a, 902b: First Array Region 404, 608, 904: First Steps 404A, 904A: First Group of Steps 404B, 904B: Second Group of Steps 406a, 406b, 906a, 906b: Second Array Region 408, 610, 908: Second step 408A: Third set of steps 408B: Fourth set of steps 410: Channel structure 412: Contact structure 414: Pseudo-channel structure 416, 418, 420, 422, 424, 426, 428, 910: Slit structure 430: Gap 431: First current portion 432: Second current portion 600: Stack 604: First step region 604A: First section 604B: Second section 606: Second step region 606A: Third section 606B: Fourth section 1000: Process S1002: Start S1004, S1006, S1008, S1010, S1012, S1014: Step S1016: End N, N+1: Block X, -X, Y, -Y: Direction Figure 1 is a schematic diagram of a 3D NAND flash memory device according to a preferred embodiment of the present invention. Figure 2 is a schematic diagram of a 3D NAND flash memory device according to a preferred embodiment of the present invention. Figure 3 is an enlarged schematic diagram of a 3D NAND flash memory device according to a preferred embodiment of the present invention. Figure 4A is a top-down enlarged schematic diagram of a stair region in a 3D NAND flash memory device according to a preferred embodiment of the present invention. Figure 4B is a schematic diagram of the flow path of a driving current in a stair region in a 3D NAND flash memory device according to a preferred embodiment of the present invention. Figure 5 is a three-dimensional enlarged schematic diagram of a stair region in a 3D NAND flash memory device according to a preferred embodiment of the present invention. Figure 6 is a three-dimensional schematic diagram of various intermediate steps in manufacturing a 3D NAND flash memory device according to a preferred embodiment of the present invention. Figure 7 is a three-dimensional schematic diagram of various intermediate steps in manufacturing a 3D NAND flash memory device according to a preferred embodiment of the present invention. Figure 8 is a three-dimensional schematic diagram of various intermediate steps in manufacturing a 3D NAND flash memory device according to a preferred embodiment of the present invention. Figure 9 is a 3D schematic diagram illustrating various intermediate steps in manufacturing a 3D NAND flash memory device according to a preferred embodiment of the present invention. Figure 10 is a flow diagram illustrating a process for manufacturing a 3D NAND flash memory device according to a preferred embodiment of the present invention. 300: Area 302: Connection area 302b: Part 2 404A: First set of steps 404B: Second set of steps 406a, 406b: second array area 408A: The third set of steps 408B: The fourth set of steps 426, 428: gap structure 431: First current part 432: Second current part N, N+1: Block X, Y: direction

Claims

1. A semiconductor element, comprising: A stack comprising alternately stacked word line layers and insulating layers; a first block comprising a first step located within the stack, wherein the first block further comprises a first array region and the first step is located between the first array region and another of the first array regions; a second block comprising a second step located within the stack, wherein the second block further comprises a second array region and the second step is located between the second array region and another of the second array regions; a connection region within the stack and located between the first step and the second step; and a slot structure within the connection region and located between the first step and the second step, the slot structure comprising a dielectric material and dividing the connection region into a first portion and a second portion, wherein: The first block includes the first portion of the connection area, the first array area, and the first step, and the first portion of the connection area is configured to be adjacent to the first step and connected to the first array area; the second block includes the second portion of the connection area, the second array area, and the second step, and the second portion of the connection area is configured to be adjacent to the second step and connected to the second array area.

2. The semiconductor device as described in claim 1, wherein, The first step has steps extending in a descending direction and steps extending in the opposite ascending direction.

3. The semiconductor device as described in claim 2, wherein, The first step extends further in a transverse downward step direction, perpendicular to both the descending and ascending step directions.

4. The semiconductor device as described in claim 3, wherein, The second step has steps extending in both the descending step direction and the ascending step direction.

5. The semiconductor device as described in claim 4, wherein, The second step extends in a direction perpendicular to the descending step direction and the ascending step direction, and opposite to the lateral descending step direction.

6. The semiconductor device as described in claim 1, wherein, The first step includes steps descending along a first lateral direction and a second lateral direction perpendicular to the first lateral direction, and the first step is divided into multiple sections along the second lateral direction.

7. The semiconductor device as described in claim 1 further includes: A first contact structure is located on the first step and connected to the word line layers in the first step; And a second contact structure, located on the second step and connected to the word line layers in the second step.

8. The semiconductor device as described in claim 7, wherein, The first step and the second step are connected to a decoding structure via the first contact structure and the second contact structure.

9. A semiconductor element, comprising: A stack, comprising alternating layers of word lines and insulating layers; A first block, the first block including a first step located in the stack and the first step extending between first array regions; a second block, the second block including a second step located in the stack and the second step extending between second array regions; a connection region located in the stack, wherein the first array region and the first step are located on a first side of the connection region, and the second array region and the second step are located on a second side of the connection region; and a slot structure located in the connection region and between the first step and the second step, the slot structure including a dielectric material and dividing the connection region into a first portion and a second portion.

10. The semiconductor device as claimed in claim 9, wherein, The first step has steps extending in a descending direction and steps extending in the opposite ascending direction.

11. The semiconductor device as described in claim 10, wherein, The first step extends further in a transverse downward step direction, perpendicular to both the descending and ascending step directions.

12. The semiconductor device as described in claim 11, wherein, The second step has steps extending in both the descending step direction and the ascending step direction.

13. The semiconductor device as described in claim 12, wherein, The second step extends in a direction perpendicular to the direction of the descending step and the direction of the ascending step, and opposite to the direction of the lateral descending step.

14. The semiconductor device as described in claim 9, wherein, The first step includes steps descending along a first lateral direction and a second lateral direction perpendicular to the first lateral direction, and the first step is divided into multiple sections along the second lateral direction.

15. The semiconductor device as described in claim 9, further comprising: A first contact structure is located on the first step and connected to the word line layers in the first step; And a second contact structure located on the second step and connected to the word line layers in the second step, wherein the first step and the second step are connected to a decoding structure through the first contact structure and the second contact structure.

16. A semiconductor element, comprising: A stack, comprising alternating layers of word lines and insulating layers; A first block, the first block including a first step located in the stack and the first step extending between first array regions; a second block, the second block including a second step located in the stack and the second step extending between second array regions; a connecting region located in the stack, wherein the first array region and the first step are located on a first side of the connecting region, and the second array region and the second step are located on a second side of the connecting region; and a channel structure located in the connecting region, the first array region, or the second array region.

17. The semiconductor device as described in claim 16, wherein, The first step has a step extending in a descending step direction and a step extending in an opposite ascending step direction, and the step of the first step extends further in a transverse descending step direction perpendicular to the descending step direction and the ascending step direction.

18. The semiconductor device as described in claim 17, wherein, The second step has steps extending in the descending step direction and the ascending step direction, and the steps of the second step extend further in a direction perpendicular to the descending step direction and the ascending step direction, and opposite to the lateral descending step direction.

19. The semiconductor device as described in claim 16, wherein, The first step includes steps descending along a first lateral direction and a second lateral direction perpendicular to the first lateral direction, and the first step is divided into multiple sections along the second lateral direction.

20. The semiconductor device as described in claim 16, further comprising: A first contact structure is located on the first step and connected to the word line layers in the first step; And a second contact structure located on the second step and connected to the word line layers in the second step, wherein the first step and the second step are connected to a decoding structure through the first contact structure and the second contact structure.

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