Read reference voltage management in flash memory

Abstract

A method for performing read reference voltage management on a flash memory includes: managing a first self-learning table based on one or more read retry operations using hard decision decoding; managing a second self-learning table based on one or more read retry operations using soft decision decoding; managing a sticky table based on a read reference voltage level or a set of read reference voltage levels used in a most recently successful read retry operation, wherein the read reference voltage level or the set of read reference voltage levels is determined by at least one of the first self-learning table, the second self-learning table, and a read retry operation using soft decision decoding; and performing a normal read operation based on the sticky table.

Claims

1. A method for performing read reference voltage management on a flash memory, comprising: managing a first self-learning table based on one or more read retry operations using hard-decision decoding; managing a second self-learning table based on one or more read retry operations using soft-decision decoding; managing a sticky table based on a read reference voltage level or a set of read reference voltage levels used in a most recently successful read retry operation, wherein the read reference voltage level or the set of read reference voltage levels is determined by at least one of the first self-learning table, the second self-learning table, and a read retry operation using soft-decision decoding; and performing a normal read operation based on the sticky table.

2. The method as described in claim 1, wherein the step of managing the first self-learning table comprises: determining a read reference voltage level or a set of read reference voltage levels according to a preset read retry table; performing at least one read retry operation according to the determined read reference voltage level or the set of read reference voltage levels; determining whether the read retry operation is successful based on hard decision decoding; and when the read retry operation is successful, storing the information of the determined read reference voltage level or the set of read reference voltage levels as an item in the first self-learning table.

3. The method as described in claim 2, wherein the step of managing the second self-learning table comprises: performing at least one read retry operation using an iteratively adjusted read reference voltage level or an iteratively adjusted set of read reference voltage levels based on soft decision decoding; determining whether the read retry operation is successful based on soft decision decoding; and storing information about the adjusted read reference voltage level or the set of read reference voltage levels as an item in the second self-learning table when the read retry operation is successful.

4. The method as described in claim 3, further comprising: in response to the failure of the normal read operation, executing a first retry procedure including one or more read retry operations using hard decision decoding, comprising: performing a first read retry operation using a read reference voltage level or a set of read reference voltage levels determined according to one of a priority subset items of the first self-learning table; and if the first read retry operation is successful, storing the determined read reference voltage level or the set of read reference voltage levels as a highest priority item in the priority subset items of the first self-learning table, and updating the sticky table accordingly.

5. The method as described in claim 4, wherein the first retry procedure comprises: if the first read retry operation is unsuccessful for all items of the priority subset of items in the first self-learning table, performing a second read retry operation using a read reference voltage level or a set of read reference voltage levels determined according to an item in the second self-learning table; and if the second read retry operation is successful, storing the information of the determined read reference voltage level or set of read reference voltage levels as a highest priority item in the second self-learning table, and updating the sticky table accordingly.

6. The method as described in claim 5, wherein the first retry procedure further comprises: if the second read retry operation based on all items in the second self-learning table fails, performing a third read retry operation using a read reference voltage level or a set of read reference voltage levels determined according to the remaining items in the preset read retry table, wherein the remaining items in the preset read retry table do not include the priority subset items already recorded in the first self-learning table; and if the third read retry operation succeeds, storing the determined read reference voltage level or the set of read reference voltage levels as a highest priority item in the first self-learning table, and updating the sticky table accordingly.

7. The method as described in claim 6, further comprising: if the third read retry operation based on all remaining items in the preset read retry table fails, executing a second retry process including one or more read retry operations using soft decision decoding, comprising: executing a fourth read retry operation using an iteratively adjusted read reference voltage level or an iteratively adjusted set of read reference voltage levels based on soft decision decoding; and if the fourth read retry operation succeeds, storing the information of the currently adjusted read reference voltage level or the currently adjusted set of read reference voltage levels in a final iteration of soft decision decoding as a highest priority item in the second self-learning table, and updating the sticky table accordingly.

8. The method of claim 1, wherein the first self-learning table and the second self-learning table are managed according to a plane, and a plane is part of a memory die or chip of the flash memory, comprising multiple memory blocks and being independently accessible.

9. The method of claim 1, wherein the sticky table is managed according to superblocks, and a superblock is a set of memory blocks logically grouped together across multiple memory chips or wafers contained in the flash memory.

10. The method of claim 1 further comprises: when the sticky meter is unavailable, performing the normal read operation using a preset read reference voltage level.

11. A memory controller for a flash memory, comprising: a storage unit for storing code; and a processing unit for executing the code to perform the following operations on the flash memory: managing a first self-learning table based on one or more read retry operations using hard-decision decoding; managing a second self-learning table based on one or more read retry operations using soft-decision decoding; managing a sticky table based on a read reference voltage level or a set of read reference voltage levels used in a most recently successful read retry operation, wherein the read reference voltage level or the set of read reference voltage levels is determined by at least one of the first self-learning table, the second self-learning table, and a read retry operation using soft-decision decoding; and performing a normal read operation based on the sticky table.

12. The memory controller of claim 11, wherein when the processing unit executes the code, the memory controller is configured to: determine a read reference voltage level or a set of read reference voltage levels according to a preset read retry table; perform at least one read retry operation according to the determined read reference voltage level or the set of read reference voltage levels; determine whether the read retry operation is successful based on hard decision decoding; and when the read retry operation is successful, store information about the determined read reference voltage level or the set of read reference voltage levels as an item in the first self-learning table.

13. The memory controller of claim 12, wherein when the processing unit executes the code, the memory controller is configured to: perform at least one read retry operation using an iteratively adjusted read reference voltage level or an iteratively adjusted set of read reference voltage levels based on soft decision decoding; determine whether the read retry operation is successful based on soft decision decoding; and when the read retry operation is successful, store information about the adjusted read reference voltage level or the set of read reference voltage levels as an item in the second self-learning table.

14. The memory controller of claim 13, wherein when the processing unit executes the code, the memory controller is configured to: in response to the failure of the normal read operation, execute a first retry procedure comprising one or more read retry operations using hard decision decoding, comprising: performing a first read retry operation using a read reference voltage level or a set of read reference voltage levels determined according to one of a priority subset of items in the first self-learning table; and if the first read retry operation is successful, storing the determined read reference voltage level or the set of read reference voltage levels as a highest priority item in the priority subset of items in the first self-learning table, and updating the sticky table accordingly.

15. The memory controller of claim 14, wherein when the processing unit executes the code, the memory controller is configured to: if the first read retry operation based on all items of the priority subset of items in the first self-learning table fails, perform a second read retry operation using a read reference voltage level or a set of read reference voltage levels determined according to an item in the second self-learning table; and if the second read retry operation succeeds, store the information of the determined read reference voltage level or set of read reference voltage levels as a highest priority item in the second self-learning table, and update the sticky table accordingly.

16. The memory controller of claim 15, wherein when the processing unit executes the code, the memory controller is configured to: if the second read retry operation based on all items in the second self-learning table fails, perform a third read retry operation using a read reference voltage level or a set of read reference voltage levels determined according to the remaining items in the preset read retry table, wherein the remaining items in the preset read retry table do not include the priority subset items already recorded in the first self-learning table; and if the third read retry operation succeeds, store the determined read reference voltage level or the set of read reference voltage levels as a highest priority item in the first self-learning table, and update the sticky table accordingly.

17. The memory controller of claim 16, wherein when the processing unit executes the code, the memory controller is configured to: if the third read retry operation based on all remaining items in the preset read retry table fails, execute a second retry process including one or more read retry operations using soft decision decoding, comprising: executing a fourth read retry operation using an iteratively adjusted read reference voltage level or an iteratively adjusted set of read reference voltage levels based on soft decision decoding; and if the fourth read retry operation succeeds, storing information of the currently adjusted read reference voltage level or the currently adjusted set of read reference voltage levels in a final iteration of the soft decision decoding as a highest priority item in the second self-learning table, and updating the sticky table accordingly.

18. The memory controller of claim 11, wherein the first self-learning table and the second self-learning table are managed according to a plane, and a plane is part of a memory die or chip of the flash memory, comprising a plurality of memory blocks and being independently accessible.

19. The memory controller as claimed in claim 11, wherein the sticky table is managed according to superblocks, and a superblock is a set of memory blocks logically grouped together across multiple memory chips or wafers contained in the flash memory.

20. The memory controller of claim 11, wherein when the processing unit executes the code, the memory controller is configured to: perform the normal read operation using a preset read reference voltage level when the sticky table is unavailable.

21. A data storage device comprising a memory controller as described in claim 11 and a flash memory.

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