Semiconductor circuit structure with composite shallow trench isolation region for heat dissipation and method for forming the same

Abstract

A method for manufacturing a semiconductor circuit structure. The method includes the following steps: first, providing a semiconductor substrate; forming shallow trenches extending from the original surface of the semiconductor substrate into the interior of the semiconductor substrate to surround an active region; forming dielectric layers on the sidewalls and bottom of the shallow trenches; and filling the shallow trenches with a thermally conductive semiconductor material, wherein the thermally conductive semiconductor material is isolated from the semiconductor substrate by the dielectric layers.

Description

Technical Field

[0001] This disclosure relates to a semiconductor circuit structure and its fabrication method, and more particularly to a transistor structure and its fabrication method surrounded by a composite shallow trench isolation region of a semiconductor material with heat dissipation properties. Prior Technology

[0002] The technology of integrating silicon components onto a single integrated circuit (IC) chip achieved the integration of over 50 billion transistors on a single chip in 2021, officially transitioning from the Very Large Scale Integration (VLSI) era (integrating millions of transistors on a single die) to the Gigabyte-Scale Integration (GSI) era (integrating billions of transistors on a single die). This achievement of higher transistor integration on a single die has significantly improved the PPAC (Power, Power, and Area) capabilities of microsystems (i.e., higher performance, better power management, efficient area utilization, and lower cost per bit), thereby creating many powerful chips such as CPUs, GPUs, FPGAs, SOCs, SRAMs, and DRAMs, enhancing system capabilities, continuously supporting Moore's Law, and becoming the foundation for exponential economic growth.

[0003] Moreover, the single-chip integration capability of silicon chips will soon evolve from gigascale integrated circuits (GSI: billions of transistors integrated on a single die) to trillion-scale integrated circuits (TSI: trillions of transistors integrated on a single die), and the performance of the chips will be significantly improved.

[0004] However, operating such a massive number of transistors would drastically increase power consumption, adversely affecting the transistor junction temperature. Furthermore, the limited heat dissipation capacity of the chip itself (e.g., silicon dioxide (SiO2) has very low thermal conductivity) would further elevate the overall chip temperature. This material and component structure problem leads to a negative cycle: increased chip temperature reduces transistor speed, inevitably requiring a forced increase in circuit power to accelerate transistor performance, which in turn causes a significant rise in chip temperature, exacerbating the heat dissipation problem.

[0005] In fact, this problem of insufficient heat dissipation leading to excessively high chip operating temperatures is considered one of the most serious issues in the entire chip industry and must be addressed to avoid becoming a major obstacle to integrating more components onto the chip. However, technologies to reduce GSI chip temperatures have not yet made smooth progress. Furthermore, with the further miniaturization of semiconductor technology nodes (e.g., the minimum feature size shrinking from 7 nanometers (nm) to 5 nanometers, then to 3 nanometers, etc.), transistor sizes must become smaller, and the percentage of oxide coverage in the total transistor size is increasing, while the heat dissipation capacity between component junctions has not been further enhanced. Although many heat dissipation solutions have been proposed in the industry, such as covering the entire chip with thermal pads with higher thermal coefficients or using liquid cooling circulation outside the chip, these solutions are very costly and still too inefficient to effectively reduce transistor junction temperatures. Summary of the Invention

[0006] One object of this specification is to provide a method for manufacturing a semiconductor circuit structure. This method includes the following steps: first, providing a semiconductor substrate; forming shallow trenches extending from the original surface of the semiconductor substrate into the interior of the semiconductor substrate to surround an active region; forming dielectric layers on the sidewalls and bottom of the shallow trenches; and filling the shallow trenches with a thermally conductive semiconductor material, wherein the thermally conductive semiconductor material is isolated from the semiconductor substrate by the dielectric layers.

[0007] According to one embodiment of this specification, the step of filling a shallow trench with a thermally conductive semiconductor material includes: first filling the shallow trench with an amorphous semiconductor material; and performing a laser annealing or thermal annealing process on the amorphous semiconductor material to form a thermally conductive semiconductor material.

[0008] According to one embodiment of this specification, the thermally conductive semiconductor material comprises silicon with an average grain size substantially between 0.1 micrometers (µm) and 2 micrometers.

[0009] According to one embodiment of this specification, before performing laser annealing or thermal annealing processes on the amorphous semiconductor material, the method further includes: curing the amorphous semiconductor material using ultraviolet light.

[0010] According to one embodiment of this specification, a first capping layer is applied over the active region after the shallow trench is filled with an amorphous thermally conductive semiconductor material, which then covers the first capping layer.

[0011] According to one embodiment of this specification, after filling the shallow trench with an amorphous thermally conductive semiconductor material, the top surface of the amorphous semiconductor material will be substantially between 800 nanometers and 2000 nanometers above the top surface of the first capping layer.

[0012] According to one embodiment of this specification, after laser annealing or thermal annealing of the crystalline semiconductor material, a planarization process is further included for the thermally conductive semiconductor material.

[0013] According to one embodiment of this specification, after a planarization process, the top surface of the thermally conductive semiconductor material is substantially flush with the top surface of the first cover.

[0014] According to one embodiment of this specification, after the planarization process, the process further includes etching the thermally conductive semiconductor material downwards so that the etched top surface of the thermally conductive semiconductor material is substantially lower than the original surface of the semiconductor substrate.

[0015] According to one embodiment of this specification, after the thermally conductive semiconductor material is etched downwards, the etched top surface of the thermally conductive semiconductor material is substantially between 5 nanometers and 30 nanometers below the original surface of the semiconductor substrate.

[0016] According to one embodiment of this specification, after etching the thermally conductive semiconductor material downwards, a second capping layer is further deposited to cover the etched top surface of the thermally conductive semiconductor material.

[0017] According to one embodiment of this specification, the thermally conductive semiconductor material includes silicon; and in the thermally conductive semiconductor material, the number of silicon grains along a depth direction of the thermally conductive semiconductor material is at most three. Simple Explanation of the Diagram

[0018] To provide a better understanding of the above and other aspects of this specification, specific embodiments are described below in conjunction with the accompanying drawings: Figure 1A(1) is a top view of a process structure after a shallow trench isolation structure is formed in a semiconductor substrate to define at least one active region, according to an embodiment of this specification; Figures 1A(2), 1A(3), 1A(4), and 1A(5) are cross-sectional views of the structure drawn along tangents CA1, CA2, CA3, and CA4 in Figure 1A(1), respectively. Figure 1A(6) is a cross-sectional view of the manufacturing process structure of the peripheral circuit area of ​​the dynamic random access memory circuit structure, drawn based on Figure 1A(1). Figure 1B(1) shows a top view of the process structure after the recessed gate pattern has been defined; Figures 1B(2), 1B(3), 1B(4), and 1B(5) are cross-sectional views of the structure drawn along tangents CB1, CB2, CB3, and CB4 in Figure 1B(1); Figure 1B(6) is a cross-sectional view of the manufacturing process structure of the peripheral circuit area of ​​the dynamic random access memory circuit structure drawn based on Figure 1B(1). Figure 1C(1) shows a top view of the process structure after the recessed gate pattern has been transferred to the remaining silicon nitride layer; Figures 1C(2), 1C(3), 1C(4), and 1C(5) are cross-sectional views of the structure drawn along tangents CC1, CC2, CC3, and CC4 in Figure 1C(1); Figure 1C(6) is a cross-sectional view of the manufacturing process structure of the peripheral circuit area of ​​the dynamic random access memory circuit structure drawn based on Figure 1C(1). Figure 1D(1) shows a top view of the process structure after at least one hollowed-out groove has been formed; Figures 1D(2), 1D(3), 1D(4), and 1D(5) are cross-sectional views of the structure drawn along tangents CD1, CD2, CD3, and CD4 in Figure 1D(1). Figure 1D(6) is a cross-sectional view of the manufacturing process structure of the peripheral circuit area of ​​the dynamic random access memory circuit structure, drawn based on Figure 1D(1). Figure 1E(1) shows a top view of the process structure after at least one heat-conducting area has been formed in at least one hollowed-out groove; Figures 1E(2), 1E(3), 1E(4), and 1E(5) are cross-sectional views of the structure drawn along tangents CE1, CE2, CE3, and CE4 in Figure 1E(1); Figure 1E(6) is a cross-sectional view of the manufacturing process structure of the peripheral circuit area of ​​the dynamic random access memory circuit structure drawn based on Figure 1E(1). Figure 1F(1) shows a top view of the fabrication structure after the formation of a silicon oxide hard mask layer and another amorphous carbon (aC) layer; Figures 1F(2), 1F(3), 1F(4), and 1F(5) are cross-sectional views of the structure drawn along tangents CF1, CF2, CF3, and CF4 in Figure 1F(1); Figure 1F(6) is a cross-sectional view of the manufacturing process structure of the peripheral circuit area of ​​the dynamic random access memory circuit structure drawn based on Figure 1F(1). Figure 1G(1) shows a top view of the process structure after the formation of a plurality of gate recesses and a plurality of character line trenches; Figures 1G(2), 1G(3), 1G(4), and 1G(5) are cross-sectional views of the structure drawn along tangents CG1, CG2, CG3, and CG4 in Figure 1G(1); Figure 1G(6) is a cross-sectional view of the manufacturing process structure of the peripheral circuit area of ​​the dynamic random access memory circuit structure drawn based on Figure 1G(1). Figure 1H(1) shows a top view of the fabrication structure after the semiconductor circuit structure has been fabricated; Figures 1H(2), 1H(3), 1H(4), and 1H(5) are cross-sectional views of the structure drawn along the tangents CH1, CH2, CH3, and CH4 in Figure 1H(1); Figure 1H(6) is a cross-sectional view of the process structure of the peripheral circuit area of ​​the semiconductor circuit structure (dynamic random access memory circuit structure) drawn according to Figure 1H(1). Implementation

[0019] This specification provides a semiconductor circuit structure and its fabrication method, which can effectively reduce the junction temperature of transistors. To make the above-described embodiments and other objects, features, and advantages of this specification more apparent and understandable, several preferred embodiments are described below in detail with reference to the accompanying drawings.

[0020] However, it must be noted that these specific implementation examples and methods are not intended to limit the present invention. The present invention can still be implemented using other features, elements, methods, and parameters. The proposed preferred embodiments are merely illustrative of the technical features of the present invention and are not intended to limit the scope of the patent application. Those skilled in the art will be able to make equivalent modifications and variations based on the description in the following specification without departing from the spirit and scope of the present invention. In different embodiments and drawings, the same elements will be represented by the same element symbols.

[0021] Example 1

[0022] This embodiment discloses a semiconductor circuit structure 100 with high heat dissipation capability. Taking a dynamic random access memory circuit structure including a memory cell circuit area and a peripheral circuit area as an example, the steps and methods for manufacturing the semiconductor circuit structure 100 are detailed below: Step S11: Provide a semiconductor substrate 101; Step S12: A composite isolation structure 102 is formed in the semiconductor substrate 101 to define at least one active region 101A within the semiconductor substrate 101; wherein the composite isolation structure 102 includes a high thermal conductivity region 106, the thermal conductivity of which is higher than that of silicon oxide; wherein step S12 of forming the composite isolation structure 102 includes sub-steps S121-S124: Sub-step S121: Forming a shallow trench isolation region with a shallow trench isolation structure 103; wherein the shallow trench isolation structure 103 extends from the original surface 101S of the semiconductor substrate 101 into the semiconductor substrate 101 and defines at least one active region 101A; Sub-step S122: Remove all or part of the shallow trench isolation structure 103 to define at least one hollowed-out trench 104; Sub-step S123: Forming a dielectric layer 105 on the bottom 104B and sidewall 104S of at least one hollowed-out trench 104; and Sub-step S124: Fill at least one hollow trench 104 with a high thermal conductivity material to form a high thermal conductivity region 106, and isolate the high thermal conductivity region 106 from the semiconductor substrate 101 by a dielectric layer 105; Step S13: Form at least one transistor 107 using at least one active region 101A as a substrate. Step S13, which forms the transistor 107, includes sub-steps S131-S134: Sub-step S131: Form at least one gate recess 108 extending from the original surface 101S into at least one active region 101A of the semiconductor substrate 101; Sub-step S132: Form a gate dielectric layer 107L, covering the bottom and sidewalls of at least one gate recess 108; Sub-step S133: Forming at least one gate electrode 107E in at least one gate recess 108; and Sub-step S134: Form at least one source region 107S and one drain region 107D in at least one active region 101A, and adjacent to at least one gate electrode 107E.

[0023] Please refer to step S11: A semiconductor substrate 101 is provided. In some embodiments of this specification, the semiconductor substrate 101 may be a silicon-containing substrate, such as a silicon wafer or a silicon-on-insula (SOI) substrate. In some other embodiments of this specification, the semiconductor substrate 101 may be made of other types of semiconductor materials such as silicon carbide (SiC), germanium (Ge), or compound semiconductor materials such as gallium arsenide (GaAs). In this embodiment, the semiconductor substrate 101 may be a silicon wafer.

[0024] Please refer to step S12: A composite isolation structure 102 is formed in the semiconductor substrate 101 to define at least one active region 101A within the semiconductor substrate 101; wherein, the composite isolation structure 102 includes a high thermal conductivity region 106, whose thermal conductivity is higher than that of silicon oxide; wherein, step S12 of forming the composite isolation structure 102 includes sub-steps S121-S124:

[0025] Please refer to sub-step S121: forming a shallow trench isolation region with a shallow trench isolation structure 103; wherein the shallow trench isolation structure 103 extends from the original surface 101S of the semiconductor substrate 101 into the semiconductor substrate 101 and defines at least one active region 101A. Taking a dynamic random access memory circuit structure including a memory cell circuit region and a peripheral circuit region 101P as an example, Figure 1A(1) is a top view of the process structure after the shallow trench isolation structure 103 is formed to extend into the semiconductor substrate 101 to define at least one active region 101A, according to an embodiment of this specification. Figures 1A(2), 1A(3), 1A(4), and 1A(5) are cross-sectional views of the structure drawn along the tangents CA1, CA2, CA3, and CA4 in Figure 1A(1), respectively. Figure 1A(6) is a cross-sectional view of the process structure of the peripheral circuit area 101P of the dynamic random access memory circuit structure, based on Figure 1A(1).

[0026] The formation of the shallow trench isolation structure 103 includes the following steps: First, an etching process is performed using a patterned pad dielectric layer 109 (including a patterned pad silicon oxide layer and a patterned pad silicon nitride layer (not shown)) as an etching mask to remove a portion of the silicon material of the semiconductor substrate 101, thereby forming a plurality of shallow trenches 103T. Then, dielectric material is filled into the shallow trenches 103T to define a plurality of fin structures in the semiconductor substrate 101. In some embodiments of this specification, silicon oxide is filled into the shallow trenches 103T, and the remaining semiconductor structure of each dielectric material can serve as an active region 101A.

[0027] Next, refer to sub-step S122: Remove a portion of the shallow trench isolation structure 103 to define at least one hollowed-out groove 104. The formation of the hollowed-out groove 104 includes the following steps:

[0028] First, a hard mask layer 110 is deposited on the pad dielectric layer 109. The hard mask layer 110 includes a first silicon oxide layer 110a, an amorphous carbon layer 110b, a silicon nitride layer 110c, and a second silicon oxide layer 110d. A first patterned bottom anti-reflective coating (BARC) 111 is formed on the hard mask layer 110. A molecular layer deposition (MLD) layer 112 is formed on the first patterned bottom anti-reflective coating, and after planarization, a second patterned bottom anti-reflective coating 113 is formed on the MLD layer 112 (surrounded by another MLD layer of the same material as the MLD layer 112). Then, a recessed gate pattern 114 is defined using self-aligned double patterning (SADP) technology (or a word line pattern is defined in the semiconductor substrate 101 of the memory cell circuit region of the dynamic random access memory circuit structure).

[0029] As shown in Figures 1B(1) to 1B(6), Figure 1B(1) is a top view of the process structure after the recessed gate pattern 114 has been defined. Figures 1B(2), 1B(3), 1B(4), and 1B(5) are cross-sectional views of the structure drawn along the tangents CB1, CB2, CB3, and CB4 in Figure 1B(1), respectively. Figure 1B(6) is a cross-sectional view of the process structure of the peripheral circuit area 101P of the dynamic random access memory circuit structure, drawn according to Figure 1B(1).

[0030] Then, using the recessed gate pattern 114 as an etching mask, at least one etching process is performed to remove a portion of the hard mask layer 110, forming multiple recesses 110O, exposing a portion of the pad dielectric layer 109 and the shallow trench isolation structure 103. A silicon nitride layer 115 (also known as a first capping layer) is then formed to fill the plurality of recesses 110O. After etching back the silicon nitride layer 115, the recessed gate pattern 114 can be transferred onto the remaining silicon nitride layer 115. Simultaneously, a portion of the hard mask layer 110 above the semiconductor substrate 101 of the peripheral circuit region 101P in the dynamic random access memory circuit structure is protected and no recesses 110O are formed. Furthermore, the above process can be included in standard processes for fabricating dynamic random access memory circuit structures.

[0031] As shown in Figures 1C(1) to 1C(6), Figure 1C(1) is a top view of the process structure after the recessed gate pattern has been transferred to the remaining silicon nitride layer. Figures 1C(2), 1C(3), 1C(4), and 1C(5) are cross-sectional views of the structure drawn along tangents CC1, CC2, CC3, and CC4 in Figure 1C(1), respectively. Figure 1C(6) is a cross-sectional view of the process structure of the peripheral circuit area of ​​the dynamic random access memory circuit structure, based on Figure 1C(1).

[0032] After the remaining portion of the hard mask layer 110 and a portion of the pad dielectric layer 109 covered by the remaining portion of the hard mask layer 110 are stripped, an etching process is performed using the remaining portion of the silicon nitride layer 115 as an etching mask to remove a portion of the shallow trench isolation structure 103, forming at least one hollow trench 104 (also referred to as a shallow trench) within the shallow trench isolation structure 103, and retaining a portion of the shallow trench isolation structure 103 covered by the remaining portion of the silicon nitride layer 115 (i.e., the recessed gate pattern 114 transferred onto the silicon nitride layer 115) (as illustrated in Figures 1D(3) and 1D(5)). Although, as shown in Figure 1D(2), there is no remaining shallow trench isolation structure 103 in the hollow trench 104, other embodiments of this specification are not limited thereto. In another embodiment, a portion of the shallow trench isolation structure 103 may be retained in the hollow trench 104 (as illustrated). In some embodiments of this specification, each active region 101A is surrounded by a hollowed-out groove 104.

[0033] As shown in Figures 1D(1) to 1D(6), Figure 1D(1) is a top view of the process structure after at least one hollowed-out groove 104 has been formed. Figures 1D(2), 1D(3), 1D(4), and 1D(5) are cross-sectional views of the structure drawn along tangents CD1, CD2, CD3, and CD4 in Figure 1D(1), respectively. Figure 1D(6) is a cross-sectional view of the process structure of the peripheral circuit area 101P of the dynamic random access memory circuit structure, drawn according to Figure 1D(1).

[0034] Please refer to sub-step S123: A dielectric layer 105 is formed on the bottom 104B and sidewalls 104S of at least one hollow trench 104. In some embodiments of this specification, the dielectric layer 105 covering the active region 101A and the sidewalls 104S and bottom 104B of at least one hollow trench 104 can be formed by a dielectric material deposition process. In this embodiment, the dielectric layer 105 is a silicon oxide film (with a thickness of approximately 2 to 3 nanometers) formed on the exposed portion of the semiconductor substrate 101 via at least one hollow trench 104 by a thermal oxidation process.

[0035] Please refer to sub-step S124: Fill at least one hollow trench 104 with a high thermal conductivity material to form at least one high thermal conductivity region 106, and isolate the high thermal conductivity region 106 from the semiconductor substrate 101 by a dielectric layer 105. The at least one high thermal conductivity region 106, the dielectric layer 105, and the remaining portion (if any) of the shallow trench isolation structure 103 can be combined to form a composite isolation structure 102 (or composite shallow trench isolation region) surrounding each active region 101A.

[0036] As shown in Figures 1E(1) to 1E(6), Figure 1E(1) is a top view of the process structure after at least one high thermal conductivity region 106 is formed in at least one hollowed-out trench 104. Figures 1E(2), 1E(3), 1E(4), and 1E(5) are cross-sectional views of the structure drawn along tangents CE1, CE2, CE3, and CE4 in Figure 1E(1), respectively. Figure 1E(6) is a cross-sectional view of the process structure of the peripheral circuit region 101P of the dynamic random access memory circuit structure, drawn according to Figure 1E(1).

[0037] In the embodiments of this specification, the high thermal conductivity region 106 can be formed by directly depositing a material with a thermal conductivity greater than that of silicon oxide to fill the hollow trench 104. The high thermal conductivity region 106 can be made of silicon, silicon carbide, boron nitride, aluminum nitride, or any combination thereof.

[0038] For example, to form polycrystalline silicon, undoped amorphous silicon can be deposited at low temperatures, and then laser recrystallization can be performed on the undoped amorphous silicon to obtain large-grained undoped crystalline silicon or undoped polycrystalline silicon. Subsequently, these large-grained undoped crystalline silicon or undoped polycrystalline silicon can be subjected to chemical mechanical polishing (CMP) to achieve the required flatness.

[0039] In this embodiment, to address the gap filling problem, the formation of the high thermal conductivity region 106 may include the following steps: First, amorphous silicon is deposited on a semiconductor substrate 101 to cover the dielectric layer 105 and fill at least one hollow trench 104. In some embodiments of the specification, after the amorphous silicon fills at least one hollow trench 104, the top surface of the amorphous silicon will be approximately 800 nanometers to 2000 nanometers above the top surface of the dielectric layer 105.

[0040] Next, these amorphous silicon particles are subjected to a UV curing process to form seamlessly gap-filled amorphous silicon. Then, laser annealing or rapid thermal annealing is performed to recrystallize the amorphous silicon filling at least one hollow trench 104 into crystalline silicon or polycrystalline silicon, thereby improving the thermal conductivity of the high thermal conductivity region 106. The average grain size of the high thermal conductivity region 106 can be between 0.5 micrometers and 2 micrometers. Subsequently, these large-grain undoped crystalline silicon particles can be subjected to a chemical mechanical polishing process to achieve the required flatness. After the chemical mechanical polishing process, the top surface of the high thermal conductivity region 106 (high thermal conductivity material) is flush with the top surface of the dielectric layer 105.

[0041] Please refer to step S13: At least one transistor 107 is formed on at least one active region 101A as a substrate. Step S13, which forms the transistor 107, includes sub-steps S131-S134:

[0042] Please refer to sub-step S131: At least one gate recess 108 is formed, extending from the original surface 101S into at least one active region 101A of the semiconductor substrate 101. The formation of at least one gate recess 108 includes the following steps:

[0043] First, the high thermal conductivity region 106 is etched back to expose the active region 101A of the semiconductor substrate 101. This ensures that the height (top surface 106S) of the etched high thermal conductivity region 106 is approximately 5 to 30 nanometers, or for example, 10 nanometers, below the original surface 101S of the semiconductor substrate 101 to prevent leakage. In other words, the top surface 106S of the high thermal conductivity region 106 (high thermal conductivity semiconductor material) is lower than the original surface 101S of the semiconductor substrate 101.

[0044] Next, a silicon oxide hard mask layer 116 (also known as a second capping layer) and another amorphous carbon layer 117 are formed sequentially to cover the high thermal conductivity region 106 and the exposed portion of the active region 101A of the semiconductor substrate 101. Then, the amorphous carbon layer 117 is planarized (e.g., by chemical mechanical polishing) using the remaining portion of the silicon nitride layer 115 as a stop layer.

[0045] As shown in Figures 1F(1) to 1F(6), Figure 1F(1) is a top view of the fabrication structure after the formation of the silicon oxide hard mask layer 116 and another amorphous carbon layer 117. Figures 1F(2), 1F(3), 1F(4), and 1F(5) are cross-sectional views of the structure drawn along tangents CF1, CF2, CF3, and CF4 in Figure 1F(1), respectively. Figure 1F(6) is a cross-sectional view of the fabrication structure of the peripheral circuit region 101P of the dynamic random access memory circuit structure, drawn based on Figure 1F(1).

[0046] A combination of a silicon oxide hard mask layer 116 and an amorphous carbon layer 117 is used as the etching mask to perform at least one etching process to remove the remaining nitride layer 115, the patterned pad dielectric layer 109, a portion of the semiconductor substrate 101, and a portion of the shallow trench isolation structure 103 located below the remaining portion of the removed silicon nitride layer 115. This forms multiple word line trenches 118T and multiple gate recesses 108 overlapping with the word line trenches 118T. In this embodiment, the multiple word line trenches 118T can expose a portion of the shallow trench isolation structure 103 between a group of multiple active regions 101A located in the memory cell circuit region of the dynamic random access memory circuit structure; and the multiple gate recesses 108 can expose a portion of the corresponding active region 101A. Notably, each gate recess 108 is located within a corresponding word line trench 118T; and each gate recess 108 is interconnected with its corresponding word line trench 118T.

[0047] As shown in Figures 1G(1) to 1G(6), Figure 1G(1) is a top view of the process structure after the formation of a plurality of gate recesses 108 and a plurality of word line trenches 118T. Figures 1G(2), 1G(3), 1G(4), and 1G(5) are cross-sectional views of the structure drawn along the tangents CG1, CG2, CG3, and CG4 in Figure 1G(1), respectively; Figure 1G(6) is a cross-sectional view of the process structure of the peripheral circuit area 101P of the dynamic random access memory circuit structure drawn according to Figure 1G(1).

[0048] Please refer to sub-step S132: Form a gate dielectric layer 107L covering the bottom and sidewalls of at least one gate recess 108 / corresponding word line trench 118T. In one embodiment of this specification, the gate dielectric layer 107L can be formed using a dielectric material deposition process. However, in this embodiment, the gate dielectric layer 107L is formed using a thermal oxidation process as a silicon oxide layer on a portion of the semiconductor substrate 101 exposed from the gate recess 108 / corresponding word line trench 118T. In another embodiment, the gate dielectric layer 107L can be a high dielectric constant (HK) dielectric layer.

[0049] Please refer to sub-step S133: At least one gate electrode 107E is formed in at least one gate recess 108. In one embodiment of this specification, the formation of the gate electrode 107E includes the following steps: First, a barrier / work function layer 107F (e.g., titanium nitride (TN) layer) is formed to cover the bottom and sidewalls of the gate recess 108 / word line trench 118T. Subsequently, the gate recess 108 / corresponding word line trench 118T is filled with a metallic material 118 (e.g., tungsten (W)) to form the gate electrode 107E in the gate recess 108 and to form a metallic connection line that spans a set of multiple active regions 101 and a portion of the shallow trench isolation structure 103 located between these multiple active regions 101. Next, the metallic material 118 is etched back. Then, a protective layer 119, such as a silicon nitride layer, is formed and fills and covers the gate electrode 107E located in the gate recess 108.

[0050] In this embodiment, a portion of the barrier / work function layer 107F and metal material 118 filling each gate recess 108 can serve as gate electrode 107E; another portion of the barrier / work function layer 107F and metal material 118 retained in the word line trench 118T can serve as word line W, used to connect the gate electrode 107E of the transistor (e.g., transistor 107) in the memory cell area of ​​the dynamic random access memory circuit.

[0051] Please refer to sub-step S134: At least one source region 107S and one drain region 107D are formed in at least one active region 101A, adjacent to at least one gate electrode 107E. The source region 107S is adjacent to one side of the gate electrode 107E; the drain region 107D is adjacent to the other side of the gate electrode 107E. The gate dielectric layer 107L, gate electrode 107E, source region 107S, and drain region 107D formed in the same active region 101A together constitute a transistor 107. In this embodiment, multiple access transistors in the memory cell circuit region of the dynamic random access memory circuit are formed in multiple active regions 101A, and their respective gate electrodes 107E can be interconnected by corresponding bit lines and arranged into an access transistor array. Then, stacked capacitors (not shown) can be formed to connect the source regions 107S of the access transistors in the memory cell circuit region. Next, a series of subsequent processes, such as metal décor processes, are performed to form an interconnect structure (not shown), thus completing the fabrication of the semiconductor circuit structure 100.

[0052] As shown in Figures 1H(1) to 1H(6), Figure 1H(1) is a top view of the fabrication structure after the semiconductor circuit structure 100 has been fabricated. Figures 1H(2), 1H(3), 1H(4), and 1H(5) are cross-sectional views of the structure drawn along the tangents CH1, CH2, CH3, and CH4 in Figure 1H(1), respectively. Figure 1H(6) is a cross-sectional view of the fabrication structure of the peripheral circuit area of ​​the semiconductor circuit structure (dynamic random access memory circuit structure) based on Figure 1H(1).

[0053] In the top view of the dynamic random access memory circuit structure of this embodiment, as shown in Figure 1H(1), there is a gap G between two adjacent active regions 101A. A portion of the composite isolation structure 102 (or composite shallow trench isolation region) located inside the gap G can be referred to as the internal block, and the remaining portion of the composite isolation structure 102 (or composite shallow trench isolation region) located outside the gap G can be referred to as the external block. The internal block can be further divided into a first portion P1 that does not overlap with the metal material 118 (or word line trench 118T) and a second portion P2 that overlaps with the metal material 118 (or word line trench 118T). The metal connection line (metal material 118) can cross the first group of active regions 101A and the second portion P2 of the internal block of the composite isolation structure 102 (or composite shallow trench isolation region).

[0054] In this embodiment, the first portion P1 of the internal block of the composite isolation structure 102 (or composite shallow trench isolation region) includes a portion of a high thermal conductivity region 106 and a dielectric layer 105 (as shown in Figure 1H(2)). The second portion P2 of the internal block of the composite isolation structure 102 (or composite shallow trench isolation region) includes a shallow trench isolation structure 103, but does not include any high thermal conductivity region 106 (as shown in Figure 1H(3)).

[0055] In conventional dynamic random access memory (DRAM) circuit structures, the active region of the memory cell circuit is surrounded by a shallow trench isolation structure made of silicon dioxide, which is a poor conductor of heat. In the embodiments of this specification, since at least a portion of the silicon dioxide shallow trench isolation structure 103 surrounding the active region / transistor is replaced by a high thermal conductivity region 106 with a higher heat dissipation capacity (higher than the silicon dioxide shallow trench isolation structure 103), the efficiency of reducing the transistor junction temperature can be significantly improved. Taking the above-described DRAM circuit structure as an example, most of the silicon dioxide shallow trench isolation structure 103 located in the memory cell circuit area surrounding the active region / access transistor can be removed and replaced with a high thermal conductivity material (as shown in Figure 1H(6)), leaving only a portion of the silicon dioxide shallow trench isolation structure 103 located below the word line W (as shown in Figure 1H(2)). On the other hand, the silicon dioxide shallow trench isolation structure 103 surrounding the active region / transistor in the peripheral region 101P of the dynamic random access memory circuit structure in the peripheral circuit of the circuit structure can be further removed and replaced with a high thermal conductivity material, as shown in Figure 1H(6). The high thermal conductivity material can be a semiconductor material, such as silicon, silicon carbide, boron nitride, aluminum nitride, etc. Taking silicon as an example, according to the above process, after thermal annealing, the silicon grain size can be between 0.1 micrometers and 2 micrometers. Therefore, when the depth of the semiconductor material is between 250 nanometers and 500 nanometers, the number of silicon grains along the depth direction of the semiconductor material is at most 3 (or, the number of silicon grain boundaries is at most 2).

[0056] Since the process and materials for forming the high thermal conductivity region 106 of the shallow trench isolation region can be provided by the standard process of the semiconductor circuit structure 100 and integrated therein, the heat dissipation capability of the semiconductor circuit structure 100 can be effectively improved without increasing expensive costs.

[0057] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

[0058] 100: Semiconductor circuit structure 101: Semiconductor substrate 101A: Active Zone 101S: Original Surface 101P: Peripheral Circuits Area 102: Composite isolation structure 103: Shallow trench isolation structure 103T: Shallow Ditch 104: Hollowed-out groove 104B: Bottom 104S: Sidewall 105: Dielectric layer 106: High thermal conductivity zone 107: Transistor 107E: Gate electrode 107S: Source Region 107D: Drainage Zone 107L: Gate dielectric layer 107F: Barrier / Work Function Layer 108: Gate recess 109: Pad Dielectric Layer 110: Rigid Screen Layer 110a: First silicon oxide layer 110b: Amorphous carbon layer 110c: Silicon nitride layer 110d: Second silicon oxide layer 110O: Concave Chamber 111: Bottom anti-reflective layer 112: Molecular layer deposition layer 113: Bottom anti-reflective layer 114: Recessed gate pattern 115: Silicon nitride layer 116: Silicon oxide hard mask layer 118T: Character line groove 118: Metallic Materials 119: Protective layer CA1, CA2, CA3, CA4: Tangents CB1, CB2, CB3, CB4: Tangents CC1, CC2, CC3, CC4: Tangents CD1, CD2, CD3, CD4: Tangents CE1, CE2, CE3, CE4: Tangent CF1, CF2, CF3, CF4: Tangents CG1, CG2, CG3, CG4: Tangents CH1, CH2, CH3, CH4: Tangents P1: Part 1 P2: Part Two G: Gap W: Character line

Claims

1. A method for fabricating a semiconductor circuit structure, comprising: providing a semiconductor substrate; forming a shallow trench extending from an original surface of the semiconductor substrate into the interior of the semiconductor substrate and located between two adjacent active regions; forming a dielectric layer on one sidewall and a bottom of the shallow trench; filling the shallow trench with a thermally conductive material, wherein the thermally conductive material is isolated from the semiconductor substrate by the dielectric layer; and forming a word line across the two adjacent active regions and the shallow trench, wherein the thermally conductive material located in the shallow trench does not overlap with the word line.

2. A method for fabricating a semiconductor circuit structure as described in claim 1, wherein the step of filling the shallow trench with the thermally conductive material includes: filling the shallow trench with an amorphous semiconductor material; and performing a laser annealing or a thermal annealing process on the amorphous semiconductor material to form the thermally conductive material, wherein the thermally conductive material is a thermally conductive semiconductor material.

3. A method for fabricating a semiconductor circuit structure as described in claim 2, wherein the thermally conductive semiconductor material comprises silicon with an average grain size substantially between 0.1 micrometers (µm) and 2 micrometers.

4. The method for fabricating a semiconductor circuit structure as described in claim 2, wherein before performing the laser annealing or thermal annealing process on the amorphous semiconductor material, the method further includes: curing the amorphous semiconductor material using ultraviolet light.

5. A method for fabricating a semiconductor circuit structure as described in claim 2, wherein a first capping layer covers the two adjacent active regions, and after the shallow trench is filled with the amorphous thermally conductive semiconductor material, the amorphous semiconductor material covers the first capping layer.

6. In the method of fabricating the semiconductor circuit structure as described in claim 5, after filling the shallow trench with the amorphous thermally conductive semiconductor material, a top surface of the amorphous semiconductor material is substantially between 800 nanometers and 2000 nanometers higher than a top surface of the first capping layer.

7. The method for fabricating a semiconductor circuit structure as described in claim 5 further includes a planarization process on the thermally conductive semiconductor material after performing the laser annealing or thermal annealing process on the amorphous semiconductor material.

8. A method for fabricating a semiconductor circuit structure as described in claim 7, wherein after the planarization process, a top surface of the thermally conductive semiconductor material is substantially flush with the top surface of the first cover.

9. The method for fabricating a semiconductor circuit structure as described in claim 7, further comprising, after performing the planarization process, etching the thermally conductive semiconductor material downwards such that a top surface of the etched thermally conductive semiconductor material is substantially lower than the original surface of the semiconductor substrate.

10. A method for fabricating a semiconductor circuit structure as claimed in claim 9, wherein after the thermally conductive semiconductor material is etched downwards, the etched top surface of the thermally conductive semiconductor material is substantially between 5 nanometers and 30 nanometers below the original surface of the semiconductor substrate.

11. The method of fabricating a semiconductor circuit structure as described in claim 9, further comprising, after etching the thermally conductive semiconductor material downward, depositing a second capping layer to cover the top surface of the thermally conductive semiconductor material.

12. A method for fabricating a semiconductor circuit structure as described in claim 2, wherein the thermally conductive semiconductor material comprises silicon; and the number of silicon grains along a depth direction of the thermally conductive semiconductor material is at most three.

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