Semiconductor device and method of forming the same

Abstract

A semiconductor device and a method of forming it are disclosed. The semiconductor device includes: an isolation region; a first dielectric layer above the isolation region; a second dielectric layer above the first dielectric layer; a first source / drain region in the second dielectric layer; a first nanostructure on the sidewall of the first source / drain region; a first gate electrode surrounding the first nanostructure; a first source / drain contact above and electrically connected to the first source / drain region; a conductive feature in the first dielectric layer and the isolation region; and a dielectric feature above the conductive feature and in the second dielectric layer. A first portion of the first source / drain contact may be located between two inner sidewalls of the dielectric feature, and the first portion of the first source / drain contact may be electrically connected to the conductive feature.

Description

Technical Field

[0001] none Prior Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate; and using lithography to pattern the material layers to form circuit components and elements on those material layers.

[0003] The semiconductor industry is constantly shrinking the minimum feature size to integrate more components into a given area, thereby continuously increasing the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). As the semiconductor industry further strives to increase device density, improve performance, and reduce costs, manufacturing and design challenges have led to the emergence of stacked device configurations, such as stacked transistors, including complementary field-effect transistors (CFETs). However, with the reduction of the minimum feature size, additional features are introduced. Summary of the Invention

[0004] none Simple Explanation of the Diagram

[0005] The various aspects of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased. Figure 1 illustrates a perspective view of an exemplary stacked transistor according to some embodiments. Figures 2, 3, 4, 5, 6A, 6B, 6C, 6D, 7A, 7B, 7C, 7D, 8A, 8B, 8C, 8D, 9A, 9B, 9C, 9D, 10A, 10B, 10C, 10D, 11A, 11B, 11C, and 11D are various views of intermediate stages in the manufacture of stacked transistors according to some embodiments. Implementation

[0006] The following disclosure provides many different embodiments or instances for implementing various features of this disclosure. Specific examples of components and arrangements described below are used to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0007] Furthermore, for ease of description, spatial relative terms such as "below," "under," "below," "above," and "above" may be used herein to describe the relationship between one element or feature and another as illustrated in the accompanying drawings. In addition to the orientations depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein shall be interpreted accordingly.

[0008] Various embodiments provide a semiconductor device and a method of forming the same. The semiconductor device may be a stacked transistor, comprising a vertically stacked upper transistor and a lower transistor. Each of the upper and lower transistors may include a gate structure surrounding a respective semiconductor nanostructure and a source / drain region located on a sidewall of the respective semiconductor nanostructure. Source / drain contacts may be located on and electrically connected to the source / drain regions. The semiconductor device may further include a vertical interconnect and a dielectric feature located on the vertical interconnect. Some source / drain contacts may extend through the dielectric feature and be electrically connected to the vertical interconnect. By forming the dielectric feature and forming source / drain contacts extending through the dielectric feature, the capacitance between the vertical interconnect and adjacent gate structures, as well as the capacitance between the source / drain contacts and adjacent gate structures, can be reduced. Therefore, the performance of the semiconductor device can be improved.

[0009] Figure 1 illustrates an example of a stacked transistor 10 according to some embodiments, including field effect transistors (FETs) 10U and 10L. The stacked transistor 10 may be a complementary field-effect transistor (CFET), a nano field-effect transistor (nano-FET), a fin field-effect transistor (fin-FET), etc. Figure 1 is a perspective view, and some features of the stacked transistor 10 are omitted for clarity. The stacked transistor 10 includes a plurality of vertically stacked FETs. For example, the stacked transistor 10 may include a lower nanostructure FET 10L of a first device type (e.g., n-type or p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type or n-type). In embodiments where the stacked transistor 10 is a CFET, the upper nanostructure FET 10U of the second device type is the opposite of the lower nanostructure FET 10L of the first device type. The upper nanostructure FET 10U and the lower nanostructure FET 10L include a semiconductor nanostructure 26 (including a lower semiconductor nanostructure 26L and an upper semiconductor nanostructure 26U), wherein the semiconductor nanostructure 26 serves as the channel region of the nanostructure FET. The lower semiconductor nanostructure 26L is used in the lower nanostructure FET 10L, and the upper semiconductor nanostructure 26U is used in the upper nanostructure FET 10U.

[0010] A gate dielectric layer 78 surrounds the corresponding semiconductor nanostructure 26. Gate electrodes 80 (including a lower gate electrode 80L and an upper gate electrode 80U) are located above the gate dielectric layer 78. Source / drain regions 62 (including a lower epitaxial source / drain region 62L and an upper epitaxial source / drain region 62U) are located on opposite sides of the gate dielectric layer 78 and the corresponding gate electrodes 80. Each source / drain region 62 may refer to a source or a drain, individually or jointly depending on the context. Isolation features (not shown) may be formed to separate selected source / drain regions 62 and / or selected gate electrodes 80.

[0011] Figure 1 further illustrates reference sections A-A' and B-B'. Reference section A-A' can be a vertical section parallel to the longitudinal axis of the semiconductor nanostructure 26 of the stacked transistor 10 and along, for example, the current direction between the source / drain regions 62 of the stacked transistor 10. Reference section A-A' can also be a vertical section perpendicular to reference section B-B' and extending through the source / drain regions 62. Reference sections A-A' and B-B' in Figure 1 may correspond to reference sections A-A' and B-B' shown in some subsequent figures.

[0012] Figures 2 through 11D are various views of intermediate stages in the manufacture of a stacked transistor according to some embodiments, similar to the stacked transistor shown in Figure 1. Figure 2 is a perspective view. Figures 6D, 7D, 8D, 9D, 10D, and 11D are top views, wherein certain features are omitted for illustrative purposes. Reference sections A-A' and B-B' shown in Figures 6D, 7D, 8D, 9D, 10D, and 11D correspond to reference sections A-A' and B-B' shown in Figure 1. Figures 3, 4, 5, 6A, 7A, 8A, 9A, 10A, and 11A are cross-sectional views along reference section A-A' shown in Figures 1, 6D, 7D, 8D, 9D, 10D, and 11D. Figures 6B, 7B, 8B, 9B, 10B, and 11B are cross-sectional views along reference section B-B' shown in Figures 1, 6D, 7D, 8D, 9D, 10D, and 11D. Figures 6C, 7C, 8C, 9C, 10C, and 11C are cross-sectional views along reference section C-C' shown in Figures 6D, 7D, 8D, 9D, 10D, and 11D.

[0013] In Figure 2, a wafer including substrate 20 is provided. Substrate 20 may be a semiconductor substrate, such as a bulk semiconductor, and may be doped or undoped (e.g., by p-type or n-type dopants). Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of substrate 20 may include silicon, germanium, carbon-doped silicon, III-V compound semiconductors, or combinations thereof.

[0014] Semiconductor strips 28 are formed extending upward from the front side of substrate 20. The opposite side of the front side of substrate 20 may be referred to as the back side of substrate 20. Each semiconductor strip 28 includes a semiconductor fin 20' (a patterned portion of substrate 20) and a multilayer stack 22 located on the semiconductor fin 20'. The stacked components of the multilayer stack 22 are referred to hereinafter as nanostructures. Specifically, the multilayer stack 22 includes dummy nanostructures 24A, dummy nanostructures 24B, a lower semiconductor nanostructure 26L, and an upper semiconductor nanostructure 26U. Dummy nanostructures 24A and dummy nanostructures 24B may be further collectively referred to as dummy nanostructures 24, and the lower semiconductor nanostructures 26L and upper semiconductor nanostructures 26U may be further collectively referred to as semiconductor nanostructures 26. Dummy nanostructures 24A are located between adjacent lower semiconductor nanostructures 26L and adjacent upper semiconductor nanostructures 26U. The virtual nanostructure 24B is located between the uppermost lower semiconductor nanostructure 26L and the lowermost upper semiconductor nanostructure 26U.

[0015] The dummy nanostructure 24A is formed of a first semiconductor material, and the dummy nanostructure 24B is formed of a second semiconductor material different from the first semiconductor material. The first and second semiconductor materials can be selected from candidate semiconductor materials of the substrate 20. The first and second semiconductor materials have high etch selectivity towards each other. Therefore, in subsequent processes, the removal rate of the dummy nanostructure 24B can be faster than that of the dummy nanostructure 24A.

[0016] Semiconductor nanostructure 26 (including lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U) is formed of one or more third semiconductor materials. The third semiconductor material can be selected from candidate semiconductor materials of substrate 20. Lower semiconductor nanostructure 26L and upper semiconductor nanostructure 26U can be formed of the same semiconductor material or different semiconductor materials. Furthermore, the first and second semiconductor materials of dummy nanostructure 24 have high etch selectivity for the third semiconductor material of semiconductor nanostructure 26. Therefore, in subsequent processes, dummy nanostructure 24 can be selectively removed without significantly removing semiconductor nanostructure 26. In some embodiments, dummy nanostructure 24A is formed of or contains silicon germanium, semiconductor nanostructure 26 is formed of silicon, and dummy nanostructure 24B can be formed of germanium or silicon germanium with a higher percentage of germanium atoms than dummy nanostructure 24A.

[0017] The lower semiconductor nanostructure 26L will serve as the channel region for the lower nanostructure FET of the stacked transistors. The upper semiconductor nanostructure 26U will serve as the channel region for the upper nanostructure FET of the stacked transistors. The semiconductor nanostructure 26 located directly above / below (e.g., at a contact) the dummy nanostructure 24B can be used for isolation and may or may not serve as the channel region for the stacked transistors. The dummy nanostructure 24B will then be replaced by isolation structures that define the boundaries between the lower and upper nanostructure FETs.

[0018] To form the semiconductor strip 28, first, second, and third semiconductor material layers (arranged as described above) can be deposited on the substrate 20. The first, second, and third semiconductor material layers can be grown using processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited using processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD). Then, a patterning process can be applied to the first, second, and third semiconductor material layers and the substrate 20 to define the semiconductor strip 28, which includes semiconductor fins 20', dummy nanostructures 24, and semiconductor nanostructures 26.

[0019] For example, the patterning process may include one or more lithography processes, including dual patterning or multi-patterning processes. Typically, dual or multi-patterning processes combine lithography and self-alignment processes to allow the creation of patterns with pitches, for example, smaller than that achievable using a single direct lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a lithography process. Spacers are formed alongside the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as an etch mask for the patterning process to etch the first, second, and third semiconductor material layers and the substrate 20. Etching can be performed by any acceptable etch process, such as reactive ion etching (RIE), neutral beam etching (NBE), or combinations thereof. Etching can be anisotropic.

[0020] As shown in Figure 2, an STI region 34 is formed over the substrate 20 and between adjacent semiconductor strips 28. The STI region 34 may include a dielectric pad and a dielectric material located above the dielectric pad. Each of the dielectric pad and the dielectric material may include an oxide (such as silicon oxide), a nitride (such as silicon nitride), or a combination thereof. Forming the STI region 34 may include depositing a dielectric layer and performing a planarization process (such as a chemical mechanical polishing (CMP) process, a mechanical polishing process, etc.) to remove excess dielectric material. The deposition process may include ALD, high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), or a combination thereof. In some embodiments, the STI region 34 includes silicon oxide formed by an FCVD process, followed by an annealing process. The dielectric layer is then recessed to define the STI region 34. The dielectric layer can be recessed so that the upper portion of the semiconductor strip 28 (including the multilayer stack 22) protrudes above the remaining STI region 34.

[0021] After forming the STI region 34, a dummy gate stack 42 may be formed above and along the sidewalls of the upper portion of the semiconductor strip 28 (the portion protruding above the STI region 34). Forming the dummy gate stack 42 may include forming a dummy dielectric layer 36 on the semiconductor strip 28. The dummy dielectric layer 36 may be formed of or contain materials such as silicon oxide, silicon nitride, or combinations thereof, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 38 is formed above the dummy dielectric layer 36. The dummy gate layer 38 may be deposited, for example, via physical vapor deposition (PVD), CVD, or other techniques, and then planarized, for example, by a CMP process. The material of the dummy gate layer 38 may be conductive or non-conductive and may be selected from the group including amorphous silicon, polycrystalline silicon, polycrystalline silicon germanium, etc.

[0022] A mask layer 40 is formed over a planarized dummy gate layer 38 and may include, for example, silicon nitride, silicon oxynitride, etc. Next, the mask layer 40 can be patterned via lithography and etching processes to form a mask (not shown), and then the dummy gate layer 38 is etched and patterned using this mask, and possibly the dummy dielectric layer 36 is etched and patterned. The remaining portions of the mask layer 40, the dummy gate layer 38, and the dummy dielectric layer 36 form a dummy gate stack 42.

[0023] In Figure 3, a gate spacer 44 and a source / drain groove 46 are formed. First, the gate spacer 44 is formed above the multilayer stack 22 and on the exposed sidewalls of the dummy gate stack 42. The gate spacer 44 can be formed by conformally forming one or more dielectric layers and subsequently anisotropically etching the dielectric layers. Suitable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, etc., and can be formed by deposition processes such as CVD, ALD, etc. The mask layer 40 and the gate spacer 44 can be used to protect the dummy gate layer 38 during subsequent etching processes.

[0024] Subsequently, a source / drain recess 46 is formed in the semiconductor strip 28 (see Figure 2). The source / drain recess 46 is formed by etching and can extend through the multilayer stack 22 and into the semiconductor fin 20'. The bottom surface of the source / drain recess 46 can be located above, below, or flush with the top surface of the STI region 34 (not shown). During the etching process, the gate spacer 44 and the dummy gate stack 42 shield some portions of the semiconductor strip 28. Etching can include a single etching process or multiple etching processes. A timing etching process can be used to terminate the etching of the source / drain recess 46 when it reaches a selected depth.

[0025] In Figure 4, dummy nanostructure 24A is partially removed, and dummy nanostructure 24B is completely removed. Then, an inner spacer 54 and a dielectric isolation layer 56 are formed. After the partial removal of dummy nanostructure 24A, the sidewalls of dummy nanostructure 24A can be recessed. Dummy nanostructures 24A and dummy nanostructure 24B can be removed by an appropriate etching process. The etching process can selectively remove material from dummy nanostructures 24A and dummy nanostructure 24B without significantly removing material from the upper semiconductor nanostructure 26U, the lower semiconductor nanostructure 26L, or the semiconductor fin 20'. The etching process can remove dummy nanostructure 24A at a slower rate than dummy nanostructure 24B.

[0026] In embodiments where dummy nanostructure 24B is formed of germanium or silicon-germanium with a high percentage of germanium atoms, dummy nanostructure 24A is formed of silicon-germanium with a low percentage of germanium atoms, and semiconductor nanostructure 26 is formed of germanium-free silicon, the etching process can be a dry etching process using an etchant (such as chlorine and / or the like). Because the dummy gate stack 42 bends around the sidewalls of semiconductor nanostructure 26 (see Figure 2), the dummy gate stack 42 can support the upper semiconductor nanostructure 26U so that the upper semiconductor nanostructure 26U does not collapse when the dummy nanostructure 24B is completely removed.

[0027] An inner spacer 54 may be formed on the recessed sidewall of the dummy nanostructure 24A. A dielectric isolation layer 56 may be formed in the space occupied before the dummy nanostructure 24B is removed. Subsequently, source / drain regions may be formed in the source / drain recess 46, and the dummy nanostructure 24A may be replaced with a corresponding gate structure. The inner spacer 54 may be used to isolate the subsequently formed source / drain regions from the subsequently formed gate structure. The dielectric isolation layer 56 may be used to isolate the upper semiconductor nanostructure 26U from the lower semiconductor nanostructure 26L.

[0028] An inner spacer 54 and a dielectric isolation layer 56 can be formed by conformally depositing a suitable dielectric material in the source / drain groove 46, on the sidewalls of the dummy nanostructure 24A, and between the bottom upper semiconductor nanostructure 26U and the top lower semiconductor nanostructure 26L. The dielectric material can then be etched to remove excess portions. The dielectric material can be a hard dielectric material, such as a carbon-containing dielectric material, such as silicon carbide, silicon carbide, silicon carbonitride, etc. Other low dielectric constant (low-k) materials with a k-value less than about 3.5 can be used. The dielectric material can be formed by a suitable deposition process, such as ALD, CVD, etc. The etching of the dielectric material can be anisotropic or isotropic etching processes.

[0029] In Figure 5, a lower epitaxial source / drain region 62L and an upper epitaxial source / drain region 62U are formed. The lower epitaxial source / drain region 62L is formed in the lower portion of the source / drain groove 46 (see Figure 4). The lower epitaxial source / drain region 62L is in contact with the lower semiconductor nanostructure 26L, but not with the upper semiconductor nanostructure 26U. The upper epitaxial source / drain region 62U is in contact with the upper semiconductor nanostructure 26U, but not with the lower semiconductor nanostructure 26L. The lower epitaxial source / drain region 62L is in contact with inner spacers 54, which electrically insulate the lower epitaxial source / drain region 62L from the dummy nanostructure 24A. The upper epitaxial source / drain region 62U is in contact with inner spacers 54, which electrically insulate the upper epitaxial source / drain region 62U from the dummy nanostructure 24A. In subsequent processes, the dummy nanostructure 24A will be replaced by a replacement gate.

[0030] The lower epitaxial source / drain region 62L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source / drain region 62L is an n-type source / drain region, the corresponding material may include silicon or carbon-doped silicon, doped with n-type dopants such as phosphorus, arsenic, etc. When the lower epitaxial source / drain region 62L is a p-type source / drain region, the corresponding material may include silicon or silicon-germanium, doped with p-type dopants such as boron, indium, etc. The lower epitaxial source / drain region 62L may be in-situ doped and may or may not have the corresponding p-type or n-type dopants planted. During the epitaxy of the lower epitaxial source / drain region 62L, the exposed surface (e.g., sidewall) of the upper semiconductor nanostructure 26U may be shielded to prevent unwanted epitaxial growth on the upper semiconductor nanostructure 26U. After the epitaxial source / drain region 62L is grown, the mask on the upper semiconductor nanostructure 26U can be removed.

[0031] Due to the epitaxial process used to form the lower epitaxial source / drain region 62L, the upper surface of the lower epitaxial source / drain region 62L has a face that extends laterally outward beyond the sidewalls of the multilayer stack 22. In some embodiments, adjacent lower epitaxial source / drain regions 62L remain separated after the epitaxial process is completed. In other embodiments, these faces cause adjacent lower epitaxial source / drain regions 62L of the same FET to merge.

[0032] A first contact etch stop layer (CESL) 66 and a first ILD 68 are formed above the lower epitaxial source / drain region 62L. The first CESL 66 can be formed from a dielectric material with high etch selectivity to the etching of the first ILD 68, such as silicon nitride, silicon oxide, or silicon oxynitride, and can be formed by any suitable deposition process, such as CVD or ALD. The first ILD 68 can be formed from a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Suitable dielectric materials for the first ILD 68 may include silicon phosphate glass (PSG), borosilicate glass (BSG), borosilicate silica glass (BPSG), undoped silica glass (USG), silicon oxide, etc.

[0033] The fabrication process may include the following steps: depositing a conformal CESL layer; depositing material for the first ILD 68, followed by a planarization process; and then performing an etch-back process. In some embodiments, the first ILD 68 is first etched, leaving the first CESL 66 unetched. An anisotropic etch process is then performed to remove the portion of the first CESL 66 above the recessed first ILD 68. After recessing, the sidewalls of the on-semiconductor nanostructure 26U are exposed.

[0034] Then, an upper epitaxial source / drain region 62U is formed in the upper portion of the source / drain recess 46. The upper epitaxial source / drain region 62U may be epitaxially grown from the exposed surface of the upper semiconductor nanostructure 26U. The material of the upper epitaxial source / drain region 62U may be selected from the same group of candidate materials used to form the lower epitaxial source / drain region 62L, depending on the selected conductivity type of the upper epitaxial source / drain region 62U. In embodiments where the stacked transistor is a CFET, the conductivity type of the upper epitaxial source / drain region 62U may be opposite to that of the lower epitaxial source / drain region 62L. For example, the upper epitaxial source / drain region 62U may be doped in opposite directions to the lower epitaxial source / drain region 62L. Alternatively, the upper epitaxial source / drain region 62U and the lower epitaxial source / drain region 62L may have the same conductivity type. The epitaxial source / drain region 62U can be in-situ doped and / or implanted with n-type or p-type dopants.

[0035] Due to the epitaxial process used to form the epitaxial source / drain regions 62U, the upper surface of the epitaxial source / drain regions 62U has a face that extends laterally outward beyond the sidewalls of the multilayer stack 22. In some embodiments, adjacent epitaxial source / drain regions 62U remain separated after the epitaxial process is completed. In other embodiments, these faces cause adjacent epitaxial source / drain regions 62U of the same FET to merge.

[0036] After forming the epitaxial source / drain region 62U, a second CESL 70 and a second ILD 72 are formed. The materials and formation methods are similar to those of the first CESL 66 and the first ILD 68, respectively, and will not be discussed in detail here. The formation process may include depositing layers of the second CESL 70 and the second ILD 72, and performing a planarization process to remove excess portions of the respective layers. After the planarization process, the top surfaces of the second ILD 72, the gate spacer 44, the masking layer 40 (if present), or the dummy gate layer 38 are substantially coplanar (within the range of process variations). Therefore, the top surface of the masking layer 40 (if present) or the dummy gate layer 38 is exposed via the second ILD 72. In the illustrated embodiment, the masking layer 40 is retained after the removal process. In other embodiments, the masking layer 40 is removed, such that the top surface of the dummy gate layer 38 is exposed via the second ILD 72.

[0037] In Figures 6A through 6D, a gate replacement process is performed to replace the dummy gate stack 42 and the dummy nanostructure 24A with the gate structure 90. Figure 6A shows a cross-sectional view obtainable along reference section A-A' shown in the top view of Figure 6D. Figure 6B shows a cross-sectional view obtainable along reference section B-B' shown in the top view of Figure 6D. Figure 6C shows a cross-sectional view obtainable along reference section C-C' shown in the top view of Figure 6D. For clarity, some features in Figure 6D are omitted. For clarity, the upper semiconductor nanostructure 26U and the upper epitaxial source / drain region 62U are shown in dashed lines in Figure 6D.

[0038] The gate replacement process may include first removing the dummy gate stack 42 and the dummy nanostructure 24A. The dummy gate stack 42 may be removed by one or more suitable etching processes. Then, the dummy nanostructure 24A may be removed by additional suitable etching processes. The etching process for removing the dummy nanostructure 24A may selectively remove material from the dummy nanostructure 24A without significantly removing material from the semiconductor nanostructure 26. In embodiments where the dummy nanostructure 24A comprises silicon germanium and the semiconductor nanostructure 26 comprises silicon, the etching process may be a wet isotropic etching process and may use etchants such as tetramethylammonium hydroxide, ammonium hydroxide, etc.

[0039] Then, a gate dielectric layer 78 can be deposited in the grooves between the gate spacers 44 and on the exposed semiconductor nanostructure 26. The gate dielectric layer 78 can be conformally formed on the exposed surface of the grooves (removed dummy gate stack 42 and dummy nanostructure 24A) including the semiconductor nanostructure 26 and the gate spacers 44. In some embodiments, the gate dielectric layer 78 surrounds all (e.g., four) sides of the semiconductor nanostructure 26. Specifically, the gate dielectric layer 78 can be formed on the top surface of the semiconductor fin 20'; on the top surface, sidewalls, and bottom surface of the semiconductor nanostructure 26; and on the sidewalls of the inner spacers 54.

[0040] The gate dielectric layer 78 may comprise oxides (such as silicon oxide or metal oxides), silicates (such as metal silicates), combinations thereof, and multilayers thereof. The gate dielectric layer 78 may comprise a high dielectric constant (high-k) material having a k value greater than about 7.0, such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, and lead, or combinations thereof. Methods for forming the gate dielectric layer 78 may include molecular-beam deposition (MBD), ALD, PECVD, etc., followed by a planarization process (e.g., CMP) to remove the portion of the gate dielectric layer 78 located above the second ILD 72. Although a single-layer gate dielectric layer 78 may be described, the gate dielectric layer 78 may comprise multiple layers, such as an interface layer and an overlying high-k dielectric layer.

[0041] A lower gate electrode 80L may be formed on a gate dielectric layer 78 surrounding the lower semiconductor nanostructure 26L. The lower gate electrode 80L may surround the lower semiconductor nanostructure 26L. The lower gate electrode 80L may be formed of a metallic material, such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, and combinations thereof, as well as multilayers thereof. Although a single-layer gate electrode is described, the lower gate electrode 80L may include any number of work function tuning layers, any number of barrier layers, any number of adhesive layers, and filler materials. The lower gate electrode 80L may be formed by conformally depositing one or more gate electrode layers and recessing the gate electrode layers. Any acceptable etching process, such as dry etching, wet etching, or combinations thereof, may be performed to recess the gate electrode layers. The etching may be isotropic. Etching the lower gate electrode 80L exposes the upper semiconductor nanostructure 26U.

[0042] The lower gate electrode 80L may be formed of a material suitable for a lower nanostructure FET of a device type. For example, the lower gate electrode 80L may include one or more work function tuning layers formed of a material suitable for a lower nanostructure FET of a device type. In some embodiments, the lower gate electrode 80L includes an n-type work function tuning layer, which may be formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, and combinations thereof. In some embodiments, the lower gate electrode 80L includes a p-type work function tuning layer, which may be formed of titanium nitride, tantalum nitride, and combinations thereof. Alternatively or additionally, the lower gate electrode 80L may include a dipole sensing element suitable for a lower nanostructure FET of a device type. Acceptable dipole sensing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0043] In some embodiments, an isolation layer (not shown) may optionally be formed on the lower gate electrode 80L. The isolation layer serves as an isolation feature between the lower gate electrode 80L and the subsequently formed upper gate electrode 80U. The isolation layer may be formed by conformally depositing a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, and combinations thereof) and subsequently recessing the dielectric material to expose the upper semiconductor nanostructure 26U.

[0044] The upper gate electrode 80U may be formed on the aforementioned isolation layer (if present) or the lower gate electrode 80L. The upper gate electrode 80U may be disposed between the upper semiconductor nanostructures 26U. In some embodiments, the upper gate electrode 80U surrounds the upper semiconductor nanostructure 26U. The upper gate electrode 80U may be formed of the same or similar material as the lower gate electrode 80L and formed by the same or similar processes. The upper gate electrode 80U may be formed of a material suitable for an upper nanostructure FET of a device type. For example, the upper gate electrode 80U may include one or more work function tuning layers (e.g., n-type work function tuning layers and / or p-type work function tuning layers) formed of a material suitable for an upper nanostructure FET of a device type. Although a single-layer upper gate electrode 80U is described, the upper gate electrode 80U may include any number of work function tuning layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0045] A planarization process can then be performed. The planarization process can be a CMP process, an etch-back process, or a combination thereof. After the planarization process, the top surfaces of the upper gate electrode 80U, the gate dielectric layer 78, the second ILD 72, and the gate spacer 44 can be substantially coplanar (within the range of process variations). Each pair of gate dielectric layers 78 and gate electrodes 80 (including the upper gate electrode 80U and / or the lower gate electrode 80L) can be collectively referred to as a "gate structure" 90 (including the upper gate structure 90U and the lower gate structure 90L). Each gate structure 90 extends along three sides (e.g., the top surface, sidewalls, and bottom surface) of the channel region of the semiconductor nanostructure 26 (see Figure 1). The lower gate structure 90L can also extend along the sidewalls and / or the top surface of the semiconductor fin 20'.

[0046] In Figures 7A through 7D, a hard mask 120, a pad 122, and a vertical interconnect 124 are formed via the hard mask 120. The vertical interconnect 124 can electrically connect source / drain contacts 140 (as shown in Figures 11A through 11D) subsequently formed above the vertical interconnect 124 to conductive features (not shown) that can be formed on the back side of the substrate 20 of the stacked transistors. Figure 7A shows a cross-sectional view obtainable along reference section A-A' shown in the top view of Figure 7D. Figure 7B shows a cross-sectional view obtainable along reference section B-B' shown in the top view of Figure 7D. Figure 7C shows a cross-sectional view obtainable along reference section C-C' shown in the top view of Figure 7D. Some features in Figure 7D are omitted for illustrative purposes. For clarity, the upper semiconductor nanostructure 26U and the upper epitaxial source / drain region 62U are shown in dashed lines in Figure 7D.

[0047] The pad 122 and vertical interconnect 124 may extend through the hard mask 120, the second ILD 72, the second CESL 70, the first ILD 68, the first CESL 66, and the STI region 34. The pad 122 may contact the substrate 20. The pad 122 may cover the bottom surface and sidewalls of the vertical interconnect 124, as shown in the cross-sectional views of Figures 7B and 7C. The pad 122 may surround the vertical interconnect 124, as shown in the top view of Figure 7D. The pad 122 may be T-shaped and may include two horizontal protrusions excluding the vertical interconnect 124, as shown in the top view of Figure 7D. The pad 122 and vertical interconnect 124 may also extend through the gate electrode 80, the gate dielectric layer 78, and the gate spacer 44. Therefore, the pad 122 and the vertical interconnect 124 can serve as gate cleaving structures to divide the selected gate structure 90 (including the gate electrode 80 and the gate dielectric layer 78) into discrete and isolated segments. The shape of the pad 122 discussed above can result in the effective separation of the selected gate structure 90.

[0048] A hard mask 120 can first be formed over the gate electrode 80 and the second ILD 72. The hard mask 120 can be formed from a dielectric material with high etch selectivity to the material of the second ILD 72, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and can be formed by any suitable deposition process, such as CVD, ALD, etc. Figures 7A to 7D illustrate an embodiment with a hard mask layer over the gate electrode 80 and the second ILD 72. In other embodiments, a plurality of hard mask layers can be formed over the gate electrode 80 and the second ILD 72. The hard mask 120 can then be patterned using a suitable lithography process to form openings that expose selected portions of the gate electrode 80, the gate dielectric layer 78, the gate spacer 44, the second ILD 72, and the second CESL 70.

[0049] Then, portions of the gate electrode 80, gate dielectric layer 78, gate spacer 44, second ILD 72, second CESL 70, first ILD 68, first CESL 66, and STI region 34 can be removed to form a trench that exposes a portion of the substrate 20. Removal may include a plurality of etching processes using various etchants that effectively remove material from the gate electrode 80, gate dielectric layer 78, gate spacer 44, second ILD 72, second CESL 70, first ILD 68, first CESL 66, and STI region 34. The etching process may be a dry etching process, and the etchant used may include a chlorine-based etchant. In some embodiments, the bottom of the trench may be located within the STI region 34 and may not expose the substrate 20. In some embodiments, the etching process may remove a portion of the substrate 20.

[0050] A liner 122 and a vertical interconnect 124 are then formed in the trench. The liner 122 may cover the surface of the trench, while the vertical interconnect 124 may cover the surface of the liner 122 and fill the remaining space of the trench. The liner 122 may comprise a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, etc. The liner 122 may be formed by a suitable deposition process, such as CVD, ALD, etc. Figures 7A to 7D illustrate an embodiment with one liner. In other embodiments, a plurality of liners may be formed between the vertical interconnect 124 and the surface of the trench. The vertical interconnect 124 may comprise a conductive material with a resistivity of less than about 48 μΩ·cm, such as cobalt, tungsten, molybdenum, copper, ruthenium, etc., or combinations thereof. A conductive material with such resistivity allows the vertical interconnect 124 to have a low resistance. The vertical interconnect 124 may be formed by a suitable deposition process, such as CVD, PVD, etc. Planarization processes, such as CMP, can be performed to remove excess dielectric and conductive materials formed on the top surface of the hard mask 120 during the deposition process.

[0051] In Figures 8A, 8B, 8C, and 8D, a pad 128 and a dielectric feature 130 are formed to replace the upper portion of the vertical interconnect 124, and the hard mask 120 is removed. Replacing the upper portion of the vertical interconnect 124 with the dielectric feature 130 reduces the volume of the vertical interconnect 124, which may result in a smaller capacitance between the vertical interconnect 124 and the gate electrode 80, as discussed in more detail below. Figure 8A shows a cross-sectional view obtainable along reference section A-A' shown in the top view of Figure 8D. Figure 8B shows a cross-sectional view obtainable along reference section B-B' shown in the top view of Figure 8D. Figure 8C shows a cross-sectional view obtainable along reference section C-C' shown in the top view of Figure 8D. For clarity, some features in Figure 8D are omitted. For clarity, the upper semiconductor nanostructure 26U and the upper epitaxial source / drain region 62U are shown in dashed lines in Figure 8D.

[0052] The trench can be formed first by removing the upper portion of the vertical interconnect 124. Removal may include an etching process that selectively removes material from the vertical interconnect 124. The etching process may be a dry etching process, and the etchant used may include a chlorine-based etchant. The etching process may be terminated at a time after a certain amount of material has been removed from the vertical interconnect 124. The trench may expose the inner sidewalls of the pad 122. In some embodiments, after the etching process, the top surface of the vertical interconnect 124 is flush with the top surface of the first ILD 68 (within a range of process variations).

[0053] A liner 128 and a dielectric feature 130 are then formed in the trench. The liner 128 may cover the top surface of the vertical interconnect 124 and the inner sidewalls of the liner 122, while the dielectric feature 130 may cover the surface of the liner 122 and fill the remaining space in the trench. The liner 128 may cover the bottom surface and sidewalls of the dielectric feature 130, as shown in the cross-sectional views of Figures 8B and 8C. In some embodiments, the bottom surface of the liner 128 may be flush with the bottom surface of the second CESL 70 (within process variations). The liner 128 may surround the dielectric feature 130, as shown in the top view of Figure 8D.

[0054] The pad 128 may comprise a dielectric material, such as silicon nitride, silicon oxynitride, silicon oxycarbide, silicon oxycarbide nitride, etc. The pad 122 may be formed by a suitable deposition process, such as CVD, ALD, etc. The dielectric feature 130 may comprise a dielectric material, such as silicon oxide, etc. In some embodiments, the dielectric feature 130 and the second ILD 72 comprise the same material. The dielectric feature 130 may be formed by a suitable deposition process, such as CVD, ALD, etc. A planarization process (such as CMP) may be performed to remove excess dielectric material formed on the top surface of the hard mask 120 and the hard mask 120 during the deposition process. After the planarization process, the top surfaces of the pad 128, dielectric feature 130, pad 122, second ILD 72, second CESL 70, gate spacer 44, upper gate electrode 80U, and gate dielectric layer 78 may be substantially coplanar (within the range of process variations).

[0055] In Figures 9A, 9B, 9C, and 9D, a hard mask 134 is formed, an opening 135 is formed through the hard mask 134, and a pad 136 is formed on the sidewall of the opening 135. Figure 9A shows a cross-sectional view obtainable along reference section A-A' shown in the top view of Figure 9D. Figure 9B shows a cross-sectional view obtainable along reference section B-B' shown in the top view of Figure 9D. Figure 9C shows a cross-sectional view obtainable along reference section C-C' shown in the top view of Figure 9D. For clarity, some features in Figure 9D are omitted. For clarity, the semiconductor nanostructure 26U is shown in dashed lines in Figure 9D.

[0056] A hard mask 134 may be initially formed over the dielectric feature 130 and the second ILD 72. The hard mask 134 may be formed from a dielectric material with high etch selectivity to the materials of the dielectric feature 130 and the second ILD 72, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and may be formed by any suitable deposition process, such as CVD, ALD, etc. Figures 9A to 9D illustrate an embodiment having a hard mask layer over the dielectric feature 130 and the second ILD 72. In other embodiments, a plurality of hard mask layers may be formed over the dielectric feature 130 and the second ILD 72. The hard mask 134 may then be patterned using a suitable lithography process to expose selected portions of the dielectric feature 130, pad 128, pad 122, and the second ILD 72.

[0057] Then, an opening 135 is formed by removing portions of the second ILD 72, the second CESL 70, the dielectric feature 130, the pad 128, and the pad 122. After removal, the opening 135 may extend through the hard mask 134, the second ILD 72, and the second CESL 70, and expose a portion of the epitaxial source / drain region 62U. An opening 135 adjacent to the dielectric feature 130 may also extend through the pad 128 and the dielectric feature 130, and expose the vertical interconnect 124, the pad 122, the first ILD 68, the pad 128, and the dielectric feature 130. Removal may include multiple etching processes using various etchants that can effectively remove material from the second ILD 72, the second CESL 70, the pad 122, the pad 128, and the dielectric feature 130. The etching process may be a dry etching process, and the etchant used may include a chlorine-based etchant.

[0058] The pad 136 may comprise a dielectric material, such as silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, etc. The pad 136 may be formed by first performing an appropriate deposition process (such as CVD, ALD, etc.). After the deposition process, a conformal layer may be formed and cover the lower surface and sidewalls of the opening 135. An etching process (such as an anisotropic dry etching process) may then be performed to remove the lower portion of the conformal layer. After the etching process, the remaining portion of the conformal layer on the sidewalls of the opening 135 (including the pad 128 and the sidewalls of the dielectric feature 130) may be referred to as the pad 136. After the etching process, portions of the epitaxial source / drain region 62U, vertical interconnect 124, pad 122, and the first ILD 68 may be exposed again.

[0059] In Figures 10A, 10B, 10C, and 10D, a metal layer 137 is formed on the sidewalls and lower surface of the opening 135, and a portion of the epitaxial source / drain region 62U is converted into a metal-semiconductor alloy layer 138. Figure 10A shows a cross-sectional view obtainable along reference section A-A' shown in the top view of Figure 10D. Figure 10B shows a cross-sectional view obtainable along reference section B-B' shown in the top view of Figure 10D. Figure 10C shows a cross-sectional view obtainable along reference section C-C' shown in the top view of Figure 10D. For clarity, some features in Figure 10D are omitted. For clarity, the upper semiconductor nanostructure 26U is shown in dashed lines in Figure 10D.

[0060] Metal layer 137 may cover the sidewalls of pad 136 and the exposed surfaces of epitaxial source / drain regions 62U, vertical interconnect 124, pad 122, and first ILD 68. Metal layer 137 may comprise a metallic material capable of reacting with the semiconductor material of the epitaxial source / drain regions 62U, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, zirconium, scandium, yttrium, niobium, molybdenum, ruthenium, etc. Metal layer 137 may be formed by a suitable deposition process, such as CVD, PVD, etc. Metal-semiconductor alloy layer 138 may be located between metal layer 137 and the corresponding epitaxial source / drain regions 62U, and improve the conductivity between metal layer 137 and the corresponding epitaxial source / drain regions 62U. The metal-semiconductor alloy layer 138 may comprise silicide materials (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.) and germanide materials (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.). The metal-semiconductor alloy layer 138 may be formed after the metal layer 137 is formed by an annealing process. During the annealing process, the material of the metal layer 137 may react with the material of the epitaxial source / drain region 62U, and a portion of the epitaxial source / drain region 62U may be converted into the metal-semiconductor alloy layer 138.

[0061] In Figures 11A, 11B, 11C, and 11D, source / drain contacts 140 are formed in opening 135, and the hard mask 134 is removed. The structure shown in Figures 11A, 11B, 11C, and 11D can be referred to as a stacked transistor 150. Figure 11A shows a cross-sectional view obtainable along reference section A-A' shown in the top view of Figure 11D. Figure 11B shows a cross-sectional view obtainable along reference section B-B' shown in the top view of Figure 11D. Figure 11C shows a cross-sectional view obtainable along reference section C-C' shown in the top view of Figure 11D. For clarity, some features in Figure 11D are omitted. For clarity, the upper semiconductor nanostructure 26U is shown in dashed lines in Figure 11D.

[0062] Source / drain contacts 140 may include source / drain contacts 140A and source / drain contacts 140B. The source / drain contact 140 adjacent to dielectric feature 130 may be referred to as source / drain contact 140B, while other source / drain contacts 140 may be referred to as source / drain contacts 140A. Source / drain contacts 140 may be electrically connected to the upper epitaxial source / drain region 62U via metal layer 137 and metal-semiconductor alloy layer 138. Metal layer 137 may cover the lower surface and sidewalls of source / drain contacts 140, as shown in the cross-sectional views of Figures 11B and 11C. Metal layer 137 may surround source / drain contacts 140, as shown in the top view of Figure 11D. The top surfaces of source / drain contacts 140 and the upper gate electrode 80U may be flush.

[0063] Dielectric feature 130 may be located between source / drain contact 140B and adjacent source / drain contact 140A. A first portion of source / drain contact 140B may extend through dielectric feature 130 to be electrically connected to vertical interconnect 124 via metal layer 137, as shown in the cross-sectional view of Figure 11C. The first portion of source / drain contact 140B may protrude into a recess in dielectric feature 130 and may be located between two inner sidewalls of dielectric feature 130, as shown in the top view of Figure 11D. By forming dielectric feature 130 and forming source / drain contact 140B through dielectric feature 130, the volume of vertical interconnect 124 can be reduced, which can result in a smaller capacitance between vertical interconnect 124 and adjacent gate electrode 80, while maintaining sufficient electrical connection between vertical interconnect 124 and epitaxial source / drain region 62U and conductive features (not shown) that may be formed on source / drain contact 140. By forming the source / drain contact 140B through the dielectric feature 130, source / drain contacts 140A and 140B with smaller height and volume can be formed, which can result in a smaller capacitance between the source / drain contact 140 and the adjacent upper gate electrode 80U. Therefore, the performance of the stacked transistor 150 can be improved.

[0064] The height H1 of the source / drain contact 140 may be less than about 50 nm, and the height H2 of the dielectric feature 130 may be less than about 50 nm. In some embodiments, the height H1 and height H2 are the same. The width W1 of the source / drain contact 140 may be in the range of about 1 nm to about 10 nm, and the width W2 of the dielectric feature 130 may be in the range of about 10 nm to about 30 nm. In some embodiments, the ratio of width W2 to width W1 may be in the range of about 3 to about 10. The source / drain contact 140 having this size can result in a small capacitance between the source / drain contact 140 and the adjacent upper gate electrode 80U, while maintaining sufficient electrical connection between the epitaxial source / drain region 62U and the conductive feature (not shown) that may be formed on the source / drain contact 140.

[0065] The source / drain contact 140 may comprise a conductive material with a resistivity of less than about 60 μΩ·cm, such as cobalt, tungsten, molybdenum, copper, ruthenium, or combinations thereof. The source / drain contact 140 may be formed by a suitable deposition process, such as CVD, PVD, etc. A planarization process (such as CMP) may be performed to remove excess conductive material formed on the top surface of the hard mask 134 and on the hard mask 134 during the deposition process. After the planarization process, the top surfaces of the source / drain contact 140, metal layer 137, pad 136, dielectric feature 130, pad 128, pad 122, gate spacer 44, second CESL 70, second ILD 72, gate dielectric layer 78, and upper gate electrode 80U may be substantially coplanar (within the range of process variations).

[0066] After the source / drain contacts 140 are formed, an interconnect structure (not shown) may be formed on the top surface of the source / drain contacts 140. The interconnect structure may include a dielectric layer and conductive features located in the dielectric layer. The conductive features may include conductive lines and vias that are electrically connected to the source / drain contacts 140. In some embodiments, after the interconnect structure is formed, the bottom portion of the substrate 20 and the pad 122 is removed in a subsequent process to expose the bottom surface of the vertical interconnect 124. Conductive features 142 (illustrated in dashed lines in Figures 11B and 11C) may then be formed on the bottom surface of the vertical interconnect 124. Conductive features 142 are electrically connected to the vertical interconnect 124.

[0067] The embodiments disclosed herein have several advantageous features. By forming the dielectric feature 130 and forming the source / drain contact 140B through the dielectric feature 130, the capacitance between the vertical interconnect 124 and the adjacent gate electrode 80, as well as the capacitance between the source / drain contact 140 and the adjacent upper gate electrode 80U, can be reduced. Therefore, the performance of the stacked transistor 150 can be improved.

[0068] In some embodiments, a semiconductor device includes: an isolation region; a first dielectric layer above the isolation region; a second dielectric layer above the first dielectric layer; a first source / drain region in the second dielectric layer; a first nanostructure on a sidewall of the first source / drain region; a first gate electrode surrounding the first nanostructure; a first source / drain contact above the first source / drain region, wherein the first source / drain contact is electrically connected to the first source / drain region; a conductive feature in the first dielectric layer and the isolation region; and a dielectric feature above the conductive feature and in the second dielectric layer, wherein a first portion of the first source / drain contact is located between two inner sidewalls of the dielectric feature, and the first portion of the first source / drain contact is electrically connected to the conductive feature. In some embodiments, the top surfaces of the first source / drain contact and the first gate electrode are flush. In some embodiments, the top surface of the dielectric feature is flush with the top surface of the first source / drain contact. In some embodiments, in a top view, the first portion of the first source / drain contact extends into a recess in the dielectric feature. In some embodiments, the semiconductor device further includes a metal layer located between the first source / drain contact and the conductive feature, and between the first source / drain contact and the first source / drain region. In some embodiments, the semiconductor device further includes a dielectric pad located between the conductive feature and the isolation region, between the conductive feature and the first dielectric layer, and between the dielectric feature and the second dielectric layer. In some embodiments, the semiconductor device further includes a second gate electrode, wherein, in a top view, the dielectric feature is located between the first gate electrode and the second gate electrode.

[0069] In some embodiments, a method of forming a semiconductor device includes the following steps: depositing an isolation region; forming a first nanostructure; growing a first source / drain region over the isolation region, wherein the first source / drain region is located on a sidewall of the first nanostructure; depositing a first dielectric layer over the first source / drain region; forming a first gate electrode over the first nanostructure; forming a trench through the first dielectric layer and into the isolation region; filling a lower portion of the trench with a conductive feature; filling an upper portion of the trench with a dielectric feature above the conductive feature; forming a first opening through the first dielectric layer and the dielectric feature to expose the first source / drain region and the conductive feature; and depositing a first source / drain contact in the first opening, wherein the first source / drain contact is electrically connected to the first source / drain region and the conductive feature, and the top surfaces of the first source / drain contact and the first gate electrode are flush. In some embodiments, the trench divides the first gate electrode into two discrete segments. In some embodiments, a first portion of the first source / drain contact is located between two inner sidewalls of the dielectric feature. In some embodiments, the dielectric feature has a first width, and a first portion of the first source / drain contact has a second width, wherein the ratio of the first width to the second width is in the range of 3 to 10. In some embodiments, the first source / drain contact has the same height as the dielectric feature. In some embodiments, the method further includes the steps of: forming a second nanostructure; growing a second source / drain region over an isolation region, wherein the second source / drain region is located on a sidewall of the second nanostructure; and depositing a second source / drain contact, wherein the second source / drain contact is electrically connected to the second source / drain region, and the dielectric feature is located between the first source / drain contact and the second source / drain contact.

[0070] In some embodiments, a method of forming a semiconductor device includes the steps of: growing a first source / drain region; depositing a first dielectric layer over the first source / drain region; growing a second source / drain region over the first dielectric layer; depositing a second dielectric layer over the second source / drain region; forming a conductive feature in the first dielectric layer adjacent to the first source / drain region; forming a dielectric feature in the second dielectric layer over the conductive feature and adjacent to the second source / drain region; and forming a first source / drain contact in the second dielectric layer, wherein the first source / drain contact is electrically connected to the second source / drain region and the conductive feature, wherein a first portion of the first source / drain contact extends between two inner sidewalls of the dielectric feature. In some embodiments, in a top view, the first portion of the first source / drain contact extends into a recess in the dielectric feature. In some embodiments, the second dielectric layer and the dielectric feature comprise the same material. In some embodiments, the method further includes the step of forming a first gate electrode, wherein a second dielectric layer is located between a first source / drain contact and the first gate electrode, and the top surfaces of the first source / drain contact and the first gate electrode are flush. In some embodiments, the conductive feature and the top surface of the first dielectric layer are flush. In some embodiments, the method further includes the step of forming a metal layer, wherein the metal layer is located between the first source / drain contact and the conductive feature, wherein the metal layer is located between the first source / drain contact and the first dielectric layer, and wherein the metal layer is located between the first source / drain contact and the first source / drain region. In some embodiments, the method further includes the step of depositing a dielectric pad, wherein the dielectric pad is deposited along the sidewalls of the conductive feature and the dielectric feature.

[0071] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of this disclosure.

[0072] 10: Stacked Transistors 10L: Lower nanostructure FET 10U: Top-nano structure FET 20:Substrate 20': Semiconductor fin 22: Multi-layer stacking 24, 24A, 24B: Virtual nanostructures 26: Semiconductor nanostructures 26L: Lower semiconductor nanostructure 26U: Semiconductor Nanostructure 28: Semiconductor Strip 34: STI area 36: Dummy dielectric layer 38: Virtual gate layer 40: Masking layer 42: Dummy gate stack 44: Gate spacer 46: Source / Drain Groove 54: Internal spacers 56: Dielectric isolation layer 62: Source / Drain Region 62L: Lower epitaxial source / drain region 62U: Epitaxial Source / Drain Region 66: First CESL 68: First ILD 70: Second CESL 72: Second ILD 78: Gate dielectric layer 80: Gate electrode 80L: Lower gate electrode 80U: Upper gate electrode 90: Gate structure 90L: Lower gate structure 90U: Top-gate structure 120,134: Hard mask 122, 128, 136: Padding 124: Vertical Interconnect 130: Dielectric characteristics 135: Opening 137: Metal layer 138: Metal-semiconductor alloy layer 140, 140A, 140B: Source / Drain Contacts 142: Electrical conductivity characteristics 150: Stacked Transistors A-A', B-B', C-C': Reference profiles H1, H2: Height W1, W2: Width

Claims

1. A semiconductor device comprising: an isolation region; a first dielectric layer above the isolation region; a second dielectric layer above the first dielectric layer; a first source / drain region in the second dielectric layer; a first nanostructure on a sidewall of the first source / drain region; a first gate electrode surrounding the first nanostructure; a first source / drain contact above the first source / drain region, wherein the first source / drain contact is electrically connected to the first source / drain region; a conductive feature in the first dielectric layer and the isolation region; and a dielectric feature above the conductive feature and in the second dielectric layer, wherein a first portion of the first source / drain contact is located between two inner sidewalls of the dielectric feature, and the first portion of the first source / drain contact is electrically connected to the conductive feature, wherein a top surface of the dielectric feature is flush with a top surface of the first source / drain contact.

2. The semiconductor device as claimed in claim 1, wherein the top surface of the first source / drain contact and the top surface of the first gate electrode are flush.

3. The semiconductor device as claimed in claim 1, further comprising a dielectric pad, wherein the dielectric pad is located between the conductive feature and the isolation region, wherein the dielectric pad is located between the conductive feature and the first dielectric layer, and wherein the dielectric pad is located between the dielectric feature and the second dielectric layer.

4. The semiconductor device as claimed in claim 1, wherein, in a top view, the first portion of the first source / drain contact extends into a recess in the dielectric feature.

5. A method of forming a semiconductor device, the method comprising the steps of: depositing an isolation region; forming a first nanostructure; growing a first source / drain region over the isolation region, wherein the first source / drain region is located on a sidewall of the first nanostructure; depositing a first dielectric layer over the first source / drain region; forming a first gate electrode over the first nanostructure; forming a trench through the first dielectric layer and into the isolation region; filling a lower portion of the trench with a conductive feature; and filling an upper portion of the trench with a dielectric feature above the conductive feature. A first opening is formed through the first dielectric layer and the dielectric feature to expose the first source / drain region and the conductive feature; and a first source / drain contact is deposited in the first opening, wherein the first source / drain contact is electrically connected to the first source / drain region and the conductive feature, a top surface of the first source / drain contact is flush with a top surface of the first gate electrode, and a top surface of the dielectric feature is flush with the top surface of the first source / drain contact.

6. The method as described in claim 5, wherein the trench divides the first gate electrode into two discrete segments.

7. The method of claim 5 further comprises the following steps: forming a second nanostructure; growing a second source / drain region over the isolation region, wherein the second source / drain region is located on a sidewall of the second nanostructure; and depositing a second source / drain contact, wherein the second source / drain contact is electrically connected to the second source / drain region, and the dielectric feature is located between the first source / drain contact and the second source / drain contact.

8. A method of forming a semiconductor device, the method comprising the steps of: growing a first source / drain region; depositing a first dielectric layer over the first source / drain region; growing a second source / drain region over the first dielectric layer; depositing a second dielectric layer over the second source / drain region; forming a conductive feature in the first dielectric layer adjacent to the first source / drain region; forming a dielectric feature in the second dielectric layer over the conductive feature and adjacent to the second source / drain region; and forming a first source / drain contact in the second dielectric layer, wherein the first source / drain contact is electrically connected to the second source / drain region and the conductive feature, wherein a first portion of the first source / drain contact extends between two inner sidewalls of the dielectric feature, and a top surface of the dielectric feature is flush with a top surface of the first source / drain contact.

9. The method as described in claim 8, wherein, in a top view, the first portion of the first source / drain contact extends into a groove in the dielectric feature.

10. The method as described in claim 8 further comprises the step of: depositing a dielectric pad, wherein the dielectric pad is disposed along the conductive feature and the sidewall of the dielectric feature.

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