Semiconductor structure and method for forming the same

Abstract

The semiconductor structure disclosed herein includes: a first active region and a second active region; a first gate structure disposed above the first active region; a second gate structure disposed above the second active region; and a gate isolation feature sandwiched between the sidewalls of the first gate structure and the second gate structure. The gate isolation feature includes: a first dielectric layer, interfacing with the sidewalls of the first gate structure and the second gate structure; a diffusion barrier pad, interfacing with the first dielectric layer; and a second dielectric layer, interfacing with the diffusion barrier pad. The second dielectric layer is separated from the first dielectric layer by the diffusion barrier pad.

Description

Technical Field

[0001] none Prior Technology

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have spawned generations of ICs, each generation featuring smaller and more complex circuits than the previous one. During IC development, functional density (i.e., the number of interconnects per die area) typically increases, while geometry (i.e., the smallest component (or line) that can be produced using manufacturing processes) decreases. This scaling down process typically yields benefits through increased production efficiency and reduced associated costs. This scaling down also increases the complexity of handling and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology has evolved to smaller technology nodes, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing the short-channel effect (SCE). Multi-gate devices generally refer to devices having a gate structure or a portion thereof located on more than one side of the channel region. Fin-like field-effect transistors (FinFETs) and gate-all-around (GAA) transistors are examples of multi-gate devices and have become popular and promising candidates for high-performance and low-leakage applications. FinFETs have a raised channel surrounded by a gate on more than one side (e.g., the gate surrounds the top and sidewalls of a semiconductor material "fin" extending from the substrate). GAA transistors have a gate structure that can extend partially or completely around the channel region to access the channel region on two or more sides. Because the gate structure surrounds the channel region, GAA transistors can also be called surrounding gate transistors (SGT) or multi-bridge-channel (MBC) transistors. The channel region of a GAA transistor can be formed from nanowires, nanosheets, other nanostructures, and / or other suitable structures. The shape of the channel region also gives GAA transistors other names, such as nanosheet transistors or nanowire transistors.

[0004] As the semiconductor industry further advances to technology nodes below 10 nanometers (nm) in pursuit of higher device density, higher performance, and lower costs, the challenges posed by manufacturing and design issues have led to the emergence of stacked device structure configurations, such as complementary field-effect transistors (CFETs). In these CFETs, n-type multi-gate transistors and p-type multi-gate transistors are vertically stacked, with one transistor on top of the other. While existing CFET structures and manufacturing processes are generally sufficient for intended applications, they are not satisfactory in all configurations. Summary of the Invention

[0005] none Simple Explanation of the Diagram

[0006] The contents of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with standard industry practice, the various features are not drawn to scale and are for illustrative purposes only. In practice, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Figure 1 illustrates the layout of the top device layer of an exemplary 6-transistor (6T) static random access memory (SRAM) cell implemented using a CFET construction according to one or more of the present disclosure. Figure 2 illustrates the layout of the bottom device layer of an exemplary 6T SRAM cell implemented using a CFET construction according to one or more of the present disclosure. Figure 3 illustrates the layout of the top device layer of a logic standard cell implemented using a CFET construction according to one or more of the present disclosure. Figure 4 illustrates the layout of the bottom device layer of a logic standard cell implemented using a CFET construction according to one or more of the present disclosure. Figure 5 illustrates a cross-sectional view of one or more specimens according to this disclosure, along line A-A' in Figures 1, 2, 3 or 4. Figure 6 illustrates a cross-sectional view of one or more of the states according to this disclosure along line B-B' in Figures 1, 2, 3 or 4. Figure 7 illustrates a cross-sectional view of one or more specimens according to this disclosure, along line C-C' in Figures 1, 2, 3 or 4. Figure 8 is a flowchart illustrating a method for forming gate isolation features in a CFET structure according to one or more states of this disclosure. Figures 9 through 15 illustrate cross-sectional views of precursor segments undergoing various manufacturing processes in the method of Figure 8, according to one or more of the states disclosed herein. Figure 16 is a schematic diagram illustrating the oxygen blocking benefits of one or more gate isolation features according to this disclosure. Figure 17 is a schematic diagram illustrating the threshold voltage benefit of one or more gate isolation features according to this disclosure. Figure 18 illustrates a flowchart of a method for forming different gate isolation features in different device regions according to one or more states of this disclosure. Figures 19 through 26 illustrate cross-sectional views of precursor segments undergoing various manufacturing processes in the method of Figure 18, according to one or more of the states disclosed herein. Implementation

[0007] The following disclosure provides several different embodiments or examples for implementing various features of the provided object. Specific examples of components and arrangements described below are used to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, forming a first feature above or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0008] Furthermore, for ease of description, spatial relative terms such as "below," "under," "below," "above," and "above" may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0009] Furthermore, when using terms such as "about" or "approximately" to describe a number or range of numbers, the term is intended to encompass a reasonable range of numbers that take into account variations inherent in manufacturing, as understood by one of ordinary skill in the art. For example, based on known manufacturing tolerances associated with a feature having characteristics related to that number, a number or range of numbers encompasses a reasonable range including said number, such as within + / - 10% of said number. For example, a material layer with a thickness of "about 5 nm" can encompass a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerances associated with the deposited material layer are known by one of ordinary skill in the art to be + / - 15%.

[0010] A stacked multi-gate device refers to a semiconductor device comprising a bottom multi-gate device and a top multi-gate device stacked on top of the bottom multi-gate device. When the bottom and top multi-gate devices have different conductivity types, the stacked multi-gate device can be called a complementary field-effect transistor (CFET). The multi-gate devices in a CFET can be FinFETs or GAA transistors. The gate structures of the top and second multi-gate devices can be electrically coupled together or insulated from each other, depending on the design. During the fabrication of a CFET on a substrate, the gate stack can be formed across multiple active regions, and a gate dicing process can be performed to divide the gate stack into multiple segments by gate isolation features. Since each gate isolation feature is located between two gate segments, the industry has been working to reduce or minimize the effective dielectric constant of the gate isolation features. These efforts aim to reduce parasitic capacitance between gate segments and increase device speed.

[0011] The reduction in the dielectric constant of gate isolation features is not without its implications. The low-k dielectric material in gate isolation features often contains oxygen and can become an oxygen source in the gate oxidation process. When the metal in the gate structure oxidizes, the device's threshold voltage may deviate from its design value. These logic devices are less sensitive to threshold voltage drops as long as they can still switch with appropriate response times. However, this is not the case for memory devices, such as static random access memory (SRAM). When the oxidation of components in the gate structure at different locations in an SRAM array is uneven, the minimum supply voltage (Vmin) on the SRAM array may increase, and some SRAM cells may cease normal operation. At least for memory devices, controlling oxygen diffusion from the gate isolation feature is necessary.

[0012] This disclosure provides multiple methods for forming gate isolation features to reduce gate oxidation of devices in memory structures. According to one embodiment, a gate isolation trench is formed in the gate structure of a CFET structure in a logic device region and a memory device region. A nitrogen-containing layer is deposited in the gate isolation trench. A pad is deposited over the nitrogen-containing layer. An oxygen-containing dielectric layer is deposited over the pad. A planarization process is performed to form a gate isolation feature in the gate isolation trench. The pad helps reduce or control oxygen diffusion into the gate structure. According to another embodiment, a first gate isolation trench is formed in the gate structure of a CFET structure in a logic device region and a second gate isolation trench is formed in the gate structure of a CFET structure in a memory device region. A nitrogen-containing dielectric layer is deposited to fill the first and second gate isolation trenches. In the case of covering the memory device region, an inner trench is formed in the nitrogen-containing dielectric layer in the first gate isolation trench. Then, an oxygen-containing dielectric layer is deposited into the inner trench. Then, a planarization process is performed to form a first gate isolation feature in the logic device region and a second gate isolation feature in the memory device region. The first gate isolation feature is used to provide fast switching speed to the logic device, while the second gate isolation feature is used to minimize the diffusion of oxygen into the gate structure of the memory device.

[0013] Gate isolation features can be implemented in the CFET structure of the logic device and memory device. Figures 1 and 2 illustrate the layout of a 6-transistor (6T) static random access memory (SRAM) cell 10 with a CFET structure. Figure 1 illustrates the layout of the top device layer of the SRAM cell 10, and Figure 2 illustrates the layout of the bottom device layer of the SRAM cell 10. Referring to Figure 1, in the top device layer, the SRAM cell 10 includes a first top active region 12T and a second top active region 14T extending longitudinally parallel to each other in the Y direction. As shown in the fragmented cross-sectional views in Figures 4 and 6, each of the first top active region 12T and the second top active region 14T includes a plurality of channel structures or nanostructures also extending longitudinally in the Y direction. A first top gate structure 16T is joined to the first top active region 12T to form a first pull-down transistor (PD1). A second top gate structure 18T is joined to the second top active region 14T to form a second pass-gate transistor (PG2). A third top gate structure 20T is joined to a first top active region 12T to form a first transmission gate transistor (PG1). A fourth top gate structure 22T is joined to a second top active region 14T to form a second pull-down transistor (PD2). The first top gate structure 16T and the second top gate structure 18T extend longitudinally along the X direction and are aligned along the X direction. The third top gate structure 20T and the fourth top gate structure 22T extend longitudinally along the X direction and are aligned along the X direction. A first gate isolation feature 30 extends longitudinally along the Y direction and is disposed between the first top gate structure 16T and the second top gate structure 18T, and between the third top gate structure 20T and the fourth top gate structure 22T. The drains of the first pull-down transistor (PD1) and the second pull-down transistor (PD2) are coupled to ground voltage (Vss) via a first contact via 40 and a second contact via 42. The second gate isolation feature 32 disconnects the first top gate structure 16T. The third gate isolation feature 34 cuts off the fourth top gate structure 22T.

[0014] Referring to Figure 2, in the bottom device layer, the SRAM cell 10 includes a first bottom active region 12B and a second bottom active region 14B extending longitudinally parallel to each other in the Y direction. As shown in the fragmented cross-sectional views in Figures 4 and 6, each of the first bottom active region 12B and the second bottom active region 14B includes a plurality of channel structures or nanostructures also extending longitudinally in the Y direction. A first bottom gate structure 16B is bonded to the first bottom active region 12B to form a first pull-up transistor (PU1). A second bottom gate structure 18B is bonded to the second bottom active region 14B and is electrically floating. A third top gate structure 20T is bonded to the first bottom active region 12B and is electrically floating. A fourth bottom gate structure 22B is bonded to the second bottom active region 14B to form a second pull-up transistor (PU2). The first bottom gate structure 16B and the second bottom gate structure 18B extend longitudinally in the X direction and are aligned in the X direction. The third bottom gate structure 20B and the fourth bottom gate structure 22B extend longitudinally in the X direction and are aligned in the X direction. The first gate isolation feature 30 extends longitudinally along the Y direction to be disposed between the first bottom gate structure 16B and the second bottom gate structure 18B, and between the third bottom gate structure 20B and the fourth bottom gate structure 22B. The source of the first pull-up transistor (PU1) and the source of the second pull-up transistor (PU2) are coupled to the power supply voltage (Vdd) through the third contact via 44 and the fourth contact via 46. The second gate isolation feature 32 cuts off the first bottom gate structure 16B. The third gate isolation feature 34 cuts off the fourth bottom gate structure 22B. It can be seen that the first gate isolation feature 30, the second gate isolation feature 32, and the third gate isolation feature 34 extend through the top device layer and the bottom device layer.

[0015] Figures 3 and 4 illustrate the layout of a logic standard cell 50 with a CFET configuration. Figure 3 illustrates the layout of the top device layer of the logic standard cell 50. As shown in Figure 3, in the top device layer, the logic standard cell 50 includes a first top active region 12T and a second top active region 14T extending longitudinally parallel to each other along the Y direction. As shown in the fragmented cross-sectional views in Figures 4 and 6, each of the first top active region 12T and the second top active region 14T includes a plurality of channel structures or nanostructures also extending longitudinally along the Y direction. A first top gate structure 16T is joined to the first top active region 12T. A second top gate structure 18T is joined to the second top active region 14T. A third top gate structure 20T is joined to the first top active region 12T. A fourth top gate structure 22T is joined to the second top active region 14T. The first top gate structure 16T and the second top gate structure 18T extend longitudinally along the X direction and are aligned along the X direction. The third top gate structure 20T and the fourth top gate structure 22T extend longitudinally along the X direction and are aligned along the X direction. The first gate isolation feature 30 extends longitudinally along the Y direction and is disposed between the first top gate structure 16T and the second top gate structure 18T and between the third top gate structure 20T and the fourth top gate structure 22T. The fourth gate isolation feature 36 cuts off the first top gate structure 16T and the third top gate structure 20T. The fifth gate isolation feature 38 cuts off the second top gate structure 18T and the fourth top gate structure 22T.

[0016] As shown in Figure 4, in the bottom device layer, the logic standard cell 50 includes a first bottom active region 12B and a second bottom active region 14B extending longitudinally parallel to each other along the Y direction. As shown in the fragmented cross-sectional views in Figures 4 and 6, each of the first bottom active region 12B and the second bottom active region 14B includes a plurality of channel structures or nanostructures also extending longitudinally along the Y direction. A first bottom gate structure 16B is engaged with the first bottom active region 12B. A second bottom gate structure 18B is engaged with the second bottom active region 14B. A third bottom gate structure 20B is engaged with the first bottom active region 12B. A fourth bottom gate structure 22B is engaged with the second bottom active region 14B. The first bottom gate structure 16B and the second bottom gate structure 18B extend longitudinally along the X direction and are aligned along the X direction. The third bottom gate structure 20B and the fourth bottom gate structure 22B extend longitudinally along the X direction and are aligned along the X direction. The first gate isolation feature 30 extends longitudinally along the Y direction to be disposed between the first bottom gate structure 16B and the second bottom gate structure 18B, and between the third bottom gate structure 20B and the fourth bottom gate structure 22B. The fourth gate isolation feature 36 cuts off the first bottom gate structure 16B and the third bottom gate structure 20B. The fifth gate isolation feature 38 cuts off the second bottom gate structure 18B and the fourth bottom gate structure 22B.

[0017] It can be seen that SRAM cell 10 and logic standard cell 50 have similarities regarding the first gate isolation feature 30, the first top active region 12T, the second top active region 14T, the first bottom active region 12B, the second bottom active region 14B, the first top gate structure 16T, the second top gate structure 18T, the third top gate structure 20T, the fourth top gate structure 22T, the first bottom gate structure 16B, the second bottom gate structure 18B, the third bottom gate structure 20B, and the fourth bottom gate structure 22B. Figures 5, 6, and 7 illustrate cross-sectional views of segments along line A-A', line B-B', and line C-C' in the X direction and Y direction, respectively.

[0018] Figure 5 illustrates a cross-sectional view along line A-A' in Figures 1, 2, 3, or 4. A first bottom active region 12B includes a first bottom channel structure 106B stacked above the substrate fin 104. A first top active region 12T includes a first top channel structure 106T stacked above the first bottom channel structure 106B. A first bottom gate structure 16B surrounds each first bottom channel structure 106B. A first top gate structure 16T surrounds each first top channel structure 106T. A second top gate structure 18T surrounds each second top channel structure 108T. A second bottom gate structure 18B surrounds each second bottom channel structure 108B. The substrate fin 104 is patterned from a substrate 102, which is omitted in subsequent figures for simplicity. An isolation feature 103 is deposited above the substrate 102 and extends between the sidewalls of the substrate fin 104. The first gate isolation feature 30 extends between the first bottom gate structure 16B and the second bottom gate structure 18B, and between the first top gate structure 16T and the second top gate structure 18T. In some embodiments, the first gate isolation feature 30 extends partially into the isolation feature 103 and between the substrate fins 104. An insulating layer 128 is disposed between the first bottom channel structure 106B and the first top channel structure 106T. In some embodiments, the insulating layer 128 is vertically sandwiched between two intermediate semiconductor layers 106M. In some embodiments, the first bottom gate structure 16B and the second bottom gate structure 18B are p-type gate structures and include a p-type work function metal (p-WFM) layer, while the first top gate structure 16T and the second top gate structure 18T are n-type gate structures and include an n-type work function metal (n-WFM) layer.

[0019] Figure 6 illustrates a cross-sectional view along line B-B' in Figures 1, 2, 3, or 4. The sidewall of the first bottom channel structure 106B contacts the first bottom source / drain feature 150B. The sidewall of the second bottom channel structure 108B contacts the second bottom source / drain feature 160B. The sidewall of the first top channel structure 106T contacts the first top source / drain feature 150T. The sidewall of the second top channel structure 108T contacts the second top source / drain feature 160T. A bottom contact etch stop layer (CESL) 152B is disposed on the surfaces of the isolation feature 103, the first bottom source / drain feature 150B, and the second bottom source / drain feature 160B. A bottom interlayer dielectric (ILD) 154B is disposed above the bottom CESL 152B. The top CESL 152T is located on the surface of the first top source / drain feature 150T and the surface of the second top source / drain feature 160T. The top ILD layer 154T is disposed above the top CESL 152T.

[0020] Figure 7 illustrates a cross-sectional view along line C-C' in Figures 1, 2, 3, or 4. As shown in Figure 7, the first bottom channel structure 106B is sandwiched between two first bottom source / drain features 150B; the first top channel structure 106T is sandwiched between two first top source / drain features 150T. Similarly, although not explicitly shown in any cross-sectional view, the second bottom channel structure 108B is sandwiched between two second bottom source / drain features 160B; the second top channel structure 108T is sandwiched between two first top source / drain features 150T.

[0021] The methods described below, such as method 200 in Figure 8 and method 400 in Figure 18, include the operation of forming different gate isolation features to replace the first gate isolation feature 30 shown in Figures 1 through 6. That is, Figures 1 through 7 provide details of the structure surrounding the gate isolation feature formed using method 200 or method 400.

[0022] Figures 8 and 18 are flowcharts illustrating methods 200 and 400 for forming gate isolation features in CFET structures in logic device regions and memory device regions according to various states of this disclosure. Methods 200 and 400 are merely examples and are not intended to limit this disclosure to the content explicitly described in methods 200 and 400. Additional steps may be provided before, during, and after methods 200 and 400, and some described steps may be replaced, eliminated, or moved for additional embodiments of the method. For simplicity, not all steps are described in detail herein. Method 200 is described below with reference to Figures 9 through 15, which are partial cross-sectional views of precursor structures at different manufacturing stages according to embodiments of method 200. Method 400 is described below with reference to Figures 19 through 26, which are partial cross-sectional views of precursor structures at different manufacturing stages according to embodiments of method 400. Since the precursor structure will be formed into semiconductor device 100 after the manufacturing process is completed, the precursor structure may be referred to as semiconductor device 100 as needed by the context. Furthermore, in this application and various embodiments, unless otherwise stated, the same element symbols denote the same features having similar structures and compositions. Source / drain regions may refer individually or collectively to the source or drain, depending on the context.

[0023] Method 200 forms the same type of gate isolation feature in the logic device region and the memory device region.

[0024] Referring to Figures 8 and 9, method 200 includes block 202: forming a hard mask layer 170 over a precursor structure. The precursor structure includes: a substrate 102 (shown in dashed lines and omitted in subsequent figures); base fins 104 formed from the substrate 102; isolation features 103 located above the substrate 102 and disposed between the base fins 104; a first bottom channel structure 106B; a second bottom channel structure 108B; a first top channel structure 106T; a second top channel structure 108T; a bottom gate structure 80 surrounding the first bottom channel structure 106B and the second bottom channel structure 108B; and a top gate structure 90 surrounding the first top channel structure 106T and the second top channel structure 108T.

[0025] In one embodiment, substrate 102 may be a silicon (Si) substrate. In some other embodiments, substrate 102 may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Exemplary III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). Substrate 102 may also include an insulating layer, such as a silicon oxide layer, to have a silicon-on-insulator (SOI) structure. Base fin 104 is formed from substrate 102 and may share the same composition as substrate 102. In one embodiment, base fin 104 may include silicon (Si). Isolation feature 103 may also be referred to as shallow trench isolation (STI) feature 103. The isolation feature 103 may include silicon oxide, silicon oxynitride, fluorosilicone glass (FSG), a low-k dielectric layer and combinations thereof, and / or other suitable materials.

[0026] The first bottom channel structure 106B, the second bottom channel structure 108B, the first top channel structure 106T, and the second top channel structure 108T are formed by epitaxial layer stacking on a substrate 102. In an exemplary process, the epitaxial layer stack includes a plurality of silicon layers interleaved with a plurality of silicon-germanium layers. After patterning the stack to form a fin structure, a dummy gate stack is formed over the fin structure. After forming the source / drain features, the dummy gate stack is selectively removed, and the silicon-germanium layers are selectively removed to release the first bottom channel structure 106B, the second bottom channel structure 108B, the first top channel structure 106T, and the second top channel structure 108T. In some embodiments, the first bottom channel structure 106B, the second bottom channel structure 108B, the first top channel structure 106T, and the second top channel structure 108T may include silicon (Si). A bottom gate structure 80 is deposited to surround each of the first bottom channel structure 106B and the second bottom channel structure 108B. A top gate structure 90 is deposited to surround each of the first top channel structure 106T and the second top channel structure 108T. The precursor structure further includes two intermediate semiconductor layers 108M. An insulating layer 128 is vertically disposed between the two intermediate semiconductor layers 108M. The insulating layer 128 may include silicon oxide, silicon nitride, or silicon oxynitride to separate the bottom channel structure from the top channel structure.

[0027] The bottom gate structure 80 includes: an interface layer, interfacing with a first bottom channel structure 106B and a second bottom channel structure 108B; a gate dielectric layer 114, located above the interface layer; and a bottom gate electrode, located above the gate dielectric layer 114. In some embodiments, the interface layer may include silicon oxide or hafnium silicate. The gate dielectric layer 114 is formed of a high-k dielectric material. As used and described herein, a high-k dielectric material includes a dielectric material having a high dielectric constant, for example, greater than the dielectric constant of thermally heated silicon oxide (~3.9). In one embodiment, the gate dielectric layer 114 may include hafnium oxide. Alternatively, the gate dielectric layer 114 may include other high-k dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), and combinations thereof or other suitable materials. In the illustrated embodiment, the bottom gate structure 80 is a p-type gate structure, and the bottom gate electrode includes at least one p-type work function metal layer. In some cases, the p-type work function metal layer may include titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), or platinum (Pt).

[0028] The top gate structure 90 includes: an interface layer, interfacing with a first top channel structure 106T and a second top channel structure 108T; a gate dielectric layer 114, located above the interface layer; and a top gate electrode, located above the gate dielectric layer 114. In the illustrated embodiment, the top gate structure 90 is an n-type gate structure, and the top gate electrode includes at least one n-type work function metal layer. In some cases, the n-type work function metal layer may include titanium (Ti), aluminum (Al), tantalum carbide (TiC), tantalum carbide nitride (TiCN), titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), or tantalum silicon nitride (TiSiN). When the n-type work function metal layer includes aluminum, it is more prone to oxidation due to oxygen diffusion from adjacent structures (such as gate isolation features).

[0029] In block 202, a hard masking layer 170 is deposited over a precursor structure, such as on the top surface of a top gate structure 90. The hard masking layer 170 can be a single layer or multiple layers. In the illustrated embodiment, the hard masking layer 170 includes a first layer 172, a second layer 173 above the first layer 172, and a third layer 174 above the second layer 173. In some embodiments, the first layer 172 and the third layer 174 may share the same composition, while the second layer 173 has a different composition from the first layer 172 or the third layer 174. To prevent oxygen diffusion into the top gate structure 90, the first layer 172, the second layer 173, and the third layer 174 are oxygen-free. In some embodiments, the first layer 172 and the third layer 174 comprise silicon nitride or silicon carbonitride, while the second layer comprises silicon. In one embodiment, the first layer 172 and the third layer 174 comprise silicon nitride, while the second layer comprises silicon. In some implementations, a hard mask layer 170 is deposited using chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0030] Referring to Figures 8, 10, and 11, method 200 includes block 204: a gate isolation trench 184 extending through a top gate structure 90 and a bottom gate structure 80. Operations at block 204 may include forming a first patterned photoresist layer 180 (as shown in Figure 10) and using the first patterned photoresist layer 180 as an etch mask to etch a precursor structure (as shown in Figure 11). Referring to Figure 10, the first patterned photoresist layer 180 is deposited over a hard mask layer 170 using spin coating. At block 204, the first patterned photoresist layer 180 is patterned by soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. The first patterned photoresist layer 180 includes a mask opening 182. An etching process, such as dry etching (e.g., RIE etching), wet etching, or a combination thereof, is performed to etch the hard mask layer 170, the top gate structure 90, the bottom gate structure 80, and the isolation feature 103. Referring to Figure 11, the etching at block 204 can form a gate isolation trench 184 that extends vertically through the hard mask layer 170, dividing the top gate structure 90 into a first top gate structure 120 and a second top gate structure 122, and dividing the bottom gate structure 80 into a first bottom gate structure 110 and a second bottom gate structure 112. In some embodiments shown in Figure 11, to ensure complete dissociation of the bottom gate structure 80, the gate isolation trench 184 extends at least partially into the isolation feature 103. As shown in Figure 11, the sidewalls of the hard mask layer 170, the sidewalls of the first top gate structure 120 and the second top gate structure 122, the sidewalls of the first bottom gate structure 110 and the second bottom gate structure 112, the sidewalls of the isolation feature 103, and the top surface of the isolation feature 103 are exposed in the gate isolation trench 184. After the gate isolation trench 184 is formed, any remaining first patterned photoresist layer 180 is removed from the precursor structure. In some cases, the gate isolation trench 184 may also be referred to as a gate cut trench.

[0031] Referring to Figures 8 and 12, method 200 includes block 206: depositing an oxygen-free dielectric layer 142 over a gate isolation trench 184. In some embodiments, the oxygen-free dielectric layer 142 may include silicon nitride and may be deposited using CVD or ALD. As shown in Figure 12, the deposited oxygen-free dielectric layer 142 may be conformally deposited over the gate isolation trench 184 to interface with the sidewalls of the hard mask layer 170, the sidewalls of the first top gate structure 120 and the second top gate structure 122, the sidewalls of the first bottom gate structure 110 and the second bottom gate structure 112, the sidewalls of the isolation feature 103, and the top surface of the isolation feature 103. The oxygen-free dielectric layer 142 may have a first thickness (T1) between about 3 nm and about 4 nm.

[0032] Referring to Figures 8 and 13, method 200 includes block 208: depositing an oxygen blocking layer 144 over a gate isolation trench 184. The oxygen blocking layer 144 may use more than one mechanism to "block" oxygen diffusion. For example, the oxygen blocking layer 144 may be a sacrificial layer to consume and capture oxygen during its own oxidation. In this example, the oxygen blocking layer 144 may include amorphous silicon, silicon carbonitride, or amorphous carbon. Alternatively, the oxygen blocking layer 144 may be a dense oxygen barrier layer that reduces or restricts oxygen diffusion. In this example, the oxygen blocking layer 144 may include a polymer, such as polyimide. In one embodiment, the oxygen blocking layer 144 may include amorphous silicon. The oxygen blocking layer 144 may be referred to as a liner and has a second thickness T2 less than a first thickness T1. In some cases, the second thickness T2 may be between about 1 nm and about 1.5 nm. The ratio of the second thickness T2 to the first thickness T1 may be between about 1:4 and about 1:2. The oxygen barrier layer 144 can be deposited using ALD or plasma-enhanced ALD (PEALD). Although not explicitly shown in the figures, the oxygen barrier layer 144 can be multilayered. In one example, the oxygen barrier layer 144 may include: a silicon layer, interfacing with the oxygen-free dielectric layer 142; and a carbonitride silicon layer, interfacing with the oxygen-containing dielectric layer to be deposited. It should be noted that the additional layer interface created by introducing the oxygen barrier layer 144 also helps to slow oxygen diffusion. For example, without the oxygen barrier layer 144, the oxygen-free dielectric layer 142 directly interfaces with the oxygen-containing dielectric layer 146 (described below). With the introduction of the oxygen barrier layer 144, the oxygen-free dielectric layer 142 interfaces with the oxygen barrier layer 144, while the oxygen barrier layer 144 interfaces with the oxygen-containing dielectric layer 146. The additional interface creates a barrier to oxygen diffusion from the oxygen-containing dielectric layer 146.

[0033] Referring to Figures 8 and 14, method 200 includes block 210: an oxygen-containing dielectric layer 146 is located above the oxygen blocking layer 144. In some embodiments, the oxygen-containing dielectric layer 146 may include silicon oxide and may be deposited using flowable CVD (FCVD), spin coating, CVD, or ALD. As shown in Figure 14, at block 210, the oxygen-containing dielectric layer 146 not only completely fills the gate isolation trench 184 but also includes a thickness above the top surface of the oxygen blocking layer 144.

[0034] Referring to Figures 8 and 15, method 200 includes block 212: performing a planarization process 300 to expose first top gate structures 120 and 122. The planarization process 300 may include a chemical mechanical polishing (CMP) process. At block 212, the planarization process 300 is performed to remove excess oxygen-free dielectric layer 142, oxygen-blocking layer 144, and oxygen-containing dielectric layer 146 to expose the top surfaces of the first top gate structure 120 and the second top gate structure 122. At this stage, a gate isolation feature 140 is substantially formed. As shown in Figure 15, the gate isolation feature 140 includes an oxygen-free dielectric layer 142 for interfacing with the gate structures (including the first top gate structure 120, the second top gate structure 122, the first bottom gate structure 110, and the second bottom gate structure 112). The gate isolation feature 140 also includes an oxygen blocking layer 144 for protecting the oxygen-free dielectric layer 142 from oxygen diffusion from the innermost oxygen-containing dielectric layer 146.

[0035] Referring to Figure 8, method 200 includes block 214: performing further processes. These further processes may include forming middle-end-of-line (MEOL) features and forming back-end-of-line (BEOL) features. MEOL features may include front-side source / drain contacts, gate contact vias, back-side source / drain contact vias, and back-side gate contact vias. BEOL features may include front-side interconnect structures and back-side interconnect structures. The front-side interconnect structure includes a plurality of dielectric layers and a plurality of metal layers disposed in the dielectric layers. In some embodiments, the front-side interconnect structure includes about 8 metal layers and about 20 metal layers. The back-side interconnect structure includes a plurality of dielectric layers and a plurality of metal layers disposed in the dielectric layers. In some embodiments, the back-side interconnect structure includes about 2 metal layers and about 10 metal layers.

[0036] Simulations and experiments have demonstrated the oxygen barrier benefits of oxygen blocking layer 144. First, refer to Figure 16, which plots the distance of oxygen concentration relative to the gate isolation feature with and without oxygen blocking layer 144. The graph in Figure 16 illustrates the retreat of oxygen concentration distribution towards gate isolation feature 140. This indicates that oxygen blocking layer 144 slows oxygen diffusion into the gate structure and channels. Figure 17 includes a graph showing that implementing oxygen blocking layer 144 can reduce threshold voltage variation by approximately 8% to approximately 10%. As mentioned above, non-uniform oxidation of the gate structure (especially n-type gate structures including aluminum (Al)) can increase the minimum supply voltage (Vmin) on the SRAM array, and some SRAM cells may cease normal operation. By reducing threshold voltage variation, implementing oxygen blocking layer 144 in the SRAM structure can reduce the variation or increase of Vmin.

[0037] Method 400 forms different types of gate isolation features in the logic device region and the memory device region.

[0038] Referring to Figures 18 and 19, method 400 includes block 402: forming a hard mask 170 over a first device region 1000 and a second device region 2000 of a precursor structure. The precursor structure shown in Figure 19 is similar to the precursor structure shown in Figure 9. For brevity, a detailed description of the precursor structure in Figure 19 is omitted. The precursor structure includes a first device region 1000 and a second device region 2000. In some embodiments, the first device region 1000 is a memory device region including the SRAM cell 10 shown in Figures 1 and 2, while the second device region 2000 is a logic device region including the logic standard cell 50 shown in Figures 3 and 4. It should be noted that different device regions are not referred to in the description of method 200 above because similar operations are performed on different device regions, and the non-precursor structure does not include a plurality of device regions.

[0039] The precursor structure includes: a substrate 102 (shown in dashed lines and omitted in subsequent figures); base fins 104 formed from the substrate 102; isolation features 103 located above the substrate 102 and disposed between the base fins 104; a first bottom channel structure 106B, a second bottom channel structure 108B, a first top channel structure 106T, and a second top channel structure 108T, all located in the first device region 1000 and the second device region 2000. To facilitate the description of the different arrangements of the gate structures in the two device regions, the element symbols for the top and bottom gate structures in the two device regions are different from those used in Figure 9. Referring to Figure 19, the bottom gate structure 1080 surrounding the first bottom channel structure 106B and the second bottom channel structure 108B, and the top gate structure 1090 surrounding the first top channel structure 106T and the second top channel structure 108T, are located above the first device region 1000. The bottom gate structure 2080 surrounding the first bottom channel structure 106B and the second bottom channel structure 108B, and the top gate structure 2090 surrounding the first top channel structure 106T and the second top channel structure 108T, are located above the second device region 2000.

[0040] Block 402, a hard masking layer 170 is deposited above the first device region 1000 and the second device region 2000, such as deposited above the top surface of the top gate structure 1090 and the top surface of the top gate structure 2090. The hard masking layer 170 may be a single layer or multiple layers. In the illustrated embodiment, the hard masking layer 170 includes a first layer 172, a second layer 173 above the first layer 172, and a third layer 174 above the second layer 173. In some embodiments, the first layer 172 and the third layer 174 may share the same composition, while the second layer 173 has a different composition from the first layer 172 or the third layer 174. To prevent oxygen diffusion into the top gate structure 90, the first layer 172, the second layer 173, and the third layer 174 are oxygen-free. In some embodiments, the first layer 172 and the third layer 174 comprise silicon nitride or silicon carbonitride, while the second layer comprises silicon. In one embodiment, the first layer 172 and the third layer 174 comprise silicon nitride, while the second layer comprises silicon. In some embodiments, the hard mask layer 170 is deposited using chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0041] Referring to Figures 18, 20, and 21, method 400 includes block 404: forming a first gate isolation trench 184-1 in a first device region 1000 and forming a second gate isolation trench 184-2 in a second device region 2000. Operations at block 204 may include forming a first patterned photoresist layer 180 (as shown in Figure 20) and using the first patterned photoresist layer 180 as an etch mask to etch a precursor structure (as shown in Figure 21). Referring to Figure 20, the first patterned photoresist layer 180 is deposited over a hard mask layer 170 using spin coating. At block 404, the first patterned photoresist layer 180 is patterned by soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. The first patterned photoresist layer 180 includes a first masking opening 182-1 located above the first device region 1000 and a second masking opening 182-2 located above the second device region 2000. An etching process, such as dry etching (e.g., RIE etching), wet etching, or a combination thereof, is performed to etch the hard masking layer 170, top gate structures 1090 and 2090, bottom gate structures 1080 and 2080, and isolation feature 103. Referring to Figure 21, the etching at block 404 may form a first gate isolation trench 184-1 in the first device region 1000, which extends vertically through the hard masking layer 170, dividing the top gate structure 1090 into a first top gate structure 1020 and a second top gate structure 1022, and dividing the bottom gate structure 1080 into a first bottom gate structure 1010 and a second bottom gate structure 1012. The etching at block 404 can also form a second gate isolation trench 184-2 in the second device region 2000. This second gate isolation trench 184-2 extends vertically through the hard mask layer 170, dividing the top gate structure 2090 into a first top gate structure 2020 and a second top gate structure 2022, and dividing the bottom gate structure 2080 into a first bottom gate structure 2010 and a second bottom gate structure 2012. In some embodiments shown in Figure 21, to ensure complete dissociation of the bottom gate structure 1080 or 2080, the first gate isolation trenches 184-1 and 184-2 extend at least partially into the isolation feature 103. As shown in Figure 21, the sidewalls of the hard masking layer 170, the sidewalls of the first top gate structure 1020 and the second top gate structure 1022, the sidewalls of the first bottom gate structure 1010 and the second bottom gate structure 1012, the sidewalls of the isolation feature 103, and the top surface of the isolation feature 103 are exposed in the first gate isolation trench 184-1.In the second device region 2000, the sidewalls of the hard mask layer 170, the sidewalls of the first top gate structure 2020 and the second top gate structure 2022, the sidewalls of the first bottom gate structure 2010 and the second bottom gate structure 2012, the sidewalls of the isolation feature 103, and the top surface of the isolation feature 103 are exposed in the second gate isolation trench 184-2. After forming the first gate isolation trench 184-1 and the second gate isolation trench 184-2, any remaining first patterned photoresist layer 180 is removed from the precursor structure. In some cases, the first gate isolation trench 184-1 and the second gate isolation trench 184-2 may also be referred to as the first gate isolation trench 184-1 and the second gate isolation trench 184-2.

[0042] Referring to Figures 18 and 22, method 400 includes block 406: depositing an oxygen-free dielectric layer 142 over a first gate isolation trench 184-1 and a second gate isolation trench 184-2. In some embodiments, the oxygen-free dielectric layer 142 may include silicon nitride and may be deposited using CVD or ALD. As shown in Figure 22, the deposited oxygen-free dielectric layer 142 may be deposited over the first gate isolation trench 184-1 and the second gate isolation trench 184-2. In the illustrated embodiment, the oxygen-free dielectric layer 142 completely fills the first gate isolation trench 184-1 in the first device region 1000 and the second gate isolation trench 184-2 in the second device region 2000. In some cases, the oxygen-free dielectric layer 142 deposited at block 416 covers the top surface of the hard mask layer 170.

[0043] Referring to Figures 18 and 23, method 400 includes block 408: planarizing the first device region 1000 and the second device region 2000 in a planarization process 320 to thin the oxygen-free dielectric layer 142. To form a smooth and flat top surface for subsequent operations, block 408 planarizes the precursor structure to reduce the thickness of the oxygen-free dielectric layer 142 above the top surface of the hard mask layer 170. In some cases, the planarization process 300 includes a chemical mechanical polishing (CMP) process.

[0044] Referring to Figures 18 and 24, method 400 includes block 410: an inner trench 192 extending through an oxygen-free dielectric layer 142 in a second gate isolation trench 184-2. Operations at block 410 may include forming a second patterned photoresist layer 190 and using the second patterned photoresist layer 190 as an etch mask to etch a precursor structure. Referring to Figure 24, the second patterned photoresist layer 190 is deposited on a hard mask layer 170 using spin coating. At block 410, the second patterned photoresist layer 190 is patterned by soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. The second patterned photoresist layer 190 includes a mask opening located directly above the second gate isolation trench 184-2, which is filled with the oxygen-free dielectric layer 142. An etching process, such as dry etching (e.g., RIE etching), wet etching, or a combination thereof, is performed to etch the oxygen-free dielectric layer 142 in the second gate isolation trench 184-2. Referring to Figure 24, etching at block 410 can form an inner trench 192 that extends vertically through the oxygen-free dielectric layer 142 in the second gate isolation trench 184-2. As shown in Figure 24, the inner trench 192 is separated from the sidewalls of the first top gate structure 2020 and the second top gate structure 2022, the sidewalls of the first bottom gate structure 2010 and the second bottom gate structure 2012, and the isolation feature 103 by the oxygen-free dielectric layer. In some embodiments shown in Figure 24, the bottom surface of the inner trench 192 may extend below the top surface of the isolation feature 103. After forming the inner trench 192, any remaining second patterned photoresist layer 190 is removed from the precursor structure.

[0045] Referring to Figures 18 and 25, method 400 includes block 412: depositing an oxygen-containing dielectric layer 146 over an inner trench 192. In some embodiments, the oxygen-containing dielectric layer 146 may include silicon oxide and may be deposited using flowable CVD (FCVD), spin coating, CVD, or ALD. As shown in Figure 25, at block 412, the oxygen-containing dielectric layer 146 not only completely fills the inner trench 192 in the second device region 2000 but is also deposited above the top surface of the oxygen-free dielectric layer 142 in the first device region 1000.

[0046] Referring to Figures 18 and 26, method 400 includes block 414: performing a planarization process 340 to expose first top gate structures 120 and 122. The planarization process 340 may include a chemical mechanical polishing (CMP) process and is used to remove excess oxygen-free dielectric layer 142 and oxygen-containing dielectric layer 146 above the top surfaces of the first top gate structure 1020 and the second top gate structure 1022 in the first device region 1000 and the second top gate structure 2020 and the second top gate structure 2022 in the second device region 2000. At this time, a first type gate isolation feature 1400 is formed in the first device region 1000, and a second type gate isolation feature 1402 is formed in the second device region 2000. The first type gate isolation feature 1400 is formed entirely of the oxygen-free dielectric layer 142 and helps reduce oxygen diffusion into the gate structure it contacts. Type 1 gate isolation feature 1400 is suitable for applications where device performance degradation is primarily caused by oxygen diffusion. Type 2 gate isolation feature 1402 includes an oxygen-free dielectric layer 142 and an oxygen-containing dielectric layer 146. Type 2 gate isolation feature 1402 typically has a lower dielectric constant and is suitable for logic devices requiring fast switching and low parasitic capacitance.

[0047] Referring to Figure 18, method 400 includes block 416: performing further processes. These further processes may include forming middle-end-of-line (MEOL) features and forming back-end-of-line (BEOL) features. MEOL features may include front-side source / drain contacts, gate contact vias, back-side source / drain contact vias, and back-side gate contact vias. BEOL features may include front-side interconnect structures and back-side interconnect structures. The front-side interconnect structure includes a plurality of dielectric layers and a plurality of metal layers disposed in the dielectric layers. In some embodiments, the front-side interconnect structure includes about 8 metal layers and about 20 metal layers. The back-side interconnect structure includes a plurality of dielectric layers and a plurality of metal layers disposed in the dielectric layers. In some embodiments, the back-side interconnect structure includes about 2 metal layers and about 10 metal layers.

[0048] In one exemplary embodiment, this disclosure relates to a semiconductor structure. The semiconductor structure includes: a first active region and a second active region; a first gate structure disposed above the first active region; a second gate structure disposed above the second active region; and a gate isolation feature sandwiched between the sidewalls of the first gate structure and the second gate structure. The gate isolation feature includes: a first dielectric layer, interfacing with the sidewalls of the first gate structure and the second gate structure; a diffusion barrier pad, interfacing with the first dielectric layer; and a second dielectric layer, interfacing with the diffusion barrier pad. The second dielectric layer is separated from the first dielectric layer by the diffusion barrier pad, and the composition of the first dielectric layer is different from that of the second dielectric layer.

[0049] In some embodiments, the diffusion barrier pad comprises amorphous silicon, silicon carbonitride, amorphous carbon, or a polymer. In some embodiments, the first active region comprises a plurality of first nanostructures, the second active region comprises a plurality of second nanostructures, a first gate structure surrounds each of the first nanostructures, and a second gate structure surrounds each of the second nanostructures. In some embodiments, the semiconductor structure further comprises: a third active region above the first active region; a fourth active region above the second active region; a third gate structure disposed above the third active region; and a fourth gate structure disposed above the fourth active region. A gate isolation feature is also sandwiched between the sidewalls of the third gate structure and the sidewalls of the fourth gate structure. In some embodiments, the third gate structure is disposed above the first gate structure, and the fourth gate structure is disposed above the second gate structure. In some embodiments, the first and second gate structures comprise p-type work function layers, while the third and fourth gate structures comprise n-type work function layers. In some embodiments, the n-type work function layer comprises titanium aluminum. In some embodiments, the diffusion barrier pad includes a first thickness, and the first dielectric layer includes a second thickness greater than the first thickness. In some embodiments, the ratio of the first thickness to the second thickness is between about 1:4 and about 1:2. In some embodiments, the first thickness is between about 1 nm and about 1.5 nm, and the second thickness is between about 3 nm and about 4 nm.

[0050] In another exemplary embodiment, this disclosure relates to a semiconductor structure. The semiconductor structure includes: a substrate having a memory device region and a logic device region; a first gate structure and a second gate structure located above the memory device region; a third gate structure and a fourth gate structure located above the logic device region; a first gate isolation feature sandwiched between the first gate structure and the second gate structure; and a second gate isolation feature sandwiched between the third gate structure and the fourth gate structure. The composition of the first gate isolation feature differs from the composition of the second gate isolation feature.

[0051] In some embodiments, the first gate isolation feature includes silicon nitride, and the second gate isolation feature includes: an outer layer, interfacing with the sidewalls of the first gate structure and the sidewalls of the second gate structure; and an inner layer, separated from the sidewalls of the first gate structure and the second gate structure by the outer layer. The composition of the outer layer differs from that of the inner layer. In some embodiments, the dielectric constant of the outer layer is greater than that of the inner layer. In some embodiments, the outer layer includes silicon nitride, and the inner layer includes silicon oxide. In some embodiments, the semiconductor structure further includes: a first top gate structure located above the first gate structure; a second top gate structure located above the second gate structure; a third top gate structure located above the third gate structure; and a fourth top gate structure located above the fourth gate structure. The first gate isolation feature extends between the first top gate structure and the second top gate structure, and the second gate isolation feature extends between the third top gate structure and the fourth top gate structure. In some embodiments, the first gate structure, the second gate structure, the third gate structure, and the fourth gate structure include a p-type work function metal layer, and the first top gate structure, the second top gate structure, the third top gate structure, and the fourth top gate structure include an n-type work function metal layer.

[0052] In another exemplary embodiment, this disclosure relates to a method for forming a semiconductor structure. The method for forming a semiconductor structure includes the following steps: providing a precursor structure, the precursor structure comprising: a substrate including a first device region and a second device region; a first bottom gate structure located above the first device region; a first top gate structure located above the first bottom gate structure; a first hard mask layer located above the first top gate structure; a second bottom gate structure located above the second device region; a second top gate structure located above the second bottom gate structure; and a second hard mask layer located above the second top gate structure; forming a first trench passing through the first hard mask layer, the first top gate structure, and the first bottom gate structure; and forming a trench passing through the second hard mask layer and the second top gate structure. A second trench is formed, comprising a second bottom gate structure; a first dielectric layer is deposited over the first device region and the second device region to fill the first trench and the second trench; a patterned mask is formed over the first device region and the second device region, while a portion of the first dielectric layer over the second trench is exposed through an opening in the patterned mask; the first dielectric layer in the second trench is etched to form an inner trench; the patterned mask is removed; a second dielectric layer is deposited over the inner trench; and after depositing the second dielectric layer, a precursor structure is planarized to expose the top surfaces of the first top gate structure and the second top gate structure, and a first gate cleaving feature is formed in the first trench, and a second gate cleaving feature is formed in the second trench. The composition of the first dielectric layer is different from that of the second dielectric layer.

[0053] In some embodiments, the first dielectric layer comprises silicon nitride, and the second dielectric layer comprises silicon oxide. In some embodiments, the first bottom gate structure and the second bottom gate structure comprise p-type work function metal layers, and the first top gate structure and the second top gate structure comprise n-type work function metal layers. In some embodiments, a first gate cleaving feature is disposed between the first nanostructure stack and the second nanostructure stack, the first gate cleaving feature dividing the first bottom gate structure into a first gate segment and a second gate segment, the first gate segment surrounding each of the first nanostructure stack, and the second gate segment surrounding each of the second nanostructure stack.

[0054] The foregoing summary outlines the features of several embodiments, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as the basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of this disclosure.

[0055] 10: SRAM cell 12B: First bottom active region 12T: First Top Active Region 14B: Second bottom active region 14T: Second Top Active Region 16B: First bottom gate structure 16T: First top gate structure 18B: Second bottom gate structure 18T: Second top gate structure 20B: Third bottom gate structure 20T: Third top gate structure 22B: Fourth bottom gate structure 22T: Fourth top gate structure 30: First gate isolation characteristics 32: Second gate isolation characteristics 34: Third gate isolation characteristics 36: Fourth gate isolation characteristics 38: Fifth gate isolation characteristics 40: First contact hole [ ] 42: Second contact via 44: Third contact via 46: Fourth contact hole 50: Logic Standard Unit 80: Bottom gate structure 90: Top gate structure 100: Semiconductor devices 102: Substrate 103: Isolation Features 104: Basement fins 106B: First bottom channel structure 106M, 108M: Intermediate semiconductor layer 106T: First top channel structure 108B: Second bottom channel structure 108T: Second top channel structure 110: First bottom gate structure 112: Second bottom gate structure 114: Gate dielectric layer 120: First top gate structure 122: Second top gate structure 128: Insulation layer 140: Gate isolation characteristics 142: Oxygen-free dielectric layer 144: Oxygen Barrier Layer 146: Oxygen-containing dielectric layer 150B: First Bottom Source / Drain Characteristics 150T: First Top Source / Drain Characteristics 152B: Bottom CESL 152T: Top CESL 154B: Bottom ILD layer 154T: Top ILD layer 160B: Second Bottom Source / Drain Characteristics 160T: Second Top Source / Drain Characteristics 170: Hard mask layer 172: First Floor 173: Second Floor 174: Third Floor 180: First patterned photoresist layer 182: Masking opening 182-1: First mask opening 182-2: Second mask opening 184: Gate isolation trench 184-1: First gate isolation trench 184-2: Second gate isolation trench 190: Second patterned photoresist layer 192: Inner groove 200, 400: Method Blocks 202, 204, 206, 208, 210, 212, 214, 402, 404, 406, 408, 410, 412, 414, 416: 300, 320, 340: Planarization process 1000: First device area 1010: First bottom gate structure 1012: Second bottom gate structure 1020: First top gate structure 1022: Second top gate structure 1080, 2080: Bottom gate structure 1090, 2090: Top gate structure 1400: Type I gate isolation characteristics 1402: Type II gate isolation characteristics 2000: Second Device Area 2010: First bottom gate structure 2012: Second bottom gate structure 2020: First Top Gate Structure 2022: Second Top Gate Structure A-A', B-B', C-C': lines PD1: First pull-down transistor PD2: Second pull-down transistor PG1: First Transmission Gate Transistor PG2: Second Transmission Gate Transistor PU1: First pull-up transistor PU2: Second pull-up transistor T1: First thickness T2: Second thickness X, Y, Z: Direction

[0056] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A semiconductor structure comprising: a first active region and a second active region; a first gate structure disposed above the first active region; a second gate structure disposed above the second active region; and a gate isolation feature sandwiched between a sidewall of the first gate structure and a sidewall of the second gate structure, wherein the gate isolation feature comprises: a first dielectric layer, interfacing with the sidewall of the first gate structure and the sidewall of the second gate structure; a diffusion barrier pad, interfacing with the first dielectric layer; and a second dielectric layer, interfacing with the diffusion barrier pad, wherein the second dielectric layer is separated from the first dielectric layer by the diffusion barrier pad; wherein a composition of the first dielectric layer is different from a composition of the second dielectric layer; wherein the diffusion barrier pad has a first thickness, and the first dielectric layer has a second thickness, the second thickness being greater than the first thickness.

2. The semiconductor structure as claimed in claim 1, wherein the diffusion barrier pad comprises amorphous silicon, silicon carbonitride, amorphous carbon, or a polymer.

3. The semiconductor structure of claim 1, wherein the first active region comprises a plurality of first nanostructures, wherein the second active region comprises a plurality of second nanostructures, wherein the first gate structure surrounds each of the first nanostructures, and wherein the second gate structure surrounds each of the second nanostructures.

4. The semiconductor structure as claimed in claim 1, further comprising: a third active region located above the first active region; a fourth active region located above the second active region; a third gate structure located above the third active region; and a fourth gate structure located above the fourth active region, wherein the gate isolation feature is also sandwiched between a sidewall of the third gate structure and a sidewall of the fourth gate structure.

5. The semiconductor structure as claimed in claim 4, wherein the third gate structure is disposed above the first gate structure, and wherein the fourth gate structure is disposed above the second gate structure.

6. A semiconductor structure comprising: a substrate having a memory device region and a logic device region; a first gate structure and a second gate structure located above the memory device region; a third gate structure and a fourth gate structure located above the logic device region; a first gate isolation feature sandwiched between the first gate structure and the second gate structure; and a second gate isolation feature sandwiched between the third gate structure and the fourth gate structure, wherein a component of the first gate isolation feature is different from a component of the second gate isolation feature.

7. The semiconductor structure of claim 6, wherein the first gate isolation feature comprises silicon nitride, wherein the second gate isolation feature comprises: an outer layer, which interfaces with a sidewall of the first gate structure and a sidewall of the second gate structure, and an inner layer, which is separated from the sidewall of the first gate structure and the sidewall of the second gate structure by the outer layer, wherein a component of the outer layer is different from a component of the inner layer.

8. The semiconductor structure as claimed in claim 7, wherein the dielectric constant of the outer layer is greater than the dielectric constant of the inner layer.

9. A method for forming a semiconductor structure, comprising the following steps: providing a precursor structure, the precursor structure comprising: A substrate includes a first device region and a second device region, a first bottom gate structure located above the first device region, a first top gate structure located above the first bottom gate structure, a first hard mask layer located above the first top gate structure, a second bottom gate structure located above the second device region, a second top gate structure located above the second bottom gate structure, and a second hard mask layer located above the second top gate structure. A first trench is formed through the first hard mask layer, the first top gate structure, and the first bottom gate structure; a second trench is formed through the second hard mask layer, the second top gate structure, and the second bottom gate structure; a first dielectric layer is deposited over the first device region and the second device region to fill the first trench and the second trench; a patterned mask is formed over the first device region and the second device region, with a portion of the first dielectric layer above the second trench exposed through an opening in the patterned mask. The first dielectric layer in the second trench is etched to form an inner trench; the patterned mask is removed; a second dielectric layer is deposited over the inner trench; and after depositing the second dielectric layer, the precursor structure is planarized to expose the top surfaces of the first top gate structure and the second top gate structure, and a first gate cleaving feature is formed in the first trench, and a second gate cleaving feature is formed in the second trench, wherein a composition of the first dielectric layer is different from a composition of the second dielectric layer.

10. The method of claim 9, wherein the first gate cleaving feature is disposed between a first nanostructure stack and a second nanostructure stack, wherein the first gate cleaving feature divides the first bottom gate structure into a first gate segment and a second gate segment, wherein the first gate segment surrounds each of the first nanostructure stack, and wherein the second gate segment surrounds each of the second nanostructure stack.

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