Semiconductor device and manufacturing method thereof

Abstract

The semiconductor device includes a cage-like structure, a semiconductor wafer, a package, and a first redistribution layer. The cage-like structure has a first cage-like structure surface, a second cage-like structure surface opposite to the first cage-like structure surface, and a cavity extending from the first cage-like structure surface to the second cage-like structure surface. The semiconductor wafer is disposed within the cavity. The package covers the semiconductor wafer. The first redistribution layer is formed over the package and the semiconductor wafer.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method for manufacturing the same. Prior Technology

[0002] The wafer (or die) and the substrate need to be aligned to ensure accurate contact between them. Generally, wafer displacement / slippage may be caused by (1) the difference in the coefficients of thermal expansion between the wafer and the substrate, and (2) the wafer size. The larger the wafer size, the greater the warping of the substrate, and the greater the warping, the less accurate the contact. Summary of the Invention

[0003] This disclosure provides an embodiment of a semiconductor device. The semiconductor device includes a cage-like structure, a semiconductor wafer, a package, and a first redistribution layer. The cage-like structure has a first cage-like structure surface, a second cage-like structure surface opposite to the first cage-like structure surface, and a cavity extending from the first cage-like structure surface to the second cage-like structure surface. The semiconductor wafer is disposed in the cavity. The package covers the semiconductor wafer. The first redistribution layer is formed over the package and the semiconductor wafer.

[0004] In one example, the cavity extends to the surface of the first cage-like member.

[0005] In one example, the semiconductor wafer has a wafer back side, and the wafer back side of the semiconductor wafer is flush with the surface of the second cage of the cage.

[0006] In one example, the semiconductor wafer protrudes relative to the surface of the first cage-like member of the cage-like member.

[0007] In one example, the package has a package side, the cage has a cage side, and the package side and the cage side are flush with each other.

[0008] In one example, the cage-like component has a cage-like surface, and the package covers the cage-like surface and the first cage-like surface, but exposes the second cage-like surface.

[0009] In one example, the cavity is a blind hole located on a cage-like component, which is a substrate. The semiconductor wafer is a flip-chip with an active surface, which is bonded to the substrate in the blind hole, with the active surface facing the blind hole.

[0010] In one example, the semiconductor wafer is a flip-chip with an active surface, a first redistribution layer is disposed on the surface of the second cage and the active surface, and the package covers the first cage surface of the cage.

[0011] In one example, the semiconductor device further includes a conductive layer. The conductive layer is located within the cavity. A semiconductor wafer is disposed on the conductive layer, the package has a package surface and a through-hole extending from the package surface to the conductive layer, and the semiconductor device further includes a conductive portion located within the through-hole.

[0012] In one example, the semiconductor device further includes a conductive portion. The conductive portion extends from the surface of the second cage to the surface of the first cage.

[0013] In one example, the semiconductor device further includes a second layer and a third layer. The second layer is disposed on the surface of the second cage-like member. The third layer is disposed on the surface of the first cage-like member and located between the first layer and the surface of the first cage-like member. A conductive portion electrically connects the second layer and the third layer.

[0014] In one example, the package is disposed in a cavity and between one side of the semiconductor wafer and the side of the cavity.

[0015] This disclosure provides another embodiment of a method for manufacturing a semiconductor device. The manufacturing method includes the following steps: disposing a cage-like member on a carrier, wherein the cage-like member has a first cage-like member surface, a second cage-like member surface opposite to the first cage-like member surface, and a cavity extending from the first cage-like member surface to the second cage-like member surface; disposing a semiconductor wafer in the cavity; disposing a package covering the semiconductor wafer; disposing a first overlay layer covering the package and the semiconductor wafer; and removing the carrier to expose the first overlay layer.

[0016] In one example, the step of configuring the first overlay to cover the package and the semiconductor wafer includes: configuring the first overlay on a carrier; transferring the first overlay via the carrier to the package and the semiconductor wafer; and removing the carrier.

[0017] In one example, the manufacturing method further includes: removing a portion of the cage-like component and the semiconductor wafer.

[0018] In one example, during the step of configuring the package to cover the semiconductor wafer, the package further covers one side of the cage-like component.

[0019] In one example, a cage-like member containing a cavity with a blind via is disposed on a carrier; the semiconductor wafer is a flip-chip bonded to the blind via, with one active surface of the semiconductor wafer facing the blind via.

[0020] In one example, the manufacturing method further includes: disposing a conductive layer in a cavity; disposing a semiconductor wafer on the conductive layer in the cavity; disposing a package covering the semiconductor wafer; forming a through-hole extending from one of the package surfaces of the package to the conductive layer; and forming a conductive portion in the through-hole.

[0021] In one example, the step of configuring a cage-like member on a carrier includes: forming a conductive portion, wherein the conductive portion extends from the surface of the second cage-like member to the surface of the first cage-like member.

[0022] In one example, the step of configuring the cage-like member on the carrier includes: configuring a second layer of fabric on the surface of the second cage-like member; and configuring a third layer of fabric on the surface of the first cage-like member, wherein the third layer of fabric is located between the first layer of fabric and the surface of the first cage-like member, and the conductive portion electrically connects the second layer of fabric and the third layer of fabric.

[0023] In one example, in the step of configuring the package to cover the semiconductor wafer, the package is configured in a cavity and between one side of the semiconductor wafer and one side of the cavity.

[0024] This invention primarily addresses the issue that during the wafer-level packaging or panel-level packaging process, the molding compound may cause excessive wafer displacement when covering the package, thus affecting the workability and stability of subsequent processes (such as the fabrication of redistribution layers). Therefore, this invention proposes various improvements to the package structure and manufacturing process to improve and ensure high yield and output of the final product.

[0025] To provide a better understanding of the above and other aspects of this disclosure, specific embodiments are described below in conjunction with the accompanying drawings: Simple Explanation of the Diagram

[0026] Figure 1A illustrates a schematic diagram of a semiconductor device according to an embodiment of the present disclosure. Figure 1B shows a cross-sectional view of the semiconductor device according to Figure 1A along direction 1B-1B'. Figure 2 illustrates a cross-sectional view of a semiconductor device according to another embodiment of this disclosure. Figure 3 illustrates a cross-sectional view of a semiconductor device according to another embodiment of this disclosure. Figure 4 illustrates a cross-sectional view of a semiconductor device according to another embodiment of this disclosure. Figure 5 illustrates a cross-sectional view of a semiconductor device according to another embodiment of this disclosure. Figure 6 illustrates a cross-sectional view of a semiconductor device according to another embodiment of this disclosure. Figure 7 illustrates a cross-sectional view of a semiconductor device according to another embodiment of this disclosure. Figure 8 illustrates a cross-sectional view of a semiconductor device according to another embodiment of this disclosure. Figures 9A to 9I illustrate a process diagram of a manufacturing method for an embodiment of the semiconductor device in Figure 1B. Figures 10A to 10C illustrate process diagrams of a manufacturing method for another embodiment of the semiconductor device in Figure 1B. Figures 11A-11C illustrate a process diagram of a manufacturing method for an embodiment of the semiconductor device in Figure 2. Figures 12A to 12I illustrate a process diagram of a manufacturing method for an embodiment of the semiconductor device in Figure 3. Figures 13A-13C illustrate a process diagram of a manufacturing method for another embodiment of the semiconductor device in Figure 3. Figures 14A to 14I illustrate a process diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figures 15A to 15I illustrate the process of manufacturing the semiconductor device shown in Figure 3. Figures 16A to 16G illustrate process diagrams of a manufacturing method for one embodiment of the semiconductor device in Figure 4. Figures 17A-17J illustrate process diagrams of a manufacturing method for one embodiment of the semiconductor device in Figure 5. Figures 18A to 18I illustrate process diagrams of a manufacturing method for one embodiment of the semiconductor device in Figure 6. Figures 19A-19J illustrate process diagrams of a manufacturing method for one embodiment of the semiconductor device in Figure 7. Figures 20A-20C illustrate process diagrams of a manufacturing method for another embodiment of the semiconductor device in Figure 7. Figures 21A to 21G illustrate process diagrams of a manufacturing method for one embodiment of the semiconductor device in Figure 8. Figure 22A illustrates a schematic diagram of a panel-level package according to one embodiment. Figure 22B shows a cross-sectional view of the panel-level package of Figure 22A along direction 22B-22B'. Implementation

[0027] The following embodiments are disclosed to illustrate the present invention in detail. These embodiments are for illustrative purposes only and are not intended to limit the scope of patent protection of the present invention. Furthermore, minor elements may be omitted in the following embodiments to highlight the technical features of the present invention.

[0028] Please refer to Figures 1A and 1B. Figure 1A shows a schematic diagram of a semiconductor device 100 according to an embodiment of the present disclosure, and Figure 1B shows a cross-sectional view of the semiconductor device 100 according to Figure 1A along direction 1B-1B'.

[0029] As shown in Figures 1A and 1B, the semiconductor device 100 includes at least one cage-like member 110, at least one semiconductor wafer 120, a package 130, a first redistribution layer (RDL) 140, and at least one contact 150. The cage-like member 110 has a first cage-like member surface 110s1, a second cage-like member surface 110s2 opposite to the first cage-like member surface 110s1, and a cavity 110c extending from the first cage-like member surface 110s1 toward the second cage-like member surface 110s2. The semiconductor wafer 120 is disposed within the cavity 110c. The package 130 covers the semiconductor wafer 120. The first redistribution layer 140 is disposed above the package 130 and the semiconductor wafer 120. The cage-like member 110 can restrain the displacement of the semiconductor wafer 120. Furthermore, during the manufacturing process of the semiconductor device 100, the semiconductor wafer 120 can be placed in the cavity 110c of the cage 110 to be confined in the cavity 110c, thereby improving the positioning accuracy of the semiconductor wafer 120 and the first overlapping layer 140.

[0030] Furthermore, wafer displacement / slippage is caused by: (1) the difference in the coefficient of thermal expansion (CTE) between the carrier, the molding compound, and the embedded wafer, as well as the chemical shrinkage of the molding compound; and (2) the influence of wafer size, wafer adhesion to the release layer, flow behavior of the molding compound, and related forces on the wafer during compression molding. Geometry (e.g., carrier type and thickness, mold thickness, wafer thickness, total silicon content / density, side panel size, etc.) also plays an important role in wafer displacement / slippage and panel warpage. The solutions of this application, including but not limited to wafer cages / stops / constraints, permanent die bonding, related processes, and adaptive patterning, may help to minimize the impact. The term "bonding" as used herein may also be referred to as "bonding".

[0031] Furthermore, warpage is also caused by the difference in the coefficients of thermal expansion between the carrier, molding compound, and embedded wafer, and is affected by the chemical shrinkage of the molding compound. Geometry (e.g., carrier type and thickness, mold thickness, wafer thickness, total silicon content / density, side panel dimensions, etc.) also plays a significant role in wafer displacement / slippage and panel warpage. The solutions of this application include thicker, more rigid carriers (including cage-like treatments) / support substrates with sufficient thickness and thermomechanical properties (e.g., coefficient of thermal expansion, modulus, etc.) to minimize warpage. Separate overmolding islands (see Figures 22A and 22B) can be used to separate die blocks from other die blocks to minimize the mismatch of coefficients of thermal expansion, mold flow, and other effects. Lower coefficients of thermal expansion, lower modulus molding compounds or encapsulation materials, and adaptive patterning can minimize warpage effects.

[0032] Furthermore, the fine-line / space (L / S) capability in semiconductor devices can be equal to or less than 2 / 2. Significant development of the FOPLP process is required to address the major technological and material challenges brought about by the substantial increase in panel area. Building more and finer L / S redistribution layers on large panels leads to reduced yield and increased wafer scrap. This application's solution involves heterogeneous integration of wafer and substrate technologies, aided by FOPLP (e.g., building finer L / S redistribution layers on a carrier wafer, testing them to ensure known good structures, dicing the wafer, and bonding the known good redistribution layers to the dies on the panel). A horizontal-level fine L / S redistribution layer is created using liquid resist spraying, and a vertical-level fine L / S redistribution layer is formed using laser drilling, DRIE, dry argon desmear, physical vapor deposition (CVD) of barrier / seed layers, dry film, metal hard mask, copper pillar plating, wet cleaning, and combinations thereof. Built-in redistribution layer test circuitry (e.g., daisy chains), multi-site panel-level testing, and / or wafer-related built-in self-test (BIST) are implemented.

[0033] In this embodiment, the cage-like member 110 may be formed of materials including metal, glass, ceramic, etc. In one embodiment, the cage-like member 110 may not include any circuit elements.

[0034] As shown in Figure 1A, the cage-like member 110 is a closed loop. In another embodiment, the cage-like member 110 may be an open-ring. Viewed from above (towards the -Z axis), the cage-like member 110 may be polygonal (e.g., rectangular, triangular, etc.), circular, elliptical, etc. The cage-like member 110 has a first cage-like member side 110s3 and a second cage-like member side 110s4 opposite to the first cage-like member side 110s3. The distance d1 between the second cage-like member side 110s4 of the cage-like member 110 and the side 120s of the semiconductor wafer 120 may be between, for example, 1 micrometer to 10 micrometers, such as 1 micrometer, 2 micrometers, 3 micrometers, 4 micrometers, 5 micrometers, 6 micrometers, 7 micrometers, 8 micrometers, 9 micrometers, or 10 micrometers. Such a distance d1 can improve the positioning accuracy of the semiconductor wafer 120 and the first redistribution layer 140.

[0035] In this embodiment, the cavity 110c is a through hole. For example, the cavity 110c extends from the surface 110s2 of the second cage-like member to the surface 110s1 of the first cage-like member. In another embodiment, the cavity 110c is, for example, a blind hole.

[0036] As shown in Figure 1B, the semiconductor wafer 120 includes a substrate 121, a front-end-of-line (FEOL) structure 122, a back-end-of-line (BEOL) structure 123, and at least one contact 124. The substrate 121 is, for example, a portion of a silicon wafer. The front-end-of-line structure 122 is formed within and / or on the substrate 121, the back-end-of-line structure 123 is formed within and / or on the front-end-of-line structure 122 and electrically connected to it, and the contact 124 is formed on and electrically connected to the back-end-of-line structure 123. The contact 124 is, for example, a solder ball, a microbump, or a micropillar.

[0037] As shown in Figure 1B, the semiconductor wafer 120 has a wafer surface (wafer back side) 120b, which is exposed outside the cavity 110c, and the wafer surface 120b of the semiconductor wafer 120 is aligned with (e.g., flush with) the second cage surface 110s2 of the cage 110. Furthermore, the semiconductor wafer 120 protrudes relative to the first cage surface 110s1 of the cage 110.

[0038] As shown in Figure 1B, the package 130 encapsulates the cage 110 and the semiconductor wafer 120. For example, the package 130 covers the first cage surface 110s1 and the second cage side surface 110s4 of the cage 110, the side surface 120s of the semiconductor wafer 120, and the side surface of the contact 124, but exposes the second cage surface 110s2 and the first cage side surface 110s3 of the cage 110. In addition, the package 130 also fills a portion of the cavity 110c.

[0039] As shown in Figure 1B, the package 130 has a package side 130s, and the package side 130s and the first cage side 110s3 are aligned with each other (e.g., flush). Furthermore, during the manufacturing process of the semiconductor device 100, the package side 130s and the first cage side 110s3 are formed, for example, by dicing (e.g., by sawing, such as diamond blade sawing or laser sawing).

[0040] Furthermore, the encapsulation 130 may be, for example, a molding compound or a laminated photoresist. The molding compound includes, for example, a novolac-based resin, epoxy resin, silicone resin, or other suitable encapsulation material, and may contain suitable fillers such as powdered silicon dioxide (SiO2). The molding compound may be formed through, for example, transfer molding, compression molding, or lamination.

[0041] As shown in Figure 1B, a first re-layout layer 140 is disposed on and / or above the package body 130 and the semiconductor wafer 120. The first re-layout layer 140 is electrically connected to the semiconductor wafer 120. For example, the first re-layout layer 140 is electrically connected to the contacts 124 of the semiconductor wafer 120. The first re-layout layer 140 includes at least one conductive pad 141 for receiving the contacts 150. Since the semiconductor wafer 120 is confined in the cavity 110c, the positioning accuracy of the contacts 124 of the semiconductor wafer 120 and the conductive pad 141 of the first re-layout layer 140 can be improved. The first re-layout layer 140 includes a conductive portion 142 and a dielectric layer 143. Furthermore, the first re-layout layer 140 has re-layout side surfaces 140s, and the re-layout side surfaces 140s and the first cage-like member side surfaces 110s3 are aligned with each other (e.g., flush). Furthermore, during the manufacturing process of the semiconductor device 100, the redistribution layer side 140s and the first cage-like member side 110s3 are formed, for example, by slicing (e.g., by sawing, such as diamond blade sawing or laser sawing). The conductive portion 142 may be formed of a material including metals (e.g., copper), and the dielectric layer 143 may be formed of a material including polyimide (PI), oxides, etc.

[0042] As shown in Figure 1B, contacts 150 are disposed on the first layer 140. For example, each contact 150 is disposed on a corresponding conductive pad 141 of the first layer 140. The semiconductor device 100 is, for example, a ball grid array (BGA), and the contacts 150 are, for example, solder balls (or BGA balls), microbumps, etc.

[0043] Please refer to Figure 2, which shows a cross-sectional view of a semiconductor device 200 according to another embodiment of this disclosure.

[0044] As shown in Figure 2, semiconductor device 200 includes at least one semiconductor wafer 220, package 230, first redistribution layer 140, and at least one contact 150. Semiconductor device 200 includes the same or similar features as semiconductor device 100, wherein at least one difference is that the cage member 110 may be omitted in semiconductor device 200.

[0045] As shown in Figure 2, the semiconductor wafer 220 includes a substrate 221, a front-end process structure 122, a back-end process structure 123, and at least one contact 124. The substrate 221 is, for example, a portion of a silicon wafer. The front-end process structure 122 is formed within and / or on the substrate 221, the back-end process structure 123 is formed within and / or on the front-end process structure 122 and is electrically connected to the front-end process structure 122, and the contact 124 is formed on and electrically connected to the back-end process structure 123. The contact 124 is, for example, a solder ball, a microbump, a micropillar, etc.

[0046] As shown in Figure 2, the substrate 221 has a thickness t1. Compared to the substrate 121 in Figure 1B, the thickness t1 of the substrate 221 is less than the thickness of the substrate 121 in the same direction. The package 230 has a thickness t2. Compared to the package 130 in Figure 1B, the thickness t2 of the package 230 is less than the thickness of the package 130 in the same direction. Furthermore, during the manufacturing of the semiconductor device 200, the cage 110, a portion of the semiconductor wafer 120, and a portion of the package 130 in Figure 1B can be removed, for example, by grinding. After removal, a thinned semiconductor wafer 220 and a thinned package 230 are formed. After removal, the substrate 221 of the semiconductor wafer 220 forms a wafer surface 220b, and the package 230 forms a package surface 230b, wherein the wafer surface 220b of the semiconductor wafer 220 and the package surface 230b of the package 230 are aligned with each other (e.g., flush).

[0047] Please refer to Figure 3, which shows a cross-sectional view of a semiconductor device 300 according to another embodiment of this disclosure.

[0048] As shown in Figure 3, the semiconductor device 300 includes at least one cage-like member 310, at least one semiconductor wafer 120, a package 130, a first redistribution layer 140, and at least one contact 150. The cage-like member 310 has a first cage-like member surface 310s1, a second cage-like member surface 310s2 opposite to the first cage-like member surface 310s1, and a cavity 310c extending from the first cage-like member surface 310s1 to the second cage-like member surface 310s2. The semiconductor wafer 120 is disposed in the cavity 310c. The package 130 covers the semiconductor wafer 120. The first redistribution layer 140 is disposed above the package 130 and the semiconductor wafer 120. The cage-like member 310 can restrain the displacement of the semiconductor wafer 120. Furthermore, during the manufacturing process of the semiconductor device 300, the semiconductor wafer 120 can be placed in the cavity 310c of the cage 310 to be constrained in the cavity 310c, thereby improving the positioning accuracy of the semiconductor wafer 120 and the first layer 140.

[0049] In this embodiment, the cage-like member 310 may be formed of a material including organic or inorganic materials, such as metal, glass, ceramic, etc. In one embodiment, the cage-like member 310 does not include any circuit elements. The cage-like member 310 may be formed of the same or similar material as the cage-like member 110.

[0050] In an embodiment, cavity 310c may include features identical or similar to those described above. In this embodiment, cavity 310c is a through hole. For example, cavity 310c extends from the second cage surface 310s2 to the first cage surface 310s1. In another embodiment, cavity 310c is, for example, a blind hole.

[0051] As shown in Figure 3, the package 130 covers the first cage-like member side 310s3 and the first cage-like member surface 310s1, but exposes the second cage-like member surface 310s2. Furthermore, the redistribution side 140s of the first redistribution layer 140 and the package side 130s of the package 130 are exposed from the semiconductor device 300. The redistribution side 140s of the first redistribution layer 140 and the package side 130s of the package 130 are aligned with each other (e.g., flush). Moreover, during the manufacturing of the semiconductor device 300, the redistribution side 140s and the package side 130s are formed, for example, by splitting (e.g., by sawing, such as diamond blade sawing or laser sawing).

[0052] Please refer to Figure 4, which shows a cross-sectional view of a semiconductor device 400 according to another embodiment of this disclosure.

[0053] As shown in Figure 4, the semiconductor device 400 includes a cage-like member 410, at least one semiconductor wafer 120, a package 430, a first redistribution layer 140, at least one contact 150, a second redistribution layer 440, at least one conductive portion 450, and a third redistribution layer 460. The cage-like member 410 has a first cage-like surface 410s1, a second cage-like surface 410s2 opposite to the first cage-like surface 410s1, and a cavity 410c extending from the first cage-like surface 410s1 to the second cage-like surface 410s2. The semiconductor wafer 120 is disposed in the cavity 410c. The package 430 covers the semiconductor wafer 120. The first redistribution layer 140 is disposed above the package 430 and the semiconductor wafer 120. The cage-like member 410 can restrain the displacement of the semiconductor wafer 120. Furthermore, during the manufacturing process of the semiconductor device 400, the semiconductor wafer 120 can be placed in the cavity 410c of the cage 410 to be constrained in the cavity 410c, thereby improving the positioning accuracy of the semiconductor wafer 120 and the first overlapping layer 140.

[0054] In this embodiment, the cage-like member 410 is, for example, a substrate, such as a laminated substrate, a silicon substrate, etc. The substrate may include at least one circuit element.

[0055] In this embodiment, the cavity 410c of the cage-like member 410 is, for example, a blind hole. Furthermore, the cavity 410c extends from the first cage-like member surface 410s1 to the second cage-like member surface 410s2, but does not extend to the second cage-like member surface 410s2.

[0056] As shown in Figure 4, in this embodiment, at least a portion of the package 430 is disposed within the cavity 410c and located between the side 120s of the semiconductor wafer 120 and the side 410c1 of the cavity 410c. In this embodiment, the package 430 does not cover the first cage surface 410s1 of the cage 410. Furthermore, the package 430 may be formed of the same or similar material as the package 130. In another embodiment, the package 430 may be formed of materials such as epoxy resin, polyimides, silicones, polyxylylenes, soloxane polyimide, benzocy clobutene, etc.

[0057] As shown in Figure 4, the first folding layer 140 is disposed above and / or above the third folding layer 460. The second folding layer 440 is disposed on the second cage-like surface 410s2, and the third folding layer 460 is disposed on the first cage-like surface 410s1 and located between the first folding layer 140 and the first cage-like surface 410s1. The second folding layer 440 includes the same or similar features (e.g., structure) as the first folding layer 140, and the third folding layer 460 includes the same or similar features (e.g., structure) as the first folding layer 140.

[0058] As shown in Figure 4, the cage-like member 410 has a first cage-like member side 410s3, the first layer 140 has a layer side 140s, the second layer 440 has a layer side 440s, and the third layer 460 has a layer side 460s. The first cage-like member side 410s3, the layer side 140s, the layer side 440s, and the layer side 460s are aligned with each other (e.g., flush). Furthermore, during the manufacturing of the semiconductor device 400, the first cage-like member side 410s3, the layer side 140s, the layer side 440s, and the layer side 460s are formed, for example, by division (e.g., by sawing, such as diamond blade sawing or laser sawing).

[0059] As shown in Figure 4, the conductive portion 450 electrically connects the second repetitive layer 440 and the third repetitive layer 460. Furthermore, the conductive portion 450 extends from the surface 410s2 of the second cage-like member to the surface 410s1 of the first cage-like member to electrically connect the second repetitive layer 440 and the third repetitive layer 460. In embodiments, the conductive portion 450 is, for example, a conductive via or a conductive pillar. The conductive portion 450 can be formed of, for example, a material including metals (e.g., copper) or alloys thereof.

[0060] Please refer to Figure 5, which illustrates a cross-sectional view of a semiconductor device 500 according to another embodiment of this disclosure.

[0061] As shown in Figure 5, the semiconductor device 500 includes at least one cage-like member 110, at least one semiconductor wafer 520, a package 130, a first redistribution layer 140, and at least one contact 150. The cage-like member 110 has a first cage-like member surface 110s1, a second cage-like member surface 110s2 opposite to the first cage-like member surface 110s1, and a cavity 110c extending from the first cage-like member surface 110s1 to the second cage-like member surface 110s2. The semiconductor wafer 520 is disposed within the cavity 110c. The package 130 covers the semiconductor wafer 520. The first redistribution layer 140 is disposed above the package 130 and the semiconductor wafer 520. The cage-like member 110 can restrain the displacement of the semiconductor wafer 520. Furthermore, during the manufacturing process of a semiconductor wafer, the semiconductor wafer 520 can be placed in the cavity 110c of the cage-like member 110 and confined within the cavity 110c, which can increase the positioning accuracy of the semiconductor wafer 520 and the first overlapping layer 140.

[0062] As shown in Figure 5, the cage-like member 110 is a closed loop. In another embodiment, the cage-like member 110 may be an open loop. Viewed from above, the cage-like member 110 may be polygonal (e.g., rectangular, triangular, etc.), circular, elliptical, etc. The cage-like member 110 has a first cage-like member side 110s3 and a second cage-like member side 110s4 opposite to the first cage-like member side 110s3. The distance d1 between the second cage-like member side 110s4 of the cage-like member 110 and the side 520s of the semiconductor wafer 520 may be, for example, between 1 micrometer and 10 micrometers, such as 1 micrometer, 2 micrometers, 3 micrometers, 4 micrometers, 5 micrometers, 6 micrometers, 7 micrometers, 8 micrometers, 9 micrometers, or 10 micrometers. Such a distance d1 can improve the positioning accuracy of the semiconductor wafer 520 and the first redistribution layer 140.

[0063] In this embodiment, the cavity 110c is a through hole. Furthermore, the cavity 110c extends from the surface 110s2 of the second cage-like member to the surface 110s1 of the first cage-like member. In another embodiment, the cavity 110c is, for example, a blind hole.

[0064] As shown in Figure 5, the semiconductor wafer 520 includes a substrate 121, a front-end process structure 122, and a back-end process structure 123. Compared to the semiconductor wafer 120, the semiconductor wafer 520 may omit the contact 124. The substrate 121 is, for example, part of a silicon wafer. The front-end process structure 122 is formed within and / or on the substrate 121, and the back-end process structure 123 is formed within and / or on the front-end process structure 122 and electrically connected to it. The back-end process structure 123 is electrically connected to the contact 150 through a first redistribution layer 140.

[0065] As shown in Figure 5, the semiconductor wafer 520 has a wafer surface 520b, which is exposed in the cavity 110c, and the wafer surface 520b of the semiconductor wafer 520 is aligned with (e.g., flush with) the second cage surface 110s2 of the cage 110. Furthermore, the semiconductor wafer 520 protrudes relative to the first cage surface 110s1 of the cage 110. Additionally, the semiconductor wafer 520 has a wafer surface 520u relative to the wafer surface 520b, and the package 130 has a package surface 130u, which is aligned with (e.g., flush with) the wafer surface 520u. Furthermore, during the manufacturing of the semiconductor device 500, the package surface 130u and the wafer surface 520u are formed, for example, through techniques such as polishing and chemical-mechanical planarization (CMP).

[0066] As shown in Figure 5, the package 130 encloses the cage-like member 110 and the semiconductor wafer 520. For example, the package 130 covers the first cage-like member surface 110s1, the second cage-like member side 110s4, and the side 520s of the semiconductor wafer 520, but exposes the wafer surface 520u of the semiconductor wafer 520. In addition, the package 130 also fills a portion of the cavity 110c.

[0067] As shown in Figure 5, the package 130 has a package side 130s, and the package side 130s and the first cage side 110s3 are aligned with each other (e.g., flush). Furthermore, during the manufacturing process of the semiconductor device 500, the package side 130s and the first cage side 110s3 are formed, for example, by division (e.g., by sawing, such as diamond blade sawing or laser sawing).

[0068] As shown in Figure 5, the first redistribution layer 140 is disposed above and / or below the package 130 and the semiconductor wafer 520. The first redistribution layer 140 is electrically connected to the semiconductor wafer 520. For example, the first redistribution layer 140 is electrically connected to the back-end process structure 123 of the semiconductor wafer 520. The first redistribution layer 140 includes at least one conductive pad 141 for receiving a contact 150. Furthermore, the first redistribution layer 140 has redistribution sidewalls 140s, and the redistribution sidewalls 140s and the first cage-like sidewalls 110s3 are aligned with each other (e.g., flush). In addition, during the manufacturing of the semiconductor device 500, the redistribution sidewalls 140s and the first cage-like sidewalls 110s3 are formed by, for example, division (e.g., sawing, such as diamond blade sawing or laser sawing).

[0069] Please refer to Figure 6, which illustrates a cross-sectional view of a semiconductor device 600 according to another embodiment of this disclosure.

[0070] As shown in Figure 6, the semiconductor device 600 includes at least one cage-like member 610, at least one semiconductor wafer 620, a package 630, at least one contact 150, and an underfill 670. The cage-like member 610 has a first cage-like member surface 610s1, a second cage-like member surface 610s2 opposite to the first cage-like member surface 610s1, and a cavity 610c extending from the first cage-like member surface 610s1 to the second cage-like member surface 610s2. In this embodiment, the cavity 610c is, for example, a blind via. The semiconductor wafer 620 is disposed in the cavity 610c. The package 630 covers the semiconductor wafer 620 and the cage-like member 610. The cage-like member 610 can restrain the displacement of the semiconductor wafer 620. Furthermore, during the manufacturing process of the semiconductor device 600, the semiconductor wafer 620 can be placed in the cavity 610c of the cage-like member 610 to be constrained in the cavity 610c, thereby improving the positioning accuracy of the semiconductor wafer 620.

[0071] In this embodiment, the cage-like component 610 may include at least one circuit element. The cage-like component 610 is, for example, a semiconductor substrate such as a circuit board. Alternatively, the cage-like component 610 may be a laminate substrate, a silicon substrate, a high thermal conductivity substrate, a metal substrate, a combination thereof, or based on other types of materials.

[0072] As shown in Figure 6, the semiconductor wafer 620 is a flip chip with a wafer surface 620b (e.g., an active surface). The semiconductor wafer 620 is bonded to a cage-like member 610 (e.g., a substrate) in a cavity 610c (e.g., a blind via), with the wafer surface 620b facing the cavity 610c. The semiconductor wafer 620 includes a substrate 121, a front-end process structure 122, a back-end process structure 123, and at least one contact 624. The substrate 121 is, for example, part of a silicon wafer. The front-end process structure 122 is formed within and / or on the substrate 121, the back-end process structure 123 is formed within and / or on the front-end process structure 122 and electrically connected to the front-end process structure 122, and the contact 624 is formed on the back-end process structure 123 and electrically connected to the back-end process structure 123. Contact 624 is disposed on and electrically connected to the wafer surface 620b. Contact 624 may be, for example, a solder ball, a microbump, or a micropillar. Semiconductor wafer 620 is electrically connected to cage 610 through contact 624.

[0073] As shown in Figure 6, the semiconductor wafer 620 protrudes from the first cage-like surface 610s1 of the cage-like member 610. Furthermore, the semiconductor wafer 620 has a wafer surface 620u, and the package 630 has a package surface 630u, wherein the package surface 630u and the wafer surface 620u are aligned with each other (e.g., flush). Moreover, during the manufacturing process of the semiconductor device 600, the package surface 630u and the wafer surface 620u are formed, for example, through grinding, chemical mechanical planarization, etc.

[0074] As shown in Figure 6, the package 630 encapsulates the cage-like component 610 and the semiconductor wafer 620. For example, the package 630 covers the first cage-like surface 610s1 and the second cage-like side surface 610s4 of the cage-like component 610, the side surface 620s of the semiconductor wafer 620, and the side surface of the contact 624, but exposes the second cage-like surface 610s2 and the first cage-like side surface 610s3 of the cage-like component 610. In addition, the package 630 also fills a portion of the cavity 610c.

[0075] As shown in Figure 6, the package 630 has a package side 630s, and the package side 630s and the first cage side 610s3 are aligned with each other (e.g., flush). Furthermore, during the manufacturing process of the semiconductor device 600, the package side 630s and the first cage side 610s3 are formed, for example, by dicing (e.g., by sawing, such as diamond blade sawing or laser sawing).

[0076] Furthermore, the encapsulation 630 may be formed of the same or similar material as the encapsulation 130. In another embodiment, the encapsulation 630 may be formed of a material including epoxy resin, polyimide, silicone, polyxylene, polyimide, benzocyclobutene, etc.

[0077] As shown in Figure 6, the contact 150 is disposed on the second cage surface 610s2 of the cage 610. The semiconductor device 600 is, for example, a ball grid array, and the contact 150 is, for example, a solder ball (or BGA ball), a microbump, etc.

[0078] Please refer to Figure 7, which shows a cross-sectional view of a semiconductor device 700 according to another embodiment of this disclosure.

[0079] As shown in Figure 7, the semiconductor element 700 includes at least one cage-like member 110, at least one semiconductor wafer 720, a package 130, a first redistribution layer 140, at least one contact 150, at least one conductive portion 750, and a conductive layer 770. The cage-like member 110 has a first cage-like surface 110s1, a second cage-like surface 110s2 opposite to the first cage-like surface 110s1, and a cavity 110c extending from the first cage-like surface 110s1 to the second cage-like surface 110s2. The semiconductor wafer 720 is disposed within the cavity 110c. The package 130 covers the semiconductor wafer 720. The first redistribution layer 140 is disposed above the package 130 and the semiconductor wafer 720. The cage-like member 110 can restrain the displacement of the semiconductor wafer 720. Furthermore, during the manufacturing process of the semiconductor device 700, the semiconductor wafer 720 can be placed in the cavity 110c of the cage 110 to be confined within the cavity 110c, thereby improving the positioning accuracy of the semiconductor wafer 720 and the first layer 140.

[0080] As shown in Figure 7, a semiconductor wafer 720 is disposed on a conductive layer 770, and a package 130 has a package surface 130u and a through-hole extending from the package surface 130u to the conductive layer 770. A conductive portion 750 is disposed within the through-hole. In one embodiment, the conductive portion 750 is, for example, a conductive via or a conductive pillar. The conductive portion 750 may be formed of a material comprising, for example, a metal (e.g., copper) or an alloy thereof. The conductive layer 770 may be formed of a material comprising, for example, a metal (e.g., copper) or an alloy thereof.

[0081] As shown in Figure 7, in this embodiment, the semiconductor wafer 720 is, for example, a transistor. The semiconductor wafer 720 includes a substrate 721, electrodes 722, solder 723, and a plurality of electrodes 724 and 725. The substrate 721 is, for example, a portion of a silicon wafer. Although not shown, the substrate 121 includes at least one transistor circuit. Electrodes 722 are formed in and / or on a first surface 721b of the substrate 721, and solder 723 is formed in and / or on the electrodes 722 and electrically connected to the electrodes 722. The semiconductor wafer 720 is disposed on a conductive layer 770 through the solder 723. The transistor circuit of the substrate 721 is electrically connected to the conductive layer 770 through the electrodes 722 and the solder 723, and electrically connected to the first redistribution layer 140 through the electrodes 724 and 725. Electrodes 724 and 725 are formed on a second surface 721u of the substrate 721 and electrically connected to the first redistribution layer 140.

[0082] As shown in Figure 7, the cage-like member 110 is a closed ring. In another embodiment, the cage-like member 110 may be an open ring. Viewed from above, the cage-like member 110 may be a polygon (rectangle, triangle, etc.), a circle, an ellipse, etc. The cage-like member 110 has a first cage-like member side 110s3 and a second cage-like member side 110s4 opposite to the first cage-like member side 110s3.

[0083] In this embodiment, the cavity 110c is a through hole. Furthermore, the cavity 110c extends from the surface 110s2 of the second cage-like member to the surface 110s1 of the first cage-like member. In another embodiment, the cavity 110c is, for example, a blind hole.

[0084] As shown in Figure 7, the package 130 encapsulates the cage 110 and the semiconductor wafer 720. For example, the package 130 covers the first cage surface 110s1, the second cage side 110s4, and the side 720s of the semiconductor wafer 720. In addition, the package 130 also fills a portion of the cavity 110c.

[0085] As shown in Figure 7, the package 130 has a package side 130s, and the package side 130s and the first cage side 110s3 are aligned with each other (e.g., flush). Furthermore, during the manufacturing process of the semiconductor device 700, the package side 130s and the first cage side 110s3 are formed, for example, by splitting (e.g., by sawing, such as diamond blade sawing or laser sawing).

[0086] As shown in Figure 7, the first redistribution layer 140 has redistribution layer side surfaces 140s, wherein the redistribution layer side surfaces 140s and the first cage-like member side surfaces 110s3 are, for example, aligned with each other (e.g., flush). Furthermore, during the manufacturing process of the semiconductor device 700, the redistribution layer side surfaces 140s and the first cage-like member side surfaces 110s3 are formed, for example, by division (e.g., by sawing, such as diamond blade sawing or laser sawing).

[0087] As described above, any of the semiconductor elements 100 to 700 is, for example, a fan-out structure, such as a fan-out wafer-level packaging (FOWLP). FOWLP can be used in a wide variety of applications, including application processors, PMICs, RF, 5G antenna-in-packags (AiP), audio codecs, automotive radar, and high-performance computing and data centers (HPCs) for mobile devices (e.g., smartphones) and wearable devices (e.g., smartwatches). Compared to conventional flip-chip packages, FOWLP offers advantages such as thinner, smaller packages, higher I / O density, better RF performance, and lower thermal resistance. However, in another embodiment, the semiconductor device can also be designed as a fan-in structure.

[0088] Please refer to Figure 8, which shows a cross-sectional view of a semiconductor device 800 according to another embodiment of this disclosure.

[0089] As shown in Figure 8, the semiconductor device 800 includes a substrate 810, a redistribution layer 140, and at least one contact 150. The substrate 810 is, for example, a semiconductor substrate containing at least one semiconductor circuit. The redistribution layer 140 is disposed on the substrate 810 and includes at least one conductive pad 141. The contact 150 is disposed on the redistribution layer 140. The semiconductor device 800 is, for example, a ball grid array (BGA), and the contact 150 is, for example, a solder ball (or BGA ball), a microbump, etc.

[0090] Please refer to Figures 9A-9I, which illustrate a flowchart of a manufacturing method for an embodiment of the semiconductor device 100 in Figure 1B.

[0091] As shown in Figure 9A, a carrier 10 is provided, on which a release layer 11 is disposed. In one embodiment, the release layer 11 is formed on the carrier 10, for example, by deposition. The carrier 10 may be based on glass, an IC substrate, metal, or a suitable material with sufficient thickness to minimize warpage.

[0092] As shown in Figure 9B, a cage-like plate 110' is disposed on the carrier 10 through the release layer 11. The cage-like plate 110' includes at least one cage-like member 110, each cage-like member 110 having a cavity 110c. When the cage-like plate 110' includes multiple cage-like members 110, the cage-like members 110 are connected to each other. The cage-like members 110 can be separated in subsequent processes using, for example, a splitting technique. The cage-like members 110 can be thin, laminated photoresist. In one embodiment, the cage-like plate 110' can be formed by a deposition method, including printing, coating, etc. Furthermore, the thickness of the cage-like plate 110' can be, for example, between 200 micrometers and 300 micrometers.

[0093] As shown in Figure 9C, at least one semiconductor wafer 120 is disposed on a carrier 10 via a release layer 11. Each semiconductor wafer 120 is disposed in a corresponding cavity 110c of a cage-like plate 110'. Each semiconductor wafer 120 includes a substrate 121, a front-end process structure 122, a back-end process structure 123, and at least one contact 124. The substrate 121 is, for example, a portion of a silicon wafer. The front-end process structure 122 is formed in and / or on the substrate 121, the back-end process structure 123 is formed in and / or on the front-end process structure 122 and electrically connected to the front-end process structure 122, and the contact 124 is formed on and electrically connected to the back-end process structure 123. The contact 124 is, for example, a solder ball, a microbump, a micropillar, etc. The substrate 121 has a wafer surface 120b, wherein the wafer surface 120b of the substrate 121 is disposed on the carrier 10 via a release layer 11. Furthermore, the thickness t3 of the semiconductor wafer 120 is greater than the thickness t4 of the cage plate 110'.

[0094] As shown in Figure 9D, a package material 130' covering the semiconductor wafer 120 and the cage plate 110' is formed using methods such as transfer molding and compression molding. The package material 130' covers the sidewalls of the semiconductor wafer 120 and fills a portion of the cavity 110c.

[0095] As shown in Figure 9E, a portion of the package material 130' in Figure 9D can be removed by methods such as polishing or chemical mechanical planarization. After removal, a contact surface 124u of the contact 124 of the semiconductor wafer 120 and a package surface 130u of the package surface 130' are formed, wherein the contact surface 124u and the package surface 130u are aligned with each other (e.g., flush).

[0096] As shown in Figure 9F, the first redistribution structure 140' on the carrier 20 is transferred onto the semiconductor wafer 120 and package material 130' in Figure 9E. Prior to the transfer, the first redistribution structure 140' may be pre-formed on the carrier 20 using, for example, at least one semiconductor process. In one embodiment, the first redistribution structure 140' may be formed on a release layer 21 disposed on the carrier 20.

[0097] As shown in Figure 9G, the carrier 20 and release layer 21 in Figure 9F are removed from the first re-fabricated structure 140', where the conductive pad 141 of the first re-fabricated structure 140' is exposed.

[0098] As shown in Figure 9H, at least one contact 150 is formed on the conductive pad 141 of the first layer structure 140'. Multiple contacts 150 are arranged in a grid array. Contacts 150 are, for example, solder balls (or BGA balls), microbumps, etc.

[0099] As shown in Figure 9I, techniques such as sawing (e.g., diamond blade sawing or laser sawing) can be used to form at least one segmented channel P1 passing through a portion of the first re-layout structure 140', the cage plate 110', the package material 130', and the carrier 10 to form at least one semiconductor device 100. After segmentation, the cage plate 110' forms at least one cage member 110, the first re-layout structure 140' forms at least one first re-layout 140, and the package material 130' forms at least one package 130. After segmentation, each semiconductor device 100 includes the cage member 110, at least one semiconductor wafer 120, the package 130, the first re-layout 140, and at least one contact 150.

[0100] Then, the semiconductor device 100 is separated from the release layer 11 and the carrier 10 in Figure 9I. After separation, the second cage surface 110s2 of the cage 110, the wafer surface 120b of the semiconductor wafer 120, and the package surface 130b of the package 130 of the semiconductor device 100 are exposed.

[0101] In another embodiment, the carrier 10 and release layer 11 in Figure 9G can be replaced by a tape. Then, at least one contact 150 is formed on the conductive pad 141 of the first layered structure 140' (as shown in Figure 9H). Then, using methods such as sawing (e.g., diamond blade sawing or laser sawing) (as shown in Figure 9I), at least one segmented channel P1 is formed penetrating the first layered structure 140', the cage plate 110', the encapsulation material 130', and a portion of the tape to form at least one semiconductor device 100. Furthermore, the manufacturing methods of the semiconductor device in other embodiments include cutting techniques that are the same as or similar to the manufacturing method of the semiconductor device 10, and will not be described further here.

[0102] Please refer to Figures 10A-10C, which illustrate a process diagram of a manufacturing method for another embodiment of the semiconductor device 100 in Figure 1B.

[0103] As shown in Figure 10A, after the steps in Figure 9E, a first overlay structure 140' is formed on the package material 130' and the semiconductor wafer 120 using techniques such as plating, lithography, deposition, and etching. The conductive pads 141 of the first overlay structure 140' are exposed and facing upwards. In this embodiment, the first overlay structure 140' is formed through a process other than transfer. In other words, the first overlay structure 140' is formed directly on the package material 130' and the semiconductor wafer 120 without the need for the carrier 20.

[0104] As shown in Figure 10B, at least one contact 150 is formed on the conductive pad 141 of the first layer structure 140'. Multiple contacts 150 are arranged in a grid array. Contacts 150 may be, for example, solder balls (or BGA balls), microbumps, etc.

[0105] As shown in Figure 10C, at least one segmented channel P1 can be formed by using techniques such as sawing (e.g., diamond blade sawing or laser sawing) to pass through a portion of the first re-layout structure 140', the cage plate 110', the package material 130', and the carrier 10 to form at least one semiconductor device 100. After segmentation, the cage plate 110' forms at least one cage member 110, the first re-layout structure 140' forms at least one first re-layout 140, and the package material 130' forms at least one package 130. After segmentation, each semiconductor device 100 includes the cage member 110, at least one semiconductor wafer 120, the package 130, the first re-layout 140, and at least one contact 150.

[0106] Then, the semiconductor device 100 is separated from the release layer 11 and the carrier 10 of Figure 10C. After separation, the second cage surface 110s2 of the cage 110, the wafer surface 120b of the semiconductor wafer 120, and the package surface 130b of the package 130 of the semiconductor device 100 are exposed.

[0107] Please refer to Figures 11A-11C, which illustrate a process diagram of a manufacturing method of an embodiment of the semiconductor device 200 in Figure 2.

[0108] As shown in Figure 11A, after the steps in Figure 10A, methods such as polishing and chemical mechanical planarization can be used to remove a portion of the cage plate 110', the semiconductor wafer 120 (e.g., substrate 121), and the package material 130' in Figure 10A. After removal, the substrate 121 in Figure 10A is thinned to form a substrate 221 having a thickness t1, and the package material 130' in Figure 10A is thinned to form a package material 230' having a thickness t2. After removal, the package material 230' forms a package surface 230b, and the substrate 121 of the semiconductor wafer 220 forms a wafer surface 220b, wherein the wafer surface 220b of the semiconductor wafer 220 and the package surface 230b of the package 230 are aligned (e.g., flush).

[0109] As shown in Figure 11B, at least one contact 150 is formed on the conductive pad 141 of the first layer structure 140'. Multiple contacts 150 are arranged in a grid array. Contacts 150 may be, for example, contact balls (or BGA balls), microbumps, etc.

[0110] As shown in Figure 11C, the structure shown in Figure 11B is disposed on the carrier 20 through the release layer 21. Then, at least one segmented channel P1 is formed through a portion of the first reflow structure 140', the package material 230', and the carrier 20 using methods such as sawing (e.g., diamond blade sawing or laser sawing) to form at least one semiconductor device 200. After segmentation, the first reflow structure 140' forms at least one first reflow layer 140, and the package material 230' forms at least one package 230. After segmentation, each semiconductor device 200 includes at least one semiconductor wafer 220, a package 230, a first reflow layer 140, and at least one contact 150. In one embodiment, the carrier 20 is, for example, an adhesive tape.

[0111] Then, the semiconductor device 200 is separated from the release layer 21 and the carrier 20 in Figure 11C. After separation, the wafer surface 220b of the semiconductor wafer 220 and the package surface 230b of the package 230 are exposed.

[0112] Please refer to Figures 12A to 12I, which illustrate a process diagram of a manufacturing method of an embodiment of the semiconductor device 300 in Figure 3.

[0113] As shown in Figure 12A, a carrier 10 is provided on which a release layer 11 is disposed. In one embodiment, the release layer 11 is formed on the carrier 10, for example, by deposition.

[0114] As shown in Figure 12B, at least one cage-like member 310 is disposed on the carrier 10 through the release layer 11, and each cage-like member 310 has a cavity 310c. The cage-like member 310 can be a metal, organic or inorganic stopper.

[0115] As shown in Figure 12C, at least one semiconductor wafer 120 is disposed on the carrier 10 through the release layer 11. Each semiconductor wafer 120 is disposed in a corresponding cavity 310c of the cage 310. The semiconductor wafer 120 includes a substrate 121, a front-end process structure 122, a back-end process structure 123, and at least one contact 124. The substrate 121 is, for example, a portion of a silicon wafer. The front-end process structure 122 is formed in and / or on the substrate 121, the back-end process structure 123 is formed in and / or on the front-end process structure 122 and electrically connected to the front-end process structure 122, and the contact 124 is formed on and electrically connected to the back-end process structure 123. The contact 124 is, for example, a solder ball, a microbump, a micropillar, etc. The substrate 121 has a wafer surface 120b, wherein the wafer surface 120b of the substrate 121 is disposed on the carrier 10 via a release layer 11. Furthermore, the thickness t3 of the semiconductor wafer 120 is greater than the thickness t4 of the cage-like member 310.

[0116] As shown in Figure 12D, a package material 130' covering the semiconductor wafer 120 and the cage 310 is formed using methods such as transfer molding and compression molding. The package material 130' fills a portion of the cavity 310c.

[0117] As shown in Figure 12E, a portion of the package material 130' can be removed using techniques such as polishing or chemical mechanical planarization. After removal, the contact surface 124u of the contact 124 of the semiconductor wafer 120 and the package surface 130u of the package surface 130' are formed, wherein the contact surface 124u and the package surface 130u are aligned with each other (e.g., flush).

[0118] As shown in Figure 12F, the first redistribution structure 140' on the carrier 20 is transferred to the semiconductor wafer 120 and package material 130' in Figure 12E. Prior to the transfer, the first redistribution structure 140' may be pre-formed on the carrier 20 using, for example, at least one semiconductor process. In one embodiment, the first redistribution structure 140' may be formed on a release layer 21 disposed on the carrier 20.

[0119] As shown in Figure 12G, the carrier 20 and release layer 21 of Figure 12F are removed from the first re-fabricated structure 140', where the conductive pad 141 of the first re-fabricated structure 140' is exposed.

[0120] As shown in Figure 12H, at least one contact 150 is formed on the conductive pad 141 of the first layer structure 140'. Multiple contacts 150 are arranged in a grid array. Contacts 150 are, for example, solder balls (or BGA balls), microbumps, etc.

[0121] As shown in Figure 12I, techniques such as sawing (e.g., diamond blade sawing or laser sawing) can be used to form at least one segmented channel P1 passing through a portion of the first re-layer structure 140', the package material 130', and the carrier 10 to form at least one semiconductor device 300. After segmentation, the first re-layer structure 140' forms at least one first re-layer 140, and the package material 130' forms at least one package 130. After segmentation, each semiconductor element 300 includes a cage-like member 310, at least one semiconductor wafer 120, a package 130, a first re-layer 140, and at least one contact 150.

[0122] Then, the semiconductor device 300 is separated from the release layer 11 and the carrier 10 in Figure 12I. After separation, the wafer surface 120b of the semiconductor wafer 120, the second cage surface 310s2 of the cage 310, and the package surface 130b of the package 130 are exposed.

[0123] Please refer to Figures 13A-13C, which illustrate a process diagram of a manufacturing method of another embodiment of the semiconductor device 300 in Figure 3.

[0124] As shown in Figure 13A, after the steps in Figure 12E, techniques such as deposition, lithography, etching, and electroplating can be used to form a first overlay structure 140' on the package material 130' and the semiconductor wafer 120, with the conductive pads 141 of the first overlay 140 exposed and facing upwards. In this embodiment, the first overlay structure 140' is formed through processes other than transfer. In other words, the first overlay structure 140' is formed directly on the package material 130' and the semiconductor wafer 120 without the need for the carrier 20.

[0125] As shown in Figure 13B, contacts 150 are formed on the conductive pad 141 of the first layer structure 140'. Multiple contacts 150 are arranged in a grid array. Contacts 150 may be, for example, solder balls (or BGA balls), microbumps, etc.

[0126] As shown in Figure 13C, techniques such as sawing (e.g., diamond blade sawing or laser sawing) can be used to form at least one segmented channel P1 passing through a portion of the first relay structure 140', the package material 130', and the carrier 10 to form at least one semiconductor device 300. After segmentation, the first relay structure 140' forms at least one first relay 140, and the package material 130' forms at least one package 130. After segmentation, each semiconductor device 300 includes a cage-like member 310, at least one semiconductor wafer 120, a package 130, a first relay 140, and at least one contact 150.

[0127] Then, the semiconductor device 300 is separated from the release layer 11 and the carrier 10 in Figure 13C. After separation, the wafer surface 120b of the semiconductor wafer 120, the second cage surface 310s2 of the cage 310, and the package surface 130b of the package 130 are exposed.

[0128] In another embodiment, after the steps in Figure 13A, the semiconductor device 300 may be formed using the same or similar manufacturing steps as those in Figures 11A-11C.

[0129] Please refer to Figures 14A-14I, which illustrate a process diagram of a method for manufacturing a semiconductor device 100' according to an embodiment of the present invention.

[0130] As shown in Figure 14A, at least one semiconductor wafer 120 is bonded to a carrier 10' through a bonding layer 11', wherein the bonding layer 11' is formed, for example, by anodizing.

[0131] As shown in Figure 14B, techniques such as transfer molding and compression molding can be used to form a package material 130' covering the semiconductor wafer 120 on the carrier 10'.

[0132] As shown in Figure 14C, a portion of the package material 130' in Figure 14B can be removed using techniques such as polishing or chemical mechanical planarization. After removal, the contact surface 124u of the contact 124 of the semiconductor wafer 120 and the package surface 130u of the package surface 130' are formed, wherein the contact surface 124u and the package surface 130u are aligned with each other (e.g., flush).

[0133] As shown in Figure 14D, the first redistribution structure 140' on the carrier 20 is transferred onto the semiconductor wafer 120 and package material 130' of Figure 14C. Prior to the transfer, the first redistribution structure 140' may be pre-formed on the carrier 20 using, for example, at least one semiconductor process. In one embodiment, the first redistribution structure 140' may be formed on a release layer 21 disposed on the carrier 20.

[0134] As shown in Figure 14E, the carrier 20 and release layer 21 in Figure 14D are removed from the first re-fabricated structure 140', where the conductive pad 141 of the first re-fabricated structure 140' is exposed.

[0135] As shown in Figure 14F, the carrier 10 and bonding layer 11' in Figure 14E can be removed using, for example, wet etching, back grinding, chemical-mechanical polishing, dry etching (e.g., reactive ion etching), or a combination thereof. After removal, the wafer surface 120b of the semiconductor wafer 120 and the package surface 130b of the package material 130' are formed, wherein the wafer surface 120b and the package surface 130b can be aligned with each other (e.g., flush).

[0136] As shown in Figure 14G, the structure of Figure 14F is configured on a carrier 10', wherein the carrier 10' is, for example, an adhesive tape.

[0137] As shown in Figure 14H, contacts 150 are formed on the conductive pads 141 of the first layer structure 140'. Multiple contacts 150 are arranged in a grid array. Contacts 150 may be, for example, solder balls (or BGA balls), microbumps, etc.

[0138] As shown in Figure 14I, techniques such as sawing (e.g., diamond blade sawing or laser sawing) can be used to form at least one segmented channel P1 passing through a portion of the first relay structure 140', the package material 130', and the carrier 10' to form at least one semiconductor device 100'. After segmentation, the first relay structure 140' forms at least one first relay 140, and the package material 130' forms at least one package 130. After segmentation, each semiconductor device 100' includes a semiconductor wafer 120, a package 130, a first relay 140, and at least one contact 150.

[0139] Then, the semiconductor device 100' is separated from the carrier 10' in Figure 14I. After separation, the wafer surface 120b of the semiconductor wafer 120 in Figure 14I and the package surface 130b of the package 130 are exposed.

[0140] Please refer to Figures 15A to 15I, which illustrate the process of manufacturing the semiconductor device 200 shown in Figure 2.

[0141] As shown in Figure 15A, a carrier 40 is provided on which a release layer 41 is disposed. In one embodiment, the release layer 41 is formed on the carrier 40, for example, by deposition. The carrier 40 has a cavity 40r, wherein the release layer 41 is also formed on at least one of all sidewalls of the cavity 40r.

[0142] As shown in Figure 15B, at least one semiconductor wafer 120 is disposed on the carrier 40 via a release layer 41, wherein the semiconductor wafer 120 is disposed within a cavity 40r of the carrier 40. The cavity 40r of the carrier 40 can restrain the displacement of the semiconductor wafer 120. Furthermore, the semiconductor wafer 120 can be disposed within the cavity 40r of the carrier 40 to be restrained within the cavity 40r.

[0143] As shown in Figure 15C, techniques such as transfer molding and compression molding can be used to form a package material 130' covering the semiconductor wafer 120 and the carrier 40. The package material 130' fills a portion of the cavity 40r, thereby improving the positioning accuracy of the semiconductor wafer 120 and the first overlay structure 140' (formed in the process shown in Figure 15E).

[0144] As shown in Figure 15D, a portion of the package material 130' can be removed using techniques such as polishing or chemical mechanical planarization. After removal, the contact surface 124u of the junction 124 of the semiconductor wafer 120 and the package surface 130u of the package surface 130' are aligned with each other (e.g., flush).

[0145] As shown in Figure 15E, a first overlay structure 140' can be formed over the package material 130' and the semiconductor wafer 120 using, for example, at least one semiconductor process. The first overlay structure 140' includes at least one conductive pad 141, which is exposed and facing upwards.

[0146] As shown in Figure 15F, techniques such as grinding and chemical mechanical planarization can be used to remove a portion of the substrate 121 and the entire carrier 40 in Figure 15E. After removal, the substrate 121 in Figure 15E is thinned to form a substrate 221 having a thickness t1, and the encapsulation material 130' in Figure 15E is thinned to form an encapsulation material 230' having a thickness t2.

[0147] As shown in Figure 15G, the structure in Figure 15F is disposed on the carrier 20 through the release layer 21.

[0148] As shown in Figure 15H, at least one contact 150 is formed on the conductive pad 141 of the first layer structure 140'. Multiple contacts 150 are arranged in a grid array. Contacts 150 are, for example, solder balls (or BGA balls), microbumps, etc.

[0149] As shown in Figure 15I, at least one segmented channel P1 can be formed through a portion of the first refolding structure 140', the package material 230', and the carrier 20 using techniques such as sawing (e.g., diamond sawing or laser sawing) to form at least one semiconductor device 200. After segmentation, the first refolding structure 140' forms at least one first refold 140, and the package material 230' forms at least one package 230. After segmentation, each semiconductor device 200 includes at least one semiconductor wafer 220, a package 230, a first refold 140, and at least one contact 150.

[0150] Then, the semiconductor device 200 is separated from the release layer 21 and the carrier 20 in Figure 15I. After separation, the wafer surface 220b of the semiconductor wafer 220 and the package surface 230b of the package 230 are exposed.

[0151] Please refer to Figures 16A to 16G, which illustrate process diagrams of a manufacturing method for one embodiment of the semiconductor device 400 in Figure 4.

[0152] As shown in Figure 16A, a carrier 10 is provided on which a release layer 11 is disposed. In one embodiment, the release layer 11 is formed on the carrier 10, for example, by deposition.

[0153] As shown in Figure 16B, a semiconductor element 400A is disposed on a carrier 10 through a release layer 11. The semiconductor element 400A includes a cage-like plate 410', a second re-layer structure 440', at least one conductive portion 450, and a third re-layer structure 460'. The cage-like plate 410' has a first cage-like surface 410s1, a second cage-like surface 410s2 opposite to the first cage-like surface 410s1, and at least one cavity 410c extending from the first cage-like surface 410s1 to the second cage-like surface 410s2. In this embodiment, the cavity 410c is, for example, a blind via. The cage-like component 410' can be a laminated substrate, a silicon substrate, a high thermal conductivity substrate, a metal substrate, a combination thereof, or based on other types of materials. The conductive portion 450 electrically connects the second re-layer structure 440' and the third re-layer structure 460'. In addition, the conductive part 450 extends from the surface 410s2 of the second cage-like member to the surface 410s1 of the first cage-like member to electrically connect the second layered structure 440' and the third layered structure 460'.

[0154] As shown in Figure 16C, at least one semiconductor wafer 120 is disposed in the corresponding cavity 410c. The cage plate 410' can restrain the displacement of the semiconductor wafer 120, and since the semiconductor wafer 120 can be placed in the cavity 410c of the cage plate 410' and thus restrained in the cavity 410c, the positioning accuracy of the semiconductor wafer 120 and the first layered structure 140' (formed in the step of Figure 16E) can be improved.

[0155] As shown in Figure 16D, a package 430 filling the cavity 410c is formed using techniques such as glue dispense, transfer molding, or compression molding. In another embodiment, if necessary, techniques such as polishing or chemical mechanical planarization may be used to remove a portion of the package 430 to expose the contacts 124 of the semiconductor wafer 120.

[0156] As shown in Figure 16E, a first overlay structure 140' is formed over the third overlay structure 460' and the contact 124 of the semiconductor wafer 120 using techniques such as electroplating, lithography, deposition, and etching. The first overlay structure 140' includes at least one conductive pad 141 exposed therefrom. In another embodiment, the first overlay structure 140' may be formed using, for example, the transfer method shown in Figure 9F.

[0157] As shown in Figure 16F, at least one contact 150 is formed on the conductive pad 141 of the first layer structure 140'. Multiple contacts 150 are arranged in a grid array. Contacts 150 are, for example, solder balls (or BGA balls), microbumps, etc.

[0158] As shown in Figure 16G, at least one segmented channel P1 can be formed by sawing (e.g., diamond blade sawing or laser sawing) through a portion of the first re-layer structure 140', the third re-layer structure 460', the cage plate 410', the second re-layer structure 440', and the carrier 10 to form at least one semiconductor device 400. After segmentation, the cage plate 410' forms at least one cage member 410, the first re-layer structure 140' forms at least one first re-layer 140, the third re-layer structure 460' forms at least one third re-layer 460, and the second re-layer structure 440' forms at least one second re-layer 440. After segmentation, each semiconductor device 400 includes a cage member 410, at least one semiconductor wafer 120, a package 430, a first re-layer 140, at least one contact 150, a second re-layer 440, at least one conductive portion 450, and a third re-layer 460.

[0159] Then, the semiconductor device 400 is separated from the release layer 11 and the carrier 10 in Figure 16G. After separation, the second re-laid layer 440 is exposed.

[0160] Please refer to Figures 17A-17J, which illustrate a process diagram of a manufacturing method for one embodiment of the semiconductor device 500 in Figure 5.

[0161] As shown in Figure 17A, a carrier 10 is provided on which a release layer 11 is disposed. In one embodiment, the release layer 11 is formed on the carrier 10, for example, by deposition.

[0162] As shown in Figure 17B, the cage plate 110' is disposed on the carrier 10 via the release layer 11. The cage plate 110' includes at least one cage member 110, each cage member 110 having a cavity 110c. When the cage plate 110' includes multiple cage members 110, the cage members 110 are connected to each other. The cage members 110 can be divided in subsequent processes using, for example, a segmentation technique.

[0163] As shown in Figure 17C, at least one semiconductor wafer 520 is disposed on the carrier 10 through the release layer 11. Each semiconductor wafer 520 is disposed in a cavity 110c corresponding to the cage plate 410'. The semiconductor wafer 520 includes a substrate 121, a front-end processing structure 122, and a back-end processing structure 123. Compared to the semiconductor wafer 120, the semiconductor wafer 520 can omit the contact 124. The semiconductor wafer 520 is disposed on the carrier 10 through the back-end processing structure 123.

[0164] As shown in Figure 17D, a package material 130' covering the semiconductor wafer 520 and the cage plate 110' is formed using techniques such as transfer molding and compression molding. The package material 130' covers the side of the semiconductor wafer 520 and fills a portion of the cavity 110c.

[0165] As shown in Figure 17E, techniques such as polishing and chemical mechanical planarization can be used to remove a portion of the package material 130' to expose the wafer surface 520u of the semiconductor wafer 520. After dicing, the package material 130' forms the package surface 130u, and the package surface 130u is aligned with (e.g., flush with) the wafer surface 520u.

[0166] As shown in Figure 17F, the carrier 10 with the release layer 11 is removed from the carrier 10, exposing the wafer surface 520b of the back-end process structure 123 of the semiconductor wafer 520 and the second cage plate surface 110s2 of the cage plate 110'.

[0167] As shown in Figure 17G, techniques such as electroplating, lithography, deposition, and etching can be used to form a first overlay structure 140' above the cage-like plate 110' and the back-end process structure 123 of the semiconductor wafer 520. The first overlay structure 140' includes at least one conductive pad 141.

[0168] As shown in Figure 17H, the structure shown in Figure 17G is flipped so that the first layer structure 140' faces upward, and then disposed on the carrier 20 via the release layer 21, wherein the encapsulation surface 130u and the wafer surface 520u are disposed on the carrier 20, and the conductive pad 141 faces upward.

[0169] As shown in Figure 17I, at least one contact 150 is formed on the conductive pad 141 of the first layer structure 140'. Multiple contacts 150 are arranged in a grid array. Contacts 150 are, for example, solder balls (or BGA balls), microbumps, etc.

[0170] As shown in Figure 17J, techniques such as sawing (e.g., diamond blade sawing or laser sawing) can be used to form at least one segmented channel P1 passing through a portion of the first relay structure 140', the cage plate 110', the package material 130', and the carrier 20 to form at least one semiconductor device 500. After segmentation, the cage plate 110' forms at least one cage member 110, the first relay structure 140' forms at least one first relay 140, and the package material 130' forms at least one package 130. After segmentation, each semiconductor device 500 includes the cage member 110, at least one semiconductor wafer 520, the package 130, the first relay 140, and at least one contact 150.

[0171] Then, the semiconductor device 500 is separated from the release layer 21 and the carrier 20 in Figure 17J. After separation, the wafer surface 520u of the semiconductor wafer 520 and the package surface 130u of the package 130 are exposed.

[0172] Please refer to Figures 18A-18I, which illustrate process diagrams of a manufacturing method for one embodiment of the semiconductor device 600 in Figure 6.

[0173] As shown in Figure 18A, a carrier 10 is provided on which a release layer 11 is disposed. In one embodiment, the release layer 11 is formed on the carrier 10, for example, by deposition.

[0174] As shown in Figure 18B, the cage-like plate 610' is disposed on the carrier 10 via the release layer 11. The cage-like plate 610' has a first cage-like surface 610s1, a second cage-like surface 610s2 opposite to the first cage-like surface 610s1, and at least one cavity 610c extending from the first cage-like surface 610s1 toward the second cage-like surface 610s2. In this embodiment, the cavity 610c is, for example, a blind via. In this embodiment, the cage-like plate 610' may include at least one circuit element. The cage-like plate 610' may be a laminated substrate, a silicon substrate, a high thermal conductivity substrate, a metal substrate, a combination thereof, or based on other types of materials.

[0175] As shown in Figure 18C, at least one semiconductor wafer 620 is disposed on the bottom surface of cavity 610c. The semiconductor wafer 620 is a flip-chip having a wafer surface 620b (e.g., an active surface). The semiconductor wafer 620 includes a substrate 121, a front-end process structure 122, a back-end process structure 123, and at least one contact 624. The substrate 121 is, for example, part of a silicon wafer. The front-end process structure 122 is formed within and / or on the substrate 121, the back-end process structure 123 is formed within and / or on the front-end process structure 122 and electrically connected to the front-end process structure 122, and the contact 624 is formed on and connected to the back-end process structure 123. The contact 624 is disposed on and electrically connected to the wafer surface 620b, and the contact 624 is, for example, a solder ball, a microbump, a micropillar, etc. The semiconductor chip 620 is electrically connected to the cage-like member 610 through the contact 624.

[0176] As shown in Figure 18C, a bottom filler 670 is formed by using, for example, dispensing, to cover the contacts 624 of the semiconductor wafer 620.

[0177] As shown in Figure 18D, the package material 630' covering the semiconductor wafer 620, the cage plate 610' and the bottom filler 670 are formed by methods such as transfer molding and compression molding.

[0178] As shown in Figure 18E, a portion of the package material 630' can be removed using methods such as polishing or chemical mechanical planarization to expose the wafer surface 620u of the semiconductor wafer 620. After dicing, the package material 630' forms the package surface 630u, wherein the package surface 630u is aligned with (e.g., flush with) the wafer surface 620u.

[0179] As shown in Figure 18F, the carrier 10 with release layer 11 is removed to expose the second cage surface 610s2 of cage plate 610'.

[0180] As shown in Figure 18G, the structure shown in Figure 18F is flipped so that the second cage-like surface 610s2 of the cage plate 610' faces upward, and this structure is then disposed on the carrier 20 through the release layer 21, wherein the packaging surface 630u and the wafer surface 620u are both disposed on the carrier 20.

[0181] As shown in Figure 18H, at least one contact 150 is formed on the second cage-like surface 610s2 of the cage-like plate 610'. Multiple contacts 150 are arranged in a grid array. Contacts 150 are, for example, solder balls (or BGA balls), microbumps, etc.

[0182] As shown in Figure 18I, at least one slit channel P1 can be formed through a portion of the cage plate 610', the package material 630', and the carrier 20 using techniques such as sawing (e.g., diamond blade sawing or laser slicing) to form at least one semiconductor device 600. After slicing, the cage plate 610' forms at least one cage member 610, and the package material 630' forms at least one package 630. After slicing, each semiconductor device 600 includes the cage member 610, at least one semiconductor wafer 620, the package 630, and the underfill adhesive 670.

[0183] Then, as shown in the figure, the semiconductor device 600 is separated from the release layer 21 and the carrier 20 in Figure 18I. After separation, the wafer surface 620u of the semiconductor wafer 620 and the package surface 630u of the package 630 are exposed.

[0184] Please refer to Figures 19A-19J, which illustrate a process diagram of a manufacturing method for one embodiment of the semiconductor device 700 in Figure 7.

[0185] As shown in Figure 19A, a carrier 10 is provided on which a release layer 11 is disposed. In one embodiment, the release layer 11 is formed on the carrier 10, for example, by deposition.

[0186] As shown in Figure 19B, the cage-like plate 110' is disposed on the carrier 10 via a release layer 11. The cage-like plate 110' includes at least one cage-like member 110, each cage-like member 110 having a cavity 110c. When the cage-like plate 110' includes multiple cage-like members 110, the cages 110 are connected to each other. The cage-like members 110 can be separated in subsequent processes using, for example, splitting techniques. Furthermore, the cage-like member 110' is, for example, a thin, laminated photoresist layer.

[0187] As shown in Figure 19C, at least one conductive layer 770 can be disposed on the release layer 11 of the carrier 10 in the cavity 110c using methods such as electroplating or deposition. Next, at least one semiconductor wafer 720 is disposed on the conductive layer 770. The semiconductor wafer 720 includes a substrate 721, an electrode 722, solder 723, and a plurality of electrodes 724 and 725. The substrate 721 is, for example, part of a silicon wafer. Although not shown, the substrate 121 includes at least one transistor circuit. The electrode 722 is formed in and / or on a first surface 721b of the substrate 721, and the solder 723 is formed in and / or on the electrode 722 and electrically connected to the electrode 722. The semiconductor wafer 720 is disposed on the conductive layer 770 through the solder 723. The transistor circuit in the substrate 721 is electrically connected to the conductive layer 770 through the electrode 722 and the solder 723. Electrodes 724 and 725 are formed on the second surface 721u of the substrate 721. Electrodes 724 and 725 are, for example, solder bumps, solder balls, etc. A semiconductor wafer 720 is disposed on a portion of the surface 770u of the conductive layer 770, and another portion of the surface 770u of the conductive layer 770 is exposed (not covered by the semiconductor wafer 720).

[0188] As shown in Figure 19D, the package material 130' can be formed to cover the semiconductor wafer 720, the cage plate 110', and the conductive layer 770 by methods such as transfer molding and compression molding. The package material 130' covers the side of the semiconductor wafer 720 and fills a portion of the cavity 110c.

[0189] As shown in Figure 19E, a portion of the package material 130' can be removed using methods such as polishing or chemical mechanical planarization to expose the electrodes 724 and 725 of the semiconductor wafer 720. Then, electrode 724 forms electrode surface 724u, electrode 725 forms electrode surface 725u, and package material 130' forms package surface 130u, wherein electrode surface 724u, electrode surface 725u, and package surface 130u are aligned with each other (e.g., flush).

[0190] As shown in Figure 19F, at least one hole 750a extending from the package surface 130u of the package 130 to the conductive layer 770 can be formed using methods such as laser drilling, lithography, etching, etc.

[0191] As shown in Figure 19G, at least one conductive portion 750 filling the corresponding hole 750a can be formed using methods such as electroplating or deposition, wherein the conductive portion 750 is electrically connected to the conductive layer 770. In one embodiment, if necessary, methods such as polishing or chemical mechanical planarization can be used to remove part of the package material 130' and part of the conductive portion 750 to expose the electrodes 724 and 725 of the semiconductor wafer 720. In one embodiment, the electrode surface 724u, the electrode surface 725u, the package surface 130u, and the conductive surface 750u of the conductive portion 750 are aligned with each other (e.g., flush).

[0192] As shown in Figure 19H, the first re-layer structure 140' on the carrier 20 is transferred to the semiconductor wafer 720, conductive portion 750, and package material 130' in Figure 19G. Prior to the transfer, the first re-layer structure 140' can be pre-formed on the carrier 20 using at least one semiconductor process (e.g., deposition, lithography, electroplating, etching, etc.). In one embodiment, the first re-layer structure 140' may be formed on a release layer 21 disposed on the carrier 20. The first re-layer structure 140' is electrically connected to the electrodes 724, 725 and the conductive portion 750 of the semiconductor wafer 720.

[0193] As shown in Figure 19I, at least one contact 150 is formed on the conductive pad 141 of the first layer structure 140'. Multiple contacts 150 are arranged in a grid array. Contacts 150 are, for example, solder balls (or BGA balls), microbumps, etc.

[0194] As shown in Figure 19J, techniques such as sawing (e.g., diamond blade sawing or laser sawing) can be used to form at least one segmented channel P1 passing through a portion of the first relay structure 140', the cage plate 110', the package material 130', and the carrier 10 to form at least one semiconductor device 700. After segmentation, the cage plate 110' forms at least one cage element 110, the first relay structure 140' forms at least one first relay 140, and the package material 130' forms at least one package 130. After segmentation, each semiconductor device 700 includes the cage element 110, at least one semiconductor wafer 720, the package 130, the first relay 140, at least one contact 150, at least one conductive portion 750, and at least one conductive layer 770.

[0195] Then, the semiconductor element 700 is separated from the release layer 11 and the carrier 10 in Figure 19J. After separation, the second cage surface 110s2 of the cage 110, the conductive surface 770b of the conductive layer 770, and the package surface 130b of the package 130 are exposed.

[0196] Please refer to Figures 20A-20C, which illustrate a process diagram of a manufacturing method for another embodiment of the semiconductor device 700 in Figure 7.

[0197] As shown in Figure 20A, after the steps in Figure 19G, techniques such as electroplating, lithography, deposition, and etching can be used to form a first overlay structure 140' on the package material 130', the semiconductor wafer 720, and the conductive portion 750. The conductive pad 141 of the first overlay structure 140' is exposed and facing upwards. The first overlay structure 140' is electrically connected to the conductive portion 750 of the semiconductor wafer 720 and the electrodes 724 and 725. In this embodiment, the first overlay structure 140' is formed through processes other than transfer. In other words, the first overlay structure 140' is formed directly on the package material 130', the semiconductor wafer 720, and the conductive portion 750, without the need for the carrier 20.

[0198] As shown in Figure 20B, at least one contact 150 is formed on the conductive pad 141 of the first layer structure 140'. Multiple contacts 150 are arranged in a grid array. The contacts 150 are, for example, solder balls (or BGA balls), microbumps, etc.

[0199] As shown in Figure 20C, techniques such as sawing (e.g., diamond saw or laser saw) can be used to form at least one segmented channel P1 passing through a portion of the first re-layer structure 140', the cage plate 110', the package material 130', and the carrier 10 to form at least one semiconductor device 700. After segmentation, the cage plate 110' forms at least one cage element 110, the first re-layer structure 140' forms at least one first re-layer 140, and the package material 130' forms at least one package 130. After segmentation, each semiconductor device 700 includes the cage element 110, at least one semiconductor wafer 720, the package 130, the first re-layer 140, at least one contact 150, at least one conductive portion 750, and at least one conductive layer 770.

[0200] Then, the semiconductor element 700 is separated from the release layer 11 and the carrier 10 as shown in Figure 20C. After separation, the second cage surface 110s2 of the cage 110, the conductive surface 770b of the conductive layer 770, and the package surface 130b of the package 130 are exposed.

[0201] Please refer to Figures 21A to 21G, which illustrate process diagrams of a manufacturing method for one embodiment of the semiconductor device 800 in Figure 8.

[0202] As shown in Figure 21A, a carrier 50 is provided. The carrier 50 is, for example, glass.

[0203] As shown in Figure 21B, a spacer 55 is provided, wherein the spacer 55 has at least one hole 55a. In this embodiment, the hole 55a is, for example, a through hole. The spacer 55 may be formed of materials including polyimide, metal, etc.

[0204] As shown in Figures 21C1 and 21C2, Figure 21C2 illustrates a cross-sectional view of the structure in Figure 21C1 along the direction 21C2-21C2'. The spacer 55 is disposed on the carrier 50 through the release layer 51, wherein the release layer 51 is formed on the carrier 50, for example, by deposition.

[0205] As shown in Figures 21D1 and 21D2, Figure 21D2 illustrates a cross-sectional view of the structure in Figure 21D1 along the direction 21D2-21D2'. At least one substrate 810 is disposed in a hole 55a, wherein each substrate 810 is disposed within a corresponding hole 55a. Then, using techniques such as coating, dispensing, and molding, a filler 57 is formed to fill the space between the substrate 810 and the sidewalls of the hole 55a. Then, using techniques such as electroplating, photolithography, deposition, and etching, a first overlapping layer structure 140' is formed above the substrate 810 and the filler 57. The first overlapping layer structure 140' includes at least one conductive pad 141, and the conductive pad 141 is located above the substrate 810. In other words, the conductive pad 141 overlaps with the substrate 810 on the Z-axis. The filler 57 can fix the relative position between the spacer 55 and the substrate 810. The filler 57 here can be a polymer encapsulant, oxide, silicon substrate, etc., commonly used in integrated circuit (IC) packages or liquid-crystal display (LCD) driver IC packages. In one embodiment, the substrate 810 is, for example, an uncutter semiconductor wafer. The substrate 810 may include at least one integrated circuit. Furthermore, the thickness of the substrate 810 is equal to the thickness of the spacer 55 (e.g., on the Z-axis).

[0206] As shown in Figure 21E, at least one dividing channel P1 is formed along the edge of the substrate 810 through the first re-layer structure 140' using a method such as laser cutting. After dividing, the first re-layer structure 140' forms at least one first re-layer 140.

[0207] Then, the filler 57 and release layer 51 of Figure 21E (in the case of using a UV-release layer) are photodissociated (e.g., irradiated with UV). Preferably, the spacer 55 can be reused.

[0208] As shown in Figure 21F, after photodissociation, the structure including the first re-layer 140 and the substrate 810 is separated from the filler 57 and the release layer 51.

[0209] As shown in Figure 21G, at least one contact 150 is formed on the conductive pad 141 of the first redistribution layer 140 to form a semiconductor device 800. Multiple contacts 150 are arranged in a grid array. Contacts 150 are, for example, solder bumps, solder balls (or BGA balls). The semiconductor device 800 of Figure 21G can then be individualized using techniques such as sawing (e.g., diamond blade sawing or laser sawing) to form multiple semiconductor dies.

[0210] In another embodiment, techniques such as sawing (e.g., diamond blade sawing or laser sawing) can be used to unify the structure of Figure 21F to form multiple semiconductor grains, and then at least one contact 150 is formed on the conductive pad 141 of the first redistribution layer 140 of the semiconductor grains.

[0211] Please refer to Figures 22A and 22B. Figure 22A shows a schematic diagram of a panel-level packaging according to one embodiment, while Figure 22B shows a cross-sectional view of the panel-level packaging of Figure 22A along direction 22B-22B'.

[0212] Fan-out panel-level packaging (FOPLP) can significantly reduce assembly costs by 30% to 40% compared to FOWLP, provided that the related processes of chip placement, molding, and redistribution can be scaled up at the same production volume. Currently, FOPLP is used in low-end / mid-range, high-volume applications, such as power management ICs, which have relatively relaxed size requirements, such as a linewidth / pitch (L / S) equal to or greater than 10. / 10 And a looser, more layered fabric.

[0213] As shown in Figures 22A and 22B, in a panel-level package (e.g., a fan-out panel-level package or a fan-in panel-level package), multiple semiconductor devices 900 are disposed on a carrier 10 through a release layer 11. Each semiconductor device 900 is, for example, a semiconductor die, such as an active chip or a passive component. In another embodiment, this semiconductor die can be pre-bumped using a mature, high-volume, fine L / S wafer-level process (relative to the relatively new via-aperture / metal-fill process in large-panel fan-out panel-level packages) prior to FOPLP, wherein the bumps include solder bumps, copper pillar microbumps, gold bumps, or other bumps suitable for fine pitch. The package material 130' includes multiple package islands 130A, wherein a dividing channel DS is formed at adjacent package islands 130A. Therefore, it can minimize thermal expansion coefficient mismatch, mold flow, and other effects. Lower thermal expansion coefficients, lower modulus molding compounds or package materials, and adaptive patterning can be used to minimize warpage effects.

[0214] In summary, although this disclosure has been presented above with reference to embodiments, it is not intended to limit the scope of this disclosure. Those skilled in the art to which this disclosure pertains can make various modifications and refinements without departing from the spirit and scope of this disclosure, and such modifications and refinements are not limited to the embodiments of this invention, but remain within the protection scope of this invention. Therefore, the protection scope of this disclosure shall be determined by the appended claims.

[0215] 10, 20, 40: Carrier 11, 21: Release layer 40r: Cavity 55a: Hole 55: Spacers 57: Filler 100, 100', 200, 300, 400, 500, 600, 700, 800, 900: Semiconductor devices 110, 310, 410, 610: Cage-like components 110', 410', 610': cage plate 110c, 310c, 410c, 610c: Cavity 110s1, 310s1, 410s1, 610s1: Surface of the first cage-like component 110s², 310s², 410s², 610s²: Surface of the second cage-like component 110s3, 310s3, 410s3, 610s3: Side of the first cage-like component 110s4, 610s4: Side of the second cage-like component 120, 220, 520, 620, 720: Semiconductor wafers 120s, 520s, 720s: Side view 120b, 520b, 520u, 620b, 620u: wafer surface 121, 221, 721: Base 122: Front-end process structure 123: Back-end process structure 124, 150, 624: Contact 124u: Contact surface 130, 230, 430, 630: Package 130', 230': Package material 130s, 130u: Package side view 130A: Packaging Island 140: First layer of fabric 140': First layer structure 140s, 440s, 460s: Side of the re-weave layer 141: Conductive pad 142, 450, 750: Conductive parts 143: Dielectric layer 220b: Wafer surface 230b, 630u: Package surface 400A: Semiconductor Components 440: Second layer 440': Second layer structure 460: Third layer 460': Third layer structure 520u: wafer surface 670: Bottom filling 721b: First Surface 721u: Second Surface 722, 724, 725: Electrodes 723: Solder 724u, 725u: Electrode surface 750a: Hole 750u, 770b: Conductive surfaces 770: Conductive layer 770u: Surface 810:Substrate d1: Distance DS: Divider P1: Cutting Channel t1, t2, t3, t4: Thickness

Claims

1. A semiconductor device, comprising: A cage-like component has a first cage-like component surface, a second cage-like component surface opposite to the first cage-like component surface, and a cavity extending from the first cage-like component surface to the second cage-like component surface. A semiconductor wafer is disposed in the cavity; a package covers the semiconductor wafer; and a first overlay is formed on the package and the semiconductor wafer.

2. The semiconductor device as claimed in claim 1, wherein the cavity extends to the surface of the first cage-like member.

3. The semiconductor device of claim 1, wherein the semiconductor wafer has a wafer back side, and the wafer back side of the semiconductor wafer is flush with the surface of the second cage of the cage.

4. The semiconductor device as claimed in claim 1, wherein the semiconductor wafer protrudes relative to the surface of the first cage-like member of the cage-like member.

5. The semiconductor device of claim 1, wherein the package has a package side, the cage has a cage side, and the package side and the cage side are flush with each other.

6. The semiconductor device of claim 1, wherein the cage has a cage surface and the package covers the cage surface and the first cage surface, but exposes the second cage surface.

7. The semiconductor device of claim 1, wherein the cavity is a blind via located on the cage-like member, the cage-like member being a substrate, the semiconductor wafer being a flip-chip having an active surface, the flip-chip being bonded to the substrate in the blind via, the active surface facing the blind via.

8. The semiconductor device of claim 1, wherein the semiconductor wafer is a flip-chip having an active surface, the first redistribution layer is disposed on the surface of the second cage and the active surface, and the package covers the first cage surface of the cage.

9. The semiconductor device as claimed in claim 1, further comprising: A conductive layer is located within the cavity; wherein the semiconductor wafer is disposed on the conductive layer, the package has a package surface and a through hole extending from the package surface to the conductive layer, and the semiconductor device further includes a conductive portion located within the through hole.

10. The semiconductor device as claimed in claim 1, further comprising: A conductive portion extends from the surface of the second cage-like member to the surface of the first cage-like member.

11. The semiconductor device as claimed in claim 10, further comprising: A second layer of fabric is disposed on the surface of the second cage-like member; And a third layer of fabric, disposed on the surface of the first cage-like member and located between the first layer of fabric and the surface of the first cage-like member; wherein the conductive portion is electrically connected to the second layer of fabric and the third layer of fabric.

12. The semiconductor device of claim 10, wherein the package is disposed in the cavity and between one side of the semiconductor wafer and the side of the cavity.

13. A manufacturing method, further comprising: A cage-like component is disposed on a carrier, wherein the cage-like component has a first cage-like component surface, a second cage-like component surface opposite to the first cage-like component surface, and a cavity extending from the first cage-like component surface to the second cage-like component surface. A semiconductor wafer is disposed in the cavity; a package is disposed to cover the semiconductor wafer; a first overlay layer is disposed to cover the package and the semiconductor wafer; and the carrier is removed to expose the first overlay layer.

14. The manufacturing method as claimed in claim 13, wherein the step of configuring the first overlay layer to cover the package and the semiconductor wafer includes: The first repetitive layer is configured on the carrier; the first repetitive layer is transferred via the carrier to the package and the semiconductor wafer; And remove the carrier.

15. The manufacturing method as described in claim 13, further comprising: Remove the cage-like component and a portion of the semiconductor wafer.

16. The manufacturing method as claimed in claim 13, wherein in the step of configuring the package to cover the semiconductor wafer, the package further covers one side of the cage-like member.

17. The manufacturing method of claim 13, wherein the cage-like member comprising the cavity of a blind via is disposed on the carrier; the semiconductor wafer is a flip-chip bonded to the blind via, and an active surface of the semiconductor wafer faces the blind via.

18. The manufacturing method as described in claim 13, further comprising: A conductive layer is disposed within the cavity; a semiconductor wafer is disposed on the conductive layer within the cavity; a package is disposed to cover the semiconductor wafer; a through-hole is formed extending from one of the package surfaces of the package to the conductive layer; and a conductive portion is formed within the through-hole.

19. The manufacturing method as claimed in claim 13, wherein the step of configuring the cage-like member on the carrier includes: A conductive portion is formed, wherein the conductive portion extends from the surface of the second cage to the surface of the first cage.

20. The manufacturing method as claimed in claim 19, wherein the step of configuring the cage-like member on the carrier includes: A second layer of fabric is disposed on the surface of the second cage-like member; A third layer of fabric is disposed on the surface of the first cage-like member, wherein the third layer of fabric is located between the first layer of fabric and the surface of the first cage-like member, and the conductive portion is electrically connected to the second layer of fabric and the third layer of fabric.

Images